2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
30 #include <linux/clk-provider.h>
34 #define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
37 /* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
38 #define RK1108_PLL_CON(x) ((x) * 0x4)
39 #define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
40 #define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
41 #define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
42 #define RK1108_GLB_SRST_FST 0x1c0
43 #define RK1108_GLB_SRST_SND 0x1c4
44 #define RK1108_MISC_CON 0x1cc
45 #define RK1108_SDMMC_CON0 0x1d8
46 #define RK1108_SDMMC_CON1 0x1dc
47 #define RK1108_SDIO_CON0 0x1e0
48 #define RK1108_SDIO_CON1 0x1e4
49 #define RK1108_EMMC_CON0 0x1e8
50 #define RK1108_EMMC_CON1 0x1ec
52 #define RK2928_PLL_CON(x) ((x) * 0x4)
53 #define RK2928_MODE_CON 0x40
54 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
55 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
56 #define RK2928_GLB_SRST_FST 0x100
57 #define RK2928_GLB_SRST_SND 0x104
58 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
59 #define RK2928_MISC_CON 0x134
61 #define RK3036_SDMMC_CON0 0x144
62 #define RK3036_SDMMC_CON1 0x148
63 #define RK3036_SDIO_CON0 0x14c
64 #define RK3036_SDIO_CON1 0x150
65 #define RK3036_EMMC_CON0 0x154
66 #define RK3036_EMMC_CON1 0x158
68 #define RK3228_GLB_SRST_FST 0x1f0
69 #define RK3228_GLB_SRST_SND 0x1f4
70 #define RK3228_SDMMC_CON0 0x1c0
71 #define RK3228_SDMMC_CON1 0x1c4
72 #define RK3228_SDIO_CON0 0x1c8
73 #define RK3228_SDIO_CON1 0x1cc
74 #define RK3228_EMMC_CON0 0x1d8
75 #define RK3228_EMMC_CON1 0x1dc
77 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
78 #define RK3288_MODE_CON 0x50
79 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
80 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
81 #define RK3288_GLB_SRST_FST 0x1b0
82 #define RK3288_GLB_SRST_SND 0x1b4
83 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
84 #define RK3288_MISC_CON 0x1e8
85 #define RK3288_SDMMC_CON0 0x200
86 #define RK3288_SDMMC_CON1 0x204
87 #define RK3288_SDIO0_CON0 0x208
88 #define RK3288_SDIO0_CON1 0x20c
89 #define RK3288_SDIO1_CON0 0x210
90 #define RK3288_SDIO1_CON1 0x214
91 #define RK3288_EMMC_CON0 0x218
92 #define RK3288_EMMC_CON1 0x21c
94 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
95 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
96 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
97 #define RK3368_GLB_SRST_FST 0x280
98 #define RK3368_GLB_SRST_SND 0x284
99 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
100 #define RK3368_MISC_CON 0x380
101 #define RK3368_SDMMC_CON0 0x400
102 #define RK3368_SDMMC_CON1 0x404
103 #define RK3368_SDIO0_CON0 0x408
104 #define RK3368_SDIO0_CON1 0x40c
105 #define RK3368_SDIO1_CON0 0x410
106 #define RK3368_SDIO1_CON1 0x414
107 #define RK3368_EMMC_CON0 0x418
108 #define RK3368_EMMC_CON1 0x41c
110 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
111 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
112 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
113 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
114 #define RK3399_GLB_SRST_FST 0x500
115 #define RK3399_GLB_SRST_SND 0x504
116 #define RK3399_GLB_CNT_TH 0x508
117 #define RK3399_MISC_CON 0x50c
118 #define RK3399_RST_CON 0x510
119 #define RK3399_RST_ST 0x514
120 #define RK3399_SDMMC_CON0 0x580
121 #define RK3399_SDMMC_CON1 0x584
122 #define RK3399_SDIO_CON0 0x588
123 #define RK3399_SDIO_CON1 0x58c
125 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
126 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
127 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
128 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
130 enum rockchip_pll_type
{
136 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
137 _postdiv2, _dsmpd, _frac) \
141 .postdiv1 = _postdiv1, \
143 .postdiv2 = _postdiv2, \
148 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
154 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
157 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
167 * struct rockchip_clk_provider - information about clock provider
168 * @reg_base: virtual address for the register base.
169 * @clk_data: holds clock related data like clk* and number of clocks.
170 * @cru_node: device-node of the clock-provider
171 * @grf: regmap of the general-register-files syscon
172 * @lock: maintains exclusion between callbacks for a given clock-provider.
174 struct rockchip_clk_provider
{
175 void __iomem
*reg_base
;
176 struct clk_onecell_data clk_data
;
177 struct device_node
*cru_node
;
182 struct rockchip_pll_rate_table
{
188 /* for RK3036/RK3399 */
190 unsigned int postdiv1
;
192 unsigned int postdiv2
;
198 * struct rockchip_pll_clock - information about pll clock
199 * @id: platform specific id of the clock.
200 * @name: name of this pll clock.
201 * @parent_names: name of the parent clock.
202 * @num_parents: number of parents
203 * @flags: optional flags for basic clock.
204 * @con_offset: offset of the register for configuring the PLL.
205 * @mode_offset: offset of the register for configuring the PLL-mode.
206 * @mode_shift: offset inside the mode-register for the mode of this pll.
207 * @lock_shift: offset inside the lock register for the lock status.
208 * @type: Type of PLL to be registered.
209 * @pll_flags: hardware-specific flags
210 * @rate_table: Table of usable pll rates
213 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
214 * rate_table parameters and ajust them if necessary.
216 struct rockchip_pll_clock
{
219 const char *const *parent_names
;
226 enum rockchip_pll_type type
;
228 struct rockchip_pll_rate_table
*rate_table
;
231 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
233 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
234 _lshift, _pflags, _rtable) \
239 .parent_names = _pnames, \
240 .num_parents = ARRAY_SIZE(_pnames), \
241 .flags = CLK_GET_RATE_NOCACHE | _flags, \
242 .con_offset = _con, \
243 .mode_offset = _mode, \
244 .mode_shift = _mshift, \
245 .lock_shift = _lshift, \
246 .pll_flags = _pflags, \
247 .rate_table = _rtable, \
250 struct clk
*rockchip_clk_register_pll(struct rockchip_clk_provider
*ctx
,
251 enum rockchip_pll_type pll_type
,
252 const char *name
, const char *const *parent_names
,
253 u8 num_parents
, int con_offset
, int grf_lock_offset
,
254 int lock_shift
, int mode_offset
, int mode_shift
,
255 struct rockchip_pll_rate_table
*rate_table
,
256 unsigned long flags
, u8 clk_pll_flags
);
258 struct rockchip_cpuclk_clksel
{
263 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
264 struct rockchip_cpuclk_rate_table
{
266 struct rockchip_cpuclk_clksel divs
[ROCKCHIP_CPUCLK_NUM_DIVIDERS
];
270 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
271 * @core_reg: register offset of the core settings register
272 * @div_core_shift: core divider offset used to divide the pll value
273 * @div_core_mask: core divider mask
274 * @mux_core_alt: mux value to select alternate parent
275 * @mux_core_main: mux value to select main parent of core
276 * @mux_core_shift: offset of the core multiplexer
277 * @mux_core_mask: core multiplexer mask
279 struct rockchip_cpuclk_reg_data
{
289 struct clk
*rockchip_clk_register_cpuclk(const char *name
,
290 const char *const *parent_names
, u8 num_parents
,
291 const struct rockchip_cpuclk_reg_data
*reg_data
,
292 const struct rockchip_cpuclk_rate_table
*rates
,
293 int nrates
, void __iomem
*reg_base
, spinlock_t
*lock
);
295 struct clk
*rockchip_clk_register_mmc(const char *name
,
296 const char *const *parent_names
, u8 num_parents
,
297 void __iomem
*reg
, int shift
);
300 * DDRCLK flags, including method of setting the rate
301 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
303 #define ROCKCHIP_DDRCLK_SIP BIT(0)
305 struct clk
*rockchip_clk_register_ddrclk(const char *name
, int flags
,
306 const char *const *parent_names
,
307 u8 num_parents
, int mux_offset
,
308 int mux_shift
, int mux_width
,
309 int div_shift
, int div_width
,
310 int ddr_flags
, void __iomem
*reg_base
,
313 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
315 struct clk
*rockchip_clk_register_inverter(const char *name
,
316 const char *const *parent_names
, u8 num_parents
,
317 void __iomem
*reg
, int shift
, int flags
,
320 #define PNAME(x) static const char *const x[] __initconst
322 enum rockchip_clk_branch_type
{
326 branch_fraction_divider
,
334 struct rockchip_clk_branch
{
336 enum rockchip_clk_branch_type branch_type
;
338 const char *const *parent_names
;
348 struct clk_div_table
*div_table
;
352 struct rockchip_clk_branch
*child
;
355 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
359 .branch_type = branch_composite, \
361 .parent_names = pnames, \
362 .num_parents = ARRAY_SIZE(pnames), \
364 .muxdiv_offset = mo, \
376 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
380 .branch_type = branch_composite, \
382 .parent_names = (const char *[]){ pname }, \
385 .muxdiv_offset = mo, \
394 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
395 df, dt, go, gs, gf) \
398 .branch_type = branch_composite, \
400 .parent_names = (const char *[]){ pname }, \
403 .muxdiv_offset = mo, \
413 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
417 .branch_type = branch_composite, \
419 .parent_names = pnames, \
420 .num_parents = ARRAY_SIZE(pnames), \
422 .muxdiv_offset = mo, \
431 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
435 .branch_type = branch_composite, \
437 .parent_names = pnames, \
438 .num_parents = ARRAY_SIZE(pnames), \
440 .muxdiv_offset = mo, \
450 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
451 mw, mf, ds, dw, df, dt) \
454 .branch_type = branch_composite, \
456 .parent_names = pnames, \
457 .num_parents = ARRAY_SIZE(pnames), \
459 .muxdiv_offset = mo, \
470 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
473 .branch_type = branch_fraction_divider, \
475 .parent_names = (const char *[]){ pname }, \
478 .muxdiv_offset = mo, \
487 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
490 .branch_type = branch_fraction_divider, \
492 .parent_names = (const char *[]){ pname }, \
495 .muxdiv_offset = mo, \
505 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
508 .branch_type = branch_fraction_divider, \
510 .parent_names = (const char *[]){ pname }, \
513 .muxdiv_offset = mo, \
521 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
525 .branch_type = branch_ddrclk, \
527 .parent_names = pnames, \
528 .num_parents = ARRAY_SIZE(pnames), \
530 .muxdiv_offset = mo, \
539 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
542 .branch_type = branch_mux, \
544 .parent_names = pnames, \
545 .num_parents = ARRAY_SIZE(pnames), \
547 .muxdiv_offset = o, \
554 #define DIV(_id, cname, pname, f, o, s, w, df) \
557 .branch_type = branch_divider, \
559 .parent_names = (const char *[]){ pname }, \
562 .muxdiv_offset = o, \
569 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
572 .branch_type = branch_divider, \
574 .parent_names = (const char *[]){ pname }, \
577 .muxdiv_offset = o, \
584 #define GATE(_id, cname, pname, f, o, b, gf) \
587 .branch_type = branch_gate, \
589 .parent_names = (const char *[]){ pname }, \
597 #define MMC(_id, cname, pname, offset, shift) \
600 .branch_type = branch_mmc, \
602 .parent_names = (const char *[]){ pname }, \
604 .muxdiv_offset = offset, \
605 .div_shift = shift, \
608 #define INVERTER(_id, cname, pname, io, is, if) \
611 .branch_type = branch_inverter, \
613 .parent_names = (const char *[]){ pname }, \
615 .muxdiv_offset = io, \
620 #define FACTOR(_id, cname, pname, f, fm, fd) \
623 .branch_type = branch_factor, \
625 .parent_names = (const char *[]){ pname }, \
632 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
635 .branch_type = branch_factor, \
637 .parent_names = (const char *[]){ pname }, \
647 struct rockchip_clk_provider
*rockchip_clk_init(struct device_node
*np
,
648 void __iomem
*base
, unsigned long nr_clks
);
649 void rockchip_clk_of_add_provider(struct device_node
*np
,
650 struct rockchip_clk_provider
*ctx
);
651 void rockchip_clk_add_lookup(struct rockchip_clk_provider
*ctx
,
652 struct clk
*clk
, unsigned int id
);
653 void rockchip_clk_register_branches(struct rockchip_clk_provider
*ctx
,
654 struct rockchip_clk_branch
*list
,
655 unsigned int nr_clk
);
656 void rockchip_clk_register_plls(struct rockchip_clk_provider
*ctx
,
657 struct rockchip_pll_clock
*pll_list
,
658 unsigned int nr_pll
, int grf_lock_offset
);
659 void rockchip_clk_register_armclk(struct rockchip_clk_provider
*ctx
,
660 unsigned int lookup_id
, const char *name
,
661 const char *const *parent_names
, u8 num_parents
,
662 const struct rockchip_cpuclk_reg_data
*reg_data
,
663 const struct rockchip_cpuclk_rate_table
*rates
,
665 void rockchip_clk_protect_critical(const char *const clocks
[], int nclocks
);
666 void rockchip_register_restart_notifier(struct rockchip_clk_provider
*ctx
,
667 unsigned int reg
, void (*cb
)(void));
669 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
671 #ifdef CONFIG_RESET_CONTROLLER
672 void rockchip_register_softrst(struct device_node
*np
,
673 unsigned int num_regs
,
674 void __iomem
*base
, u8 flags
);
676 static inline void rockchip_register_softrst(struct device_node
*np
,
677 unsigned int num_regs
,
678 void __iomem
*base
, u8 flags
)