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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos3250.c
blob1b81e283f60589c900c5bfc6370a125d8c8c845d
1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for Exynos3250 SoC.
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/syscore_ops.h>
16
17 #include <dt-bindings/clock/exynos3250.h>
18
19 #include "clk.h"
20 #include "clk-cpu.h"
21 #include "clk-pll.h"
22
23 #define SRC_LEFTBUS 0x4200
24 #define DIV_LEFTBUS 0x4500
25 #define GATE_IP_LEFTBUS 0x4800
26 #define SRC_RIGHTBUS 0x8200
27 #define DIV_RIGHTBUS 0x8500
28 #define GATE_IP_RIGHTBUS 0x8800
29 #define GATE_IP_PERIR 0x8960
30 #define MPLL_LOCK 0xc010
31 #define MPLL_CON0 0xc110
32 #define VPLL_LOCK 0xc020
33 #define VPLL_CON0 0xc120
34 #define UPLL_LOCK 0xc030
35 #define UPLL_CON0 0xc130
36 #define SRC_TOP0 0xc210
37 #define SRC_TOP1 0xc214
38 #define SRC_CAM 0xc220
39 #define SRC_MFC 0xc228
40 #define SRC_G3D 0xc22c
41 #define SRC_LCD 0xc234
42 #define SRC_ISP 0xc238
43 #define SRC_FSYS 0xc240
44 #define SRC_PERIL0 0xc250
45 #define SRC_PERIL1 0xc254
46 #define SRC_MASK_TOP 0xc310
47 #define SRC_MASK_CAM 0xc320
48 #define SRC_MASK_LCD 0xc334
49 #define SRC_MASK_ISP 0xc338
50 #define SRC_MASK_FSYS 0xc340
51 #define SRC_MASK_PERIL0 0xc350
52 #define SRC_MASK_PERIL1 0xc354
53 #define DIV_TOP 0xc510
54 #define DIV_CAM 0xc520
55 #define DIV_MFC 0xc528
56 #define DIV_G3D 0xc52c
57 #define DIV_LCD 0xc534
58 #define DIV_ISP 0xc538
59 #define DIV_FSYS0 0xc540
60 #define DIV_FSYS1 0xc544
61 #define DIV_FSYS2 0xc548
62 #define DIV_PERIL0 0xc550
63 #define DIV_PERIL1 0xc554
64 #define DIV_PERIL3 0xc55c
65 #define DIV_PERIL4 0xc560
66 #define DIV_PERIL5 0xc564
67 #define DIV_CAM1 0xc568
68 #define CLKDIV2_RATIO 0xc580
69 #define GATE_SCLK_CAM 0xc820
70 #define GATE_SCLK_MFC 0xc828
71 #define GATE_SCLK_G3D 0xc82c
72 #define GATE_SCLK_LCD 0xc834
73 #define GATE_SCLK_ISP_TOP 0xc838
74 #define GATE_SCLK_FSYS 0xc840
75 #define GATE_SCLK_PERIL 0xc850
76 #define GATE_IP_CAM 0xc920
77 #define GATE_IP_MFC 0xc928
78 #define GATE_IP_G3D 0xc92c
79 #define GATE_IP_LCD 0xc934
80 #define GATE_IP_ISP 0xc938
81 #define GATE_IP_FSYS 0xc940
82 #define GATE_IP_PERIL 0xc950
83 #define GATE_BLOCK 0xc970
84 #define APLL_LOCK 0x14000
85 #define APLL_CON0 0x14100
86 #define SRC_CPU 0x14200
87 #define DIV_CPU0 0x14500
88 #define DIV_CPU1 0x14504
89 #define PWR_CTRL1 0x15020
90 #define PWR_CTRL2 0x15024
91
92 /* Below definitions are used for PWR_CTRL settings */
93 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
94 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
95 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
96 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
97 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
98 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
99 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
100 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
101 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
102 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
103 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
104 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
105
106 static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
107 SRC_LEFTBUS,
108 DIV_LEFTBUS,
109 GATE_IP_LEFTBUS,
110 SRC_RIGHTBUS,
111 DIV_RIGHTBUS,
112 GATE_IP_RIGHTBUS,
113 GATE_IP_PERIR,
114 MPLL_LOCK,
115 MPLL_CON0,
116 VPLL_LOCK,
117 VPLL_CON0,
118 UPLL_LOCK,
119 UPLL_CON0,
120 SRC_TOP0,
121 SRC_TOP1,
122 SRC_CAM,
123 SRC_MFC,
124 SRC_G3D,
125 SRC_LCD,
126 SRC_ISP,
127 SRC_FSYS,
128 SRC_PERIL0,
129 SRC_PERIL1,
130 SRC_MASK_TOP,
131 SRC_MASK_CAM,
132 SRC_MASK_LCD,
133 SRC_MASK_ISP,
134 SRC_MASK_FSYS,
135 SRC_MASK_PERIL0,
136 SRC_MASK_PERIL1,
137 DIV_TOP,
138 DIV_CAM,
139 DIV_MFC,
140 DIV_G3D,
141 DIV_LCD,
142 DIV_ISP,
143 DIV_FSYS0,
144 DIV_FSYS1,
145 DIV_FSYS2,
146 DIV_PERIL0,
147 DIV_PERIL1,
148 DIV_PERIL3,
149 DIV_PERIL4,
150 DIV_PERIL5,
151 DIV_CAM1,
152 CLKDIV2_RATIO,
153 GATE_SCLK_CAM,
154 GATE_SCLK_MFC,
155 GATE_SCLK_G3D,
156 GATE_SCLK_LCD,
157 GATE_SCLK_ISP_TOP,
158 GATE_SCLK_FSYS,
159 GATE_SCLK_PERIL,
160 GATE_IP_CAM,
161 GATE_IP_MFC,
162 GATE_IP_G3D,
163 GATE_IP_LCD,
164 GATE_IP_ISP,
165 GATE_IP_FSYS,
166 GATE_IP_PERIL,
167 GATE_BLOCK,
168 APLL_LOCK,
169 SRC_CPU,
170 DIV_CPU0,
171 DIV_CPU1,
172 PWR_CTRL1,
173 PWR_CTRL2,
174 };
175
176 /* list of all parent clock list */
177 PNAME(mout_vpllsrc_p) = { "fin_pll", };
178
179 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
180 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
181 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
182 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
183
184 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
185 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
186 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
187 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
188
189 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
190 PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
191
192 PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
193 PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
194
195 PNAME(mout_aclk_400_mcuisp_sub_p)
196 = { "fin_pll", "div_aclk_400_mcuisp", };
197 PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
198 PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
199 PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
200 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
201
202 PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
203 PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
204 PNAME(group_sclk_p) = { "xxti", "xusbxti",
205 "none", "none",
206 "none", "none", "div_mpll_pre",
207 "mout_epll_user", "mout_vpll", };
208 PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
209 "none", "none",
210 "xxti", "xusbxti",
211 "div_mpll_pre", "mout_epll_user",
212 "mout_vpll", };
213 PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
214 "none", "none", "none",
215 "none", "div_mpll_pre",
216 "mout_epll_user", "mout_vpll",
217 "none", "none", "none",
218 "div_cam_blk_320", };
219 PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
220 "m_bitclkhsdiv4_2l", "none",
221 "none", "none", "div_mpll_pre",
222 "mout_epll_user", "mout_vpll",
223 "none", "none", "none",
224 "div_lcd_blk_145", };
225
226 PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
227 PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
228
229 static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
230 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
231 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
232 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
233 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
234 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
235
236 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
237 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
238 };
239
240 static const struct samsung_mux_clock mux_clks[] __initconst = {
241 /*
242 * NOTE: Following table is sorted by register address in ascending
243 * order and then bitfield shift in descending order, as it is done
244 * in the User's Manual. When adding new entries, please make sure
245 * that the order is preserved, to avoid merge conflicts and make
246 * further work with defined data easier.
247 */
248
249 /* SRC_LEFTBUS */
250 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
251 SRC_LEFTBUS, 4, 1),
252 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
253
254 /* SRC_RIGHTBUS */
255 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
256 SRC_RIGHTBUS, 4, 1),
257 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
258
259 /* SRC_TOP0 */
260 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
261 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
262 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
263 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
264 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
265 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
266 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
267 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
268 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
269 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
270
271 /* SRC_TOP1 */
272 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
273 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
274 SRC_TOP1, 24, 1),
275 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
276 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
277 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
278 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
279
280 /* SRC_CAM */
281 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
282 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
283
284 /* SRC_MFC */
285 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
286 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
287 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
288
289 /* SRC_G3D */
290 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
291 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
292 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
293
294 /* SRC_LCD */
295 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
296 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
297
298 /* SRC_ISP */
299 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
300 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
301 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
302
303 /* SRC_FSYS */
304 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
305 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
306 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
307 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
308
309 /* SRC_PERIL0 */
310 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
311 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
312 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
313
314 /* SRC_PERIL1 */
315 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
316 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
317 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
318
319 /* SRC_CPU */
320 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
321 SRC_CPU, 24, 1),
322 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
323 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
324 CLK_SET_RATE_PARENT, 0),
325 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
326 CLK_SET_RATE_PARENT, 0),
327 };
328
329 static const struct samsung_div_clock div_clks[] __initconst = {
330 /*
331 * NOTE: Following table is sorted by register address in ascending
332 * order and then bitfield shift in descending order, as it is done
333 * in the User's Manual. When adding new entries, please make sure
334 * that the order is preserved, to avoid merge conflicts and make
335 * further work with defined data easier.
336 */
337
338 /* DIV_LEFTBUS */
339 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
340 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
341
342 /* DIV_RIGHTBUS */
343 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
344 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
345
346 /* DIV_TOP */
347 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
348 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
349 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
350 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
351 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
352 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
353 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
354 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
355
356 /* DIV_CAM */
357 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
358 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
359
360 /* DIV_MFC */
361 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
362
363 /* DIV_G3D */
364 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
365
366 /* DIV_LCD */
367 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
368 CLK_SET_RATE_PARENT, 0),
369 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
370 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
371
372 /* DIV_ISP */
373 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
374 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
375 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
376 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
377 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
378 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
379 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
380
381 /* DIV_FSYS0 */
382 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
383 CLK_SET_RATE_PARENT, 0),
384 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
385
386 /* DIV_FSYS1 */
387 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
388 CLK_SET_RATE_PARENT, 0),
389 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
390 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
391 CLK_SET_RATE_PARENT, 0),
392 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
393
394 /* DIV_FSYS2 */
395 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
396 CLK_SET_RATE_PARENT, 0),
397 DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
398
399 /* DIV_PERIL0 */
400 DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
401 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
402 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
403
404 /* DIV_PERIL1 */
405 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
406 CLK_SET_RATE_PARENT, 0),
407 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
408 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
409 CLK_SET_RATE_PARENT, 0),
410 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
411
412 /* DIV_PERIL4 */
413 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
414 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
415
416 /* DIV_PERIL5 */
417 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
418
419 /* DIV_CPU0 */
420 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
421 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
422 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
423 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
424 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
425 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
426
427 /* DIV_CPU1 */
428 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
429 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
430 };
431
432 static const struct samsung_gate_clock gate_clks[] __initconst = {
433 /*
434 * NOTE: Following table is sorted by register address in ascending
435 * order and then bitfield shift in descending order, as it is done
436 * in the User's Manual. When adding new entries, please make sure
437 * that the order is preserved, to avoid merge conflicts and make
438 * further work with defined data easier.
439 */
440
441 /* GATE_IP_LEFTBUS */
442 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
443 CLK_IGNORE_UNUSED, 0),
444 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
445 CLK_IGNORE_UNUSED, 0),
446 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
447 CLK_IGNORE_UNUSED, 0),
448 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
449 CLK_IGNORE_UNUSED, 0),
450
451 /* GATE_IP_RIGHTBUS */
452 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
453 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
454 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
455 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
456 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
457 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
458 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
459 CLK_IGNORE_UNUSED, 0),
460 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
461 CLK_IGNORE_UNUSED, 0),
462 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
463 CLK_IGNORE_UNUSED, 0),
464
465 /* GATE_IP_PERIR */
466 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
467 CLK_IGNORE_UNUSED, 0),
468 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
469 CLK_IGNORE_UNUSED, 0),
470 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
471 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
472 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
473 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
474 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
475 CLK_IGNORE_UNUSED, 0),
476 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
477 GATE_IP_PERIR, 17, 0, 0),
478 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
479 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
480 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
481 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
482 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
483 CLK_IGNORE_UNUSED, 0),
484 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
485 CLK_IGNORE_UNUSED, 0),
486 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
487 CLK_IGNORE_UNUSED, 0),
488 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
489 CLK_IGNORE_UNUSED, 0),
490 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
491 CLK_IGNORE_UNUSED, 0),
492 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
493 CLK_IGNORE_UNUSED, 0),
494 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
495 CLK_IGNORE_UNUSED, 0),
496 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
497 CLK_IGNORE_UNUSED, 0),
498 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
499 CLK_IGNORE_UNUSED, 0),
500 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
501 CLK_IGNORE_UNUSED, 0),
502 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
503 CLK_IGNORE_UNUSED, 0),
504 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
505 CLK_IGNORE_UNUSED, 0),
506
507 /* GATE_SCLK_CAM */
508 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
509 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
510 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
511 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
512 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
513 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
514 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
515 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
516
517 /* GATE_SCLK_MFC */
518 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
519 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
520
521 /* GATE_SCLK_G3D */
522 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
523 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
524
525 /* GATE_SCLK_LCD */
526 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
527 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
528 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
529 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
530 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
531 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
532
533 /* GATE_SCLK_ISP_TOP */
534 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
535 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
536 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
537 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
538 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
539 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
540 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
541 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
542
543 /* GATE_SCLK_FSYS */
544 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
545 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
546 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
547 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
548 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
549 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
550 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
551 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
552 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
553 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
554 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
555
556 /* GATE_SCLK_PERIL */
557 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
558 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
560 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
562 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
564 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
565
566 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
567 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
568 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
569 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
570 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
571 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
572
573 /* GATE_IP_CAM */
574 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
575 CLK_IGNORE_UNUSED, 0),
576 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
577 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
578 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
579 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
580 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
581 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
582 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
583 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
584 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
585 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
586 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
587 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
588 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
589 GATE_IP_CAM, 11, 0, 0),
590 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
591 GATE_IP_CAM, 9, 0, 0),
592 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
593 GATE_IP_CAM, 8, 0, 0),
594 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
595 GATE_IP_CAM, 7, 0, 0),
596 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
597 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
598 GATE_IP_CAM, 2, 0, 0),
599 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
600 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
601
602 /* GATE_IP_MFC */
603 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
604 CLK_IGNORE_UNUSED, 0),
605 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
606 CLK_IGNORE_UNUSED, 0),
607 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
608 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
609
610 /* GATE_IP_G3D */
611 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
612 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
613 CLK_IGNORE_UNUSED, 0),
614 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
615 CLK_IGNORE_UNUSED, 0),
616 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
617
618 /* GATE_IP_LCD */
619 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
620 CLK_IGNORE_UNUSED, 0),
621 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
622 CLK_IGNORE_UNUSED, 0),
623 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
624 CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
626 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
627 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
628 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
629
630 /* GATE_IP_ISP */
631 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
632 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
633 GATE_IP_ISP, 3, 0, 0),
634 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
635 GATE_IP_ISP, 2, 0, 0),
636 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
637 GATE_IP_ISP, 1, 0, 0),
638
639 /* GATE_IP_FSYS */
640 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
641 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
642 CLK_IGNORE_UNUSED, 0),
643 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
644 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
645 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
646 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
647 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
648 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
649 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
650 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
651
652 /* GATE_IP_PERIL */
653 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
654 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
655 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
656 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
657 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
658 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
659 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
660 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
661 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
662 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
663 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
664 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
665 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
666 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
667 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
668 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
669 };
670
671 /* APLL & MPLL & BPLL & UPLL */
672 static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
673 PLL_35XX_RATE(1200000000, 400, 4, 1),
674 PLL_35XX_RATE(1100000000, 275, 3, 1),
675 PLL_35XX_RATE(1066000000, 533, 6, 1),
676 PLL_35XX_RATE(1000000000, 250, 3, 1),
677 PLL_35XX_RATE( 960000000, 320, 4, 1),
678 PLL_35XX_RATE( 900000000, 300, 4, 1),
679 PLL_35XX_RATE( 850000000, 425, 6, 1),
680 PLL_35XX_RATE( 800000000, 200, 3, 1),
681 PLL_35XX_RATE( 700000000, 175, 3, 1),
682 PLL_35XX_RATE( 667000000, 667, 12, 1),
683 PLL_35XX_RATE( 600000000, 400, 4, 2),
684 PLL_35XX_RATE( 533000000, 533, 6, 2),
685 PLL_35XX_RATE( 520000000, 260, 3, 2),
686 PLL_35XX_RATE( 500000000, 250, 3, 2),
687 PLL_35XX_RATE( 400000000, 200, 3, 2),
688 PLL_35XX_RATE( 200000000, 200, 3, 3),
689 PLL_35XX_RATE( 100000000, 200, 3, 4),
690 { /* sentinel */ }
691 };
692
693 /* EPLL */
694 static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
695 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
696 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
697 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
698 PLL_36XX_RATE(144000000, 96, 2, 3, 0),
699 PLL_36XX_RATE( 96000000, 128, 2, 4, 0),
700 PLL_36XX_RATE( 84000000, 112, 2, 4, 0),
701 PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
702 PLL_36XX_RATE( 73728000, 98, 2, 4, 19923),
703 PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
704 PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
705 PLL_36XX_RATE( 50000000, 200, 3, 5, 0),
706 PLL_36XX_RATE( 49152002, 131, 2, 5, 4719),
707 PLL_36XX_RATE( 48000000, 128, 2, 5, 0),
708 PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),
709 { /* sentinel */ }
710 };
711
712 /* VPLL */
713 static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
714 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
715 PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
716 PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
717 PLL_36XX_RATE(500000000, 250, 3, 2, 0),
718 PLL_36XX_RATE(445500000, 148, 2, 2, 32768),
719 PLL_36XX_RATE(445055007, 148, 2, 2, 23047),
720 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
721 PLL_36XX_RATE(371250000, 123, 2, 2, 49152),
722 PLL_36XX_RATE(370878997, 185, 3, 2, 28803),
723 PLL_36XX_RATE(340000000, 170, 3, 2, 0),
724 PLL_36XX_RATE(335000015, 111, 2, 2, 43691),
725 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
726 PLL_36XX_RATE(330000000, 110, 2, 2, 0),
727 PLL_36XX_RATE(320000015, 106, 2, 2, 43691),
728 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
729 PLL_36XX_RATE(275000000, 275, 3, 3, 0),
730 PLL_36XX_RATE(222750000, 148, 2, 3, 32768),
731 PLL_36XX_RATE(222528007, 148, 2, 3, 23069),
732 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
733 PLL_36XX_RATE(148500000, 99, 2, 3, 0),
734 PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
735 PLL_36XX_RATE(108000000, 144, 2, 4, 0),
736 PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
737 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
738 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
739 PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
740 { /* sentinel */ }
741 };
742
743 static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
744 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
745 APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
746 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
747 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
748 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
749 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
750 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
751 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
752 };
753
754 static void __init exynos3_core_down_clock(void __iomem *reg_base)
755 {
756 unsigned int tmp;
757
758 /*
759 * Enable arm clock down (in idle) and set arm divider
760 * ratios in WFI/WFE state.
761 */
762 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
763 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
764 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
765 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
766 __raw_writel(tmp, reg_base + PWR_CTRL1);
767
768 /*
769 * Disable the clock up feature on Exynos4x12, in case it was
770 * enabled by bootloader.
771 */
772 __raw_writel(0x0, reg_base + PWR_CTRL2);
773 }
774
775 static const struct samsung_cmu_info cmu_info __initconst = {
776 .pll_clks = exynos3250_plls,
777 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
778 .mux_clks = mux_clks,
779 .nr_mux_clks = ARRAY_SIZE(mux_clks),
780 .div_clks = div_clks,
781 .nr_div_clks = ARRAY_SIZE(div_clks),
782 .gate_clks = gate_clks,
783 .nr_gate_clks = ARRAY_SIZE(gate_clks),
784 .fixed_factor_clks = fixed_factor_clks,
785 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
786 .nr_clk_ids = CLK_NR_CLKS,
787 .clk_regs = exynos3250_cmu_clk_regs,
788 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
789 };
790
791 #define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
792 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
793 ((corem) << 4))
794 #define E3250_CPU_DIV1(hpm, copy) \
795 (((hpm) << 4) | ((copy) << 0))
796
797 static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
798 { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
799 { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
800 { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
801 { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
802 { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
803 { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
804 { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
805 { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
806 { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
807 { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
808 { 0 },
809 };
810
811 static void __init exynos3250_cmu_init(struct device_node *np)
812 {
813 struct samsung_clk_provider *ctx;
814
815 ctx = samsung_cmu_register_one(np, &cmu_info);
816 if (!ctx)
817 return;
818
819 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
820 mout_core_p[0], mout_core_p[1], 0x14200,
821 e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
822 CLK_CPU_HAS_DIV1);
823
824 exynos3_core_down_clock(ctx->reg_base);
825 }
826 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
827
828 /*
829 * CMU DMC
830 */
831
832 #define BPLL_LOCK 0x0118
833 #define BPLL_CON0 0x0218
834 #define BPLL_CON1 0x021c
835 #define BPLL_CON2 0x0220
836 #define SRC_DMC 0x0300
837 #define DIV_DMC1 0x0504
838 #define GATE_BUS_DMC0 0x0700
839 #define GATE_BUS_DMC1 0x0704
840 #define GATE_BUS_DMC2 0x0708
841 #define GATE_BUS_DMC3 0x070c
842 #define GATE_SCLK_DMC 0x0800
843 #define GATE_IP_DMC0 0x0900
844 #define GATE_IP_DMC1 0x0904
845 #define EPLL_LOCK 0x1110
846 #define EPLL_CON0 0x1114
847 #define EPLL_CON1 0x1118
848 #define EPLL_CON2 0x111c
849 #define SRC_EPLL 0x1120
850
851 static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
852 BPLL_LOCK,
853 BPLL_CON0,
854 BPLL_CON1,
855 BPLL_CON2,
856 SRC_DMC,
857 DIV_DMC1,
858 GATE_BUS_DMC0,
859 GATE_BUS_DMC1,
860 GATE_BUS_DMC2,
861 GATE_BUS_DMC3,
862 GATE_SCLK_DMC,
863 GATE_IP_DMC0,
864 GATE_IP_DMC1,
865 EPLL_LOCK,
866 EPLL_CON0,
867 EPLL_CON1,
868 EPLL_CON2,
869 SRC_EPLL,
870 };
871
872 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
873 PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
874 PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
875 PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
876
877 static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
878 /*
879 * NOTE: Following table is sorted by register address in ascending
880 * order and then bitfield shift in descending order, as it is done
881 * in the User's Manual. When adding new entries, please make sure
882 * that the order is preserved, to avoid merge conflicts and make
883 * further work with defined data easier.
884 */
885
886 /* SRC_DMC */
887 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
888 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
889 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
890 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
891
892 /* SRC_EPLL */
893 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
894 };
895
896 static const struct samsung_div_clock dmc_div_clks[] __initconst = {
897 /*
898 * NOTE: Following table is sorted by register address in ascending
899 * order and then bitfield shift in descending order, as it is done
900 * in the User's Manual. When adding new entries, please make sure
901 * that the order is preserved, to avoid merge conflicts and make
902 * further work with defined data easier.
903 */
904
905 /* DIV_DMC1 */
906 DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
907 DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
908 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
909 DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
910 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
911 };
912
913 static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
914 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
915 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
916 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
917 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
918 };
919
920 static const struct samsung_cmu_info dmc_cmu_info __initconst = {
921 .pll_clks = exynos3250_dmc_plls,
922 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
923 .mux_clks = dmc_mux_clks,
924 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
925 .div_clks = dmc_div_clks,
926 .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
927 .nr_clk_ids = NR_CLKS_DMC,
928 .clk_regs = exynos3250_cmu_dmc_clk_regs,
929 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
930 };
931
932 static void __init exynos3250_cmu_dmc_init(struct device_node *np)
933 {
934 samsung_cmu_register_one(np, &dmc_cmu_info);
935 }
936 CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
937 exynos3250_cmu_dmc_init);
938
939
940 /*
941 * CMU ISP
942 */
943
944 #define DIV_ISP0 0x300
945 #define DIV_ISP1 0x304
946 #define GATE_IP_ISP0 0x800
947 #define GATE_IP_ISP1 0x804
948 #define GATE_SCLK_ISP 0x900
949
950 static const struct samsung_div_clock isp_div_clks[] __initconst = {
951 /*
952 * NOTE: Following table is sorted by register address in ascending
953 * order and then bitfield shift in descending order, as it is done
954 * in the User's Manual. When adding new entries, please make sure
955 * that the order is preserved, to avoid merge conflicts and make
956 * further work with defined data easier.
957 */
958 /* DIV_ISP0 */
959 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
960 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
961
962 /* DIV_ISP1 */
963 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
964 DIV_ISP1, 8, 3),
965 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
966 DIV_ISP1, 4, 3),
967 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
968 };
969
970 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
971 /*
972 * NOTE: Following table is sorted by register address in ascending
973 * order and then bitfield shift in descending order, as it is done
974 * in the User's Manual. When adding new entries, please make sure
975 * that the order is preserved, to avoid merge conflicts and make
976 * further work with defined data easier.
977 */
978
979 /* GATE_IP_ISP0 */
980 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
981 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
982 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
983 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
984 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
985 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
986 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
987 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
988 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
989 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
990 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
991 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
992 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
993 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
994 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
995 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
996 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
997 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
998 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
999 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1000 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
1001 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1002 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
1003 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1004 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
1005 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1006 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
1007 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
1008 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
1009 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1010 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
1011 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1012 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
1013 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
1014 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
1015 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
1016 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
1017 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
1018 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
1019 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
1020 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
1021 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
1022 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
1023 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
1024 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
1025 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
1026 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
1027 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1028 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
1029 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
1030 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1031 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
1032 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1033 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
1034 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1035 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1036
1037 /* GATE_IP_ISP1 */
1038 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
1039 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
1040 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1041 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
1042 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1043 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
1044 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1045 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1046 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1047 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1048 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1049 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1050 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1051 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1052 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1053 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1054 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1055 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1056 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1057 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1058 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1059 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1060
1061 /* GATE_SCLK_ISP */
1062 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
1063 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1064 };
1065
1066 static const struct samsung_cmu_info isp_cmu_info __initconst = {
1067 .div_clks = isp_div_clks,
1068 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
1069 .gate_clks = isp_gate_clks,
1070 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
1071 .nr_clk_ids = NR_CLKS_ISP,
1072 };
1073
1074 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1075 {
1076 struct device_node *np = pdev->dev.of_node;
1077
1078 samsung_cmu_register_one(np, &isp_cmu_info);
1079 return 0;
1080 }
1081
1082 static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
1083 { .compatible = "samsung,exynos3250-cmu-isp", },
1084 { /* sentinel */ }
1085 };
1086
1087 static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
1088 .driver = {
1089 .name = "exynos3250-cmu-isp",
1090 .suppress_bind_attrs = true,
1091 .of_match_table = exynos3250_cmu_isp_of_match,
1092 },
1093 };
1094
1095 static int __init exynos3250_cmu_platform_init(void)
1096 {
1097 return platform_driver_probe(&exynos3250_cmu_isp_driver,
1098 exynos3250_cmu_isp_probe);
1099 }
1100 subsys_initcall(exynos3250_cmu_platform_init);
1101
Linux with added FPC-III support