drivers/clk/samsung/clk-pll.h

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Copyright (c) 2013 Linaro Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for all PLL's in Samsung platforms
  10 */
  11
  12 #ifndef __SAMSUNG_CLK_PLL_H
  13 #define __SAMSUNG_CLK_PLL_H
  14
  15 enum samsung_pll_type {
  16         pll_2126,
  17         pll_3000,
  18         pll_35xx,
  19         pll_36xx,
  20         pll_2550,
  21         pll_2650,
  22         pll_4500,
  23         pll_4502,
  24         pll_4508,
  25         pll_4600,
  26         pll_4650,
  27         pll_4650c,
  28         pll_6552,
  29         pll_6552_s3c2416,
  30         pll_6553,
  31         pll_s3c2410_mpll,
  32         pll_s3c2410_upll,
  33         pll_s3c2440_mpll,
  34         pll_2550x,
  35         pll_2550xx,
  36         pll_2650x,
  37         pll_2650xx,
  38         pll_1450x,
  39         pll_1451x,
  40         pll_1452x,
  41         pll_1460x,
  42 };
  43
  44 #define PLL_35XX_RATE(_rate, _m, _p, _s)                        \
  45         {                                                       \
  46                 .rate   =       (_rate),                                \
  47                 .mdiv   =       (_m),                           \
  48                 .pdiv   =       (_p),                           \
  49                 .sdiv   =       (_s),                           \
  50         }
  51
  52 #define PLL_36XX_RATE(_rate, _m, _p, _s, _k)                    \
  53         {                                                       \
  54                 .rate   =       (_rate),                                \
  55                 .mdiv   =       (_m),                           \
  56                 .pdiv   =       (_p),                           \
  57                 .sdiv   =       (_s),                           \
  58                 .kdiv   =       (_k),                           \
  59         }
  60
  61 #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)                  \
  62         {                                                       \
  63                 .rate   =       (_rate),                        \
  64                 .mdiv   =       (_m),                           \
  65                 .pdiv   =       (_p),                           \
  66                 .sdiv   =       (_s),                           \
  67                 .afc    =       (_afc),                         \
  68         }
  69
  70 #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)             \
  71         {                                                       \
  72                 .rate   =       (_rate),                        \
  73                 .mdiv   =       (_m),                           \
  74                 .pdiv   =       (_p),                           \
  75                 .sdiv   =       (_s),                           \
  76                 .kdiv   =       (_k),                           \
  77                 .vsel   =       (_vsel),                        \
  78         }
  79
  80 #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  81         {                                                       \
  82                 .rate   =       (_rate),                        \
  83                 .mdiv   =       (_m),                           \
  84                 .pdiv   =       (_p),                           \
  85                 .sdiv   =       (_s),                           \
  86                 .kdiv   =       (_k),                           \
  87                 .mfr    =       (_mfr),                         \
  88                 .mrr    =       (_mrr),                         \
  89                 .vsel   =       (_vsel),                        \
  90         }
  91
  92 /* NOTE: Rate table should be kept sorted in descending order. */
  93
  94 struct samsung_pll_rate_table {
  95         unsigned int rate;
  96         unsigned int pdiv;
  97         unsigned int mdiv;
  98         unsigned int sdiv;
  99         unsigned int kdiv;
 100         unsigned int afc;
 101         unsigned int mfr;
 102         unsigned int mrr;
 103         unsigned int vsel;
 104 };
 105
 106 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
 107                         const char *pname, const void __iomem *reg_base,
 108                         const unsigned long offset);
 109
 110 #endif /* __SAMSUNG_CLK_PLL_H */