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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun6i-a31.c
blobfc75a335a7ce12480f12f41a95091417466b6a92
1 /*
2 * Copyright (c) 2016 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * Based on ccu-sun8i-h3.c by Maxime Ripard.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk-provider.h>
19 #include <linux/of_address.h>
20
21 #include "ccu_common.h"
22 #include "ccu_reset.h"
23
24 #include "ccu_div.h"
25 #include "ccu_gate.h"
26 #include "ccu_mp.h"
27 #include "ccu_mult.h"
28 #include "ccu_mux.h"
29 #include "ccu_nk.h"
30 #include "ccu_nkm.h"
31 #include "ccu_nkmp.h"
32 #include "ccu_nm.h"
33 #include "ccu_phase.h"
34
35 #include "ccu-sun6i-a31.h"
36
37 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
38 "osc24M", 0x000,
39 8, 5, /* N */
40 4, 2, /* K */
41 0, 2, /* M */
42 BIT(31), /* gate */
43 BIT(28), /* lock */
44 0);
45
46 /*
47 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * the base (2x, 4x and 8x), and one variable divider (the one true
49 * pll audio).
50 *
51 * We don't have any need for the variable divider for now, so we just
52 * hardcode it to match with the clock names
53 */
54 #define SUN6I_A31_PLL_AUDIO_REG 0x008
55
56 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
57 "osc24M", 0x008,
58 8, 7, /* N */
59 0, 5, /* M */
60 BIT(31), /* gate */
61 BIT(28), /* lock */
62 CLK_SET_RATE_UNGATE);
63
64 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
65 "osc24M", 0x010,
66 8, 7, /* N */
67 0, 4, /* M */
68 BIT(24), /* frac enable */
69 BIT(25), /* frac select */
70 270000000, /* frac rate 0 */
71 297000000, /* frac rate 1 */
72 BIT(31), /* gate */
73 BIT(28), /* lock */
74 CLK_SET_RATE_UNGATE);
75
76 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
77 "osc24M", 0x018,
78 8, 7, /* N */
79 0, 4, /* M */
80 BIT(24), /* frac enable */
81 BIT(25), /* frac select */
82 270000000, /* frac rate 0 */
83 297000000, /* frac rate 1 */
84 BIT(31), /* gate */
85 BIT(28), /* lock */
86 CLK_SET_RATE_UNGATE);
87
88 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
89 "osc24M", 0x020,
90 8, 5, /* N */
91 4, 2, /* K */
92 0, 2, /* M */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
95 CLK_SET_RATE_UNGATE);
96
97 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
98 "osc24M", 0x028,
99 8, 5, /* N */
100 4, 2, /* K */
101 BIT(31), /* gate */
102 BIT(28), /* lock */
103 2, /* post-div */
104 CLK_SET_RATE_UNGATE);
105
106 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
107 "osc24M", 0x030,
108 8, 7, /* N */
109 0, 4, /* M */
110 BIT(24), /* frac enable */
111 BIT(25), /* frac select */
112 270000000, /* frac rate 0 */
113 297000000, /* frac rate 1 */
114 BIT(31), /* gate */
115 BIT(28), /* lock */
116 CLK_SET_RATE_UNGATE);
117
118 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
119 "osc24M", 0x038,
120 8, 7, /* N */
121 0, 4, /* M */
122 BIT(24), /* frac enable */
123 BIT(25), /* frac select */
124 270000000, /* frac rate 0 */
125 297000000, /* frac rate 1 */
126 BIT(31), /* gate */
127 BIT(28), /* lock */
128 CLK_SET_RATE_UNGATE);
129
130 /*
131 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
132 *
133 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
134 * integer / fractional clock with switchable multipliers and dividers.
135 * This is not supported here. We hardcode the PLL to MIPI mode.
136 */
137 #define SUN6I_A31_PLL_MIPI_REG 0x040
138
139 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
140 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
141 pll_mipi_parents, 0x040,
142 8, 4, /* N */
143 4, 2, /* K */
144 0, 4, /* M */
145 21, 0, /* mux */
146 BIT(31) | BIT(23) | BIT(22), /* gate */
147 BIT(28), /* lock */
148 CLK_SET_RATE_UNGATE);
149
150 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
151 "osc24M", 0x044,
152 8, 7, /* N */
153 0, 4, /* M */
154 BIT(24), /* frac enable */
155 BIT(25), /* frac select */
156 270000000, /* frac rate 0 */
157 297000000, /* frac rate 1 */
158 BIT(31), /* gate */
159 BIT(28), /* lock */
160 CLK_SET_RATE_UNGATE);
161
162 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
163 "osc24M", 0x048,
164 8, 7, /* N */
165 0, 4, /* M */
166 BIT(24), /* frac enable */
167 BIT(25), /* frac select */
168 270000000, /* frac rate 0 */
169 297000000, /* frac rate 1 */
170 BIT(31), /* gate */
171 BIT(28), /* lock */
172 CLK_SET_RATE_UNGATE);
173
174 static const char * const cpux_parents[] = { "osc32k", "osc24M",
175 "pll-cpu", "pll-cpu" };
176 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
177 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
178
179 static struct clk_div_table axi_div_table[] = {
180 { .val = 0, .div = 1 },
181 { .val = 1, .div = 2 },
182 { .val = 2, .div = 3 },
183 { .val = 3, .div = 4 },
184 { .val = 4, .div = 4 },
185 { .val = 5, .div = 4 },
186 { .val = 6, .div = 4 },
187 { .val = 7, .div = 4 },
188 { /* Sentinel */ },
189 };
190
191 static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
192 0x050, 0, 3, axi_div_table, 0);
193
194 #define SUN6I_A31_AHB1_REG 0x054
195
196 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
197 "axi", "pll-periph" };
198
199 static struct ccu_div ahb1_clk = {
200 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
201
202 .mux = {
203 .shift = 12,
204 .width = 2,
205
206 .variable_prediv = {
207 .index = 3,
208 .shift = 6,
209 .width = 2,
210 },
211 },
212
213 .common = {
214 .reg = 0x054,
215 .features = CCU_FEATURE_VARIABLE_PREDIV,
216 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
217 ahb1_parents,
218 &ccu_div_ops,
219 0),
220 },
221 };
222
223 static struct clk_div_table apb1_div_table[] = {
224 { .val = 0, .div = 2 },
225 { .val = 1, .div = 2 },
226 { .val = 2, .div = 4 },
227 { .val = 3, .div = 8 },
228 { /* Sentinel */ },
229 };
230
231 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
232 0x054, 8, 2, apb1_div_table, 0);
233
234 static const char * const apb2_parents[] = { "osc32k", "osc24M",
235 "pll-periph", "pll-periph" };
236 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
237 0, 5, /* M */
238 16, 2, /* P */
239 24, 2, /* mux */
240 0);
241
242 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
243 0x060, BIT(1), 0);
244 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
245 0x060, BIT(5), 0);
246 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
247 0x060, BIT(6), 0);
248 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
249 0x060, BIT(8), 0);
250 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
251 0x060, BIT(9), 0);
252 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
253 0x060, BIT(10), 0);
254 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
255 0x060, BIT(12), 0);
256 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
257 0x060, BIT(13), 0);
258 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
259 0x060, BIT(13), 0);
260 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
261 0x060, BIT(14), 0);
262 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
263 0x060, BIT(17), 0);
264 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
265 0x060, BIT(18), 0);
266 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
267 0x060, BIT(19), 0);
268 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
269 0x060, BIT(20), 0);
270 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
271 0x060, BIT(21), 0);
272 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
273 0x060, BIT(22), 0);
274 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
275 0x060, BIT(23), 0);
276 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
277 0x060, BIT(24), 0);
278 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
279 0x060, BIT(26), 0);
280 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
281 0x060, BIT(27), 0);
282 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
283 0x060, BIT(29), 0);
284 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
285 0x060, BIT(30), 0);
286 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
287 0x060, BIT(31), 0);
288
289 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
290 0x064, BIT(0), 0);
291 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
292 0x064, BIT(4), 0);
293 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
294 0x064, BIT(5), 0);
295 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
296 0x064, BIT(8), 0);
297 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
298 0x064, BIT(11), 0);
299 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
300 0x064, BIT(12), 0);
301 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
302 0x064, BIT(13), 0);
303 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
304 0x064, BIT(14), 0);
305 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
306 0x064, BIT(15), 0);
307 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
308 0x064, BIT(18), 0);
309 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
310 0x064, BIT(20), 0);
311 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
312 0x064, BIT(23), 0);
313 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
314 0x064, BIT(24), 0);
315 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
316 0x064, BIT(25), 0);
317 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
318 0x064, BIT(26), 0);
319
320 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
321 0x068, BIT(0), 0);
322 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
323 0x068, BIT(1), 0);
324 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
325 0x068, BIT(4), 0);
326 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
327 0x068, BIT(5), 0);
328 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
329 0x068, BIT(12), 0);
330 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
331 0x068, BIT(13), 0);
332
333 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
334 0x06c, BIT(0), 0);
335 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
336 0x06c, BIT(1), 0);
337 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
338 0x06c, BIT(2), 0);
339 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
340 0x06c, BIT(3), 0);
341 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
342 0x06c, BIT(16), 0);
343 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
344 0x06c, BIT(17), 0);
345 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
346 0x06c, BIT(18), 0);
347 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
348 0x06c, BIT(19), 0);
349 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
350 0x06c, BIT(20), 0);
351 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
352 0x06c, BIT(21), 0);
353
354 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
355 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
356 0x080,
357 0, 4, /* M */
358 16, 2, /* P */
359 24, 2, /* mux */
360 BIT(31), /* gate */
361 0);
362
363 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
364 0x084,
365 0, 4, /* M */
366 16, 2, /* P */
367 24, 2, /* mux */
368 BIT(31), /* gate */
369 0);
370
371 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
372 0x088,
373 0, 4, /* M */
374 16, 2, /* P */
375 24, 2, /* mux */
376 BIT(31), /* gate */
377 0);
378
379 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
380 0x088, 20, 3, 0);
381 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
382 0x088, 8, 3, 0);
383
384 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
385 0x08c,
386 0, 4, /* M */
387 16, 2, /* P */
388 24, 2, /* mux */
389 BIT(31), /* gate */
390 0);
391
392 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
393 0x08c, 20, 3, 0);
394 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
395 0x08c, 8, 3, 0);
396
397 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
398 0x090,
399 0, 4, /* M */
400 16, 2, /* P */
401 24, 2, /* mux */
402 BIT(31), /* gate */
403 0);
404
405 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
406 0x090, 20, 3, 0);
407 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
408 0x090, 8, 3, 0);
409
410 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
411 0x094,
412 0, 4, /* M */
413 16, 2, /* P */
414 24, 2, /* mux */
415 BIT(31), /* gate */
416 0);
417
418 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
419 0x094, 20, 3, 0);
420 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
421 0x094, 8, 3, 0);
422
423 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
424 0, 4, /* M */
425 16, 2, /* P */
426 24, 2, /* mux */
427 BIT(31), /* gate */
428 0);
429
430 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
431 0, 4, /* M */
432 16, 2, /* P */
433 24, 2, /* mux */
434 BIT(31), /* gate */
435 0);
436
437 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
438 0, 4, /* M */
439 16, 2, /* P */
440 24, 2, /* mux */
441 BIT(31), /* gate */
442 0);
443
444 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
445 0, 4, /* M */
446 16, 2, /* P */
447 24, 2, /* mux */
448 BIT(31), /* gate */
449 0);
450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
451 0, 4, /* M */
452 16, 2, /* P */
453 24, 2, /* mux */
454 BIT(31), /* gate */
455 0);
456
457 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
458 0, 4, /* M */
459 16, 2, /* P */
460 24, 2, /* mux */
461 BIT(31), /* gate */
462 0);
463
464 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
465 "pll-audio-2x", "pll-audio" };
466 static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
467 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
468 static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
469 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
470
471 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
472 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
473
474 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
475 0x0cc, BIT(8), 0);
476 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
477 0x0cc, BIT(9), 0);
478 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
479 0x0cc, BIT(10), 0);
480 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
481 0x0cc, BIT(16), 0);
482 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
483 0x0cc, BIT(17), 0);
484 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
485 0x0cc, BIT(18), 0);
486
487 /* TODO emac clk not supported yet */
488
489 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
490 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
491 0, 4, /* M */
492 16, 2, /* P */
493 24, 2, /* mux */
494 BIT(31), /* gate */
495 CLK_IS_CRITICAL);
496
497 static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
498 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
499 static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
500 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
501
502 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
503 0x100, BIT(0), 0);
504 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
505 0x100, BIT(1), 0);
506 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
507 0x100, BIT(3), 0);
508 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
509 0x100, BIT(16), 0);
510 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
511 0x100, BIT(17), 0);
512 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
513 0x100, BIT(18), 0);
514 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
515 0x100, BIT(19), 0);
516 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
517 0x100, BIT(24), 0);
518 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
519 0x100, BIT(25), 0);
520 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
521 0x100, BIT(26), 0);
522 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
523 0x100, BIT(27), 0);
524 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
525 0x100, BIT(28), 0);
526
527 static const char * const de_parents[] = { "pll-video0", "pll-video1",
528 "pll-periph-2x", "pll-gpu",
529 "pll9", "pll10" };
530 static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
531 0x104, 0, 4, 24, 3, BIT(31), 0);
532 static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
533 0x108, 0, 4, 24, 3, BIT(31), 0);
534 static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
535 0x10c, 0, 4, 24, 3, BIT(31), 0);
536 static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
537 0x110, 0, 4, 24, 3, BIT(31), 0);
538
539 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
540 "pll9", "pll10" };
541 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
542 0x114, 0, 4, 24, 3, BIT(31), 0);
543
544 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
545 "pll-video0-2x",
546 "pll-video1-2x", "pll-mipi" };
547 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
548 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
549 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
550 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
551
552 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
553 "pll-video0-2x",
554 "pll-video1-2x" };
555 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
556 0x12c, 0, 4, 24, 3, BIT(31),
557 CLK_SET_RATE_PARENT);
558 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
559 0x12c, 0, 4, 24, 3, BIT(31),
560 CLK_SET_RATE_PARENT);
561
562 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
563 "pll9", "pll10", "pll-mipi",
564 "pll-ve" };
565 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
566 0x134, 16, 4, 24, 3, BIT(31), 0);
567
568 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
569 "osc24M" };
570 static const u8 csi_mclk_table[] = { 0, 1, 5 };
571 static struct ccu_div csi0_mclk_clk = {
572 .enable = BIT(15),
573 .div = _SUNXI_CCU_DIV(0, 4),
574 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
575 .common = {
576 .reg = 0x134,
577 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
578 csi_mclk_parents,
579 &ccu_div_ops,
580 0),
581 },
582 };
583
584 static struct ccu_div csi1_mclk_clk = {
585 .enable = BIT(15),
586 .div = _SUNXI_CCU_DIV(0, 4),
587 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
588 .common = {
589 .reg = 0x138,
590 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
591 csi_mclk_parents,
592 &ccu_div_ops,
593 0),
594 },
595 };
596
597 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
598 0x13c, 16, 3, BIT(31), 0);
599
600 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
601 0x140, BIT(31), CLK_SET_RATE_PARENT);
602 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
603 0x144, BIT(31), 0);
604 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
605 0x148, BIT(31), CLK_SET_RATE_PARENT);
606
607 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
608 0x150, 0, 4, 24, 2, BIT(31),
609 CLK_SET_RATE_PARENT);
610
611 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);
612
613 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
614
615 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
616 "pll-ddr" };
617 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
618 0, 3, /* M */
619 16, 2, /* P */
620 24, 2, /* mux */
621 BIT(31), /* gate */
622 CLK_IS_CRITICAL);
623
624 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
625 0, 3, /* M */
626 16, 2, /* P */
627 24, 2, /* mux */
628 BIT(31), /* gate */
629 CLK_IS_CRITICAL);
630
631 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
632 0x168, 16, 3, 24, 2, BIT(31),
633 CLK_SET_RATE_PARENT);
634 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
635 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
636 BIT(15), CLK_SET_RATE_PARENT);
637 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
638 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
639 BIT(15), 0);
640
641 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
642 0x180, 0, 3, 24, 2, BIT(31), 0);
643 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
644 0x184, 0, 3, 24, 2, BIT(31), 0);
645 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
646 0x188, 0, 3, 24, 2, BIT(31), 0);
647 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
648 0x18c, 0, 3, 24, 2, BIT(31), 0);
649
650 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
651 "pll-video0", "pll-video1",
652 "pll9", "pll10" };
653 static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
654 { .index = 1, .div = 3, },
655 };
656
657 static struct ccu_div gpu_core_clk = {
658 .enable = BIT(31),
659 .div = _SUNXI_CCU_DIV(0, 3),
660 .mux = {
661 .shift = 24,
662 .width = 3,
663 .fixed_predivs = gpu_predivs,
664 .n_predivs = ARRAY_SIZE(gpu_predivs),
665 },
666 .common = {
667 .reg = 0x1a0,
668 .features = CCU_FEATURE_FIXED_PREDIV,
669 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
670 gpu_parents,
671 &ccu_div_ops,
672 0),
673 },
674 };
675
676 static struct ccu_div gpu_memory_clk = {
677 .enable = BIT(31),
678 .div = _SUNXI_CCU_DIV(0, 3),
679 .mux = {
680 .shift = 24,
681 .width = 3,
682 .fixed_predivs = gpu_predivs,
683 .n_predivs = ARRAY_SIZE(gpu_predivs),
684 },
685 .common = {
686 .reg = 0x1a4,
687 .features = CCU_FEATURE_FIXED_PREDIV,
688 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
689 gpu_parents,
690 &ccu_div_ops,
691 0),
692 },
693 };
694
695 static struct ccu_div gpu_hyd_clk = {
696 .enable = BIT(31),
697 .div = _SUNXI_CCU_DIV(0, 3),
698 .mux = {
699 .shift = 24,
700 .width = 3,
701 .fixed_predivs = gpu_predivs,
702 .n_predivs = ARRAY_SIZE(gpu_predivs),
703 },
704 .common = {
705 .reg = 0x1a8,
706 .features = CCU_FEATURE_FIXED_PREDIV,
707 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
708 gpu_parents,
709 &ccu_div_ops,
710 0),
711 },
712 };
713
714 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
715 0, 3, /* M */
716 24, 2, /* mux */
717 BIT(31), /* gate */
718 0);
719
720 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
721 0x1b0,
722 0, 3, /* M */
723 24, 2, /* mux */
724 BIT(31), /* gate */
725 0);
726
727 static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
728 "axi", "ahb1" };
729 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
730
731 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
732 { .index = 0, .div = 750, },
733 { .index = 3, .div = 4, },
734 { .index = 4, .div = 4, },
735 };
736
737 static struct ccu_mp out_a_clk = {
738 .enable = BIT(31),
739 .m = _SUNXI_CCU_DIV(8, 5),
740 .p = _SUNXI_CCU_DIV(20, 2),
741 .mux = {
742 .shift = 24,
743 .width = 4,
744 .table = clk_out_table,
745 .fixed_predivs = clk_out_predivs,
746 .n_predivs = ARRAY_SIZE(clk_out_predivs),
747 },
748 .common = {
749 .reg = 0x300,
750 .features = CCU_FEATURE_FIXED_PREDIV,
751 .hw.init = CLK_HW_INIT_PARENTS("out-a",
752 clk_out_parents,
753 &ccu_div_ops,
754 0),
755 },
756 };
757
758 static struct ccu_mp out_b_clk = {
759 .enable = BIT(31),
760 .m = _SUNXI_CCU_DIV(8, 5),
761 .p = _SUNXI_CCU_DIV(20, 2),
762 .mux = {
763 .shift = 24,
764 .width = 4,
765 .table = clk_out_table,
766 .fixed_predivs = clk_out_predivs,
767 .n_predivs = ARRAY_SIZE(clk_out_predivs),
768 },
769 .common = {
770 .reg = 0x304,
771 .features = CCU_FEATURE_FIXED_PREDIV,
772 .hw.init = CLK_HW_INIT_PARENTS("out-b",
773 clk_out_parents,
774 &ccu_div_ops,
775 0),
776 },
777 };
778
779 static struct ccu_mp out_c_clk = {
780 .enable = BIT(31),
781 .m = _SUNXI_CCU_DIV(8, 5),
782 .p = _SUNXI_CCU_DIV(20, 2),
783 .mux = {
784 .shift = 24,
785 .width = 4,
786 .table = clk_out_table,
787 .fixed_predivs = clk_out_predivs,
788 .n_predivs = ARRAY_SIZE(clk_out_predivs),
789 },
790 .common = {
791 .reg = 0x308,
792 .features = CCU_FEATURE_FIXED_PREDIV,
793 .hw.init = CLK_HW_INIT_PARENTS("out-c",
794 clk_out_parents,
795 &ccu_div_ops,
796 0),
797 },
798 };
799
800 static struct ccu_common *sun6i_a31_ccu_clks[] = {
801 &pll_cpu_clk.common,
802 &pll_audio_base_clk.common,
803 &pll_video0_clk.common,
804 &pll_ve_clk.common,
805 &pll_ddr_clk.common,
806 &pll_periph_clk.common,
807 &pll_video1_clk.common,
808 &pll_gpu_clk.common,
809 &pll_mipi_clk.common,
810 &pll9_clk.common,
811 &pll10_clk.common,
812 &cpu_clk.common,
813 &axi_clk.common,
814 &ahb1_clk.common,
815 &apb1_clk.common,
816 &apb2_clk.common,
817 &ahb1_mipidsi_clk.common,
818 &ahb1_ss_clk.common,
819 &ahb1_dma_clk.common,
820 &ahb1_mmc0_clk.common,
821 &ahb1_mmc1_clk.common,
822 &ahb1_mmc2_clk.common,
823 &ahb1_mmc3_clk.common,
824 &ahb1_nand1_clk.common,
825 &ahb1_nand0_clk.common,
826 &ahb1_sdram_clk.common,
827 &ahb1_emac_clk.common,
828 &ahb1_ts_clk.common,
829 &ahb1_hstimer_clk.common,
830 &ahb1_spi0_clk.common,
831 &ahb1_spi1_clk.common,
832 &ahb1_spi2_clk.common,
833 &ahb1_spi3_clk.common,
834 &ahb1_otg_clk.common,
835 &ahb1_ehci0_clk.common,
836 &ahb1_ehci1_clk.common,
837 &ahb1_ohci0_clk.common,
838 &ahb1_ohci1_clk.common,
839 &ahb1_ohci2_clk.common,
840 &ahb1_ve_clk.common,
841 &ahb1_lcd0_clk.common,
842 &ahb1_lcd1_clk.common,
843 &ahb1_csi_clk.common,
844 &ahb1_hdmi_clk.common,
845 &ahb1_be0_clk.common,
846 &ahb1_be1_clk.common,
847 &ahb1_fe0_clk.common,
848 &ahb1_fe1_clk.common,
849 &ahb1_mp_clk.common,
850 &ahb1_gpu_clk.common,
851 &ahb1_deu0_clk.common,
852 &ahb1_deu1_clk.common,
853 &ahb1_drc0_clk.common,
854 &ahb1_drc1_clk.common,
855 &apb1_codec_clk.common,
856 &apb1_spdif_clk.common,
857 &apb1_digital_mic_clk.common,
858 &apb1_pio_clk.common,
859 &apb1_daudio0_clk.common,
860 &apb1_daudio1_clk.common,
861 &apb2_i2c0_clk.common,
862 &apb2_i2c1_clk.common,
863 &apb2_i2c2_clk.common,
864 &apb2_i2c3_clk.common,
865 &apb2_uart0_clk.common,
866 &apb2_uart1_clk.common,
867 &apb2_uart2_clk.common,
868 &apb2_uart3_clk.common,
869 &apb2_uart4_clk.common,
870 &apb2_uart5_clk.common,
871 &nand0_clk.common,
872 &nand1_clk.common,
873 &mmc0_clk.common,
874 &mmc0_sample_clk.common,
875 &mmc0_output_clk.common,
876 &mmc1_clk.common,
877 &mmc1_sample_clk.common,
878 &mmc1_output_clk.common,
879 &mmc2_clk.common,
880 &mmc2_sample_clk.common,
881 &mmc2_output_clk.common,
882 &mmc3_clk.common,
883 &mmc3_sample_clk.common,
884 &mmc3_output_clk.common,
885 &ts_clk.common,
886 &ss_clk.common,
887 &spi0_clk.common,
888 &spi1_clk.common,
889 &spi2_clk.common,
890 &spi3_clk.common,
891 &daudio0_clk.common,
892 &daudio1_clk.common,
893 &spdif_clk.common,
894 &usb_phy0_clk.common,
895 &usb_phy1_clk.common,
896 &usb_phy2_clk.common,
897 &usb_ohci0_clk.common,
898 &usb_ohci1_clk.common,
899 &usb_ohci2_clk.common,
900 &mdfs_clk.common,
901 &sdram0_clk.common,
902 &sdram1_clk.common,
903 &dram_ve_clk.common,
904 &dram_csi_isp_clk.common,
905 &dram_ts_clk.common,
906 &dram_drc0_clk.common,
907 &dram_drc1_clk.common,
908 &dram_deu0_clk.common,
909 &dram_deu1_clk.common,
910 &dram_fe0_clk.common,
911 &dram_fe1_clk.common,
912 &dram_be0_clk.common,
913 &dram_be1_clk.common,
914 &dram_mp_clk.common,
915 &be0_clk.common,
916 &be1_clk.common,
917 &fe0_clk.common,
918 &fe1_clk.common,
919 &mp_clk.common,
920 &lcd0_ch0_clk.common,
921 &lcd1_ch0_clk.common,
922 &lcd0_ch1_clk.common,
923 &lcd1_ch1_clk.common,
924 &csi0_sclk_clk.common,
925 &csi0_mclk_clk.common,
926 &csi1_mclk_clk.common,
927 &ve_clk.common,
928 &codec_clk.common,
929 &avs_clk.common,
930 &digital_mic_clk.common,
931 &hdmi_clk.common,
932 &hdmi_ddc_clk.common,
933 &ps_clk.common,
934 &mbus0_clk.common,
935 &mbus1_clk.common,
936 &mipi_dsi_clk.common,
937 &mipi_dsi_dphy_clk.common,
938 &mipi_csi_dphy_clk.common,
939 &iep_drc0_clk.common,
940 &iep_drc1_clk.common,
941 &iep_deu0_clk.common,
942 &iep_deu1_clk.common,
943 &gpu_core_clk.common,
944 &gpu_memory_clk.common,
945 &gpu_hyd_clk.common,
946 &ats_clk.common,
947 &trace_clk.common,
948 &out_a_clk.common,
949 &out_b_clk.common,
950 &out_c_clk.common,
951 };
952
953 /* We hardcode the divider to 4 for now */
954 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
955 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
956 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
957 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
958 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
959 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
960 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
961 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
962 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
963 "pll-periph", 1, 2, 0);
964 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
965 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
966 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
967 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
968
969 static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
970 .hws = {
971 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
972 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
973 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
974 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
975 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
976 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
977 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
978 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
979 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
980 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
981 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
982 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
983 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
984 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
985 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
986 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
987 [CLK_PLL9] = &pll9_clk.common.hw,
988 [CLK_PLL10] = &pll10_clk.common.hw,
989 [CLK_CPU] = &cpu_clk.common.hw,
990 [CLK_AXI] = &axi_clk.common.hw,
991 [CLK_AHB1] = &ahb1_clk.common.hw,
992 [CLK_APB1] = &apb1_clk.common.hw,
993 [CLK_APB2] = &apb2_clk.common.hw,
994 [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
995 [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
996 [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
997 [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
998 [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
999 [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
1000 [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
1001 [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
1002 [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
1003 [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
1004 [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
1005 [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
1006 [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
1007 [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
1008 [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
1009 [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
1010 [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
1011 [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
1012 [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
1013 [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
1014 [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
1015 [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
1016 [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
1017 [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
1018 [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
1019 [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
1020 [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
1021 [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
1022 [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
1023 [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
1024 [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
1025 [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
1026 [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
1027 [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
1028 [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
1029 [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
1030 [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
1031 [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
1032 [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
1033 [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
1034 [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
1035 [CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
1036 [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
1037 [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
1038 [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
1039 [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
1040 [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
1041 [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
1042 [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
1043 [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
1044 [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
1045 [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
1046 [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
1047 [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
1048 [CLK_NAND0] = &nand0_clk.common.hw,
1049 [CLK_NAND1] = &nand1_clk.common.hw,
1050 [CLK_MMC0] = &mmc0_clk.common.hw,
1051 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1052 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1053 [CLK_MMC1] = &mmc1_clk.common.hw,
1054 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1055 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1056 [CLK_MMC2] = &mmc2_clk.common.hw,
1057 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1058 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1059 [CLK_MMC3] = &mmc3_clk.common.hw,
1060 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1061 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1062 [CLK_TS] = &ts_clk.common.hw,
1063 [CLK_SS] = &ss_clk.common.hw,
1064 [CLK_SPI0] = &spi0_clk.common.hw,
1065 [CLK_SPI1] = &spi1_clk.common.hw,
1066 [CLK_SPI2] = &spi2_clk.common.hw,
1067 [CLK_SPI3] = &spi3_clk.common.hw,
1068 [CLK_DAUDIO0] = &daudio0_clk.common.hw,
1069 [CLK_DAUDIO1] = &daudio1_clk.common.hw,
1070 [CLK_SPDIF] = &spdif_clk.common.hw,
1071 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1072 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1073 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1074 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1075 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1076 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1077 [CLK_MDFS] = &mdfs_clk.common.hw,
1078 [CLK_SDRAM0] = &sdram0_clk.common.hw,
1079 [CLK_SDRAM1] = &sdram1_clk.common.hw,
1080 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1081 [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
1082 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1083 [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
1084 [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
1085 [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
1086 [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
1087 [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
1088 [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
1089 [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
1090 [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
1091 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1092 [CLK_BE0] = &be0_clk.common.hw,
1093 [CLK_BE1] = &be1_clk.common.hw,
1094 [CLK_FE0] = &fe0_clk.common.hw,
1095 [CLK_FE1] = &fe1_clk.common.hw,
1096 [CLK_MP] = &mp_clk.common.hw,
1097 [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
1098 [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
1099 [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
1100 [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
1101 [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
1102 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1103 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1104 [CLK_VE] = &ve_clk.common.hw,
1105 [CLK_CODEC] = &codec_clk.common.hw,
1106 [CLK_AVS] = &avs_clk.common.hw,
1107 [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
1108 [CLK_HDMI] = &hdmi_clk.common.hw,
1109 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
1110 [CLK_PS] = &ps_clk.common.hw,
1111 [CLK_MBUS0] = &mbus0_clk.common.hw,
1112 [CLK_MBUS1] = &mbus1_clk.common.hw,
1113 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1114 [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
1115 [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
1116 [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
1117 [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
1118 [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
1119 [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
1120 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
1121 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
1122 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
1123 [CLK_ATS] = &ats_clk.common.hw,
1124 [CLK_TRACE] = &trace_clk.common.hw,
1125 [CLK_OUT_A] = &out_a_clk.common.hw,
1126 [CLK_OUT_B] = &out_b_clk.common.hw,
1127 [CLK_OUT_C] = &out_c_clk.common.hw,
1128 },
1129 .num = CLK_NUMBER,
1130 };
1131
1132 static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1133 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1134 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1135 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1136
1137 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1138 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1139 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1140 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1141 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1142 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1143 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1144 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1145 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1146 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1147 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1148 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1149 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1150 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1151 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1152 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1153 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1154 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1155 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1156 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1157 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1158 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1159 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1160
1161 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1162 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1163 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1164 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1165 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1166 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1167 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1168 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1169 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1170 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1171 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1172 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1173 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1174 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1175 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1176 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1177
1178 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1179 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1180 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1181 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1182 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1183
1184 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1185 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1186 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1187 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1188 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1189 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1190 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1191 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1192 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1193 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1194 };
1195
1196 static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1197 .ccu_clks = sun6i_a31_ccu_clks,
1198 .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
1199
1200 .hw_clks = &sun6i_a31_hw_clks,
1201
1202 .resets = sun6i_a31_ccu_resets,
1203 .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
1204 };
1205
1206 static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1207 .common = &cpu_clk.common,
1208 .cm = &cpu_clk.mux,
1209 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1210 .bypass_index = 1, /* index of 24 MHz oscillator */
1211 };
1212
1213 static void __init sun6i_a31_ccu_setup(struct device_node *node)
1214 {
1215 void __iomem *reg;
1216 u32 val;
1217
1218 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1219 if (IS_ERR(reg)) {
1220 pr_err("%s: Could not map the clock registers\n",
1221 of_node_full_name(node));
1222 return;
1223 }
1224
1225 /* Force the PLL-Audio-1x divider to 4 */
1226 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1227 val &= ~GENMASK(19, 16);
1228 writel(val | (3 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1229
1230 /* Force PLL-MIPI to MIPI mode */
1231 val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1232 val &= BIT(16);
1233 writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1234
1235 /* Force AHB1 to PLL6 / 3 */
1236 val = readl(reg + SUN6I_A31_AHB1_REG);
1237 /* set PLL6 pre-div = 3 */
1238 val &= ~GENMASK(7, 6);
1239 val |= 0x2 << 6;
1240 /* select PLL6 / pre-div */
1241 val &= ~GENMASK(13, 12);
1242 val |= 0x3 << 12;
1243 writel(val, reg + SUN6I_A31_AHB1_REG);
1244
1245 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1246
1247 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1248 &sun6i_a31_cpu_nb);
1249 }
1250 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1251 sun6i_a31_ccu_setup);
Linux with added FPC-III support