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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun8i-a23.c
blob5c6d37bdf247cfef1b4da1bcf185d1b56082f036
1 /*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16
17 #include "ccu_common.h"
18 #include "ccu_reset.h"
19
20 #include "ccu_div.h"
21 #include "ccu_gate.h"
22 #include "ccu_mp.h"
23 #include "ccu_mult.h"
24 #include "ccu_nk.h"
25 #include "ccu_nkm.h"
26 #include "ccu_nkmp.h"
27 #include "ccu_nm.h"
28 #include "ccu_phase.h"
29
30 #include "ccu-sun8i-a23-a33.h"
31
32
33 static struct ccu_nkmp pll_cpux_clk = {
34 .enable = BIT(31),
35 .lock = BIT(28),
36
37 .n = _SUNXI_CCU_MULT(8, 5),
38 .k = _SUNXI_CCU_MULT(4, 2),
39 .m = _SUNXI_CCU_DIV(0, 2),
40 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
41
42 .common = {
43 .reg = 0x000,
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
45 &ccu_nkmp_ops,
46 0),
47 },
48 };
49
50 /*
51 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
52 * the base (2x, 4x and 8x), and one variable divider (the one true
53 * pll audio).
54 *
55 * We don't have any need for the variable divider for now, so we just
56 * hardcode it to match with the clock names
57 */
58 #define SUN8I_A23_PLL_AUDIO_REG 0x008
59
60 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
61 "osc24M", 0x008,
62 8, 7, /* N */
63 0, 5, /* M */
64 BIT(31), /* gate */
65 BIT(28), /* lock */
66 CLK_SET_RATE_UNGATE);
67
68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
69 "osc24M", 0x010,
70 8, 7, /* N */
71 0, 4, /* M */
72 BIT(24), /* frac enable */
73 BIT(25), /* frac select */
74 270000000, /* frac rate 0 */
75 297000000, /* frac rate 1 */
76 BIT(31), /* gate */
77 BIT(28), /* lock */
78 CLK_SET_RATE_UNGATE);
79
80 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
81 "osc24M", 0x018,
82 8, 7, /* N */
83 0, 4, /* M */
84 BIT(24), /* frac enable */
85 BIT(25), /* frac select */
86 270000000, /* frac rate 0 */
87 297000000, /* frac rate 1 */
88 BIT(31), /* gate */
89 BIT(28), /* lock */
90 CLK_SET_RATE_UNGATE);
91
92 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
93 "osc24M", 0x020,
94 8, 5, /* N */
95 4, 2, /* K */
96 0, 2, /* M */
97 BIT(31), /* gate */
98 BIT(28), /* lock */
99 0);
100
101 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
102 "osc24M", 0x028,
103 8, 5, /* N */
104 4, 2, /* K */
105 BIT(31), /* gate */
106 BIT(28), /* lock */
107 2, /* post-div */
108 CLK_SET_RATE_UNGATE);
109
110 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
111 "osc24M", 0x038,
112 8, 7, /* N */
113 0, 4, /* M */
114 BIT(24), /* frac enable */
115 BIT(25), /* frac select */
116 270000000, /* frac rate 0 */
117 297000000, /* frac rate 1 */
118 BIT(31), /* gate */
119 BIT(28), /* lock */
120 CLK_SET_RATE_UNGATE);
121
122 /*
123 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
124 *
125 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
126 * integer / fractional clock with switchable multipliers and dividers.
127 * This is not supported here. We hardcode the PLL to MIPI mode.
128 */
129 #define SUN8I_A23_PLL_MIPI_REG 0x040
130 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
131 "pll-video", 0x040,
132 8, 4, /* N */
133 4, 2, /* K */
134 0, 4, /* M */
135 BIT(31), /* gate */
136 BIT(28), /* lock */
137 CLK_SET_RATE_UNGATE);
138
139 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
140 "osc24M", 0x044,
141 8, 7, /* N */
142 0, 4, /* M */
143 BIT(24), /* frac enable */
144 BIT(25), /* frac select */
145 270000000, /* frac rate 0 */
146 297000000, /* frac rate 1 */
147 BIT(31), /* gate */
148 BIT(28), /* lock */
149 CLK_SET_RATE_UNGATE);
150
151 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
152 "osc24M", 0x048,
153 8, 7, /* N */
154 0, 4, /* M */
155 BIT(24), /* frac enable */
156 BIT(25), /* frac select */
157 270000000, /* frac rate 0 */
158 297000000, /* frac rate 1 */
159 BIT(31), /* gate */
160 BIT(28), /* lock */
161 CLK_SET_RATE_UNGATE);
162
163 static const char * const cpux_parents[] = { "osc32k", "osc24M",
164 "pll-cpux" , "pll-cpux" };
165 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
166 0x050, 16, 2, CLK_IS_CRITICAL);
167
168 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
169
170 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
171 "axi" , "pll-periph" };
172 static struct ccu_div ahb1_clk = {
173 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
174
175 .mux = {
176 .shift = 12,
177 .width = 2,
178
179 .variable_prediv = {
180 .index = 3,
181 .shift = 6,
182 .width = 2,
183 },
184 },
185
186 .common = {
187 .reg = 0x054,
188 .features = CCU_FEATURE_VARIABLE_PREDIV,
189 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
190 ahb1_parents,
191 &ccu_div_ops,
192 0),
193 },
194 };
195
196 static struct clk_div_table apb1_div_table[] = {
197 { .val = 0, .div = 2 },
198 { .val = 1, .div = 2 },
199 { .val = 2, .div = 4 },
200 { .val = 3, .div = 8 },
201 { /* Sentinel */ },
202 };
203 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
204 0x054, 8, 2, apb1_div_table, 0);
205
206 static const char * const apb2_parents[] = { "osc32k", "osc24M",
207 "pll-periph" , "pll-periph" };
208 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
209 0, 5, /* M */
210 16, 2, /* P */
211 24, 2, /* mux */
212 0);
213
214 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
215 0x060, BIT(1), 0);
216 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
217 0x060, BIT(6), 0);
218 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
219 0x060, BIT(8), 0);
220 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
221 0x060, BIT(9), 0);
222 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
223 0x060, BIT(10), 0);
224 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
225 0x060, BIT(13), 0);
226 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
227 0x060, BIT(14), 0);
228 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
229 0x060, BIT(19), 0);
230 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
231 0x060, BIT(20), 0);
232 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
233 0x060, BIT(21), 0);
234 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
235 0x060, BIT(24), 0);
236 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
237 0x060, BIT(26), 0);
238 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
239 0x060, BIT(29), 0);
240
241 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
242 0x064, BIT(0), 0);
243 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
244 0x064, BIT(4), 0);
245 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
246 0x064, BIT(8), 0);
247 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
248 0x064, BIT(12), 0);
249 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
250 0x064, BIT(14), 0);
251 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
252 0x064, BIT(20), 0);
253 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
254 0x064, BIT(21), 0);
255 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
256 0x064, BIT(22), 0);
257 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
258 0x064, BIT(25), 0);
259
260 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
261 0x068, BIT(0), 0);
262 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
263 0x068, BIT(5), 0);
264 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
265 0x068, BIT(12), 0);
266 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
267 0x068, BIT(13), 0);
268
269 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
270 0x06c, BIT(0), 0);
271 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
272 0x06c, BIT(1), 0);
273 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
274 0x06c, BIT(2), 0);
275 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
276 0x06c, BIT(16), 0);
277 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
278 0x06c, BIT(17), 0);
279 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
280 0x06c, BIT(18), 0);
281 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
282 0x06c, BIT(19), 0);
283 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
284 0x06c, BIT(20), 0);
285
286 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
287 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
288 0, 4, /* M */
289 16, 2, /* P */
290 24, 2, /* mux */
291 BIT(31), /* gate */
292 0);
293
294 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
295 0, 4, /* M */
296 16, 2, /* P */
297 24, 2, /* mux */
298 BIT(31), /* gate */
299 0);
300
301 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
302 0x088, 20, 3, 0);
303 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
304 0x088, 8, 3, 0);
305
306 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
307 0, 4, /* M */
308 16, 2, /* P */
309 24, 2, /* mux */
310 BIT(31), /* gate */
311 0);
312
313 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
314 0x08c, 20, 3, 0);
315 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
316 0x08c, 8, 3, 0);
317
318 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
319 0, 4, /* M */
320 16, 2, /* P */
321 24, 2, /* mux */
322 BIT(31), /* gate */
323 0);
324
325 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
326 0x090, 20, 3, 0);
327 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
328 0x090, 8, 3, 0);
329
330 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
331 0, 4, /* M */
332 16, 2, /* P */
333 24, 2, /* mux */
334 BIT(31), /* gate */
335 0);
336
337 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
338 0, 4, /* M */
339 16, 2, /* P */
340 24, 2, /* mux */
341 BIT(31), /* gate */
342 0);
343
344 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
345 "pll-audio-2x", "pll-audio" };
346 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
347 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
348
349 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
350 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
351
352 /* TODO: the parent for most of the USB clocks is not known */
353 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
354 0x0cc, BIT(8), 0);
355 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
356 0x0cc, BIT(9), 0);
357 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
358 0x0cc, BIT(10), 0);
359 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
360 0x0cc, BIT(11), 0);
361 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
362 0x0cc, BIT(16), 0);
363
364 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
365 0x100, BIT(0), 0);
366 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
367 0x100, BIT(1), 0);
368 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
369 0x100, BIT(16), 0);
370 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
371 0x100, BIT(24), 0);
372 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
373 0x100, BIT(26), 0);
374
375 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
376 "pll-gpu", "pll-de" };
377 static const u8 de_table[] = { 0, 2, 3, 5 };
378 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
379 de_parents, de_table,
380 0x104, 0, 4, 24, 3, BIT(31), 0);
381
382 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
383 de_parents, de_table,
384 0x10c, 0, 4, 24, 3, BIT(31), 0);
385
386 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
387 "pll-mipi" };
388 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
389 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
390 lcd_ch0_parents, lcd_ch0_table,
391 0x118, 24, 3, BIT(31),
392 CLK_SET_RATE_PARENT);
393
394 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
395 static const u8 lcd_ch1_table[] = { 0, 2 };
396 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
397 lcd_ch1_parents, lcd_ch1_table,
398 0x12c, 0, 4, 24, 2, BIT(31), 0);
399
400 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
401 "pll-mipi", "pll-ve" };
402 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
403 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
404 csi_sclk_parents, csi_sclk_table,
405 0x134, 16, 4, 24, 3, BIT(31), 0);
406
407 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
408 "osc24M" };
409 static const u8 csi_mclk_table[] = { 0, 3, 5 };
410 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
411 csi_mclk_parents, csi_mclk_table,
412 0x134, 0, 5, 8, 3, BIT(15), 0);
413
414 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
415 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
416
417 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
418 0x140, BIT(31), CLK_SET_RATE_PARENT);
419 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
420 0x144, BIT(31), 0);
421
422 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
423 "pll-ddr" };
424 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
425 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
426
427 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
428 static const u8 dsi_sclk_table[] = { 0, 2 };
429 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
430 dsi_sclk_parents, dsi_sclk_table,
431 0x168, 16, 4, 24, 2, BIT(31), 0);
432
433 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
434 static const u8 dsi_dphy_table[] = { 0, 2 };
435 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
436 dsi_dphy_parents, dsi_dphy_table,
437 0x168, 0, 4, 8, 2, BIT(15), 0);
438
439 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
440 de_parents, de_table,
441 0x180, 0, 4, 24, 3, BIT(31), 0);
442
443 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
444 0x1a0, 0, 3, BIT(31), 0);
445
446 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
447 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
448 0x1b0, 0, 3, 24, 2, BIT(31), 0);
449
450 static struct ccu_common *sun8i_a23_ccu_clks[] = {
451 &pll_cpux_clk.common,
452 &pll_audio_base_clk.common,
453 &pll_video_clk.common,
454 &pll_ve_clk.common,
455 &pll_ddr_clk.common,
456 &pll_periph_clk.common,
457 &pll_gpu_clk.common,
458 &pll_mipi_clk.common,
459 &pll_hsic_clk.common,
460 &pll_de_clk.common,
461 &cpux_clk.common,
462 &axi_clk.common,
463 &ahb1_clk.common,
464 &apb1_clk.common,
465 &apb2_clk.common,
466 &bus_mipi_dsi_clk.common,
467 &bus_dma_clk.common,
468 &bus_mmc0_clk.common,
469 &bus_mmc1_clk.common,
470 &bus_mmc2_clk.common,
471 &bus_nand_clk.common,
472 &bus_dram_clk.common,
473 &bus_hstimer_clk.common,
474 &bus_spi0_clk.common,
475 &bus_spi1_clk.common,
476 &bus_otg_clk.common,
477 &bus_ehci_clk.common,
478 &bus_ohci_clk.common,
479 &bus_ve_clk.common,
480 &bus_lcd_clk.common,
481 &bus_csi_clk.common,
482 &bus_de_fe_clk.common,
483 &bus_de_be_clk.common,
484 &bus_gpu_clk.common,
485 &bus_msgbox_clk.common,
486 &bus_spinlock_clk.common,
487 &bus_drc_clk.common,
488 &bus_codec_clk.common,
489 &bus_pio_clk.common,
490 &bus_i2s0_clk.common,
491 &bus_i2s1_clk.common,
492 &bus_i2c0_clk.common,
493 &bus_i2c1_clk.common,
494 &bus_i2c2_clk.common,
495 &bus_uart0_clk.common,
496 &bus_uart1_clk.common,
497 &bus_uart2_clk.common,
498 &bus_uart3_clk.common,
499 &bus_uart4_clk.common,
500 &nand_clk.common,
501 &mmc0_clk.common,
502 &mmc0_sample_clk.common,
503 &mmc0_output_clk.common,
504 &mmc1_clk.common,
505 &mmc1_sample_clk.common,
506 &mmc1_output_clk.common,
507 &mmc2_clk.common,
508 &mmc2_sample_clk.common,
509 &mmc2_output_clk.common,
510 &spi0_clk.common,
511 &spi1_clk.common,
512 &i2s0_clk.common,
513 &i2s1_clk.common,
514 &usb_phy0_clk.common,
515 &usb_phy1_clk.common,
516 &usb_hsic_clk.common,
517 &usb_hsic_12M_clk.common,
518 &usb_ohci_clk.common,
519 &dram_ve_clk.common,
520 &dram_csi_clk.common,
521 &dram_drc_clk.common,
522 &dram_de_fe_clk.common,
523 &dram_de_be_clk.common,
524 &de_be_clk.common,
525 &de_fe_clk.common,
526 &lcd_ch0_clk.common,
527 &lcd_ch1_clk.common,
528 &csi_sclk_clk.common,
529 &csi_mclk_clk.common,
530 &ve_clk.common,
531 &ac_dig_clk.common,
532 &avs_clk.common,
533 &mbus_clk.common,
534 &dsi_sclk_clk.common,
535 &dsi_dphy_clk.common,
536 &drc_clk.common,
537 &gpu_clk.common,
538 &ats_clk.common,
539 };
540
541 /* We hardcode the divider to 4 for now */
542 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
543 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
544 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
545 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
546 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
547 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
548 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
549 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
550 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
551 "pll-periph", 1, 2, 0);
552 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
553 "pll-video", 1, 2, 0);
554
555 static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
556 .hws = {
557 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
558 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
559 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
560 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
561 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
562 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
563 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
564 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
565 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
566 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
567 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
568 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
569 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
570 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
571 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
572 [CLK_PLL_DE] = &pll_de_clk.common.hw,
573 [CLK_CPUX] = &cpux_clk.common.hw,
574 [CLK_AXI] = &axi_clk.common.hw,
575 [CLK_AHB1] = &ahb1_clk.common.hw,
576 [CLK_APB1] = &apb1_clk.common.hw,
577 [CLK_APB2] = &apb2_clk.common.hw,
578 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
579 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
580 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
581 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
582 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
583 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
584 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
585 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
586 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
587 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
588 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
589 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
590 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
591 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
592 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
593 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
594 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
595 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
596 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
597 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
598 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
599 [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
600 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
601 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
602 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
603 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
604 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
605 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
606 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
607 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
608 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
609 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
610 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
611 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
612 [CLK_NAND] = &nand_clk.common.hw,
613 [CLK_MMC0] = &mmc0_clk.common.hw,
614 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
615 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
616 [CLK_MMC1] = &mmc1_clk.common.hw,
617 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
618 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
619 [CLK_MMC2] = &mmc2_clk.common.hw,
620 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
621 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
622 [CLK_SPI0] = &spi0_clk.common.hw,
623 [CLK_SPI1] = &spi1_clk.common.hw,
624 [CLK_I2S0] = &i2s0_clk.common.hw,
625 [CLK_I2S1] = &i2s1_clk.common.hw,
626 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
627 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
628 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
629 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
630 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
631 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
632 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
633 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
634 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
635 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
636 [CLK_DE_BE] = &de_be_clk.common.hw,
637 [CLK_DE_FE] = &de_fe_clk.common.hw,
638 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
639 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
640 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
641 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
642 [CLK_VE] = &ve_clk.common.hw,
643 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
644 [CLK_AVS] = &avs_clk.common.hw,
645 [CLK_MBUS] = &mbus_clk.common.hw,
646 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
647 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
648 [CLK_DRC] = &drc_clk.common.hw,
649 [CLK_GPU] = &gpu_clk.common.hw,
650 [CLK_ATS] = &ats_clk.common.hw,
651 },
652 .num = CLK_NUMBER,
653 };
654
655 static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
656 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
657 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
658 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
659
660 [RST_MBUS] = { 0x0fc, BIT(31) },
661
662 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
663 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
664 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
665 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
666 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
667 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
668 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
669 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
670 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
671 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
672 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
673 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
674 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
675
676 [RST_BUS_VE] = { 0x2c4, BIT(0) },
677 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
678 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
679 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
680 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
681 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
682 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
683 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
684 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
685
686 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
687
688 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
689 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
690 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
691
692 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
693 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
694 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
695 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
696 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
697 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
698 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
699 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
700 };
701
702 static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
703 .ccu_clks = sun8i_a23_ccu_clks,
704 .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks),
705
706 .hw_clks = &sun8i_a23_hw_clks,
707
708 .resets = sun8i_a23_ccu_resets,
709 .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
710 };
711
712 static void __init sun8i_a23_ccu_setup(struct device_node *node)
713 {
714 void __iomem *reg;
715 u32 val;
716
717 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
718 if (IS_ERR(reg)) {
719 pr_err("%s: Could not map the clock registers\n",
720 of_node_full_name(node));
721 return;
722 }
723
724 /* Force the PLL-Audio-1x divider to 4 */
725 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
726 val &= ~GENMASK(19, 16);
727 writel(val | (3 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
728
729 /* Force PLL-MIPI to MIPI mode */
730 val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
731 val &= ~BIT(16);
732 writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
733
734 sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
735 }
736 CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
737 sun8i_a23_ccu_setup);
Linux with added FPC-III support