sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun8i-h3.h
blob78be712c74871948908fb6999412c805562f5451
1 /*
2 * Copyright 2016 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef _CCU_SUN8I_H3_H_
18 #define _CCU_SUN8I_H3_H_
20 #include <dt-bindings/clock/sun8i-h3-ccu.h>
21 #include <dt-bindings/reset/sun8i-h3-ccu.h>
23 #define CLK_PLL_CPUX 0
24 #define CLK_PLL_AUDIO_BASE 1
25 #define CLK_PLL_AUDIO 2
26 #define CLK_PLL_AUDIO_2X 3
27 #define CLK_PLL_AUDIO_4X 4
28 #define CLK_PLL_AUDIO_8X 5
29 #define CLK_PLL_VIDEO 6
30 #define CLK_PLL_VE 7
31 #define CLK_PLL_DDR 8
32 #define CLK_PLL_PERIPH0 9
33 #define CLK_PLL_PERIPH0_2X 10
34 #define CLK_PLL_GPU 11
35 #define CLK_PLL_PERIPH1 12
36 #define CLK_PLL_DE 13
38 /* The CPUX clock is exported */
40 #define CLK_AXI 15
41 #define CLK_AHB1 16
42 #define CLK_APB1 17
43 #define CLK_APB2 18
44 #define CLK_AHB2 19
46 /* All the bus gates are exported */
48 /* The first bunch of module clocks are exported */
50 #define CLK_DRAM 96
52 /* All the DRAM gates are exported */
54 /* Some more module clocks are exported */
56 #define CLK_MBUS 113
58 /* And the GPU module clock is exported */
60 #define CLK_NUMBER (CLK_GPU + 1)
62 #endif /* _CCU_SUN8I_H3_H_ */