drivers/clk/ti/clk-3xxx.c

   1 /*
   2  * OMAP3 Clock init
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc
   5  *     Tero Kristo (t-kristo@ti.com)
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/clk.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/clk/ti.h>
  22
  23 #include "clock.h"
  24
  25 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT                   1
  26 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT              5
  27 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT                   8
  28
  29 #define OMAP34XX_CM_IDLEST_VAL                          1
  30
  31 /*
  32  * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
  33  * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
  34  * at an offset of 4 from ICK enable bit.
  35  */
  36 #define AM35XX_IPSS_ICK_MASK                    0xF
  37 #define AM35XX_IPSS_ICK_EN_ACK_OFFSET           0x4
  38 #define AM35XX_IPSS_ICK_FCK_OFFSET              0x8
  39 #define AM35XX_IPSS_CLK_IDLEST_VAL              0
  40
  41 #define AM35XX_ST_IPSS_SHIFT                    5
  42
  43 /**
  44  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  45  * @clk: struct clk * being enabled
  46  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  47  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  48  * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  49  *
  50  * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
  51  * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
  52  * @idlest_reg and @idlest_bit.  No return value.
  53  */
  54 static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
  55                                             void __iomem **idlest_reg,
  56                                             u8 *idlest_bit,
  57                                             u8 *idlest_val)
  58 {
  59         u32 r;
  60
  61         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  62         *idlest_reg = (__force void __iomem *)r;
  63         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
  64         *idlest_val = OMAP34XX_CM_IDLEST_VAL;
  65 }
  66
  67 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
  68         .allow_idle     = omap2_clkt_iclk_allow_idle,
  69         .deny_idle      = omap2_clkt_iclk_deny_idle,
  70         .find_idlest    = omap3430es2_clk_ssi_find_idlest,
  71         .find_companion = omap2_clk_dflt_find_companion,
  72 };
  73
  74 /**
  75  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  76  * @clk: struct clk * being enabled
  77  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  78  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  79  * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  80  *
  81  * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
  82  * target IDLEST bits.  For our purposes, we are concerned with the
  83  * target IDLEST bits, which exist at a different bit position than
  84  * the *CLKEN bit position for these modules (DSS and USBHOST) (The
  85  * default find_idlest code assumes that they are at the same
  86  * position.)  No return value.
  87  */
  88 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
  89                                                     void __iomem **idlest_reg,
  90                                                     u8 *idlest_bit,
  91                                                     u8 *idlest_val)
  92 {
  93         u32 r;
  94
  95         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  96         *idlest_reg = (__force void __iomem *)r;
  97         /* USBHOST_IDLE has same shift */
  98         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
  99         *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 100 }
 101
 102 const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
 103         .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
 104         .find_companion = omap2_clk_dflt_find_companion,
 105 };
 106
 107 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
 108         .allow_idle     = omap2_clkt_iclk_allow_idle,
 109         .deny_idle      = omap2_clkt_iclk_deny_idle,
 110         .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
 111         .find_companion = omap2_clk_dflt_find_companion,
 112 };
 113
 114 /**
 115  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
 116  * @clk: struct clk * being enabled
 117  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 118  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 119  * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
 120  *
 121  * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
 122  * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 123  * @idlest_reg and @idlest_bit.  No return value.
 124  */
 125 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
 126                                                  void __iomem **idlest_reg,
 127                                                  u8 *idlest_bit,
 128                                                  u8 *idlest_val)
 129 {
 130         u32 r;
 131
 132         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 133         *idlest_reg = (__force void __iomem *)r;
 134         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
 135         *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 136 }
 137
 138 const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
 139         .allow_idle     = omap2_clkt_iclk_allow_idle,
 140         .deny_idle      = omap2_clkt_iclk_deny_idle,
 141         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
 142         .find_companion = omap2_clk_dflt_find_companion,
 143 };
 144
 145 /**
 146  * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
 147  * @clk: struct clk * being enabled
 148  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 149  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 150  * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
 151  *
 152  * The interface clocks on AM35xx IPSS reflects the clock idle status
 153  * in the enable register itsel at a bit offset of 4 from the enable
 154  * bit. A value of 1 indicates that clock is enabled.
 155  */
 156 static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
 157                                    void __iomem **idlest_reg,
 158                                    u8 *idlest_bit,
 159                                    u8 *idlest_val)
 160 {
 161         *idlest_reg = (__force void __iomem *)(clk->enable_reg);
 162         *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
 163         *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
 164 }
 165
 166 /**
 167  * am35xx_clk_find_companion - find companion clock to @clk
 168  * @clk: struct clk * to find the companion clock of
 169  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
 170  * @other_bit: u8 ** to return the companion clock bit shift in
 171  *
 172  * Some clocks don't have companion clocks.  For example, modules with
 173  * only an interface clock (such as HECC) don't have a companion
 174  * clock.  Right now, this code relies on the hardware exporting a bit
 175  * in the correct companion register that indicates that the
 176  * nonexistent 'companion clock' is active.  Future patches will
 177  * associate this type of code with per-module data structures to
 178  * avoid this issue, and remove the casts.  No return value.
 179  */
 180 static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
 181                                       void __iomem **other_reg,
 182                                       u8 *other_bit)
 183 {
 184         *other_reg = (__force void __iomem *)(clk->enable_reg);
 185         if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
 186                 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
 187         else
 188         *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
 189 }
 190
 191 const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
 192         .find_idlest    = am35xx_clk_find_idlest,
 193         .find_companion = am35xx_clk_find_companion,
 194 };
 195
 196 /**
 197  * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
 198  * @clk: struct clk * being enabled
 199  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 200  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 201  * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
 202  *
 203  * The IPSS target CM_IDLEST bit is at a different shift from the
 204  * CM_{I,F}CLKEN bit.  Pass back the correct info via @idlest_reg
 205  * and @idlest_bit.  No return value.
 206  */
 207 static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
 208                                         void __iomem **idlest_reg,
 209                                         u8 *idlest_bit,
 210                                         u8 *idlest_val)
 211 {
 212         u32 r;
 213
 214         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 215         *idlest_reg = (__force void __iomem *)r;
 216         *idlest_bit = AM35XX_ST_IPSS_SHIFT;
 217         *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 218 }
 219
 220 const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
 221         .allow_idle     = omap2_clkt_iclk_allow_idle,
 222         .deny_idle      = omap2_clkt_iclk_deny_idle,
 223         .find_idlest    = am35xx_clk_ipss_find_idlest,
 224         .find_companion = omap2_clk_dflt_find_companion,
 225 };
 226
 227 static struct ti_dt_clk omap3xxx_clks[] = {
 228         DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
 229         DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
 230         DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
 231         DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
 232         DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
 233         DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
 234         DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
 235         DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
 236         DT_CLK("twl", "fck", "osc_sys_ck"),
 237         DT_CLK(NULL, "sys_ck", "sys_ck"),
 238         DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
 239         DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
 240         DT_CLK(NULL, "sys_altclk", "sys_altclk"),
 241         DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
 242         DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
 243         DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
 244         DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
 245         DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
 246         DT_CLK(NULL, "core_ck", "core_ck"),
 247         DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
 248         DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
 249         DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
 250         DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
 251         DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
 252         DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
 253         DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
 254         DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
 255         DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
 256         DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
 257         DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
 258         DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
 259         DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
 260         DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
 261         DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
 262         DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
 263         DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
 264         DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
 265         DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
 266         DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
 267         DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
 268         DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
 269         DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
 270         DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
 271         DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
 272         DT_CLK(NULL, "corex2_fck", "corex2_fck"),
 273         DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
 274         DT_CLK(NULL, "mpu_ck", "mpu_ck"),
 275         DT_CLK(NULL, "arm_fck", "arm_fck"),
 276         DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
 277         DT_CLK(NULL, "l3_ick", "l3_ick"),
 278         DT_CLK(NULL, "l4_ick", "l4_ick"),
 279         DT_CLK(NULL, "rm_ick", "rm_ick"),
 280         DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
 281         DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
 282         DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
 283         DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
 284         DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
 285         DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
 286         DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
 287         DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
 288         DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
 289         DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
 290         DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
 291         DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
 292         DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
 293         DT_CLK(NULL, "uart2_fck", "uart2_fck"),
 294         DT_CLK(NULL, "uart1_fck", "uart1_fck"),
 295         DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
 296         DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
 297         DT_CLK(NULL, "hdq_fck", "hdq_fck"),
 298         DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
 299         DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
 300         DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
 301         DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
 302         DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
 303         DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
 304         DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
 305         DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
 306         DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
 307         DT_CLK(NULL, "hdq_ick", "hdq_ick"),
 308         DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
 309         DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
 310         DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
 311         DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
 312         DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
 313         DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
 314         DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
 315         DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
 316         DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
 317         DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
 318         DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
 319         DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
 320         DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
 321         DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
 322         DT_CLK(NULL, "uart2_ick", "uart2_ick"),
 323         DT_CLK(NULL, "uart1_ick", "uart1_ick"),
 324         DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
 325         DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
 326         DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
 327         DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
 328         DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
 329         DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
 330         DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
 331         DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
 332         DT_CLK(NULL, "aes2_ick", "aes2_ick"),
 333         DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
 334         DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
 335         DT_CLK(NULL, "sha12_ick", "sha12_ick"),
 336         DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
 337         DT_CLK("omap_wdt", "ick", "wdt2_ick"),
 338         DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
 339         DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
 340         DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
 341         DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
 342         DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
 343         DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
 344         DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
 345         DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
 346         DT_CLK(NULL, "uart3_fck", "uart3_fck"),
 347         DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
 348         DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
 349         DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
 350         DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
 351         DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
 352         DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
 353         DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
 354         DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
 355         DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
 356         DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
 357         DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
 358         DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
 359         DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
 360         DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
 361         DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
 362         DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
 363         DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
 364         DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
 365         DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
 366         DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
 367         DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
 368         DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
 369         DT_CLK(NULL, "uart3_ick", "uart3_ick"),
 370         DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
 371         DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
 372         DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
 373         DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
 374         DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
 375         DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
 376         DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
 377         DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
 378         DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
 379         DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
 380         DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
 381         DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
 382         DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
 383         DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
 384         DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
 385         DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
 386         DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
 387         DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
 388         DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
 389         DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
 390         DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
 391         DT_CLK(NULL, "pclk_fck", "pclk_fck"),
 392         DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
 393         DT_CLK(NULL, "atclk_fck", "atclk_fck"),
 394         DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
 395         DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
 396         DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
 397         DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
 398         DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
 399         DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
 400         DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
 401         DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
 402         { .node_name = NULL },
 403 };
 404
 405 static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
 406         DT_CLK(NULL, "aes1_ick", "aes1_ick"),
 407         DT_CLK("omap_rng", "ick", "rng_ick"),
 408         DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
 409         DT_CLK(NULL, "sha11_ick", "sha11_ick"),
 410         DT_CLK(NULL, "des1_ick", "des1_ick"),
 411         DT_CLK(NULL, "cam_mclk", "cam_mclk"),
 412         DT_CLK(NULL, "cam_ick", "cam_ick"),
 413         DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
 414         DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
 415         DT_CLK(NULL, "pka_ick", "pka_ick"),
 416         DT_CLK(NULL, "icr_ick", "icr_ick"),
 417         DT_CLK("omap-aes", "ick", "aes2_ick"),
 418         DT_CLK("omap-sham", "ick", "sha12_ick"),
 419         DT_CLK(NULL, "des2_ick", "des2_ick"),
 420         DT_CLK(NULL, "mspro_ick", "mspro_ick"),
 421         DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
 422         DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
 423         DT_CLK(NULL, "sr1_fck", "sr1_fck"),
 424         DT_CLK(NULL, "sr2_fck", "sr2_fck"),
 425         DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
 426         DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
 427         DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
 428         DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
 429         DT_CLK(NULL, "iva2_ck", "iva2_ck"),
 430         DT_CLK(NULL, "modem_fck", "modem_fck"),
 431         DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
 432         DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
 433         DT_CLK(NULL, "mspro_fck", "mspro_fck"),
 434         DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
 435         DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
 436         { .node_name = NULL },
 437 };
 438
 439 static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
 440         DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
 441         DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
 442         DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
 443         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
 444         DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
 445         DT_CLK(NULL, "usim_fck", "usim_fck"),
 446         DT_CLK(NULL, "usim_ick", "usim_ick"),
 447         { .node_name = NULL },
 448 };
 449
 450 static struct ti_dt_clk omap3430es1_clks[] = {
 451         DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
 452         DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
 453         DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
 454         DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
 455         DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
 456         DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
 457         DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
 458         DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
 459         DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
 460         DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
 461         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
 462         DT_CLK(NULL, "fac_ick", "fac_ick"),
 463         DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
 464         DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
 465         DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
 466         DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
 467         DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
 468         { .node_name = NULL },
 469 };
 470
 471 static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
 472         DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
 473         DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
 474         DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
 475         DT_CLK(NULL, "sgx_fck", "sgx_fck"),
 476         DT_CLK(NULL, "sgx_ick", "sgx_ick"),
 477         DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
 478         DT_CLK(NULL, "ts_fck", "ts_fck"),
 479         DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
 480         DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
 481         DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
 482         DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
 483         DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
 484         DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
 485         DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
 486         DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
 487         DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
 488         DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
 489         DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
 490         { .node_name = NULL },
 491 };
 492
 493 static struct ti_dt_clk am35xx_clks[] = {
 494         DT_CLK(NULL, "ipss_ick", "ipss_ick"),
 495         DT_CLK(NULL, "rmii_ck", "rmii_ck"),
 496         DT_CLK(NULL, "pclk_ck", "pclk_ck"),
 497         DT_CLK(NULL, "emac_ick", "emac_ick"),
 498         DT_CLK(NULL, "emac_fck", "emac_fck"),
 499         DT_CLK("davinci_emac.0", NULL, "emac_ick"),
 500         DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
 501         DT_CLK("vpfe-capture", "master", "vpfe_ick"),
 502         DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
 503         DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
 504         DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
 505         DT_CLK(NULL, "hecc_ck", "hecc_ck"),
 506         DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
 507         DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
 508         { .node_name = NULL },
 509 };
 510
 511 static struct ti_dt_clk omap36xx_clks[] = {
 512         DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
 513         DT_CLK(NULL, "uart4_fck", "uart4_fck"),
 514         DT_CLK(NULL, "uart4_ick", "uart4_ick"),
 515         { .node_name = NULL },
 516 };
 517
 518 static const char *enable_init_clks[] = {
 519         "sdrc_ick",
 520         "gpmc_fck",
 521         "omapctrl_ick",
 522 };
 523
 524 enum {
 525         OMAP3_SOC_AM35XX,
 526         OMAP3_SOC_OMAP3430_ES1,
 527         OMAP3_SOC_OMAP3430_ES2_PLUS,
 528         OMAP3_SOC_OMAP3630,
 529 };
 530
 531 /**
 532  * omap3_clk_lock_dpll5 - locks DPLL5
 533  *
 534  * Locks DPLL5 to a pre-defined frequency. This is required for proper
 535  * operation of USB.
 536  */
 537 void __init omap3_clk_lock_dpll5(void)
 538 {
 539         struct clk *dpll5_clk;
 540         struct clk *dpll5_m2_clk;
 541
 542         /*
 543          * Errata sprz319f advisory 2.1 documents a USB host clock drift issue
 544          * that can be worked around using specially crafted dpll5 settings
 545          * with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB
 546          * host clock rate, its .set_rate handler() will detect that frequency
 547          * and use the errata settings.
 548          */
 549         dpll5_clk = clk_get(NULL, "dpll5_ck");
 550         clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8);
 551         clk_prepare_enable(dpll5_clk);
 552
 553         /* Program dpll5_m2_clk divider */
 554         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
 555         clk_prepare_enable(dpll5_m2_clk);
 556         clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST);
 557
 558         clk_disable_unprepare(dpll5_m2_clk);
 559         clk_disable_unprepare(dpll5_clk);
 560 }
 561
 562 static int __init omap3xxx_dt_clk_init(int soc_type)
 563 {
 564         if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
 565             soc_type == OMAP3_SOC_OMAP3430_ES1 ||
 566             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
 567                 ti_dt_clocks_register(omap3xxx_clks);
 568
 569         if (soc_type == OMAP3_SOC_AM35XX)
 570                 ti_dt_clocks_register(am35xx_clks);
 571
 572         if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
 573             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
 574                 ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
 575
 576         if (soc_type == OMAP3_SOC_OMAP3430_ES1)
 577                 ti_dt_clocks_register(omap3430es1_clks);
 578
 579         if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
 580             soc_type == OMAP3_SOC_OMAP3630)
 581                 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
 582
 583         if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
 584             soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
 585             soc_type == OMAP3_SOC_OMAP3630)
 586                 ti_dt_clocks_register(omap34xx_omap36xx_clks);
 587
 588         if (soc_type == OMAP3_SOC_OMAP3630)
 589                 ti_dt_clocks_register(omap36xx_clks);
 590
 591         omap2_clk_disable_autoidle_all();
 592
 593         omap2_clk_enable_init_clocks(enable_init_clks,
 594                                      ARRAY_SIZE(enable_init_clks));
 595
 596         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
 597                 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
 598                 (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
 599                 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
 600                 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
 601
 602         if (soc_type != OMAP3_SOC_OMAP3430_ES1)
 603                 omap3_clk_lock_dpll5();
 604
 605         return 0;
 606 }
 607
 608 int __init omap3430_dt_clk_init(void)
 609 {
 610         return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
 611 }
 612
 613 int __init omap3630_dt_clk_init(void)
 614 {
 615         return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
 616 }
 617
 618 int __init am35xx_dt_clk_init(void)
 619 {
 620         return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
 621 }