drivers/clk/uniphier/clk-uniphier-sys.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/stddef.h>
  17
  18 #include "clk-uniphier.h"
  19
  20 #define UNIPHIER_SLD3_SYS_CLK_SD                                        \
  21         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8),               \
  22         UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
  23
  24 #define UNIPHIER_PRO5_SYS_CLK_SD                                        \
  25         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12),              \
  26         UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
  27
  28 #define UNIPHIER_LD20_SYS_CLK_SD                                        \
  29         UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10),              \
  30         UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
  31
  32 #define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx)                               \
  33         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
  34
  35 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                               \
  36         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
  37
  38 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx)                                  \
  39         UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
  40
  41 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)                             \
  42         UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
  43
  44 const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
  45         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
  46         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),      /* 288 MHz */
  47         UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),         /* 589.824 MHz */
  48         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
  49         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
  50         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  51         UNIPHIER_SLD3_SYS_CLK_SD,
  52         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  53         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
  54         { /* sentinel */ }
  55 };
  56
  57 const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
  58         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
  59         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),      /* 288 MHz */
  60         UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),         /* 589.824 MHz */
  61         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
  62         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
  63         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  64         UNIPHIER_SLD3_SYS_CLK_SD,
  65         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  66         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* Ether, HSC, MIO */
  67         { /* sentinel */ }
  68 };
  69
  70 const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
  71         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
  72         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
  73         UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125),     /* 589.824 MHz */
  74         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
  75         UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
  76         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
  77         UNIPHIER_SLD3_SYS_CLK_SD,
  78         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  79         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* HSC, MIO, RLE */
  80         UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
  81         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
  82         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
  83         { /* sentinel */ }
  84 };
  85
  86 const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
  87         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
  88         UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
  89         UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
  90         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
  91         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  92         UNIPHIER_SLD3_SYS_CLK_SD,
  93         UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  94         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                /* Ether, HSC, MIO */
  95         { /* sentinel */ }
  96 };
  97
  98 const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
  99         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),         /* 2400 MHz */
 100         UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),       /* 2560 MHz */
 101         UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125),     /* 2949.12 MHz */
 102         UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
 103         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 104         UNIPHIER_PRO5_SYS_CLK_SD,
 105         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                        /* HSC */
 106         UNIPHIER_PRO4_SYS_CLK_GIO(12),                          /* PCIe, USB3 */
 107         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 108         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 109         { /* sentinel */ }
 110 };
 111
 112 const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 113         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),          /* 2400 MHz */
 114         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
 115         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 116         UNIPHIER_PRO5_SYS_CLK_SD,
 117         UNIPHIER_SLD3_SYS_CLK_STDMAC(8),                        /* HSC, RLE */
 118         /* GIO is always clock-enabled: no function for 0x2104 bit6 */
 119         UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 120         UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 121         /* The document mentions 0x2104 bit 18, but not functional */
 122         UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
 123         UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
 124         { /* sentinel */ }
 125 };
 126
 127 const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 128         UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5),         /* 1960 MHz */
 129         UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* 1600 MHz */
 130         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 131         UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),         /* 2000 MHz */
 132         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 133         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 134         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
 135         UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
 136         /* CPU gears */
 137         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 138         UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
 139         UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
 140         /* Note: both gear1 and gear4 are spll/4.  This is not a bug. */
 141         UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 142                              "cpll/2", "spll/4", "cpll/3", "spll/3",
 143                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 144         UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 145                              "mpll/2", "spll/4", "mpll/3", "spll/3",
 146                              "spll/4", "spll/8", "mpll/4", "mpll/8"),
 147         { /* sentinel */ }
 148 };
 149
 150 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 151         UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1),          /* ARM: 2200 MHz */
 152         UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1),         /* Mali: 1300 MHz */
 153         UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* Codec: 1600 MHz */
 154         UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 155         UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2200 MHz */
 156         UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),        /* 2520 MHz */
 157         UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 158         UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 159         UNIPHIER_LD20_SYS_CLK_SD,
 160         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
 161         /* GIO is always clock-enabled: no function for 0x210c bit5 */
 162         /*
 163          * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
 164          * We do not use bit 15 here.
 165          */
 166         UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
 167         UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
 168         UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
 169         /* CPU gears */
 170         UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 171         UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
 172         UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
 173         UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
 174                              "cpll/2", "spll/2", "cpll/3", "spll/3",
 175                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 176         UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 177                              "cpll/2", "spll/2", "cpll/3", "spll/3",
 178                              "spll/4", "spll/8", "cpll/4", "cpll/8"),
 179         UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 180                              "s2pll/2", "spll/2", "s2pll/3", "spll/3",
 181                              "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
 182         { /* sentinel */ }
 183 };