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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / zynq / clkc.c
blob88a2cab37f627b86bebe9512ffee9db720b327e1
1 /*
2 * Zynq clock controller
3 *
4 * Copyright (C) 2012 - 2013 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License v2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <linux/clk/zynq.h>
22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/string.h>
28 #include <linux/io.h>
29
30 static void __iomem *zynq_clkc_base;
31
32 #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
33 #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
34 #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
35 #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
36 #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
37 #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
38 #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
39 #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
40 #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
41 #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
42 #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
43 #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
44 #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
45 #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
46 #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
47 #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
48 #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
49 #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
50 #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
51 #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
52 #define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
53 #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
54
55 #define NUM_MIO_PINS 54
56
57 #define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
58 #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
59
60 enum zynq_clk {
61 armpll, ddrpll, iopll,
62 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
63 ddr2x, ddr3x, dci,
64 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
65 sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
66 usb0_aper, usb1_aper, gem0_aper, gem1_aper,
67 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
68 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
69 smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
70
71 static struct clk *ps_clk;
72 static struct clk *clks[clk_max];
73 static struct clk_onecell_data clk_data;
74
75 static DEFINE_SPINLOCK(armpll_lock);
76 static DEFINE_SPINLOCK(ddrpll_lock);
77 static DEFINE_SPINLOCK(iopll_lock);
78 static DEFINE_SPINLOCK(armclk_lock);
79 static DEFINE_SPINLOCK(swdtclk_lock);
80 static DEFINE_SPINLOCK(ddrclk_lock);
81 static DEFINE_SPINLOCK(dciclk_lock);
82 static DEFINE_SPINLOCK(gem0clk_lock);
83 static DEFINE_SPINLOCK(gem1clk_lock);
84 static DEFINE_SPINLOCK(canclk_lock);
85 static DEFINE_SPINLOCK(canmioclk_lock);
86 static DEFINE_SPINLOCK(dbgclk_lock);
87 static DEFINE_SPINLOCK(aperclk_lock);
88
89 static const char *const armpll_parents[] __initconst = {"armpll_int",
90 "ps_clk"};
91 static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
92 "ps_clk"};
93 static const char *const iopll_parents[] __initconst = {"iopll_int",
94 "ps_clk"};
95 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
96 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
97 static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
98 "can0_mio_mux"};
99 static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
100 "can1_mio_mux"};
101 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
102 "dummy_name"};
103
104 static const char *const dbgtrc_emio_input_names[] __initconst = {
105 "trace_emio_clk"};
106 static const char *const gem0_emio_input_names[] __initconst = {
107 "gem0_emio_clk"};
108 static const char *const gem1_emio_input_names[] __initconst = {
109 "gem1_emio_clk"};
110 static const char *const swdt_ext_clk_input_names[] __initconst = {
111 "swdt_ext_clk"};
112
113 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
114 const char *clk_name, void __iomem *fclk_ctrl_reg,
115 const char **parents, int enable)
116 {
117 struct clk *clk;
118 u32 enable_reg;
119 char *mux_name;
120 char *div0_name;
121 char *div1_name;
122 spinlock_t *fclk_lock;
123 spinlock_t *fclk_gate_lock;
124 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
125
126 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
127 if (!fclk_lock)
128 goto err;
129 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
130 if (!fclk_gate_lock)
131 goto err_fclk_gate_lock;
132 spin_lock_init(fclk_lock);
133 spin_lock_init(fclk_gate_lock);
134
135 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
136 if (!mux_name)
137 goto err_mux_name;
138 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
139 if (!div0_name)
140 goto err_div0_name;
141 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
142 if (!div1_name)
143 goto err_div1_name;
144
145 clk = clk_register_mux(NULL, mux_name, parents, 4,
146 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
147 fclk_lock);
148
149 clk = clk_register_divider(NULL, div0_name, mux_name,
150 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
151 CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
152
153 clk = clk_register_divider(NULL, div1_name, div0_name,
154 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
155 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
156 fclk_lock);
157
158 clks[fclk] = clk_register_gate(NULL, clk_name,
159 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
160 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
161 enable_reg = clk_readl(fclk_gate_reg) & 1;
162 if (enable && !enable_reg) {
163 if (clk_prepare_enable(clks[fclk]))
164 pr_warn("%s: FCLK%u enable failed\n", __func__,
165 fclk - fclk0);
166 }
167 kfree(mux_name);
168 kfree(div0_name);
169 kfree(div1_name);
170
171 return;
172
173 err_div1_name:
174 kfree(div0_name);
175 err_div0_name:
176 kfree(mux_name);
177 err_mux_name:
178 kfree(fclk_gate_lock);
179 err_fclk_gate_lock:
180 kfree(fclk_lock);
181 err:
182 clks[fclk] = ERR_PTR(-ENOMEM);
183 }
184
185 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
186 enum zynq_clk clk1, const char *clk_name0,
187 const char *clk_name1, void __iomem *clk_ctrl,
188 const char **parents, unsigned int two_gates)
189 {
190 struct clk *clk;
191 char *mux_name;
192 char *div_name;
193 spinlock_t *lock;
194
195 lock = kmalloc(sizeof(*lock), GFP_KERNEL);
196 if (!lock)
197 goto err;
198 spin_lock_init(lock);
199
200 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
201 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
202
203 clk = clk_register_mux(NULL, mux_name, parents, 4,
204 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
205
206 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
207 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
208
209 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
210 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
211 if (two_gates)
212 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
213 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
214
215 kfree(mux_name);
216 kfree(div_name);
217
218 return;
219
220 err:
221 clks[clk0] = ERR_PTR(-ENOMEM);
222 if (two_gates)
223 clks[clk1] = ERR_PTR(-ENOMEM);
224 }
225
226 static void __init zynq_clk_setup(struct device_node *np)
227 {
228 int i;
229 u32 tmp;
230 int ret;
231 struct clk *clk;
232 char *clk_name;
233 unsigned int fclk_enable = 0;
234 const char *clk_output_name[clk_max];
235 const char *cpu_parents[4];
236 const char *periph_parents[4];
237 const char *swdt_ext_clk_mux_parents[2];
238 const char *can_mio_mux_parents[NUM_MIO_PINS];
239 const char *dummy_nm = "dummy_name";
240
241 pr_info("Zynq clock init\n");
242
243 /* get clock output names from DT */
244 for (i = 0; i < clk_max; i++) {
245 if (of_property_read_string_index(np, "clock-output-names",
246 i, &clk_output_name[i])) {
247 pr_err("%s: clock output name not in DT\n", __func__);
248 BUG();
249 }
250 }
251 cpu_parents[0] = clk_output_name[armpll];
252 cpu_parents[1] = clk_output_name[armpll];
253 cpu_parents[2] = clk_output_name[ddrpll];
254 cpu_parents[3] = clk_output_name[iopll];
255 periph_parents[0] = clk_output_name[iopll];
256 periph_parents[1] = clk_output_name[iopll];
257 periph_parents[2] = clk_output_name[armpll];
258 periph_parents[3] = clk_output_name[ddrpll];
259
260 of_property_read_u32(np, "fclk-enable", &fclk_enable);
261
262 /* ps_clk */
263 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
264 if (ret) {
265 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
266 tmp = 33333333;
267 }
268 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
269
270 /* PLLs */
271 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
272 SLCR_PLL_STATUS, 0, &armpll_lock);
273 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
274 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
275 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
276
277 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
278 SLCR_PLL_STATUS, 1, &ddrpll_lock);
279 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
280 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
281 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
282
283 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
284 SLCR_PLL_STATUS, 2, &iopll_lock);
285 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
286 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
287 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
288
289 /* CPU clocks */
290 tmp = clk_readl(SLCR_621_TRUE) & 1;
291 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
292 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
293 &armclk_lock);
294 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
295 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
296 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
297
298 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
299 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
300 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
301
302 clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
303 1, 2);
304 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
305 "cpu_3or2x_div", CLK_IGNORE_UNUSED,
306 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
307
308 clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
309 2 + tmp);
310 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
311 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
312 26, 0, &armclk_lock);
313 clk_prepare_enable(clks[cpu_2x]);
314
315 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
316 4 + 2 * tmp);
317 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
318 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
319 0, &armclk_lock);
320
321 /* Timers */
322 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
323 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
324 int idx = of_property_match_string(np, "clock-names",
325 swdt_ext_clk_input_names[i]);
326 if (idx >= 0)
327 swdt_ext_clk_mux_parents[i + 1] =
328 of_clk_get_parent_name(np, idx);
329 else
330 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
331 }
332 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
333 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
334 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
335 &swdtclk_lock);
336
337 /* DDR clocks */
338 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
339 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
340 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
341 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
342 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
343 clk_prepare_enable(clks[ddr2x]);
344 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
345 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
346 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
347 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
348 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
349 clk_prepare_enable(clks[ddr3x]);
350
351 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
352 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
353 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
354 clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
355 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
356 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
357 &dciclk_lock);
358 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
359 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
360 &dciclk_lock);
361 clk_prepare_enable(clks[dci]);
362
363 /* Peripheral clocks */
364 for (i = fclk0; i <= fclk3; i++) {
365 int enable = !!(fclk_enable & BIT(i - fclk0));
366 zynq_clk_register_fclk(i, clk_output_name[i],
367 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
368 periph_parents, enable);
369 }
370
371 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
372 SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
373
374 zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
375 SLCR_SMC_CLK_CTRL, periph_parents, 0);
376
377 zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
378 SLCR_PCAP_CLK_CTRL, periph_parents, 0);
379
380 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
381 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
382 periph_parents, 1);
383
384 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
385 clk_output_name[uart1], SLCR_UART_CLK_CTRL,
386 periph_parents, 1);
387
388 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
389 clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
390 periph_parents, 1);
391
392 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
393 int idx = of_property_match_string(np, "clock-names",
394 gem0_emio_input_names[i]);
395 if (idx >= 0)
396 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
397 idx);
398 }
399 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
400 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
401 &gem0clk_lock);
402 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
403 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
404 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
405 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
406 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
407 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
408 &gem0clk_lock);
409 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
410 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
411 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
412 &gem0clk_lock);
413 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
414 "gem0_emio_mux", CLK_SET_RATE_PARENT,
415 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
416
417 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
418 int idx = of_property_match_string(np, "clock-names",
419 gem1_emio_input_names[i]);
420 if (idx >= 0)
421 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
422 idx);
423 }
424 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
425 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
426 &gem1clk_lock);
427 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
428 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
429 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
430 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
431 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
432 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
433 &gem1clk_lock);
434 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
435 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
436 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
437 &gem1clk_lock);
438 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
439 "gem1_emio_mux", CLK_SET_RATE_PARENT,
440 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
441
442 tmp = strlen("mio_clk_00x");
443 clk_name = kmalloc(tmp, GFP_KERNEL);
444 for (i = 0; i < NUM_MIO_PINS; i++) {
445 int idx;
446
447 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
448 idx = of_property_match_string(np, "clock-names", clk_name);
449 if (idx >= 0)
450 can_mio_mux_parents[i] = of_clk_get_parent_name(np,
451 idx);
452 else
453 can_mio_mux_parents[i] = dummy_nm;
454 }
455 kfree(clk_name);
456 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
457 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
458 &canclk_lock);
459 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
460 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
461 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
462 clk = clk_register_divider(NULL, "can_div1", "can_div0",
463 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
464 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
465 &canclk_lock);
466 clk = clk_register_gate(NULL, "can0_gate", "can_div1",
467 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
468 &canclk_lock);
469 clk = clk_register_gate(NULL, "can1_gate", "can_div1",
470 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
471 &canclk_lock);
472 clk = clk_register_mux(NULL, "can0_mio_mux",
473 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
474 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
475 &canmioclk_lock);
476 clk = clk_register_mux(NULL, "can1_mio_mux",
477 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
478 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
479 0, &canmioclk_lock);
480 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
481 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
482 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
483 &canmioclk_lock);
484 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
485 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
486 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
487 0, &canmioclk_lock);
488
489 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
490 int idx = of_property_match_string(np, "clock-names",
491 dbgtrc_emio_input_names[i]);
492 if (idx >= 0)
493 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
494 idx);
495 }
496 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
497 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
498 &dbgclk_lock);
499 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
500 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
501 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
502 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
503 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
504 &dbgclk_lock);
505 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
506 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
507 0, 0, &dbgclk_lock);
508 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
509 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
510 &dbgclk_lock);
511
512 /* leave debug clocks in the state the bootloader set them up to */
513 tmp = clk_readl(SLCR_DBG_CLK_CTRL);
514 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
515 if (clk_prepare_enable(clks[dbg_trc]))
516 pr_warn("%s: trace clk enable failed\n", __func__);
517 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
518 if (clk_prepare_enable(clks[dbg_apb]))
519 pr_warn("%s: debug APB clk enable failed\n", __func__);
520
521 /* One gated clock for all APER clocks. */
522 clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
523 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
524 &aperclk_lock);
525 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
526 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
527 &aperclk_lock);
528 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
529 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
530 &aperclk_lock);
531 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
532 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
533 &aperclk_lock);
534 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
535 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
536 &aperclk_lock);
537 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
538 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
539 &aperclk_lock);
540 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
541 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
542 &aperclk_lock);
543 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
544 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
545 &aperclk_lock);
546 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
547 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
548 &aperclk_lock);
549 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
550 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
551 &aperclk_lock);
552 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
553 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
554 &aperclk_lock);
555 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
556 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
557 &aperclk_lock);
558 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
559 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
560 &aperclk_lock);
561 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
562 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
563 &aperclk_lock);
564 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
565 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
566 &aperclk_lock);
567 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
568 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
569 &aperclk_lock);
570 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
571 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
572 &aperclk_lock);
573 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
574 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
575 &aperclk_lock);
576
577 for (i = 0; i < ARRAY_SIZE(clks); i++) {
578 if (IS_ERR(clks[i])) {
579 pr_err("Zynq clk %d: register failed with %ld\n",
580 i, PTR_ERR(clks[i]));
581 BUG();
582 }
583 }
584
585 clk_data.clks = clks;
586 clk_data.clk_num = ARRAY_SIZE(clks);
587 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
588 }
589
590 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
591
592 void __init zynq_clock_init(void)
593 {
594 struct device_node *np;
595 struct device_node *slcr;
596 struct resource res;
597
598 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
599 if (!np) {
600 pr_err("%s: clkc node not found\n", __func__);
601 goto np_err;
602 }
603
604 if (of_address_to_resource(np, 0, &res)) {
605 pr_err("%s: failed to get resource\n", np->name);
606 goto np_err;
607 }
608
609 slcr = of_get_parent(np);
610
611 if (slcr->data) {
612 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
613 } else {
614 pr_err("%s: Unable to get I/O memory\n", np->name);
615 of_node_put(slcr);
616 goto np_err;
617 }
618
619 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
620
621 of_node_put(slcr);
622 of_node_put(np);
623
624 return;
625
626 np_err:
627 of_node_put(np);
628 BUG();
629 }
Linux with added FPC-III support