drivers/crypto/ccp/ccp-dev.h

   1 /*
   2  * AMD Cryptographic Coprocessor (CCP) driver
   3  *
   4  * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
   5  *
   6  * Author: Tom Lendacky <thomas.lendacky@amd.com>
   7  * Author: Gary R Hook <gary.hook@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef __CCP_DEV_H__
  15 #define __CCP_DEV_H__
  16
  17 #include <linux/device.h>
  18 #include <linux/pci.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/mutex.h>
  21 #include <linux/list.h>
  22 #include <linux/wait.h>
  23 #include <linux/dmapool.h>
  24 #include <linux/hw_random.h>
  25 #include <linux/bitops.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irqreturn.h>
  28 #include <linux/dmaengine.h>
  29
  30 #define MAX_CCP_NAME_LEN                16
  31 #define MAX_DMAPOOL_NAME_LEN            32
  32
  33 #define MAX_HW_QUEUES                   5
  34 #define MAX_CMD_QLEN                    100
  35
  36 #define TRNG_RETRIES                    10
  37
  38 #define CACHE_NONE                      0x00
  39 #define CACHE_WB_NO_ALLOC               0xb7
  40
  41 /****** Register Mappings ******/
  42 #define Q_MASK_REG                      0x000
  43 #define TRNG_OUT_REG                    0x00c
  44 #define IRQ_MASK_REG                    0x040
  45 #define IRQ_STATUS_REG                  0x200
  46
  47 #define DEL_CMD_Q_JOB                   0x124
  48 #define DEL_Q_ACTIVE                    0x00000200
  49 #define DEL_Q_ID_SHIFT                  6
  50
  51 #define CMD_REQ0                        0x180
  52 #define CMD_REQ_INCR                    0x04
  53
  54 #define CMD_Q_STATUS_BASE               0x210
  55 #define CMD_Q_INT_STATUS_BASE           0x214
  56 #define CMD_Q_STATUS_INCR               0x20
  57
  58 #define CMD_Q_CACHE_BASE                0x228
  59 #define CMD_Q_CACHE_INC                 0x20
  60
  61 #define CMD_Q_ERROR(__qs)               ((__qs) & 0x0000003f)
  62 #define CMD_Q_DEPTH(__qs)               (((__qs) >> 12) & 0x0000000f)
  63
  64 /* ------------------------ CCP Version 5 Specifics ------------------------ */
  65 #define CMD5_QUEUE_MASK_OFFSET          0x00
  66 #define CMD5_QUEUE_PRIO_OFFSET          0x04
  67 #define CMD5_REQID_CONFIG_OFFSET        0x08
  68 #define CMD5_CMD_TIMEOUT_OFFSET         0x10
  69 #define LSB_PUBLIC_MASK_LO_OFFSET       0x18
  70 #define LSB_PUBLIC_MASK_HI_OFFSET       0x1C
  71 #define LSB_PRIVATE_MASK_LO_OFFSET      0x20
  72 #define LSB_PRIVATE_MASK_HI_OFFSET      0x24
  73
  74 #define CMD5_Q_CONTROL_BASE             0x0000
  75 #define CMD5_Q_TAIL_LO_BASE             0x0004
  76 #define CMD5_Q_HEAD_LO_BASE             0x0008
  77 #define CMD5_Q_INT_ENABLE_BASE          0x000C
  78 #define CMD5_Q_INTERRUPT_STATUS_BASE    0x0010
  79
  80 #define CMD5_Q_STATUS_BASE              0x0100
  81 #define CMD5_Q_INT_STATUS_BASE          0x0104
  82 #define CMD5_Q_DMA_STATUS_BASE          0x0108
  83 #define CMD5_Q_DMA_READ_STATUS_BASE     0x010C
  84 #define CMD5_Q_DMA_WRITE_STATUS_BASE    0x0110
  85 #define CMD5_Q_ABORT_BASE               0x0114
  86 #define CMD5_Q_AX_CACHE_BASE            0x0118
  87
  88 #define CMD5_CONFIG_0_OFFSET            0x6000
  89 #define CMD5_TRNG_CTL_OFFSET            0x6008
  90 #define CMD5_AES_MASK_OFFSET            0x6010
  91 #define CMD5_CLK_GATE_CTL_OFFSET        0x603C
  92
  93 /* Address offset between two virtual queue registers */
  94 #define CMD5_Q_STATUS_INCR              0x1000
  95
  96 /* Bit masks */
  97 #define CMD5_Q_RUN                      0x1
  98 #define CMD5_Q_HALT                     0x2
  99 #define CMD5_Q_MEM_LOCATION             0x4
 100 #define CMD5_Q_SIZE                     0x1F
 101 #define CMD5_Q_SHIFT                    3
 102 #define COMMANDS_PER_QUEUE              16
 103 #define QUEUE_SIZE_VAL                  ((ffs(COMMANDS_PER_QUEUE) - 2) & \
 104                                           CMD5_Q_SIZE)
 105 #define Q_PTR_MASK                      (2 << (QUEUE_SIZE_VAL + 5) - 1)
 106 #define Q_DESC_SIZE                     sizeof(struct ccp5_desc)
 107 #define Q_SIZE(n)                       (COMMANDS_PER_QUEUE*(n))
 108
 109 #define INT_COMPLETION                  0x1
 110 #define INT_ERROR                       0x2
 111 #define INT_QUEUE_STOPPED               0x4
 112 #define ALL_INTERRUPTS                  (INT_COMPLETION| \
 113                                          INT_ERROR| \
 114                                          INT_QUEUE_STOPPED)
 115
 116 #define LSB_REGION_WIDTH                5
 117 #define MAX_LSB_CNT                     8
 118
 119 #define LSB_SIZE                        16
 120 #define LSB_ITEM_SIZE                   32
 121 #define PLSB_MAP_SIZE                   (LSB_SIZE)
 122 #define SLSB_MAP_SIZE                   (MAX_LSB_CNT * LSB_SIZE)
 123
 124 #define LSB_ENTRY_NUMBER(LSB_ADDR)      (LSB_ADDR / LSB_ITEM_SIZE)
 125
 126 /* ------------------------ CCP Version 3 Specifics ------------------------ */
 127 #define REQ0_WAIT_FOR_WRITE             0x00000004
 128 #define REQ0_INT_ON_COMPLETE            0x00000002
 129 #define REQ0_STOP_ON_COMPLETE           0x00000001
 130
 131 #define REQ0_CMD_Q_SHIFT                9
 132 #define REQ0_JOBID_SHIFT                3
 133
 134 /****** REQ1 Related Values ******/
 135 #define REQ1_PROTECT_SHIFT              27
 136 #define REQ1_ENGINE_SHIFT               23
 137 #define REQ1_KEY_KSB_SHIFT              2
 138
 139 #define REQ1_EOM                        0x00000002
 140 #define REQ1_INIT                       0x00000001
 141
 142 /* AES Related Values */
 143 #define REQ1_AES_TYPE_SHIFT             21
 144 #define REQ1_AES_MODE_SHIFT             18
 145 #define REQ1_AES_ACTION_SHIFT           17
 146 #define REQ1_AES_CFB_SIZE_SHIFT         10
 147
 148 /* XTS-AES Related Values */
 149 #define REQ1_XTS_AES_SIZE_SHIFT         10
 150
 151 /* SHA Related Values */
 152 #define REQ1_SHA_TYPE_SHIFT             21
 153
 154 /* RSA Related Values */
 155 #define REQ1_RSA_MOD_SIZE_SHIFT         10
 156
 157 /* Pass-Through Related Values */
 158 #define REQ1_PT_BW_SHIFT                12
 159 #define REQ1_PT_BS_SHIFT                10
 160
 161 /* ECC Related Values */
 162 #define REQ1_ECC_AFFINE_CONVERT         0x00200000
 163 #define REQ1_ECC_FUNCTION_SHIFT         18
 164
 165 /****** REQ4 Related Values ******/
 166 #define REQ4_KSB_SHIFT                  18
 167 #define REQ4_MEMTYPE_SHIFT              16
 168
 169 /****** REQ6 Related Values ******/
 170 #define REQ6_MEMTYPE_SHIFT              16
 171
 172 /****** Key Storage Block ******/
 173 #define KSB_START                       77
 174 #define KSB_END                         127
 175 #define KSB_COUNT                       (KSB_END - KSB_START + 1)
 176 #define CCP_SB_BITS                     256
 177
 178 #define CCP_JOBID_MASK                  0x0000003f
 179
 180 /* ------------------------ General CCP Defines ------------------------ */
 181
 182 #define CCP_DMAPOOL_MAX_SIZE            64
 183 #define CCP_DMAPOOL_ALIGN               BIT(5)
 184
 185 #define CCP_REVERSE_BUF_SIZE            64
 186
 187 #define CCP_AES_KEY_SB_COUNT            1
 188 #define CCP_AES_CTX_SB_COUNT            1
 189
 190 #define CCP_XTS_AES_KEY_SB_COUNT        1
 191 #define CCP_XTS_AES_CTX_SB_COUNT        1
 192
 193 #define CCP_SHA_SB_COUNT                1
 194
 195 #define CCP_RSA_MAX_WIDTH               4096
 196
 197 #define CCP_PASSTHRU_BLOCKSIZE          256
 198 #define CCP_PASSTHRU_MASKSIZE           32
 199 #define CCP_PASSTHRU_SB_COUNT           1
 200
 201 #define CCP_ECC_MODULUS_BYTES           48      /* 384-bits */
 202 #define CCP_ECC_MAX_OPERANDS            6
 203 #define CCP_ECC_MAX_OUTPUTS             3
 204 #define CCP_ECC_SRC_BUF_SIZE            448
 205 #define CCP_ECC_DST_BUF_SIZE            192
 206 #define CCP_ECC_OPERAND_SIZE            64
 207 #define CCP_ECC_OUTPUT_SIZE             64
 208 #define CCP_ECC_RESULT_OFFSET           60
 209 #define CCP_ECC_RESULT_SUCCESS          0x0001
 210
 211 #define CCP_SB_BYTES                    32
 212
 213 struct ccp_op;
 214 struct ccp_device;
 215 struct ccp_cmd;
 216 struct ccp_fns;
 217
 218 struct ccp_dma_cmd {
 219         struct list_head entry;
 220
 221         struct ccp_cmd ccp_cmd;
 222 };
 223
 224 struct ccp_dma_desc {
 225         struct list_head entry;
 226
 227         struct ccp_device *ccp;
 228
 229         struct list_head pending;
 230         struct list_head active;
 231
 232         enum dma_status status;
 233         struct dma_async_tx_descriptor tx_desc;
 234         size_t len;
 235 };
 236
 237 struct ccp_dma_chan {
 238         struct ccp_device *ccp;
 239
 240         spinlock_t lock;
 241         struct list_head pending;
 242         struct list_head active;
 243         struct list_head complete;
 244
 245         struct tasklet_struct cleanup_tasklet;
 246
 247         enum dma_status status;
 248         struct dma_chan dma_chan;
 249 };
 250
 251 struct ccp_cmd_queue {
 252         struct ccp_device *ccp;
 253
 254         /* Queue identifier */
 255         u32 id;
 256
 257         /* Queue dma pool */
 258         struct dma_pool *dma_pool;
 259
 260         /* Queue base address (not neccessarily aligned)*/
 261         struct ccp5_desc *qbase;
 262
 263         /* Aligned queue start address (per requirement) */
 264         struct mutex q_mutex ____cacheline_aligned;
 265         unsigned int qidx;
 266
 267         /* Version 5 has different requirements for queue memory */
 268         unsigned int qsize;
 269         dma_addr_t qbase_dma;
 270         dma_addr_t qdma_tail;
 271
 272         /* Per-queue reserved storage block(s) */
 273         u32 sb_key;
 274         u32 sb_ctx;
 275
 276         /* Bitmap of LSBs that can be accessed by this queue */
 277         DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
 278         /* Private LSB that is assigned to this queue, or -1 if none.
 279          * Bitmap for my private LSB, unused otherwise
 280          */
 281         int lsb;
 282         DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
 283
 284         /* Queue processing thread */
 285         struct task_struct *kthread;
 286         unsigned int active;
 287         unsigned int suspended;
 288
 289         /* Number of free command slots available */
 290         unsigned int free_slots;
 291
 292         /* Interrupt masks */
 293         u32 int_ok;
 294         u32 int_err;
 295
 296         /* Register addresses for queue */
 297         void __iomem *reg_control;
 298         void __iomem *reg_tail_lo;
 299         void __iomem *reg_head_lo;
 300         void __iomem *reg_int_enable;
 301         void __iomem *reg_interrupt_status;
 302         void __iomem *reg_status;
 303         void __iomem *reg_int_status;
 304         void __iomem *reg_dma_status;
 305         void __iomem *reg_dma_read_status;
 306         void __iomem *reg_dma_write_status;
 307         u32 qcontrol; /* Cached control register */
 308
 309         /* Status values from job */
 310         u32 int_status;
 311         u32 q_status;
 312         u32 q_int_status;
 313         u32 cmd_error;
 314
 315         /* Interrupt wait queue */
 316         wait_queue_head_t int_queue;
 317         unsigned int int_rcvd;
 318 } ____cacheline_aligned;
 319
 320 struct ccp_device {
 321         struct list_head entry;
 322
 323         struct ccp_vdata *vdata;
 324         unsigned int ord;
 325         char name[MAX_CCP_NAME_LEN];
 326         char rngname[MAX_CCP_NAME_LEN];
 327
 328         struct device *dev;
 329
 330         /* Bus specific device information
 331          */
 332         void *dev_specific;
 333         int (*get_irq)(struct ccp_device *ccp);
 334         void (*free_irq)(struct ccp_device *ccp);
 335         unsigned int irq;
 336
 337         /* I/O area used for device communication. The register mapping
 338          * starts at an offset into the mapped bar.
 339          *   The CMD_REQx registers and the Delete_Cmd_Queue_Job register
 340          *   need to be protected while a command queue thread is accessing
 341          *   them.
 342          */
 343         struct mutex req_mutex ____cacheline_aligned;
 344         void __iomem *io_map;
 345         void __iomem *io_regs;
 346
 347         /* Master lists that all cmds are queued on. Because there can be
 348          * more than one CCP command queue that can process a cmd a separate
 349          * backlog list is neeeded so that the backlog completion call
 350          * completes before the cmd is available for execution.
 351          */
 352         spinlock_t cmd_lock ____cacheline_aligned;
 353         unsigned int cmd_count;
 354         struct list_head cmd;
 355         struct list_head backlog;
 356
 357         /* The command queues. These represent the queues available on the
 358          * CCP that are available for processing cmds
 359          */
 360         struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
 361         unsigned int cmd_q_count;
 362
 363         /* Support for the CCP True RNG
 364          */
 365         struct hwrng hwrng;
 366         unsigned int hwrng_retries;
 367
 368         /* Support for the CCP DMA capabilities
 369          */
 370         struct dma_device dma_dev;
 371         struct ccp_dma_chan *ccp_dma_chan;
 372         struct kmem_cache *dma_cmd_cache;
 373         struct kmem_cache *dma_desc_cache;
 374
 375         /* A counter used to generate job-ids for cmds submitted to the CCP
 376          */
 377         atomic_t current_id ____cacheline_aligned;
 378
 379         /* The v3 CCP uses key storage blocks (SB) to maintain context for
 380          * certain operations. To prevent multiple cmds from using the same
 381          * SB range a command queue reserves an SB range for the duration of
 382          * the cmd. Each queue, will however, reserve 2 SB blocks for
 383          * operations that only require single SB entries (eg. AES context/iv
 384          * and key) in order to avoid allocation contention.  This will reserve
 385          * at most 10 SB entries, leaving 40 SB entries available for dynamic
 386          * allocation.
 387          *
 388          * The v5 CCP Local Storage Block (LSB) is broken up into 8
 389          * memrory ranges, each of which can be enabled for access by one
 390          * or more queues. Device initialization takes this into account,
 391          * and attempts to assign one region for exclusive use by each
 392          * available queue; the rest are then aggregated as "public" use.
 393          * If there are fewer regions than queues, all regions are shared
 394          * amongst all queues.
 395          */
 396         struct mutex sb_mutex ____cacheline_aligned;
 397         DECLARE_BITMAP(sb, KSB_COUNT);
 398         wait_queue_head_t sb_queue;
 399         unsigned int sb_avail;
 400         unsigned int sb_count;
 401         u32 sb_start;
 402
 403         /* Bitmap of shared LSBs, if any */
 404         DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
 405
 406         /* Suspend support */
 407         unsigned int suspending;
 408         wait_queue_head_t suspend_queue;
 409
 410         /* DMA caching attribute support */
 411         unsigned int axcache;
 412 };
 413
 414 enum ccp_memtype {
 415         CCP_MEMTYPE_SYSTEM = 0,
 416         CCP_MEMTYPE_SB,
 417         CCP_MEMTYPE_LOCAL,
 418         CCP_MEMTYPE__LAST,
 419 };
 420 #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
 421
 422 struct ccp_dma_info {
 423         dma_addr_t address;
 424         unsigned int offset;
 425         unsigned int length;
 426         enum dma_data_direction dir;
 427 };
 428
 429 struct ccp_dm_workarea {
 430         struct device *dev;
 431         struct dma_pool *dma_pool;
 432         unsigned int length;
 433
 434         u8 *address;
 435         struct ccp_dma_info dma;
 436 };
 437
 438 struct ccp_sg_workarea {
 439         struct scatterlist *sg;
 440         int nents;
 441
 442         struct scatterlist *dma_sg;
 443         struct device *dma_dev;
 444         unsigned int dma_count;
 445         enum dma_data_direction dma_dir;
 446
 447         unsigned int sg_used;
 448
 449         u64 bytes_left;
 450 };
 451
 452 struct ccp_data {
 453         struct ccp_sg_workarea sg_wa;
 454         struct ccp_dm_workarea dm_wa;
 455 };
 456
 457 struct ccp_mem {
 458         enum ccp_memtype type;
 459         union {
 460                 struct ccp_dma_info dma;
 461                 u32 sb;
 462         } u;
 463 };
 464
 465 struct ccp_aes_op {
 466         enum ccp_aes_type type;
 467         enum ccp_aes_mode mode;
 468         enum ccp_aes_action action;
 469 };
 470
 471 struct ccp_xts_aes_op {
 472         enum ccp_aes_action action;
 473         enum ccp_xts_aes_unit_size unit_size;
 474 };
 475
 476 struct ccp_sha_op {
 477         enum ccp_sha_type type;
 478         u64 msg_bits;
 479 };
 480
 481 struct ccp_rsa_op {
 482         u32 mod_size;
 483         u32 input_len;
 484 };
 485
 486 struct ccp_passthru_op {
 487         enum ccp_passthru_bitwise bit_mod;
 488         enum ccp_passthru_byteswap byte_swap;
 489 };
 490
 491 struct ccp_ecc_op {
 492         enum ccp_ecc_function function;
 493 };
 494
 495 struct ccp_op {
 496         struct ccp_cmd_queue *cmd_q;
 497
 498         u32 jobid;
 499         u32 ioc;
 500         u32 soc;
 501         u32 sb_key;
 502         u32 sb_ctx;
 503         u32 init;
 504         u32 eom;
 505
 506         struct ccp_mem src;
 507         struct ccp_mem dst;
 508         struct ccp_mem exp;
 509
 510         union {
 511                 struct ccp_aes_op aes;
 512                 struct ccp_xts_aes_op xts;
 513                 struct ccp_sha_op sha;
 514                 struct ccp_rsa_op rsa;
 515                 struct ccp_passthru_op passthru;
 516                 struct ccp_ecc_op ecc;
 517         } u;
 518 };
 519
 520 static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
 521 {
 522         return lower_32_bits(info->address + info->offset);
 523 }
 524
 525 static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
 526 {
 527         return upper_32_bits(info->address + info->offset) & 0x0000ffff;
 528 }
 529
 530 /**
 531  * descriptor for version 5 CPP commands
 532  * 8 32-bit words:
 533  * word 0: function; engine; control bits
 534  * word 1: length of source data
 535  * word 2: low 32 bits of source pointer
 536  * word 3: upper 16 bits of source pointer; source memory type
 537  * word 4: low 32 bits of destination pointer
 538  * word 5: upper 16 bits of destination pointer; destination memory type
 539  * word 6: low 32 bits of key pointer
 540  * word 7: upper 16 bits of key pointer; key memory type
 541  */
 542 struct dword0 {
 543         unsigned int soc:1;
 544         unsigned int ioc:1;
 545         unsigned int rsvd1:1;
 546         unsigned int init:1;
 547         unsigned int eom:1;             /* AES/SHA only */
 548         unsigned int function:15;
 549         unsigned int engine:4;
 550         unsigned int prot:1;
 551         unsigned int rsvd2:7;
 552 };
 553
 554 struct dword3 {
 555         unsigned int  src_hi:16;
 556         unsigned int  src_mem:2;
 557         unsigned int  lsb_cxt_id:8;
 558         unsigned int  rsvd1:5;
 559         unsigned int  fixed:1;
 560 };
 561
 562 union dword4 {
 563         __le32 dst_lo;          /* NON-SHA      */
 564         __le32 sha_len_lo;      /* SHA          */
 565 };
 566
 567 union dword5 {
 568         struct {
 569                 unsigned int  dst_hi:16;
 570                 unsigned int  dst_mem:2;
 571                 unsigned int  rsvd1:13;
 572                 unsigned int  fixed:1;
 573         } fields;
 574         __le32 sha_len_hi;
 575 };
 576
 577 struct dword7 {
 578         unsigned int  key_hi:16;
 579         unsigned int  key_mem:2;
 580         unsigned int  rsvd1:14;
 581 };
 582
 583 struct ccp5_desc {
 584         struct dword0 dw0;
 585         __le32 length;
 586         __le32 src_lo;
 587         struct dword3 dw3;
 588         union dword4 dw4;
 589         union dword5 dw5;
 590         __le32 key_lo;
 591         struct dword7 dw7;
 592 };
 593
 594 int ccp_pci_init(void);
 595 void ccp_pci_exit(void);
 596
 597 int ccp_platform_init(void);
 598 void ccp_platform_exit(void);
 599
 600 void ccp_add_device(struct ccp_device *ccp);
 601 void ccp_del_device(struct ccp_device *ccp);
 602
 603 extern void ccp_log_error(struct ccp_device *, int);
 604
 605 struct ccp_device *ccp_alloc_struct(struct device *dev);
 606 bool ccp_queues_suspended(struct ccp_device *ccp);
 607 int ccp_cmd_queue_thread(void *data);
 608 int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
 609
 610 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
 611
 612 int ccp_register_rng(struct ccp_device *ccp);
 613 void ccp_unregister_rng(struct ccp_device *ccp);
 614 int ccp_dmaengine_register(struct ccp_device *ccp);
 615 void ccp_dmaengine_unregister(struct ccp_device *ccp);
 616
 617 /* Structure for computation functions that are device-specific */
 618 struct ccp_actions {
 619         int (*aes)(struct ccp_op *);
 620         int (*xts_aes)(struct ccp_op *);
 621         int (*sha)(struct ccp_op *);
 622         int (*rsa)(struct ccp_op *);
 623         int (*passthru)(struct ccp_op *);
 624         int (*ecc)(struct ccp_op *);
 625         u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
 626         void (*sbfree)(struct ccp_cmd_queue *, unsigned int,
 627                                unsigned int);
 628         unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
 629         int (*init)(struct ccp_device *);
 630         void (*destroy)(struct ccp_device *);
 631         irqreturn_t (*irqhandler)(int, void *);
 632 };
 633
 634 /* Structure to hold CCP version-specific values */
 635 struct ccp_vdata {
 636         const unsigned int version;
 637         void (*setup)(struct ccp_device *);
 638         const struct ccp_actions *perform;
 639         const unsigned int bar;
 640         const unsigned int offset;
 641 };
 642
 643 extern const struct ccp_vdata ccpv3;
 644 extern const struct ccp_vdata ccpv5a;
 645 extern const struct ccp_vdata ccpv5b;
 646
 647 #endif