?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / crypto / marvell / cesa.h
blobb7872f62f67475fdc6889420c38de4f8418ffafd
1 #ifndef __MARVELL_CESA_H__
2 #define __MARVELL_CESA_H__
3
4 #include <crypto/algapi.h>
5 #include <crypto/hash.h>
6 #include <crypto/internal/hash.h>
7
8 #include <linux/crypto.h>
9 #include <linux/dmapool.h>
10
11 #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
12
13 #define CESA_TDMA_BYTE_CNT 0x800
14 #define CESA_TDMA_SRC_ADDR 0x810
15 #define CESA_TDMA_DST_ADDR 0x820
16 #define CESA_TDMA_NEXT_ADDR 0x830
17
18 #define CESA_TDMA_CONTROL 0x840
19 #define CESA_TDMA_DST_BURST GENMASK(2, 0)
20 #define CESA_TDMA_DST_BURST_32B 3
21 #define CESA_TDMA_DST_BURST_128B 4
22 #define CESA_TDMA_OUT_RD_EN BIT(4)
23 #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
24 #define CESA_TDMA_SRC_BURST_32B (3 << 6)
25 #define CESA_TDMA_SRC_BURST_128B (4 << 6)
26 #define CESA_TDMA_CHAIN BIT(9)
27 #define CESA_TDMA_BYTE_SWAP BIT(11)
28 #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
29 #define CESA_TDMA_EN BIT(12)
30 #define CESA_TDMA_FETCH_ND BIT(13)
31 #define CESA_TDMA_ACT BIT(14)
32
33 #define CESA_TDMA_CUR 0x870
34 #define CESA_TDMA_ERROR_CAUSE 0x8c8
35 #define CESA_TDMA_ERROR_MSK 0x8cc
36
37 #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
38 #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
39
40 #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
41 (((x) < 5) ? 0 : 0x14))
42
43 #define CESA_SA_CMD 0xde00
44 #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
45 #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
46 #define CESA_SA_CMD_DISABLE_SEC BIT(2)
47
48 #define CESA_SA_DESC_P0 0xde04
49
50 #define CESA_SA_DESC_P1 0xde14
51
52 #define CESA_SA_CFG 0xde08
53 #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
54 #define CESA_SA_CFG_DIG_ERR_CONT 0
55 #define CESA_SA_CFG_DIG_ERR_SKIP 1
56 #define CESA_SA_CFG_DIG_ERR_STOP 3
57 #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
58 #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
59 #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
60 #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
61 #define CESA_SA_CFG_MULTI_PKT BIT(11)
62 #define CESA_SA_CFG_PARA_DIS BIT(13)
63
64 #define CESA_SA_ACCEL_STATUS 0xde0c
65 #define CESA_SA_ST_ACT_0 BIT(0)
66 #define CESA_SA_ST_ACT_1 BIT(1)
67
68 /*
69 * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
71 * and someone forgot to remove it while switching to the core and moving to
72 * CESA_SA_INT_STATUS.
73 */
74 #define CESA_SA_FPGA_INT_STATUS 0xdd68
75 #define CESA_SA_INT_STATUS 0xde20
76 #define CESA_SA_INT_AUTH_DONE BIT(0)
77 #define CESA_SA_INT_DES_E_DONE BIT(1)
78 #define CESA_SA_INT_AES_E_DONE BIT(2)
79 #define CESA_SA_INT_AES_D_DONE BIT(3)
80 #define CESA_SA_INT_ENC_DONE BIT(4)
81 #define CESA_SA_INT_ACCEL0_DONE BIT(5)
82 #define CESA_SA_INT_ACCEL1_DONE BIT(6)
83 #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
84 #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
85 #define CESA_SA_INT_IDMA_DONE BIT(9)
86 #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
87
88 #define CESA_SA_INT_MSK 0xde24
89
90 #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
91 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
92 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
93 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
94 #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
95 #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
96 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
97 #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
98 #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
99 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
100 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
101 #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
102 #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
103 #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
104 #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
105 #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
106 #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
107 #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
108 #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
109 #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
110 #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
111 #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
112 #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
113 #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
114 #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
115 #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
116 #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
117 #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
118 #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
119 #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
120 #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
121 #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
122
123 /*
124 * /-----------\ 0
125 * | ACCEL CFG | 4 * 8
126 * |-----------| 0x20
127 * | CRYPT KEY | 8 * 4
128 * |-----------| 0x40
129 * | IV IN | 4 * 4
130 * |-----------| 0x40 (inplace)
131 * | IV BUF | 4 * 4
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
135 * | DATA OUT | 16 * x (max ->max_req_size)
136 * \-----------/ SRAM size
137 */
138
139 /*
140 * Hashing memory map:
141 * /-----------\ 0
142 * | ACCEL CFG | 4 * 8
143 * |-----------| 0x20
144 * | Inner IV | 8 * 4
145 * |-----------| 0x40
146 * | Outer IV | 8 * 4
147 * |-----------| 0x60
148 * | Output BUF| 8 * 4
149 * |-----------| 0x80
150 * | DATA IN | 64 * x (max ->max_req_size)
151 * \-----------/ SRAM size
152 */
153
154 #define CESA_SA_CFG_SRAM_OFFSET 0x00
155 #define CESA_SA_DATA_SRAM_OFFSET 0x80
156
157 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
158 #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
159
160 #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
161 #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
162 #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
163
164 #define CESA_SA_DESC_CRYPT_DATA(offset) \
165 cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
166 ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
167
168 #define CESA_SA_DESC_CRYPT_IV(offset) \
169 cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
170 ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
171
172 #define CESA_SA_DESC_CRYPT_KEY(offset) \
173 cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
174
175 #define CESA_SA_DESC_MAC_DATA(offset) \
176 cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
177 #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
178
179 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
180 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
181
182 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
183
184 #define CESA_SA_DESC_MAC_DIGEST(offset) \
185 cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
186 #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
187
188 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
189 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
190
191 #define CESA_SA_DESC_MAC_IV(offset) \
192 cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
193 ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
194
195 #define CESA_SA_SRAM_SIZE 2048
196 #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
197 CESA_SA_DATA_SRAM_OFFSET)
198
199 #define CESA_SA_DEFAULT_SRAM_SIZE 2048
200 #define CESA_SA_MIN_SRAM_SIZE 1024
201
202 #define CESA_SA_SRAM_MSK (2048 - 1)
203
204 #define CESA_MAX_HASH_BLOCK_SIZE 64
205 #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
206
207 /**
208 * struct mv_cesa_sec_accel_desc - security accelerator descriptor
209 * @config: engine config
210 * @enc_p: input and output data pointers for a cipher operation
211 * @enc_len: cipher operation length
212 * @enc_key_p: cipher key pointer
213 * @enc_iv: cipher IV pointers
214 * @mac_src_p: input pointer and total hash length
215 * @mac_digest: digest pointer and hash operation length
216 * @mac_iv: hmac IV pointers
217 *
218 * Structure passed to the CESA engine to describe the crypto operation
219 * to be executed.
220 */
221 struct mv_cesa_sec_accel_desc {
222 __le32 config;
223 __le32 enc_p;
224 __le32 enc_len;
225 __le32 enc_key_p;
226 __le32 enc_iv;
227 __le32 mac_src_p;
228 __le32 mac_digest;
229 __le32 mac_iv;
230 };
231
232 /**
233 * struct mv_cesa_blkcipher_op_ctx - cipher operation context
234 * @key: cipher key
235 * @iv: cipher IV
236 *
237 * Context associated to a cipher operation.
238 */
239 struct mv_cesa_blkcipher_op_ctx {
240 u32 key[8];
241 u32 iv[4];
242 };
243
244 /**
245 * struct mv_cesa_hash_op_ctx - hash or hmac operation context
246 * @key: cipher key
247 * @iv: cipher IV
248 *
249 * Context associated to an hash or hmac operation.
250 */
251 struct mv_cesa_hash_op_ctx {
252 u32 iv[16];
253 u32 hash[8];
254 };
255
256 /**
257 * struct mv_cesa_op_ctx - crypto operation context
258 * @desc: CESA descriptor
259 * @ctx: context associated to the crypto operation
260 *
261 * Context associated to a crypto operation.
262 */
263 struct mv_cesa_op_ctx {
264 struct mv_cesa_sec_accel_desc desc;
265 union {
266 struct mv_cesa_blkcipher_op_ctx blkcipher;
267 struct mv_cesa_hash_op_ctx hash;
268 } ctx;
269 };
270
271 /* TDMA descriptor flags */
272 #define CESA_TDMA_DST_IN_SRAM BIT(31)
273 #define CESA_TDMA_SRC_IN_SRAM BIT(30)
274 #define CESA_TDMA_END_OF_REQ BIT(29)
275 #define CESA_TDMA_BREAK_CHAIN BIT(28)
276 #define CESA_TDMA_SET_STATE BIT(27)
277 #define CESA_TDMA_TYPE_MSK GENMASK(26, 0)
278 #define CESA_TDMA_DUMMY 0
279 #define CESA_TDMA_DATA 1
280 #define CESA_TDMA_OP 2
281 #define CESA_TDMA_RESULT 3
282
283 /**
284 * struct mv_cesa_tdma_desc - TDMA descriptor
285 * @byte_cnt: number of bytes to transfer
286 * @src: DMA address of the source
287 * @dst: DMA address of the destination
288 * @next_dma: DMA address of the next TDMA descriptor
289 * @cur_dma: DMA address of this TDMA descriptor
290 * @next: pointer to the next TDMA descriptor
291 * @op: CESA operation attached to this TDMA descriptor
292 * @data: raw data attached to this TDMA descriptor
293 * @flags: flags describing the TDMA transfer. See the
294 * "TDMA descriptor flags" section above
295 *
296 * TDMA descriptor used to create a transfer chain describing a crypto
297 * operation.
298 */
299 struct mv_cesa_tdma_desc {
300 __le32 byte_cnt;
301 __le32 src;
302 __le32 dst;
303 __le32 next_dma;
304
305 /* Software state */
306 dma_addr_t cur_dma;
307 struct mv_cesa_tdma_desc *next;
308 union {
309 struct mv_cesa_op_ctx *op;
310 void *data;
311 };
312 u32 flags;
313 };
314
315 /**
316 * struct mv_cesa_sg_dma_iter - scatter-gather iterator
317 * @dir: transfer direction
318 * @sg: scatter list
319 * @offset: current position in the scatter list
320 * @op_offset: current position in the crypto operation
321 *
322 * Iterator used to iterate over a scatterlist while creating a TDMA chain for
323 * a crypto operation.
324 */
325 struct mv_cesa_sg_dma_iter {
326 enum dma_data_direction dir;
327 struct scatterlist *sg;
328 unsigned int offset;
329 unsigned int op_offset;
330 };
331
332 /**
333 * struct mv_cesa_dma_iter - crypto operation iterator
334 * @len: the crypto operation length
335 * @offset: current position in the crypto operation
336 * @op_len: sub-operation length (the crypto engine can only act on 2kb
337 * chunks)
338 *
339 * Iterator used to create a TDMA chain for a given crypto operation.
340 */
341 struct mv_cesa_dma_iter {
342 unsigned int len;
343 unsigned int offset;
344 unsigned int op_len;
345 };
346
347 /**
348 * struct mv_cesa_tdma_chain - TDMA chain
349 * @first: first entry in the TDMA chain
350 * @last: last entry in the TDMA chain
351 *
352 * Stores a TDMA chain for a specific crypto operation.
353 */
354 struct mv_cesa_tdma_chain {
355 struct mv_cesa_tdma_desc *first;
356 struct mv_cesa_tdma_desc *last;
357 };
358
359 struct mv_cesa_engine;
360
361 /**
362 * struct mv_cesa_caps - CESA device capabilities
363 * @engines: number of engines
364 * @has_tdma: whether this device has a TDMA block
365 * @cipher_algs: supported cipher algorithms
366 * @ncipher_algs: number of supported cipher algorithms
367 * @ahash_algs: supported hash algorithms
368 * @nahash_algs: number of supported hash algorithms
369 *
370 * Structure used to describe CESA device capabilities.
371 */
372 struct mv_cesa_caps {
373 int nengines;
374 bool has_tdma;
375 struct crypto_alg **cipher_algs;
376 int ncipher_algs;
377 struct ahash_alg **ahash_algs;
378 int nahash_algs;
379 };
380
381 /**
382 * struct mv_cesa_dev_dma - DMA pools
383 * @tdma_desc_pool: TDMA desc pool
384 * @op_pool: crypto operation pool
385 * @cache_pool: data cache pool (used by hash implementation when the
386 * hash request is smaller than the hash block size)
387 * @padding_pool: padding pool (used by hash implementation when hardware
388 * padding cannot be used)
389 *
390 * Structure containing the different DMA pools used by this driver.
391 */
392 struct mv_cesa_dev_dma {
393 struct dma_pool *tdma_desc_pool;
394 struct dma_pool *op_pool;
395 struct dma_pool *cache_pool;
396 struct dma_pool *padding_pool;
397 };
398
399 /**
400 * struct mv_cesa_dev - CESA device
401 * @caps: device capabilities
402 * @regs: device registers
403 * @sram_size: usable SRAM size
404 * @lock: device lock
405 * @engines: array of engines
406 * @dma: dma pools
407 *
408 * Structure storing CESA device information.
409 */
410 struct mv_cesa_dev {
411 const struct mv_cesa_caps *caps;
412 void __iomem *regs;
413 struct device *dev;
414 unsigned int sram_size;
415 spinlock_t lock;
416 struct mv_cesa_engine *engines;
417 struct mv_cesa_dev_dma *dma;
418 };
419
420 /**
421 * struct mv_cesa_engine - CESA engine
422 * @id: engine id
423 * @regs: engine registers
424 * @sram: SRAM memory region
425 * @sram_dma: DMA address of the SRAM memory region
426 * @lock: engine lock
427 * @req: current crypto request
428 * @clk: engine clk
429 * @zclk: engine zclk
430 * @max_req_len: maximum chunk length (useful to create the TDMA chain)
431 * @int_mask: interrupt mask cache
432 * @pool: memory pool pointing to the memory region reserved in
433 * SRAM
434 * @queue: fifo of the pending crypto requests
435 * @load: engine load counter, useful for load balancing
436 * @chain: list of the current tdma descriptors being processed
437 * by this engine.
438 * @complete_queue: fifo of the processed requests by the engine
439 *
440 * Structure storing CESA engine information.
441 */
442 struct mv_cesa_engine {
443 int id;
444 void __iomem *regs;
445 void __iomem *sram;
446 dma_addr_t sram_dma;
447 spinlock_t lock;
448 struct crypto_async_request *req;
449 struct clk *clk;
450 struct clk *zclk;
451 size_t max_req_len;
452 u32 int_mask;
453 struct gen_pool *pool;
454 struct crypto_queue queue;
455 atomic_t load;
456 struct mv_cesa_tdma_chain chain;
457 struct list_head complete_queue;
458 };
459
460 /**
461 * struct mv_cesa_req_ops - CESA request operations
462 * @process: process a request chunk result (should return 0 if the
463 * operation, -EINPROGRESS if it needs more steps or an error
464 * code)
465 * @step: launch the crypto operation on the next chunk
466 * @cleanup: cleanup the crypto request (release associated data)
467 * @complete: complete the request, i.e copy result or context from sram when
468 * needed.
469 */
470 struct mv_cesa_req_ops {
471 int (*process)(struct crypto_async_request *req, u32 status);
472 void (*step)(struct crypto_async_request *req);
473 void (*cleanup)(struct crypto_async_request *req);
474 void (*complete)(struct crypto_async_request *req);
475 };
476
477 /**
478 * struct mv_cesa_ctx - CESA operation context
479 * @ops: crypto operations
480 *
481 * Base context structure inherited by operation specific ones.
482 */
483 struct mv_cesa_ctx {
484 const struct mv_cesa_req_ops *ops;
485 };
486
487 /**
488 * struct mv_cesa_hash_ctx - CESA hash operation context
489 * @base: base context structure
490 *
491 * Hash context structure.
492 */
493 struct mv_cesa_hash_ctx {
494 struct mv_cesa_ctx base;
495 };
496
497 /**
498 * struct mv_cesa_hash_ctx - CESA hmac operation context
499 * @base: base context structure
500 * @iv: initialization vectors
501 *
502 * HMAC context structure.
503 */
504 struct mv_cesa_hmac_ctx {
505 struct mv_cesa_ctx base;
506 u32 iv[16];
507 };
508
509 /**
510 * enum mv_cesa_req_type - request type definitions
511 * @CESA_STD_REQ: standard request
512 * @CESA_DMA_REQ: DMA request
513 */
514 enum mv_cesa_req_type {
515 CESA_STD_REQ,
516 CESA_DMA_REQ,
517 };
518
519 /**
520 * struct mv_cesa_req - CESA request
521 * @engine: engine associated with this request
522 * @chain: list of tdma descriptors associated with this request
523 */
524 struct mv_cesa_req {
525 struct mv_cesa_engine *engine;
526 struct mv_cesa_tdma_chain chain;
527 };
528
529 /**
530 * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
531 * requests
532 * @iter: sg mapping iterator
533 * @offset: current offset in the SG entry mapped in memory
534 */
535 struct mv_cesa_sg_std_iter {
536 struct sg_mapping_iter iter;
537 unsigned int offset;
538 };
539
540 /**
541 * struct mv_cesa_ablkcipher_std_req - cipher standard request
542 * @op: operation context
543 * @offset: current operation offset
544 * @size: size of the crypto operation
545 */
546 struct mv_cesa_ablkcipher_std_req {
547 struct mv_cesa_op_ctx op;
548 unsigned int offset;
549 unsigned int size;
550 bool skip_ctx;
551 };
552
553 /**
554 * struct mv_cesa_ablkcipher_req - cipher request
555 * @req: type specific request information
556 * @src_nents: number of entries in the src sg list
557 * @dst_nents: number of entries in the dest sg list
558 */
559 struct mv_cesa_ablkcipher_req {
560 struct mv_cesa_req base;
561 struct mv_cesa_ablkcipher_std_req std;
562 int src_nents;
563 int dst_nents;
564 };
565
566 /**
567 * struct mv_cesa_ahash_std_req - standard hash request
568 * @offset: current operation offset
569 */
570 struct mv_cesa_ahash_std_req {
571 unsigned int offset;
572 };
573
574 /**
575 * struct mv_cesa_ahash_dma_req - DMA hash request
576 * @padding: padding buffer
577 * @padding_dma: DMA address of the padding buffer
578 * @cache_dma: DMA address of the cache buffer
579 */
580 struct mv_cesa_ahash_dma_req {
581 u8 *padding;
582 dma_addr_t padding_dma;
583 u8 *cache;
584 dma_addr_t cache_dma;
585 };
586
587 /**
588 * struct mv_cesa_ahash_req - hash request
589 * @req: type specific request information
590 * @cache: cache buffer
591 * @cache_ptr: write pointer in the cache buffer
592 * @len: hash total length
593 * @src_nents: number of entries in the scatterlist
594 * @last_req: define whether the current operation is the last one
595 * or not
596 * @state: hash state
597 */
598 struct mv_cesa_ahash_req {
599 struct mv_cesa_req base;
600 union {
601 struct mv_cesa_ahash_dma_req dma;
602 struct mv_cesa_ahash_std_req std;
603 } req;
604 struct mv_cesa_op_ctx op_tmpl;
605 u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
606 unsigned int cache_ptr;
607 u64 len;
608 int src_nents;
609 bool last_req;
610 bool algo_le;
611 u32 state[8];
612 };
613
614 /* CESA functions */
615
616 extern struct mv_cesa_dev *cesa_dev;
617
618
619 static inline void
620 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
621 struct crypto_async_request *req)
622 {
623 list_add_tail(&req->list, &engine->complete_queue);
624 }
625
626 static inline struct crypto_async_request *
627 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
628 {
629 struct crypto_async_request *req;
630
631 req = list_first_entry_or_null(&engine->complete_queue,
632 struct crypto_async_request,
633 list);
634 if (req)
635 list_del(&req->list);
636
637 return req;
638 }
639
640
641 static inline enum mv_cesa_req_type
642 mv_cesa_req_get_type(struct mv_cesa_req *req)
643 {
644 return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
645 }
646
647 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
648 u32 cfg, u32 mask)
649 {
650 op->desc.config &= cpu_to_le32(~mask);
651 op->desc.config |= cpu_to_le32(cfg);
652 }
653
654 static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
655 {
656 return le32_to_cpu(op->desc.config);
657 }
658
659 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
660 {
661 op->desc.config = cpu_to_le32(cfg);
662 }
663
664 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
665 struct mv_cesa_op_ctx *op)
666 {
667 u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
668
669 op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
670 op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
671 op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
672 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
673 op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
674 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
675 op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
676 op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
677 }
678
679 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
680 {
681 op->desc.enc_len = cpu_to_le32(len);
682 }
683
684 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
685 int len)
686 {
687 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
688 op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
689 }
690
691 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
692 int len)
693 {
694 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
695 op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
696 }
697
698 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
699 u32 int_mask)
700 {
701 if (int_mask == engine->int_mask)
702 return;
703
704 writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
705 engine->int_mask = int_mask;
706 }
707
708 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
709 {
710 return engine->int_mask;
711 }
712
713 static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
714 {
715 return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
716 CESA_SA_DESC_CFG_FIRST_FRAG;
717 }
718
719 int mv_cesa_queue_req(struct crypto_async_request *req,
720 struct mv_cesa_req *creq);
721
722 struct crypto_async_request *
723 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
724 struct crypto_async_request **backlog);
725
726 static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
727 {
728 int i;
729 u32 min_load = U32_MAX;
730 struct mv_cesa_engine *selected = NULL;
731
732 for (i = 0; i < cesa_dev->caps->nengines; i++) {
733 struct mv_cesa_engine *engine = cesa_dev->engines + i;
734 u32 load = atomic_read(&engine->load);
735 if (load < min_load) {
736 min_load = load;
737 selected = engine;
738 }
739 }
740
741 atomic_add(weight, &selected->load);
742
743 return selected;
744 }
745
746 /*
747 * Helper function that indicates whether a crypto request needs to be
748 * cleaned up or not after being enqueued using mv_cesa_queue_req().
749 */
750 static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
751 int ret)
752 {
753 /*
754 * The queue still had some space, the request was queued
755 * normally, so there's no need to clean it up.
756 */
757 if (ret == -EINPROGRESS)
758 return false;
759
760 /*
761 * The queue had not space left, but since the request is
762 * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
763 * the backlog and will be processed later. There's no need to
764 * clean it up.
765 */
766 if (ret == -EBUSY && req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
767 return false;
768
769 /* Request wasn't queued, we need to clean it up */
770 return true;
771 }
772
773 /* TDMA functions */
774
775 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
776 unsigned int len)
777 {
778 iter->len = len;
779 iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
780 iter->offset = 0;
781 }
782
783 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
784 struct scatterlist *sg,
785 enum dma_data_direction dir)
786 {
787 iter->op_offset = 0;
788 iter->offset = 0;
789 iter->sg = sg;
790 iter->dir = dir;
791 }
792
793 static inline unsigned int
794 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
795 struct mv_cesa_sg_dma_iter *sgiter)
796 {
797 return min(iter->op_len - sgiter->op_offset,
798 sg_dma_len(sgiter->sg) - sgiter->offset);
799 }
800
801 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
802 struct mv_cesa_sg_dma_iter *sgiter,
803 unsigned int len);
804
805 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
806 {
807 iter->offset += iter->op_len;
808 iter->op_len = min(iter->len - iter->offset,
809 CESA_SA_SRAM_PAYLOAD_SIZE);
810
811 return iter->op_len;
812 }
813
814 void mv_cesa_dma_step(struct mv_cesa_req *dreq);
815
816 static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
817 u32 status)
818 {
819 if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
820 return -EINPROGRESS;
821
822 if (status & CESA_SA_INT_IDMA_OWN_ERR)
823 return -EINVAL;
824
825 return 0;
826 }
827
828 void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
829 struct mv_cesa_engine *engine);
830 void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
831 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
832 struct mv_cesa_req *dreq);
833 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
834
835
836 static inline void
837 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
838 {
839 memset(chain, 0, sizeof(*chain));
840 }
841
842 int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
843 u32 size, u32 flags, gfp_t gfp_flags);
844
845 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
846 const struct mv_cesa_op_ctx *op_templ,
847 bool skip_ctx,
848 gfp_t flags);
849
850 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
851 dma_addr_t dst, dma_addr_t src, u32 size,
852 u32 flags, gfp_t gfp_flags);
853
854 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
855 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
856
857 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
858 struct mv_cesa_dma_iter *dma_iter,
859 struct mv_cesa_sg_dma_iter *sgiter,
860 gfp_t gfp_flags);
861
862 /* Algorithm definitions */
863
864 extern struct ahash_alg mv_md5_alg;
865 extern struct ahash_alg mv_sha1_alg;
866 extern struct ahash_alg mv_sha256_alg;
867 extern struct ahash_alg mv_ahmac_md5_alg;
868 extern struct ahash_alg mv_ahmac_sha1_alg;
869 extern struct ahash_alg mv_ahmac_sha256_alg;
870
871 extern struct crypto_alg mv_cesa_ecb_des_alg;
872 extern struct crypto_alg mv_cesa_cbc_des_alg;
873 extern struct crypto_alg mv_cesa_ecb_des3_ede_alg;
874 extern struct crypto_alg mv_cesa_cbc_des3_ede_alg;
875 extern struct crypto_alg mv_cesa_ecb_aes_alg;
876 extern struct crypto_alg mv_cesa_cbc_aes_alg;
877
878 #endif /* __MARVELL_CESA_H__ */
Linux with added FPC-III support