2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 #ifndef ADF_C3XXX_HW_DATA_H_
48 #define ADF_C3XXX_HW_DATA_H_
50 /* PCIe configuration space */
51 #define ADF_C3XXX_PMISC_BAR 0
52 #define ADF_C3XXX_ETR_BAR 1
53 #define ADF_C3XXX_RX_RINGS_OFFSET 8
54 #define ADF_C3XXX_TX_RINGS_MASK 0xFF
55 #define ADF_C3XXX_MAX_ACCELERATORS 3
56 #define ADF_C3XXX_MAX_ACCELENGINES 6
57 #define ADF_C3XXX_ACCELERATORS_REG_OFFSET 16
58 #define ADF_C3XXX_ACCELERATORS_MASK 0x7
59 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F
60 #define ADF_C3XXX_ETR_MAX_BANKS 16
61 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
62 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
63 #define ADF_C3XXX_SMIA0_MASK 0xFFFF
64 #define ADF_C3XXX_SMIA1_MASK 0x1
65 /* Error detection and correction */
66 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
67 #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
68 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
69 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
70 #define ADF_C3XXX_UERRSSMSH(i) (i * 0x4000 + 0x18)
71 #define ADF_C3XXX_CERRSSMSH(i) (i * 0x4000 + 0x10)
72 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
74 #define ADF_C3XXX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
75 #define ADF_C3XXX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i) * 0x04))
78 #define ADF_C3XXX_FW "qat_c3xxx.bin"
79 #define ADF_C3XXX_MMP "qat_c3xxx_mmp.bin"
81 void adf_init_hw_data_c3xxx(struct adf_hw_device_data
*hw_data
);
82 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data
*hw_data
);