drivers/dma/dw/regs.h

   1 /*
   2  * Driver for the Synopsys DesignWare AHB DMA Controller
   3  *
   4  * Copyright (C) 2005-2007 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/dmaengine.h>
  14
  15 #include "internal.h"
  16
  17 #define DW_DMA_MAX_NR_REQUESTS  16
  18
  19 /* flow controller */
  20 enum dw_dma_fc {
  21         DW_DMA_FC_D_M2M,
  22         DW_DMA_FC_D_M2P,
  23         DW_DMA_FC_D_P2M,
  24         DW_DMA_FC_D_P2P,
  25         DW_DMA_FC_P_P2M,
  26         DW_DMA_FC_SP_P2P,
  27         DW_DMA_FC_P_M2P,
  28         DW_DMA_FC_DP_P2P,
  29 };
  30
  31 /*
  32  * Redefine this macro to handle differences between 32- and 64-bit
  33  * addressing, big vs. little endian, etc.
  34  */
  35 #define DW_REG(name)            u32 name; u32 __pad_##name
  36
  37 /* Hardware register definitions. */
  38 struct dw_dma_chan_regs {
  39         DW_REG(SAR);            /* Source Address Register */
  40         DW_REG(DAR);            /* Destination Address Register */
  41         DW_REG(LLP);            /* Linked List Pointer */
  42         u32     CTL_LO;         /* Control Register Low */
  43         u32     CTL_HI;         /* Control Register High */
  44         DW_REG(SSTAT);
  45         DW_REG(DSTAT);
  46         DW_REG(SSTATAR);
  47         DW_REG(DSTATAR);
  48         u32     CFG_LO;         /* Configuration Register Low */
  49         u32     CFG_HI;         /* Configuration Register High */
  50         DW_REG(SGR);
  51         DW_REG(DSR);
  52 };
  53
  54 struct dw_dma_irq_regs {
  55         DW_REG(XFER);
  56         DW_REG(BLOCK);
  57         DW_REG(SRC_TRAN);
  58         DW_REG(DST_TRAN);
  59         DW_REG(ERROR);
  60 };
  61
  62 struct dw_dma_regs {
  63         /* per-channel registers */
  64         struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
  65
  66         /* irq handling */
  67         struct dw_dma_irq_regs  RAW;            /* r */
  68         struct dw_dma_irq_regs  STATUS;         /* r (raw & mask) */
  69         struct dw_dma_irq_regs  MASK;           /* rw (set = irq enabled) */
  70         struct dw_dma_irq_regs  CLEAR;          /* w (ack, affects "raw") */
  71
  72         DW_REG(STATUS_INT);                     /* r */
  73
  74         /* software handshaking */
  75         DW_REG(REQ_SRC);
  76         DW_REG(REQ_DST);
  77         DW_REG(SGL_REQ_SRC);
  78         DW_REG(SGL_REQ_DST);
  79         DW_REG(LAST_SRC);
  80         DW_REG(LAST_DST);
  81
  82         /* miscellaneous */
  83         DW_REG(CFG);
  84         DW_REG(CH_EN);
  85         DW_REG(ID);
  86         DW_REG(TEST);
  87
  88         /* reserved */
  89         DW_REG(__reserved0);
  90         DW_REG(__reserved1);
  91
  92         /* optional encoded params, 0x3c8..0x3f7 */
  93         u32     __reserved;
  94
  95         /* per-channel configuration registers */
  96         u32     DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
  97         u32     MULTI_BLK_TYPE;
  98         u32     MAX_BLK_SIZE;
  99
 100         /* top-level parameters */
 101         u32     DW_PARAMS;
 102 };
 103
 104 /*
 105  * Big endian I/O access when reading and writing to the DMA controller
 106  * registers.  This is needed on some platforms, like the Atmel AVR32
 107  * architecture.
 108  */
 109
 110 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 111 #define dma_readl_native ioread32be
 112 #define dma_writel_native iowrite32be
 113 #else
 114 #define dma_readl_native readl
 115 #define dma_writel_native writel
 116 #endif
 117
 118 /* Bitfields in DW_PARAMS */
 119 #define DW_PARAMS_NR_CHAN       8               /* number of channels */
 120 #define DW_PARAMS_NR_MASTER     11              /* number of AHB masters */
 121 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
 122 #define DW_PARAMS_DATA_WIDTH1   15              /* master 1 data width */
 123 #define DW_PARAMS_DATA_WIDTH2   17              /* master 2 data width */
 124 #define DW_PARAMS_DATA_WIDTH3   19              /* master 3 data width */
 125 #define DW_PARAMS_DATA_WIDTH4   21              /* master 4 data width */
 126 #define DW_PARAMS_EN            28              /* encoded parameters */
 127
 128 /* Bitfields in DWC_PARAMS */
 129 #define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
 130
 131 /* bursts size */
 132 enum dw_dma_msize {
 133         DW_DMA_MSIZE_1,
 134         DW_DMA_MSIZE_4,
 135         DW_DMA_MSIZE_8,
 136         DW_DMA_MSIZE_16,
 137         DW_DMA_MSIZE_32,
 138         DW_DMA_MSIZE_64,
 139         DW_DMA_MSIZE_128,
 140         DW_DMA_MSIZE_256,
 141 };
 142
 143 /* Bitfields in LLP */
 144 #define DWC_LLP_LMS(x)          ((x) & 3)       /* list master select */
 145 #define DWC_LLP_LOC(x)          ((x) & ~3)      /* next lli */
 146
 147 /* Bitfields in CTL_LO */
 148 #define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 149 #define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
 150 #define DWC_CTLL_SRC_WIDTH(n)   ((n)<<4)
 151 #define DWC_CTLL_DST_INC        (0<<7)          /* DAR update/not */
 152 #define DWC_CTLL_DST_DEC        (1<<7)
 153 #define DWC_CTLL_DST_FIX        (2<<7)
 154 #define DWC_CTLL_SRC_INC        (0<<9)          /* SAR update/not */
 155 #define DWC_CTLL_SRC_DEC        (1<<9)
 156 #define DWC_CTLL_SRC_FIX        (2<<9)
 157 #define DWC_CTLL_DST_MSIZE(n)   ((n)<<11)       /* burst, #elements */
 158 #define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
 159 #define DWC_CTLL_S_GATH_EN      (1 << 17)       /* src gather, !FIX */
 160 #define DWC_CTLL_D_SCAT_EN      (1 << 18)       /* dst scatter, !FIX */
 161 #define DWC_CTLL_FC(n)          ((n) << 20)
 162 #define DWC_CTLL_FC_M2M         (0 << 20)       /* mem-to-mem */
 163 #define DWC_CTLL_FC_M2P         (1 << 20)       /* mem-to-periph */
 164 #define DWC_CTLL_FC_P2M         (2 << 20)       /* periph-to-mem */
 165 #define DWC_CTLL_FC_P2P         (3 << 20)       /* periph-to-periph */
 166 /* plus 4 transfer types for peripheral-as-flow-controller */
 167 #define DWC_CTLL_DMS(n)         ((n)<<23)       /* dst master select */
 168 #define DWC_CTLL_SMS(n)         ((n)<<25)       /* src master select */
 169 #define DWC_CTLL_LLP_D_EN       (1 << 27)       /* dest block chain */
 170 #define DWC_CTLL_LLP_S_EN       (1 << 28)       /* src block chain */
 171
 172 /* Bitfields in CTL_HI */
 173 #define DWC_CTLH_DONE           0x00001000
 174 #define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 175
 176 /* Bitfields in CFG_LO */
 177 #define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
 178 #define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 179 #define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 180 #define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 181 #define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
 182 #define DWC_CFGL_HS_SRC         (1 << 11)       /* handshake w/src */
 183 #define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
 184 #define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
 185 #define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
 186 #define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
 187 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
 188 #define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
 189 #define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
 190 #define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
 191 #define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
 192 #define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
 193 #define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
 194 #define DWC_CFGL_RELOAD_SAR     (1 << 30)
 195 #define DWC_CFGL_RELOAD_DAR     (1 << 31)
 196
 197 /* Bitfields in CFG_HI */
 198 #define DWC_CFGH_FCMODE         (1 << 0)
 199 #define DWC_CFGH_FIFO_MODE      (1 << 1)
 200 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
 201 #define DWC_CFGH_DS_UPD_EN      (1 << 5)
 202 #define DWC_CFGH_SS_UPD_EN      (1 << 6)
 203 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
 204 #define DWC_CFGH_DST_PER(x)     ((x) << 11)
 205
 206 /* Bitfields in SGR */
 207 #define DWC_SGR_SGI(x)          ((x) << 0)
 208 #define DWC_SGR_SGC(x)          ((x) << 20)
 209
 210 /* Bitfields in DSR */
 211 #define DWC_DSR_DSI(x)          ((x) << 0)
 212 #define DWC_DSR_DSC(x)          ((x) << 20)
 213
 214 /* Bitfields in CFG */
 215 #define DW_CFG_DMA_EN           (1 << 0)
 216
 217 enum dw_dmac_flags {
 218         DW_DMA_IS_CYCLIC = 0,
 219         DW_DMA_IS_SOFT_LLP = 1,
 220         DW_DMA_IS_PAUSED = 2,
 221         DW_DMA_IS_INITIALIZED = 3,
 222 };
 223
 224 struct dw_dma_chan {
 225         struct dma_chan                 chan;
 226         void __iomem                    *ch_regs;
 227         u8                              mask;
 228         u8                              priority;
 229         enum dma_transfer_direction     direction;
 230
 231         /* software emulation of the LLP transfers */
 232         struct list_head        *tx_node_active;
 233
 234         spinlock_t              lock;
 235
 236         /* these other elements are all protected by lock */
 237         unsigned long           flags;
 238         struct list_head        active_list;
 239         struct list_head        queue;
 240         struct dw_cyclic_desc   *cdesc;
 241
 242         unsigned int            descs_allocated;
 243
 244         /* hardware configuration */
 245         unsigned int            block_size;
 246         bool                    nollp;
 247
 248         /* custom slave configuration */
 249         struct dw_dma_slave     dws;
 250
 251         /* configuration passed via .device_config */
 252         struct dma_slave_config dma_sconfig;
 253 };
 254
 255 static inline struct dw_dma_chan_regs __iomem *
 256 __dwc_regs(struct dw_dma_chan *dwc)
 257 {
 258         return dwc->ch_regs;
 259 }
 260
 261 #define channel_readl(dwc, name) \
 262         dma_readl_native(&(__dwc_regs(dwc)->name))
 263 #define channel_writel(dwc, name, val) \
 264         dma_writel_native((val), &(__dwc_regs(dwc)->name))
 265
 266 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
 267 {
 268         return container_of(chan, struct dw_dma_chan, chan);
 269 }
 270
 271 struct dw_dma {
 272         struct dma_device       dma;
 273         void __iomem            *regs;
 274         struct dma_pool         *desc_pool;
 275         struct tasklet_struct   tasklet;
 276
 277         /* channels */
 278         struct dw_dma_chan      *chan;
 279         u8                      all_chan_mask;
 280         u8                      in_use;
 281
 282         /* platform data */
 283         struct dw_dma_platform_data     *pdata;
 284 };
 285
 286 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
 287 {
 288         return dw->regs;
 289 }
 290
 291 #define dma_readl(dw, name) \
 292         dma_readl_native(&(__dw_regs(dw)->name))
 293 #define dma_writel(dw, name, val) \
 294         dma_writel_native((val), &(__dw_regs(dw)->name))
 295
 296 #define channel_set_bit(dw, reg, mask) \
 297         dma_writel(dw, reg, ((mask) << 8) | (mask))
 298 #define channel_clear_bit(dw, reg, mask) \
 299         dma_writel(dw, reg, ((mask) << 8) | 0)
 300
 301 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 302 {
 303         return container_of(ddev, struct dw_dma, dma);
 304 }
 305
 306 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 307 typedef __be32 __dw32;
 308 #else
 309 typedef __le32 __dw32;
 310 #endif
 311
 312 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
 313 struct dw_lli {
 314         /* values that are not changed by hardware */
 315         __dw32          sar;
 316         __dw32          dar;
 317         __dw32          llp;            /* chain to next lli */
 318         __dw32          ctllo;
 319         /* values that may get written back: */
 320         __dw32          ctlhi;
 321         /* sstat and dstat can snapshot peripheral register state.
 322          * silicon config may discard either or both...
 323          */
 324         __dw32          sstat;
 325         __dw32          dstat;
 326 };
 327
 328 struct dw_desc {
 329         /* FIRST values the hardware uses */
 330         struct dw_lli                   lli;
 331
 332 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 333 #define lli_set(d, reg, v)              ((d)->lli.reg |= cpu_to_be32(v))
 334 #define lli_clear(d, reg, v)            ((d)->lli.reg &= ~cpu_to_be32(v))
 335 #define lli_read(d, reg)                be32_to_cpu((d)->lli.reg)
 336 #define lli_write(d, reg, v)            ((d)->lli.reg = cpu_to_be32(v))
 337 #else
 338 #define lli_set(d, reg, v)              ((d)->lli.reg |= cpu_to_le32(v))
 339 #define lli_clear(d, reg, v)            ((d)->lli.reg &= ~cpu_to_le32(v))
 340 #define lli_read(d, reg)                le32_to_cpu((d)->lli.reg)
 341 #define lli_write(d, reg, v)            ((d)->lli.reg = cpu_to_le32(v))
 342 #endif
 343
 344         /* THEN values for driver housekeeping */
 345         struct list_head                desc_node;
 346         struct list_head                tx_list;
 347         struct dma_async_tx_descriptor  txd;
 348         size_t                          len;
 349         size_t                          total_len;
 350         u32                             residue;
 351 };
 352
 353 #define to_dw_desc(h)   list_entry(h, struct dw_desc, desc_node)
 354
 355 static inline struct dw_desc *
 356 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
 357 {
 358         return container_of(txd, struct dw_desc, txd);
 359 }