drivers/dma/qcom/hidma.h

   1 /*
   2  * Qualcomm Technologies HIDMA data structures
   3  *
   4  * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef QCOM_HIDMA_H
  17 #define QCOM_HIDMA_H
  18
  19 #include <linux/kfifo.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/dmaengine.h>
  22
  23 #define HIDMA_TRE_SIZE                  32 /* each TRE is 32 bytes  */
  24 #define HIDMA_TRE_CFG_IDX               0
  25 #define HIDMA_TRE_LEN_IDX               1
  26 #define HIDMA_TRE_SRC_LOW_IDX           2
  27 #define HIDMA_TRE_SRC_HI_IDX            3
  28 #define HIDMA_TRE_DEST_LOW_IDX          4
  29 #define HIDMA_TRE_DEST_HI_IDX           5
  30
  31 struct hidma_tre {
  32         atomic_t allocated;             /* if this channel is allocated     */
  33         bool queued;                    /* flag whether this is pending     */
  34         u16 status;                     /* status                           */
  35         u32 idx;                        /* index of the tre                 */
  36         u32 dma_sig;                    /* signature of the tre             */
  37         const char *dev_name;           /* name of the device               */
  38         void (*callback)(void *data);   /* requester callback               */
  39         void *data;                     /* Data associated with this channel*/
  40         struct hidma_lldev *lldev;      /* lldma device pointer             */
  41         u32 tre_local[HIDMA_TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy  */
  42         u32 tre_index;                  /* the offset where this was written*/
  43         u32 int_flags;                  /* interrupt flags                  */
  44         u8 err_info;                    /* error record in this transfer    */
  45         u8 err_code;                    /* completion code                  */
  46 };
  47
  48 struct hidma_lldev {
  49         bool msi_support;               /* flag indicating MSI support    */
  50         bool initialized;               /* initialized flag               */
  51         u8 trch_state;                  /* trch_state of the device       */
  52         u8 evch_state;                  /* evch_state of the device       */
  53         u8 chidx;                       /* channel index in the core      */
  54         u32 nr_tres;                    /* max number of configs          */
  55         spinlock_t lock;                /* reentrancy                     */
  56         struct hidma_tre *trepool;      /* trepool of user configs */
  57         struct device *dev;             /* device                         */
  58         void __iomem *trca;             /* Transfer Channel address       */
  59         void __iomem *evca;             /* Event Channel address          */
  60         struct hidma_tre
  61                 **pending_tre_list;     /* Pointers to pending TREs       */
  62         atomic_t pending_tre_count;     /* Number of TREs pending         */
  63
  64         void *tre_ring;                 /* TRE ring                       */
  65         dma_addr_t tre_dma;             /* TRE ring to be shared with HW  */
  66         u32 tre_ring_size;              /* Byte size of the ring          */
  67         u32 tre_processed_off;          /* last processed TRE             */
  68
  69         void *evre_ring;                /* EVRE ring                       */
  70         dma_addr_t evre_dma;            /* EVRE ring to be shared with HW  */
  71         u32 evre_ring_size;             /* Byte size of the ring           */
  72         u32 evre_processed_off;         /* last processed EVRE             */
  73
  74         u32 tre_write_offset;           /* TRE write location              */
  75         struct tasklet_struct task;     /* task delivering notifications   */
  76         DECLARE_KFIFO_PTR(handoff_fifo,
  77                 struct hidma_tre *);    /* pending TREs FIFO               */
  78 };
  79
  80 struct hidma_desc {
  81         struct dma_async_tx_descriptor  desc;
  82         /* link list node for this channel*/
  83         struct list_head                node;
  84         u32                             tre_ch;
  85 };
  86
  87 struct hidma_chan {
  88         bool                            paused;
  89         bool                            allocated;
  90         char                            dbg_name[16];
  91         u32                             dma_sig;
  92         dma_cookie_t                    last_success;
  93
  94         /*
  95          * active descriptor on this channel
  96          * It is used by the DMA complete notification to
  97          * locate the descriptor that initiated the transfer.
  98          */
  99         struct dentry                   *debugfs;
 100         struct dentry                   *stats;
 101         struct hidma_dev                *dmadev;
 102         struct hidma_desc               *running;
 103
 104         struct dma_chan                 chan;
 105         struct list_head                free;
 106         struct list_head                prepared;
 107         struct list_head                active;
 108         struct list_head                completed;
 109
 110         /* Lock for this structure */
 111         spinlock_t                      lock;
 112 };
 113
 114 struct hidma_dev {
 115         int                             irq;
 116         int                             chidx;
 117         u32                             nr_descriptors;
 118         int                             msi_virqbase;
 119
 120         struct hidma_lldev              *lldev;
 121         void                            __iomem *dev_trca;
 122         struct resource                 *trca_resource;
 123         void                            __iomem *dev_evca;
 124         struct resource                 *evca_resource;
 125
 126         /* used to protect the pending channel list*/
 127         spinlock_t                      lock;
 128         struct dma_device               ddev;
 129
 130         struct dentry                   *debugfs;
 131         struct dentry                   *stats;
 132
 133         /* sysfs entry for the channel id */
 134         struct device_attribute         *chid_attrs;
 135
 136         /* Task delivering issue_pending */
 137         struct tasklet_struct           task;
 138 };
 139
 140 int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id,
 141                         const char *dev_name,
 142                         void (*callback)(void *data), void *data, u32 *tre_ch);
 143
 144 void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch);
 145 enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch);
 146 bool hidma_ll_isenabled(struct hidma_lldev *llhndl);
 147 void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch);
 148 void hidma_ll_start(struct hidma_lldev *llhndl);
 149 int hidma_ll_disable(struct hidma_lldev *lldev);
 150 int hidma_ll_enable(struct hidma_lldev *llhndl);
 151 void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch,
 152         dma_addr_t src, dma_addr_t dest, u32 len, u32 flags);
 153 void hidma_ll_setup_irq(struct hidma_lldev *lldev, bool msi);
 154 int hidma_ll_setup(struct hidma_lldev *lldev);
 155 struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
 156                         void __iomem *trca, void __iomem *evca,
 157                         u8 chidx);
 158 int hidma_ll_uninit(struct hidma_lldev *llhndl);
 159 irqreturn_t hidma_ll_inthandler(int irq, void *arg);
 160 irqreturn_t hidma_ll_inthandler_msi(int irq, void *arg, int cause);
 161 void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
 162                                 u8 err_code);
 163 int hidma_debug_init(struct hidma_dev *dmadev);
 164 void hidma_debug_uninit(struct hidma_dev *dmadev);
 165 #endif