2 * Applied Micro X-Gene SoC DMA engine Driver
4 * Copyright (c) 2015, Applied Micro Circuits Corporation
5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 * NOTE: PM support is currently not available.
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dmapool.h>
30 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/module.h>
34 #include <linux/of_device.h>
36 #include "dmaengine.h"
38 /* X-Gene DMA ring csr registers and bit definations */
39 #define XGENE_DMA_RING_CONFIG 0x04
40 #define XGENE_DMA_RING_ENABLE BIT(31)
41 #define XGENE_DMA_RING_ID 0x08
42 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
43 #define XGENE_DMA_RING_ID_BUF 0x0C
44 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
45 #define XGENE_DMA_RING_THRESLD0_SET1 0x30
46 #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
47 #define XGENE_DMA_RING_THRESLD1_SET1 0x34
48 #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
49 #define XGENE_DMA_RING_HYSTERESIS 0x68
50 #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
51 #define XGENE_DMA_RING_STATE 0x6C
52 #define XGENE_DMA_RING_STATE_WR_BASE 0x70
53 #define XGENE_DMA_RING_NE_INT_MODE 0x017C
54 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
55 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
56 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
57 ((m) &= (~BIT(31 - (v))))
58 #define XGENE_DMA_RING_CLKEN 0xC208
59 #define XGENE_DMA_RING_SRST 0xC200
60 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
61 #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
62 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
63 #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
64 #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
65 #define XGENE_DMA_RING_CMD_OFFSET 0x2C
66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
67 #define XGENE_DMA_RING_COHERENT_SET(m) \
68 (((u32 *)(m))[2] |= BIT(4))
69 #define XGENE_DMA_RING_ADDRL_SET(m, v) \
70 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
71 #define XGENE_DMA_RING_ADDRH_SET(m, v) \
72 (((u32 *)(m))[3] |= ((v) >> 35))
73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
74 (((u32 *)(m))[3] |= BIT(19))
75 #define XGENE_DMA_RING_SIZE_SET(m, v) \
76 (((u32 *)(m))[3] |= ((v) << 23))
77 #define XGENE_DMA_RING_RECOMBBUF_SET(m) \
78 (((u32 *)(m))[3] |= BIT(27))
79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
80 (((u32 *)(m))[3] |= (0x7 << 28))
81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
82 (((u32 *)(m))[4] |= 0x3)
83 #define XGENE_DMA_RING_SELTHRSH_SET(m) \
84 (((u32 *)(m))[4] |= BIT(3))
85 #define XGENE_DMA_RING_TYPE_SET(m, v) \
86 (((u32 *)(m))[4] |= ((v) << 19))
88 /* X-Gene DMA device csr registers and bit definitions */
89 #define XGENE_DMA_IPBRR 0x0
90 #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
91 #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
92 #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
93 #define XGENE_DMA_GCR 0x10
94 #define XGENE_DMA_CH_SETUP(v) \
95 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
96 #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
97 #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
98 #define XGENE_DMA_RAID6_CONT 0x14
99 #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
100 #define XGENE_DMA_INT 0x70
101 #define XGENE_DMA_INT_MASK 0x74
102 #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
103 #define XGENE_DMA_INT_ALL_UNMASK 0x0
104 #define XGENE_DMA_INT_MASK_SHIFT 0x14
105 #define XGENE_DMA_RING_INT0_MASK 0x90A0
106 #define XGENE_DMA_RING_INT1_MASK 0x90A8
107 #define XGENE_DMA_RING_INT2_MASK 0x90B0
108 #define XGENE_DMA_RING_INT3_MASK 0x90B8
109 #define XGENE_DMA_RING_INT4_MASK 0x90C0
110 #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
111 #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
112 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
113 #define XGENE_DMA_BLK_MEM_RDY 0xD074
114 #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
115 #define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
117 /* X-Gene SoC EFUSE csr register and bit defination */
118 #define XGENE_SOC_JTAG1_SHADOW 0x18
119 #define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
121 /* X-Gene DMA Descriptor format */
122 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
123 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
124 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
125 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
126 #define XGENE_DMA_DESC_ELERR_POS 46
127 #define XGENE_DMA_DESC_RTYPE_POS 56
128 #define XGENE_DMA_DESC_LERR_POS 60
129 #define XGENE_DMA_DESC_BUFLEN_POS 48
130 #define XGENE_DMA_DESC_HOENQ_NUM_POS 48
131 #define XGENE_DMA_DESC_ELERR_RD(m) \
132 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
133 #define XGENE_DMA_DESC_LERR_RD(m) \
134 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
135 #define XGENE_DMA_DESC_STATUS(elerr, lerr) \
136 (((elerr) << 4) | (lerr))
138 /* X-Gene DMA descriptor empty s/w signature */
139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
141 /* X-Gene DMA configurable parameters defines */
142 #define XGENE_DMA_RING_NUM 512
143 #define XGENE_DMA_BUFNUM 0x0
144 #define XGENE_DMA_CPU_BUFNUM 0x18
145 #define XGENE_DMA_RING_OWNER_DMA 0x03
146 #define XGENE_DMA_RING_OWNER_CPU 0x0F
147 #define XGENE_DMA_RING_TYPE_REGULAR 0x01
148 #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
149 #define XGENE_DMA_RING_NUM_CONFIG 5
150 #define XGENE_DMA_MAX_CHANNEL 4
151 #define XGENE_DMA_XOR_CHANNEL 0
152 #define XGENE_DMA_PQ_CHANNEL 1
153 #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
155 #define XGENE_DMA_MAX_XOR_SRC 5
156 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
157 #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
159 /* X-Gene DMA descriptor error codes */
160 #define ERR_DESC_AXI 0x01
161 #define ERR_BAD_DESC 0x02
162 #define ERR_READ_DATA_AXI 0x03
163 #define ERR_WRITE_DATA_AXI 0x04
164 #define ERR_FBP_TIMEOUT 0x05
166 #define ERR_DIFF_SIZE 0x08
167 #define ERR_SCT_GAT_LEN 0x09
168 #define ERR_CRC_ERR 0x11
169 #define ERR_CHKSUM 0x12
172 /* X-Gene DMA error interrupt codes */
173 #define ERR_DIF_SIZE_INT 0x0
174 #define ERR_GS_ERR_INT 0x1
175 #define ERR_FPB_TIMEO_INT 0x2
176 #define ERR_WFIFO_OVF_INT 0x3
177 #define ERR_RFIFO_OVF_INT 0x4
178 #define ERR_WR_TIMEO_INT 0x5
179 #define ERR_RD_TIMEO_INT 0x6
180 #define ERR_WR_ERR_INT 0x7
181 #define ERR_RD_ERR_INT 0x8
182 #define ERR_BAD_DESC_INT 0x9
183 #define ERR_DESC_DST_INT 0xA
184 #define ERR_DESC_SRC_INT 0xB
186 /* X-Gene DMA flyby operation code */
187 #define FLYBY_2SRC_XOR 0x80
188 #define FLYBY_3SRC_XOR 0x90
189 #define FLYBY_4SRC_XOR 0xA0
190 #define FLYBY_5SRC_XOR 0xB0
192 /* X-Gene DMA SW descriptor flags */
193 #define XGENE_DMA_FLAG_64B_DESC BIT(0)
195 /* Define to dump X-Gene DMA descriptor */
196 #define XGENE_DMA_DESC_DUMP(desc, m) \
197 print_hex_dump(KERN_ERR, (m), \
198 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
200 #define to_dma_desc_sw(tx) \
201 container_of(tx, struct xgene_dma_desc_sw, tx)
202 #define to_dma_chan(dchan) \
203 container_of(dchan, struct xgene_dma_chan, dma_chan)
205 #define chan_dbg(chan, fmt, arg...) \
206 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
207 #define chan_err(chan, fmt, arg...) \
208 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
210 struct xgene_dma_desc_hw
{
217 enum xgene_dma_ring_cfgsize
{
218 XGENE_DMA_RING_CFG_SIZE_512B
,
219 XGENE_DMA_RING_CFG_SIZE_2KB
,
220 XGENE_DMA_RING_CFG_SIZE_16KB
,
221 XGENE_DMA_RING_CFG_SIZE_64KB
,
222 XGENE_DMA_RING_CFG_SIZE_512KB
,
223 XGENE_DMA_RING_CFG_SIZE_INVALID
226 struct xgene_dma_ring
{
227 struct xgene_dma
*pdma
;
237 void __iomem
*cmd_base
;
238 dma_addr_t desc_paddr
;
239 u32 state
[XGENE_DMA_RING_NUM_CONFIG
];
240 enum xgene_dma_ring_cfgsize cfgsize
;
243 struct xgene_dma_desc_hw
*desc_hw
;
247 struct xgene_dma_desc_sw
{
248 struct xgene_dma_desc_hw desc1
;
249 struct xgene_dma_desc_hw desc2
;
251 struct list_head node
;
252 struct list_head tx_list
;
253 struct dma_async_tx_descriptor tx
;
257 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
258 * @dma_chan: dmaengine channel object member
259 * @pdma: X-Gene DMA device structure reference
260 * @dev: struct device reference for dma mapping api
261 * @id: raw id of this channel
262 * @rx_irq: channel IRQ
263 * @name: name of X-Gene DMA channel
264 * @lock: serializes enqueue/dequeue operations to the descriptor pool
265 * @pending: number of transaction request pushed to DMA controller for
266 * execution, but still waiting for completion,
267 * @max_outstanding: max number of outstanding request we can push to channel
268 * @ld_pending: descriptors which are queued to run, but have not yet been
269 * submitted to the hardware for execution
270 * @ld_running: descriptors which are currently being executing by the hardware
271 * @ld_completed: descriptors which have finished execution by the hardware.
272 * These descriptors have already had their cleanup actions run. They
273 * are waiting for the ACK bit to be set by the async tx API.
274 * @desc_pool: descriptor pool for DMA operations
275 * @tasklet: bottom half where all completed descriptors cleans
276 * @tx_ring: transmit ring descriptor that we use to prepare actual
277 * descriptors for further executions
278 * @rx_ring: receive ring descriptor that we use to get completed DMA
279 * descriptors during cleanup time
281 struct xgene_dma_chan
{
282 struct dma_chan dma_chan
;
283 struct xgene_dma
*pdma
;
291 struct list_head ld_pending
;
292 struct list_head ld_running
;
293 struct list_head ld_completed
;
294 struct dma_pool
*desc_pool
;
295 struct tasklet_struct tasklet
;
296 struct xgene_dma_ring tx_ring
;
297 struct xgene_dma_ring rx_ring
;
301 * struct xgene_dma - internal representation of an X-Gene DMA device
302 * @err_irq: DMA error irq number
303 * @ring_num: start id number for DMA ring
304 * @csr_dma: base for DMA register access
305 * @csr_ring: base for DMA ring register access
306 * @csr_ring_cmd: base for DMA ring command register access
307 * @csr_efuse: base for efuse register access
308 * @dma_dev: embedded struct dma_device
309 * @chan: reference to X-Gene DMA channels
316 void __iomem
*csr_dma
;
317 void __iomem
*csr_ring
;
318 void __iomem
*csr_ring_cmd
;
319 void __iomem
*csr_efuse
;
320 struct dma_device dma_dev
[XGENE_DMA_MAX_CHANNEL
];
321 struct xgene_dma_chan chan
[XGENE_DMA_MAX_CHANNEL
];
324 static const char * const xgene_dma_desc_err
[] = {
325 [ERR_DESC_AXI
] = "AXI error when reading src/dst link list",
326 [ERR_BAD_DESC
] = "ERR or El_ERR fields not set to zero in desc",
327 [ERR_READ_DATA_AXI
] = "AXI error when reading data",
328 [ERR_WRITE_DATA_AXI
] = "AXI error when writing data",
329 [ERR_FBP_TIMEOUT
] = "Timeout on bufpool fetch",
330 [ERR_ECC
] = "ECC double bit error",
331 [ERR_DIFF_SIZE
] = "Bufpool too small to hold all the DIF result",
332 [ERR_SCT_GAT_LEN
] = "Gather and scatter data length not same",
333 [ERR_CRC_ERR
] = "CRC error",
334 [ERR_CHKSUM
] = "Checksum error",
335 [ERR_DIF
] = "DIF error",
338 static const char * const xgene_dma_err
[] = {
339 [ERR_DIF_SIZE_INT
] = "DIF size error",
340 [ERR_GS_ERR_INT
] = "Gather scatter not same size error",
341 [ERR_FPB_TIMEO_INT
] = "Free pool time out error",
342 [ERR_WFIFO_OVF_INT
] = "Write FIFO over flow error",
343 [ERR_RFIFO_OVF_INT
] = "Read FIFO over flow error",
344 [ERR_WR_TIMEO_INT
] = "Write time out error",
345 [ERR_RD_TIMEO_INT
] = "Read time out error",
346 [ERR_WR_ERR_INT
] = "HBF bus write error",
347 [ERR_RD_ERR_INT
] = "HBF bus read error",
348 [ERR_BAD_DESC_INT
] = "Ring descriptor HE0 not set error",
349 [ERR_DESC_DST_INT
] = "HFB reading dst link address error",
350 [ERR_DESC_SRC_INT
] = "HFB reading src link address error",
353 static bool is_pq_enabled(struct xgene_dma
*pdma
)
357 val
= ioread32(pdma
->csr_efuse
+ XGENE_SOC_JTAG1_SHADOW
);
358 return !(val
& XGENE_DMA_PQ_DISABLE_MASK
);
361 static u64
xgene_dma_encode_len(size_t len
)
363 return (len
< XGENE_DMA_MAX_BYTE_CNT
) ?
364 ((u64
)len
<< XGENE_DMA_DESC_BUFLEN_POS
) :
365 XGENE_DMA_16K_BUFFER_LEN_CODE
;
368 static u8
xgene_dma_encode_xor_flyby(u32 src_cnt
)
370 static u8 flyby_type
[] = {
371 FLYBY_2SRC_XOR
, /* Dummy */
372 FLYBY_2SRC_XOR
, /* Dummy */
379 return flyby_type
[src_cnt
];
382 static void xgene_dma_set_src_buffer(__le64
*ext8
, size_t *len
,
385 size_t nbytes
= (*len
< XGENE_DMA_MAX_BYTE_CNT
) ?
386 *len
: XGENE_DMA_MAX_BYTE_CNT
;
388 *ext8
|= cpu_to_le64(*paddr
);
389 *ext8
|= cpu_to_le64(xgene_dma_encode_len(nbytes
));
394 static void xgene_dma_invalidate_buffer(__le64
*ext8
)
396 *ext8
|= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE
);
399 static __le64
*xgene_dma_lookup_ext8(struct xgene_dma_desc_hw
*desc
, int idx
)
411 pr_err("Invalid dma descriptor index\n");
417 static void xgene_dma_init_desc(struct xgene_dma_desc_hw
*desc
,
420 desc
->m0
|= cpu_to_le64(XGENE_DMA_DESC_IN_BIT
);
421 desc
->m0
|= cpu_to_le64((u64
)XGENE_DMA_RING_OWNER_DMA
<<
422 XGENE_DMA_DESC_RTYPE_POS
);
423 desc
->m1
|= cpu_to_le64(XGENE_DMA_DESC_C_BIT
);
424 desc
->m3
|= cpu_to_le64((u64
)dst_ring_num
<<
425 XGENE_DMA_DESC_HOENQ_NUM_POS
);
428 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan
*chan
,
429 struct xgene_dma_desc_sw
*desc_sw
,
430 dma_addr_t dst
, dma_addr_t src
,
433 struct xgene_dma_desc_hw
*desc1
, *desc2
;
436 /* Get 1st descriptor */
437 desc1
= &desc_sw
->desc1
;
438 xgene_dma_init_desc(desc1
, chan
->tx_ring
.dst_ring_num
);
440 /* Set destination address */
441 desc1
->m2
|= cpu_to_le64(XGENE_DMA_DESC_DR_BIT
);
442 desc1
->m3
|= cpu_to_le64(dst
);
444 /* Set 1st source address */
445 xgene_dma_set_src_buffer(&desc1
->m1
, &len
, &src
);
451 * We need to split this source buffer,
452 * and need to use 2nd descriptor
454 desc2
= &desc_sw
->desc2
;
455 desc1
->m0
|= cpu_to_le64(XGENE_DMA_DESC_NV_BIT
);
457 /* Set 2nd to 5th source address */
458 for (i
= 0; i
< 4 && len
; i
++)
459 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2
, i
),
462 /* Invalidate unused source address field */
464 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2
, i
));
466 /* Updated flag that we have prepared 64B descriptor */
467 desc_sw
->flags
|= XGENE_DMA_FLAG_64B_DESC
;
470 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan
*chan
,
471 struct xgene_dma_desc_sw
*desc_sw
,
472 dma_addr_t
*dst
, dma_addr_t
*src
,
473 u32 src_cnt
, size_t *nbytes
,
476 struct xgene_dma_desc_hw
*desc1
, *desc2
;
477 size_t len
= *nbytes
;
480 desc1
= &desc_sw
->desc1
;
481 desc2
= &desc_sw
->desc2
;
483 /* Initialize DMA descriptor */
484 xgene_dma_init_desc(desc1
, chan
->tx_ring
.dst_ring_num
);
486 /* Set destination address */
487 desc1
->m2
|= cpu_to_le64(XGENE_DMA_DESC_DR_BIT
);
488 desc1
->m3
|= cpu_to_le64(*dst
);
490 /* We have multiple source addresses, so need to set NV bit*/
491 desc1
->m0
|= cpu_to_le64(XGENE_DMA_DESC_NV_BIT
);
493 /* Set flyby opcode */
494 desc1
->m2
|= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt
));
496 /* Set 1st to 5th source addresses */
497 for (i
= 0; i
< src_cnt
; i
++) {
499 xgene_dma_set_src_buffer((i
== 0) ? &desc1
->m1
:
500 xgene_dma_lookup_ext8(desc2
, i
- 1),
502 desc1
->m2
|= cpu_to_le64((scf
[i
] << ((i
+ 1) * 8)));
505 /* Update meta data */
507 *dst
+= XGENE_DMA_MAX_BYTE_CNT
;
509 /* We need always 64B descriptor to perform xor or pq operations */
510 desc_sw
->flags
|= XGENE_DMA_FLAG_64B_DESC
;
513 static dma_cookie_t
xgene_dma_tx_submit(struct dma_async_tx_descriptor
*tx
)
515 struct xgene_dma_desc_sw
*desc
;
516 struct xgene_dma_chan
*chan
;
522 chan
= to_dma_chan(tx
->chan
);
523 desc
= to_dma_desc_sw(tx
);
525 spin_lock_bh(&chan
->lock
);
527 cookie
= dma_cookie_assign(tx
);
529 /* Add this transaction list onto the tail of the pending queue */
530 list_splice_tail_init(&desc
->tx_list
, &chan
->ld_pending
);
532 spin_unlock_bh(&chan
->lock
);
537 static void xgene_dma_clean_descriptor(struct xgene_dma_chan
*chan
,
538 struct xgene_dma_desc_sw
*desc
)
540 list_del(&desc
->node
);
541 chan_dbg(chan
, "LD %p free\n", desc
);
542 dma_pool_free(chan
->desc_pool
, desc
, desc
->tx
.phys
);
545 static struct xgene_dma_desc_sw
*xgene_dma_alloc_descriptor(
546 struct xgene_dma_chan
*chan
)
548 struct xgene_dma_desc_sw
*desc
;
551 desc
= dma_pool_zalloc(chan
->desc_pool
, GFP_NOWAIT
, &phys
);
553 chan_err(chan
, "Failed to allocate LDs\n");
557 INIT_LIST_HEAD(&desc
->tx_list
);
558 desc
->tx
.phys
= phys
;
559 desc
->tx
.tx_submit
= xgene_dma_tx_submit
;
560 dma_async_tx_descriptor_init(&desc
->tx
, &chan
->dma_chan
);
562 chan_dbg(chan
, "LD %p allocated\n", desc
);
568 * xgene_dma_clean_completed_descriptor - free all descriptors which
569 * has been completed and acked
570 * @chan: X-Gene DMA channel
572 * This function is used on all completed and acked descriptors.
574 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan
*chan
)
576 struct xgene_dma_desc_sw
*desc
, *_desc
;
578 /* Run the callback for each descriptor, in order */
579 list_for_each_entry_safe(desc
, _desc
, &chan
->ld_completed
, node
) {
580 if (async_tx_test_ack(&desc
->tx
))
581 xgene_dma_clean_descriptor(chan
, desc
);
586 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
587 * @chan: X-Gene DMA channel
588 * @desc: descriptor to cleanup and free
590 * This function is used on a descriptor which has been executed by the DMA
591 * controller. It will run any callbacks, submit any dependencies.
593 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan
*chan
,
594 struct xgene_dma_desc_sw
*desc
)
596 struct dma_async_tx_descriptor
*tx
= &desc
->tx
;
599 * If this is not the last transaction in the group,
600 * then no need to complete cookie and run any callback as
601 * this is not the tx_descriptor which had been sent to caller
602 * of this DMA request
608 dma_cookie_complete(tx
);
609 dma_descriptor_unmap(tx
);
611 /* Run the link descriptor callback function */
612 dmaengine_desc_get_callback_invoke(tx
, NULL
);
614 /* Run any dependencies */
615 dma_run_dependencies(tx
);
619 * xgene_dma_clean_running_descriptor - move the completed descriptor from
620 * ld_running to ld_completed
621 * @chan: X-Gene DMA channel
622 * @desc: the descriptor which is completed
624 * Free the descriptor directly if acked by async_tx api,
625 * else move it to queue ld_completed.
627 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan
*chan
,
628 struct xgene_dma_desc_sw
*desc
)
630 /* Remove from the list of running transactions */
631 list_del(&desc
->node
);
634 * the client is allowed to attach dependent operations
637 if (!async_tx_test_ack(&desc
->tx
)) {
639 * Move this descriptor to the list of descriptors which is
640 * completed, but still awaiting the 'ack' bit to be set.
642 list_add_tail(&desc
->node
, &chan
->ld_completed
);
646 chan_dbg(chan
, "LD %p free\n", desc
);
647 dma_pool_free(chan
->desc_pool
, desc
, desc
->tx
.phys
);
650 static void xgene_chan_xfer_request(struct xgene_dma_chan
*chan
,
651 struct xgene_dma_desc_sw
*desc_sw
)
653 struct xgene_dma_ring
*ring
= &chan
->tx_ring
;
654 struct xgene_dma_desc_hw
*desc_hw
;
656 /* Get hw descriptor from DMA tx ring */
657 desc_hw
= &ring
->desc_hw
[ring
->head
];
660 * Increment the head count to point next
661 * descriptor for next time
663 if (++ring
->head
== ring
->slots
)
666 /* Copy prepared sw descriptor data to hw descriptor */
667 memcpy(desc_hw
, &desc_sw
->desc1
, sizeof(*desc_hw
));
670 * Check if we have prepared 64B descriptor,
671 * in this case we need one more hw descriptor
673 if (desc_sw
->flags
& XGENE_DMA_FLAG_64B_DESC
) {
674 desc_hw
= &ring
->desc_hw
[ring
->head
];
676 if (++ring
->head
== ring
->slots
)
679 memcpy(desc_hw
, &desc_sw
->desc2
, sizeof(*desc_hw
));
682 /* Increment the pending transaction count */
683 chan
->pending
+= ((desc_sw
->flags
&
684 XGENE_DMA_FLAG_64B_DESC
) ? 2 : 1);
686 /* Notify the hw that we have descriptor ready for execution */
687 iowrite32((desc_sw
->flags
& XGENE_DMA_FLAG_64B_DESC
) ?
692 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
693 * @chan : X-Gene DMA channel
695 * LOCKING: must hold chan->lock
697 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan
*chan
)
699 struct xgene_dma_desc_sw
*desc_sw
, *_desc_sw
;
702 * If the list of pending descriptors is empty, then we
703 * don't need to do any work at all
705 if (list_empty(&chan
->ld_pending
)) {
706 chan_dbg(chan
, "No pending LDs\n");
711 * Move elements from the queue of pending transactions onto the list
712 * of running transactions and push it to hw for further executions
714 list_for_each_entry_safe(desc_sw
, _desc_sw
, &chan
->ld_pending
, node
) {
716 * Check if have pushed max number of transactions to hw
717 * as capable, so let's stop here and will push remaining
718 * elements from pening ld queue after completing some
719 * descriptors that we have already pushed
721 if (chan
->pending
>= chan
->max_outstanding
)
724 xgene_chan_xfer_request(chan
, desc_sw
);
727 * Delete this element from ld pending queue and append it to
730 list_move_tail(&desc_sw
->node
, &chan
->ld_running
);
735 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
736 * and move them to ld_completed to free until flag 'ack' is set
737 * @chan: X-Gene DMA channel
739 * This function is used on descriptors which have been executed by the DMA
740 * controller. It will run any callbacks, submit any dependencies, then
741 * free these descriptors if flag 'ack' is set.
743 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan
*chan
)
745 struct xgene_dma_ring
*ring
= &chan
->rx_ring
;
746 struct xgene_dma_desc_sw
*desc_sw
, *_desc_sw
;
747 struct xgene_dma_desc_hw
*desc_hw
;
748 struct list_head ld_completed
;
751 INIT_LIST_HEAD(&ld_completed
);
753 spin_lock_bh(&chan
->lock
);
755 /* Clean already completed and acked descriptors */
756 xgene_dma_clean_completed_descriptor(chan
);
758 /* Move all completed descriptors to ld completed queue, in order */
759 list_for_each_entry_safe(desc_sw
, _desc_sw
, &chan
->ld_running
, node
) {
760 /* Get subsequent hw descriptor from DMA rx ring */
761 desc_hw
= &ring
->desc_hw
[ring
->head
];
763 /* Check if this descriptor has been completed */
764 if (unlikely(le64_to_cpu(desc_hw
->m0
) ==
765 XGENE_DMA_DESC_EMPTY_SIGNATURE
))
768 if (++ring
->head
== ring
->slots
)
771 /* Check if we have any error with DMA transactions */
772 status
= XGENE_DMA_DESC_STATUS(
773 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
775 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
778 /* Print the DMA error type */
779 chan_err(chan
, "%s\n", xgene_dma_desc_err
[status
]);
782 * We have DMA transactions error here. Dump DMA Tx
783 * and Rx descriptors for this request */
784 XGENE_DMA_DESC_DUMP(&desc_sw
->desc1
,
785 "X-Gene DMA TX DESC1: ");
787 if (desc_sw
->flags
& XGENE_DMA_FLAG_64B_DESC
)
788 XGENE_DMA_DESC_DUMP(&desc_sw
->desc2
,
789 "X-Gene DMA TX DESC2: ");
791 XGENE_DMA_DESC_DUMP(desc_hw
,
792 "X-Gene DMA RX ERR DESC: ");
795 /* Notify the hw about this completed descriptor */
796 iowrite32(-1, ring
->cmd
);
798 /* Mark this hw descriptor as processed */
799 desc_hw
->m0
= cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE
);
802 * Decrement the pending transaction count
803 * as we have processed one
805 chan
->pending
-= ((desc_sw
->flags
&
806 XGENE_DMA_FLAG_64B_DESC
) ? 2 : 1);
809 * Delete this node from ld running queue and append it to
810 * ld completed queue for further processing
812 list_move_tail(&desc_sw
->node
, &ld_completed
);
816 * Start any pending transactions automatically
817 * In the ideal case, we keep the DMA controller busy while we go
818 * ahead and free the descriptors below.
820 xgene_chan_xfer_ld_pending(chan
);
822 spin_unlock_bh(&chan
->lock
);
824 /* Run the callback for each descriptor, in order */
825 list_for_each_entry_safe(desc_sw
, _desc_sw
, &ld_completed
, node
) {
826 xgene_dma_run_tx_complete_actions(chan
, desc_sw
);
827 xgene_dma_clean_running_descriptor(chan
, desc_sw
);
831 static int xgene_dma_alloc_chan_resources(struct dma_chan
*dchan
)
833 struct xgene_dma_chan
*chan
= to_dma_chan(dchan
);
835 /* Has this channel already been allocated? */
839 chan
->desc_pool
= dma_pool_create(chan
->name
, chan
->dev
,
840 sizeof(struct xgene_dma_desc_sw
),
842 if (!chan
->desc_pool
) {
843 chan_err(chan
, "Failed to allocate descriptor pool\n");
847 chan_dbg(chan
, "Allocate descripto pool\n");
853 * xgene_dma_free_desc_list - Free all descriptors in a queue
854 * @chan: X-Gene DMA channel
855 * @list: the list to free
857 * LOCKING: must hold chan->lock
859 static void xgene_dma_free_desc_list(struct xgene_dma_chan
*chan
,
860 struct list_head
*list
)
862 struct xgene_dma_desc_sw
*desc
, *_desc
;
864 list_for_each_entry_safe(desc
, _desc
, list
, node
)
865 xgene_dma_clean_descriptor(chan
, desc
);
868 static void xgene_dma_free_chan_resources(struct dma_chan
*dchan
)
870 struct xgene_dma_chan
*chan
= to_dma_chan(dchan
);
872 chan_dbg(chan
, "Free all resources\n");
874 if (!chan
->desc_pool
)
877 /* Process all running descriptor */
878 xgene_dma_cleanup_descriptors(chan
);
880 spin_lock_bh(&chan
->lock
);
882 /* Clean all link descriptor queues */
883 xgene_dma_free_desc_list(chan
, &chan
->ld_pending
);
884 xgene_dma_free_desc_list(chan
, &chan
->ld_running
);
885 xgene_dma_free_desc_list(chan
, &chan
->ld_completed
);
887 spin_unlock_bh(&chan
->lock
);
889 /* Delete this channel DMA pool */
890 dma_pool_destroy(chan
->desc_pool
);
891 chan
->desc_pool
= NULL
;
894 static struct dma_async_tx_descriptor
*xgene_dma_prep_sg(
895 struct dma_chan
*dchan
, struct scatterlist
*dst_sg
,
896 u32 dst_nents
, struct scatterlist
*src_sg
,
897 u32 src_nents
, unsigned long flags
)
899 struct xgene_dma_desc_sw
*first
= NULL
, *new = NULL
;
900 struct xgene_dma_chan
*chan
;
901 size_t dst_avail
, src_avail
;
905 if (unlikely(!dchan
))
908 if (unlikely(!dst_nents
|| !src_nents
))
911 if (unlikely(!dst_sg
|| !src_sg
))
914 chan
= to_dma_chan(dchan
);
916 /* Get prepared for the loop */
917 dst_avail
= sg_dma_len(dst_sg
);
918 src_avail
= sg_dma_len(src_sg
);
922 /* Run until we are out of scatterlist entries */
924 /* Create the largest transaction possible */
925 len
= min_t(size_t, src_avail
, dst_avail
);
926 len
= min_t(size_t, len
, XGENE_DMA_MAX_64B_DESC_BYTE_CNT
);
930 dst
= sg_dma_address(dst_sg
) + sg_dma_len(dst_sg
) - dst_avail
;
931 src
= sg_dma_address(src_sg
) + sg_dma_len(src_sg
) - src_avail
;
933 /* Allocate the link descriptor from DMA pool */
934 new = xgene_dma_alloc_descriptor(chan
);
938 /* Prepare DMA descriptor */
939 xgene_dma_prep_cpy_desc(chan
, new, dst
, src
, len
);
945 async_tx_ack(&new->tx
);
947 /* update metadata */
951 /* Insert the link descriptor to the LD ring */
952 list_add_tail(&new->node
, &first
->tx_list
);
955 /* fetch the next dst scatterlist entry */
956 if (dst_avail
== 0) {
957 /* no more entries: we're done */
961 /* fetch the next entry: if there are no more: done */
962 dst_sg
= sg_next(dst_sg
);
967 dst_avail
= sg_dma_len(dst_sg
);
970 /* fetch the next src scatterlist entry */
971 if (src_avail
== 0) {
972 /* no more entries: we're done */
976 /* fetch the next entry: if there are no more: done */
977 src_sg
= sg_next(src_sg
);
982 src_avail
= sg_dma_len(src_sg
);
989 new->tx
.flags
= flags
; /* client is in control of this ack */
990 new->tx
.cookie
= -EBUSY
;
991 list_splice(&first
->tx_list
, &new->tx_list
);
998 xgene_dma_free_desc_list(chan
, &first
->tx_list
);
1002 static struct dma_async_tx_descriptor
*xgene_dma_prep_xor(
1003 struct dma_chan
*dchan
, dma_addr_t dst
, dma_addr_t
*src
,
1004 u32 src_cnt
, size_t len
, unsigned long flags
)
1006 struct xgene_dma_desc_sw
*first
= NULL
, *new;
1007 struct xgene_dma_chan
*chan
;
1008 static u8 multi
[XGENE_DMA_MAX_XOR_SRC
] = {
1009 0x01, 0x01, 0x01, 0x01, 0x01};
1011 if (unlikely(!dchan
|| !len
))
1014 chan
= to_dma_chan(dchan
);
1017 /* Allocate the link descriptor from DMA pool */
1018 new = xgene_dma_alloc_descriptor(chan
);
1022 /* Prepare xor DMA descriptor */
1023 xgene_dma_prep_xor_desc(chan
, new, &dst
, src
,
1024 src_cnt
, &len
, multi
);
1030 async_tx_ack(&new->tx
);
1032 /* Insert the link descriptor to the LD ring */
1033 list_add_tail(&new->node
, &first
->tx_list
);
1036 new->tx
.flags
= flags
; /* client is in control of this ack */
1037 new->tx
.cookie
= -EBUSY
;
1038 list_splice(&first
->tx_list
, &new->tx_list
);
1046 xgene_dma_free_desc_list(chan
, &first
->tx_list
);
1050 static struct dma_async_tx_descriptor
*xgene_dma_prep_pq(
1051 struct dma_chan
*dchan
, dma_addr_t
*dst
, dma_addr_t
*src
,
1052 u32 src_cnt
, const u8
*scf
, size_t len
, unsigned long flags
)
1054 struct xgene_dma_desc_sw
*first
= NULL
, *new;
1055 struct xgene_dma_chan
*chan
;
1057 dma_addr_t _src
[XGENE_DMA_MAX_XOR_SRC
];
1058 static u8 multi
[XGENE_DMA_MAX_XOR_SRC
] = {0x01, 0x01, 0x01, 0x01, 0x01};
1060 if (unlikely(!dchan
|| !len
))
1063 chan
= to_dma_chan(dchan
);
1066 * Save source addresses on local variable, may be we have to
1067 * prepare two descriptor to generate P and Q if both enabled
1068 * in the flags by client
1070 memcpy(_src
, src
, sizeof(*src
) * src_cnt
);
1072 if (flags
& DMA_PREP_PQ_DISABLE_P
)
1075 if (flags
& DMA_PREP_PQ_DISABLE_Q
)
1079 /* Allocate the link descriptor from DMA pool */
1080 new = xgene_dma_alloc_descriptor(chan
);
1088 async_tx_ack(&new->tx
);
1090 /* Insert the link descriptor to the LD ring */
1091 list_add_tail(&new->node
, &first
->tx_list
);
1094 * Prepare DMA descriptor to generate P,
1095 * if DMA_PREP_PQ_DISABLE_P flag is not set
1098 xgene_dma_prep_xor_desc(chan
, new, &dst
[0], src
,
1099 src_cnt
, &len
, multi
);
1104 * Prepare DMA descriptor to generate Q,
1105 * if DMA_PREP_PQ_DISABLE_Q flag is not set
1108 xgene_dma_prep_xor_desc(chan
, new, &dst
[1], _src
,
1109 src_cnt
, &_len
, scf
);
1111 } while (len
|| _len
);
1113 new->tx
.flags
= flags
; /* client is in control of this ack */
1114 new->tx
.cookie
= -EBUSY
;
1115 list_splice(&first
->tx_list
, &new->tx_list
);
1123 xgene_dma_free_desc_list(chan
, &first
->tx_list
);
1127 static void xgene_dma_issue_pending(struct dma_chan
*dchan
)
1129 struct xgene_dma_chan
*chan
= to_dma_chan(dchan
);
1131 spin_lock_bh(&chan
->lock
);
1132 xgene_chan_xfer_ld_pending(chan
);
1133 spin_unlock_bh(&chan
->lock
);
1136 static enum dma_status
xgene_dma_tx_status(struct dma_chan
*dchan
,
1137 dma_cookie_t cookie
,
1138 struct dma_tx_state
*txstate
)
1140 return dma_cookie_status(dchan
, cookie
, txstate
);
1143 static void xgene_dma_tasklet_cb(unsigned long data
)
1145 struct xgene_dma_chan
*chan
= (struct xgene_dma_chan
*)data
;
1147 /* Run all cleanup for descriptors which have been completed */
1148 xgene_dma_cleanup_descriptors(chan
);
1150 /* Re-enable DMA channel IRQ */
1151 enable_irq(chan
->rx_irq
);
1154 static irqreturn_t
xgene_dma_chan_ring_isr(int irq
, void *id
)
1156 struct xgene_dma_chan
*chan
= (struct xgene_dma_chan
*)id
;
1161 * Disable DMA channel IRQ until we process completed
1164 disable_irq_nosync(chan
->rx_irq
);
1167 * Schedule the tasklet to handle all cleanup of the current
1168 * transaction. It will start a new transaction if there is
1171 tasklet_schedule(&chan
->tasklet
);
1176 static irqreturn_t
xgene_dma_err_isr(int irq
, void *id
)
1178 struct xgene_dma
*pdma
= (struct xgene_dma
*)id
;
1179 unsigned long int_mask
;
1182 val
= ioread32(pdma
->csr_dma
+ XGENE_DMA_INT
);
1184 /* Clear DMA interrupts */
1185 iowrite32(val
, pdma
->csr_dma
+ XGENE_DMA_INT
);
1187 /* Print DMA error info */
1188 int_mask
= val
>> XGENE_DMA_INT_MASK_SHIFT
;
1189 for_each_set_bit(i
, &int_mask
, ARRAY_SIZE(xgene_dma_err
))
1191 "Interrupt status 0x%08X %s\n", val
, xgene_dma_err
[i
]);
1196 static void xgene_dma_wr_ring_state(struct xgene_dma_ring
*ring
)
1200 iowrite32(ring
->num
, ring
->pdma
->csr_ring
+ XGENE_DMA_RING_STATE
);
1202 for (i
= 0; i
< XGENE_DMA_RING_NUM_CONFIG
; i
++)
1203 iowrite32(ring
->state
[i
], ring
->pdma
->csr_ring
+
1204 XGENE_DMA_RING_STATE_WR_BASE
+ (i
* 4));
1207 static void xgene_dma_clr_ring_state(struct xgene_dma_ring
*ring
)
1209 memset(ring
->state
, 0, sizeof(u32
) * XGENE_DMA_RING_NUM_CONFIG
);
1210 xgene_dma_wr_ring_state(ring
);
1213 static void xgene_dma_setup_ring(struct xgene_dma_ring
*ring
)
1215 void *ring_cfg
= ring
->state
;
1216 u64 addr
= ring
->desc_paddr
;
1219 ring
->slots
= ring
->size
/ XGENE_DMA_RING_WQ_DESC_SIZE
;
1221 /* Clear DMA ring state */
1222 xgene_dma_clr_ring_state(ring
);
1224 /* Set DMA ring type */
1225 XGENE_DMA_RING_TYPE_SET(ring_cfg
, XGENE_DMA_RING_TYPE_REGULAR
);
1227 if (ring
->owner
== XGENE_DMA_RING_OWNER_DMA
) {
1228 /* Set recombination buffer and timeout */
1229 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg
);
1230 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg
);
1231 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg
);
1234 /* Initialize DMA ring state */
1235 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg
);
1236 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg
);
1237 XGENE_DMA_RING_COHERENT_SET(ring_cfg
);
1238 XGENE_DMA_RING_ADDRL_SET(ring_cfg
, addr
);
1239 XGENE_DMA_RING_ADDRH_SET(ring_cfg
, addr
);
1240 XGENE_DMA_RING_SIZE_SET(ring_cfg
, ring
->cfgsize
);
1242 /* Write DMA ring configurations */
1243 xgene_dma_wr_ring_state(ring
);
1245 /* Set DMA ring id */
1246 iowrite32(XGENE_DMA_RING_ID_SETUP(ring
->id
),
1247 ring
->pdma
->csr_ring
+ XGENE_DMA_RING_ID
);
1249 /* Set DMA ring buffer */
1250 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring
->num
),
1251 ring
->pdma
->csr_ring
+ XGENE_DMA_RING_ID_BUF
);
1253 if (ring
->owner
!= XGENE_DMA_RING_OWNER_CPU
)
1256 /* Set empty signature to DMA Rx ring descriptors */
1257 for (i
= 0; i
< ring
->slots
; i
++) {
1258 struct xgene_dma_desc_hw
*desc
;
1260 desc
= &ring
->desc_hw
[i
];
1261 desc
->m0
= cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE
);
1264 /* Enable DMA Rx ring interrupt */
1265 val
= ioread32(ring
->pdma
->csr_ring
+ XGENE_DMA_RING_NE_INT_MODE
);
1266 XGENE_DMA_RING_NE_INT_MODE_SET(val
, ring
->buf_num
);
1267 iowrite32(val
, ring
->pdma
->csr_ring
+ XGENE_DMA_RING_NE_INT_MODE
);
1270 static void xgene_dma_clear_ring(struct xgene_dma_ring
*ring
)
1274 if (ring
->owner
== XGENE_DMA_RING_OWNER_CPU
) {
1275 /* Disable DMA Rx ring interrupt */
1276 val
= ioread32(ring
->pdma
->csr_ring
+
1277 XGENE_DMA_RING_NE_INT_MODE
);
1278 XGENE_DMA_RING_NE_INT_MODE_RESET(val
, ring
->buf_num
);
1279 iowrite32(val
, ring
->pdma
->csr_ring
+
1280 XGENE_DMA_RING_NE_INT_MODE
);
1283 /* Clear DMA ring state */
1284 ring_id
= XGENE_DMA_RING_ID_SETUP(ring
->id
);
1285 iowrite32(ring_id
, ring
->pdma
->csr_ring
+ XGENE_DMA_RING_ID
);
1287 iowrite32(0, ring
->pdma
->csr_ring
+ XGENE_DMA_RING_ID_BUF
);
1288 xgene_dma_clr_ring_state(ring
);
1291 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring
*ring
)
1293 ring
->cmd_base
= ring
->pdma
->csr_ring_cmd
+
1294 XGENE_DMA_RING_CMD_BASE_OFFSET((ring
->num
-
1295 XGENE_DMA_RING_NUM
));
1297 ring
->cmd
= ring
->cmd_base
+ XGENE_DMA_RING_CMD_OFFSET
;
1300 static int xgene_dma_get_ring_size(struct xgene_dma_chan
*chan
,
1301 enum xgene_dma_ring_cfgsize cfgsize
)
1306 case XGENE_DMA_RING_CFG_SIZE_512B
:
1309 case XGENE_DMA_RING_CFG_SIZE_2KB
:
1312 case XGENE_DMA_RING_CFG_SIZE_16KB
:
1315 case XGENE_DMA_RING_CFG_SIZE_64KB
:
1318 case XGENE_DMA_RING_CFG_SIZE_512KB
:
1322 chan_err(chan
, "Unsupported cfg ring size %d\n", cfgsize
);
1329 static void xgene_dma_delete_ring_one(struct xgene_dma_ring
*ring
)
1331 /* Clear DMA ring configurations */
1332 xgene_dma_clear_ring(ring
);
1334 /* De-allocate DMA ring descriptor */
1335 if (ring
->desc_vaddr
) {
1336 dma_free_coherent(ring
->pdma
->dev
, ring
->size
,
1337 ring
->desc_vaddr
, ring
->desc_paddr
);
1338 ring
->desc_vaddr
= NULL
;
1342 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan
*chan
)
1344 xgene_dma_delete_ring_one(&chan
->rx_ring
);
1345 xgene_dma_delete_ring_one(&chan
->tx_ring
);
1348 static int xgene_dma_create_ring_one(struct xgene_dma_chan
*chan
,
1349 struct xgene_dma_ring
*ring
,
1350 enum xgene_dma_ring_cfgsize cfgsize
)
1354 /* Setup DMA ring descriptor variables */
1355 ring
->pdma
= chan
->pdma
;
1356 ring
->cfgsize
= cfgsize
;
1357 ring
->num
= chan
->pdma
->ring_num
++;
1358 ring
->id
= XGENE_DMA_RING_ID_GET(ring
->owner
, ring
->buf_num
);
1360 ret
= xgene_dma_get_ring_size(chan
, cfgsize
);
1365 /* Allocate memory for DMA ring descriptor */
1366 ring
->desc_vaddr
= dma_zalloc_coherent(chan
->dev
, ring
->size
,
1367 &ring
->desc_paddr
, GFP_KERNEL
);
1368 if (!ring
->desc_vaddr
) {
1369 chan_err(chan
, "Failed to allocate ring desc\n");
1373 /* Configure and enable DMA ring */
1374 xgene_dma_set_ring_cmd(ring
);
1375 xgene_dma_setup_ring(ring
);
1380 static int xgene_dma_create_chan_rings(struct xgene_dma_chan
*chan
)
1382 struct xgene_dma_ring
*rx_ring
= &chan
->rx_ring
;
1383 struct xgene_dma_ring
*tx_ring
= &chan
->tx_ring
;
1386 /* Create DMA Rx ring descriptor */
1387 rx_ring
->owner
= XGENE_DMA_RING_OWNER_CPU
;
1388 rx_ring
->buf_num
= XGENE_DMA_CPU_BUFNUM
+ chan
->id
;
1390 ret
= xgene_dma_create_ring_one(chan
, rx_ring
,
1391 XGENE_DMA_RING_CFG_SIZE_64KB
);
1395 chan_dbg(chan
, "Rx ring id 0x%X num %d desc 0x%p\n",
1396 rx_ring
->id
, rx_ring
->num
, rx_ring
->desc_vaddr
);
1398 /* Create DMA Tx ring descriptor */
1399 tx_ring
->owner
= XGENE_DMA_RING_OWNER_DMA
;
1400 tx_ring
->buf_num
= XGENE_DMA_BUFNUM
+ chan
->id
;
1402 ret
= xgene_dma_create_ring_one(chan
, tx_ring
,
1403 XGENE_DMA_RING_CFG_SIZE_64KB
);
1405 xgene_dma_delete_ring_one(rx_ring
);
1409 tx_ring
->dst_ring_num
= XGENE_DMA_RING_DST_ID(rx_ring
->num
);
1412 "Tx ring id 0x%X num %d desc 0x%p\n",
1413 tx_ring
->id
, tx_ring
->num
, tx_ring
->desc_vaddr
);
1415 /* Set the max outstanding request possible to this channel */
1416 chan
->max_outstanding
= tx_ring
->slots
;
1421 static int xgene_dma_init_rings(struct xgene_dma
*pdma
)
1425 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1426 ret
= xgene_dma_create_chan_rings(&pdma
->chan
[i
]);
1428 for (j
= 0; j
< i
; j
++)
1429 xgene_dma_delete_chan_rings(&pdma
->chan
[j
]);
1437 static void xgene_dma_enable(struct xgene_dma
*pdma
)
1441 /* Configure and enable DMA engine */
1442 val
= ioread32(pdma
->csr_dma
+ XGENE_DMA_GCR
);
1443 XGENE_DMA_CH_SETUP(val
);
1444 XGENE_DMA_ENABLE(val
);
1445 iowrite32(val
, pdma
->csr_dma
+ XGENE_DMA_GCR
);
1448 static void xgene_dma_disable(struct xgene_dma
*pdma
)
1452 val
= ioread32(pdma
->csr_dma
+ XGENE_DMA_GCR
);
1453 XGENE_DMA_DISABLE(val
);
1454 iowrite32(val
, pdma
->csr_dma
+ XGENE_DMA_GCR
);
1457 static void xgene_dma_mask_interrupts(struct xgene_dma
*pdma
)
1460 * Mask DMA ring overflow, underflow and
1461 * AXI write/read error interrupts
1463 iowrite32(XGENE_DMA_INT_ALL_MASK
,
1464 pdma
->csr_dma
+ XGENE_DMA_RING_INT0_MASK
);
1465 iowrite32(XGENE_DMA_INT_ALL_MASK
,
1466 pdma
->csr_dma
+ XGENE_DMA_RING_INT1_MASK
);
1467 iowrite32(XGENE_DMA_INT_ALL_MASK
,
1468 pdma
->csr_dma
+ XGENE_DMA_RING_INT2_MASK
);
1469 iowrite32(XGENE_DMA_INT_ALL_MASK
,
1470 pdma
->csr_dma
+ XGENE_DMA_RING_INT3_MASK
);
1471 iowrite32(XGENE_DMA_INT_ALL_MASK
,
1472 pdma
->csr_dma
+ XGENE_DMA_RING_INT4_MASK
);
1474 /* Mask DMA error interrupts */
1475 iowrite32(XGENE_DMA_INT_ALL_MASK
, pdma
->csr_dma
+ XGENE_DMA_INT_MASK
);
1478 static void xgene_dma_unmask_interrupts(struct xgene_dma
*pdma
)
1481 * Unmask DMA ring overflow, underflow and
1482 * AXI write/read error interrupts
1484 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1485 pdma
->csr_dma
+ XGENE_DMA_RING_INT0_MASK
);
1486 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1487 pdma
->csr_dma
+ XGENE_DMA_RING_INT1_MASK
);
1488 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1489 pdma
->csr_dma
+ XGENE_DMA_RING_INT2_MASK
);
1490 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1491 pdma
->csr_dma
+ XGENE_DMA_RING_INT3_MASK
);
1492 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1493 pdma
->csr_dma
+ XGENE_DMA_RING_INT4_MASK
);
1495 /* Unmask DMA error interrupts */
1496 iowrite32(XGENE_DMA_INT_ALL_UNMASK
,
1497 pdma
->csr_dma
+ XGENE_DMA_INT_MASK
);
1500 static void xgene_dma_init_hw(struct xgene_dma
*pdma
)
1504 /* Associate DMA ring to corresponding ring HW */
1505 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1
,
1506 pdma
->csr_dma
+ XGENE_DMA_CFG_RING_WQ_ASSOC
);
1508 /* Configure RAID6 polynomial control setting */
1509 if (is_pq_enabled(pdma
))
1510 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1511 pdma
->csr_dma
+ XGENE_DMA_RAID6_CONT
);
1513 dev_info(pdma
->dev
, "PQ is disabled in HW\n");
1515 xgene_dma_enable(pdma
);
1516 xgene_dma_unmask_interrupts(pdma
);
1518 /* Get DMA id and version info */
1519 val
= ioread32(pdma
->csr_dma
+ XGENE_DMA_IPBRR
);
1521 /* DMA device info */
1523 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1524 XGENE_DMA_REV_NO_RD(val
), XGENE_DMA_BUS_ID_RD(val
),
1525 XGENE_DMA_DEV_ID_RD(val
), XGENE_DMA_MAX_CHANNEL
);
1528 static int xgene_dma_init_ring_mngr(struct xgene_dma
*pdma
)
1530 if (ioread32(pdma
->csr_ring
+ XGENE_DMA_RING_CLKEN
) &&
1531 (!ioread32(pdma
->csr_ring
+ XGENE_DMA_RING_SRST
)))
1534 iowrite32(0x3, pdma
->csr_ring
+ XGENE_DMA_RING_CLKEN
);
1535 iowrite32(0x0, pdma
->csr_ring
+ XGENE_DMA_RING_SRST
);
1537 /* Bring up memory */
1538 iowrite32(0x0, pdma
->csr_ring
+ XGENE_DMA_RING_MEM_RAM_SHUTDOWN
);
1540 /* Force a barrier */
1541 ioread32(pdma
->csr_ring
+ XGENE_DMA_RING_MEM_RAM_SHUTDOWN
);
1543 /* reset may take up to 1ms */
1544 usleep_range(1000, 1100);
1546 if (ioread32(pdma
->csr_ring
+ XGENE_DMA_RING_BLK_MEM_RDY
)
1547 != XGENE_DMA_RING_BLK_MEM_RDY_VAL
) {
1549 "Failed to release ring mngr memory from shutdown\n");
1553 /* program threshold set 1 and all hysteresis */
1554 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL
,
1555 pdma
->csr_ring
+ XGENE_DMA_RING_THRESLD0_SET1
);
1556 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL
,
1557 pdma
->csr_ring
+ XGENE_DMA_RING_THRESLD1_SET1
);
1558 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL
,
1559 pdma
->csr_ring
+ XGENE_DMA_RING_HYSTERESIS
);
1561 /* Enable QPcore and assign error queue */
1562 iowrite32(XGENE_DMA_RING_ENABLE
,
1563 pdma
->csr_ring
+ XGENE_DMA_RING_CONFIG
);
1568 static int xgene_dma_init_mem(struct xgene_dma
*pdma
)
1572 ret
= xgene_dma_init_ring_mngr(pdma
);
1576 /* Bring up memory */
1577 iowrite32(0x0, pdma
->csr_dma
+ XGENE_DMA_MEM_RAM_SHUTDOWN
);
1579 /* Force a barrier */
1580 ioread32(pdma
->csr_dma
+ XGENE_DMA_MEM_RAM_SHUTDOWN
);
1582 /* reset may take up to 1ms */
1583 usleep_range(1000, 1100);
1585 if (ioread32(pdma
->csr_dma
+ XGENE_DMA_BLK_MEM_RDY
)
1586 != XGENE_DMA_BLK_MEM_RDY_VAL
) {
1588 "Failed to release DMA memory from shutdown\n");
1595 static int xgene_dma_request_irqs(struct xgene_dma
*pdma
)
1597 struct xgene_dma_chan
*chan
;
1600 /* Register DMA error irq */
1601 ret
= devm_request_irq(pdma
->dev
, pdma
->err_irq
, xgene_dma_err_isr
,
1602 0, "dma_error", pdma
);
1605 "Failed to register error IRQ %d\n", pdma
->err_irq
);
1609 /* Register DMA channel rx irq */
1610 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1611 chan
= &pdma
->chan
[i
];
1612 irq_set_status_flags(chan
->rx_irq
, IRQ_DISABLE_UNLAZY
);
1613 ret
= devm_request_irq(chan
->dev
, chan
->rx_irq
,
1614 xgene_dma_chan_ring_isr
,
1615 0, chan
->name
, chan
);
1617 chan_err(chan
, "Failed to register Rx IRQ %d\n",
1619 devm_free_irq(pdma
->dev
, pdma
->err_irq
, pdma
);
1621 for (j
= 0; j
< i
; j
++) {
1622 chan
= &pdma
->chan
[i
];
1623 irq_clear_status_flags(chan
->rx_irq
, IRQ_DISABLE_UNLAZY
);
1624 devm_free_irq(chan
->dev
, chan
->rx_irq
, chan
);
1634 static void xgene_dma_free_irqs(struct xgene_dma
*pdma
)
1636 struct xgene_dma_chan
*chan
;
1639 /* Free DMA device error irq */
1640 devm_free_irq(pdma
->dev
, pdma
->err_irq
, pdma
);
1642 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1643 chan
= &pdma
->chan
[i
];
1644 irq_clear_status_flags(chan
->rx_irq
, IRQ_DISABLE_UNLAZY
);
1645 devm_free_irq(chan
->dev
, chan
->rx_irq
, chan
);
1649 static void xgene_dma_set_caps(struct xgene_dma_chan
*chan
,
1650 struct dma_device
*dma_dev
)
1652 /* Initialize DMA device capability mask */
1653 dma_cap_zero(dma_dev
->cap_mask
);
1655 /* Set DMA device capability */
1656 dma_cap_set(DMA_SG
, dma_dev
->cap_mask
);
1658 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1659 * and channel 1 supports XOR, PQ both. First thing here is we have
1660 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1661 * we can make sure this by reading SoC Efuse register.
1662 * Second thing, we have hw errata that if we run channel 0 and
1663 * channel 1 simultaneously with executing XOR and PQ request,
1664 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1665 * if XOR and PQ supports on channel 1 is disabled.
1667 if ((chan
->id
== XGENE_DMA_PQ_CHANNEL
) &&
1668 is_pq_enabled(chan
->pdma
)) {
1669 dma_cap_set(DMA_PQ
, dma_dev
->cap_mask
);
1670 dma_cap_set(DMA_XOR
, dma_dev
->cap_mask
);
1671 } else if ((chan
->id
== XGENE_DMA_XOR_CHANNEL
) &&
1672 !is_pq_enabled(chan
->pdma
)) {
1673 dma_cap_set(DMA_XOR
, dma_dev
->cap_mask
);
1676 /* Set base and prep routines */
1677 dma_dev
->dev
= chan
->dev
;
1678 dma_dev
->device_alloc_chan_resources
= xgene_dma_alloc_chan_resources
;
1679 dma_dev
->device_free_chan_resources
= xgene_dma_free_chan_resources
;
1680 dma_dev
->device_issue_pending
= xgene_dma_issue_pending
;
1681 dma_dev
->device_tx_status
= xgene_dma_tx_status
;
1682 dma_dev
->device_prep_dma_sg
= xgene_dma_prep_sg
;
1684 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1685 dma_dev
->device_prep_dma_xor
= xgene_dma_prep_xor
;
1686 dma_dev
->max_xor
= XGENE_DMA_MAX_XOR_SRC
;
1687 dma_dev
->xor_align
= DMAENGINE_ALIGN_64_BYTES
;
1690 if (dma_has_cap(DMA_PQ
, dma_dev
->cap_mask
)) {
1691 dma_dev
->device_prep_dma_pq
= xgene_dma_prep_pq
;
1692 dma_dev
->max_pq
= XGENE_DMA_MAX_XOR_SRC
;
1693 dma_dev
->pq_align
= DMAENGINE_ALIGN_64_BYTES
;
1697 static int xgene_dma_async_register(struct xgene_dma
*pdma
, int id
)
1699 struct xgene_dma_chan
*chan
= &pdma
->chan
[id
];
1700 struct dma_device
*dma_dev
= &pdma
->dma_dev
[id
];
1703 chan
->dma_chan
.device
= dma_dev
;
1705 spin_lock_init(&chan
->lock
);
1706 INIT_LIST_HEAD(&chan
->ld_pending
);
1707 INIT_LIST_HEAD(&chan
->ld_running
);
1708 INIT_LIST_HEAD(&chan
->ld_completed
);
1709 tasklet_init(&chan
->tasklet
, xgene_dma_tasklet_cb
,
1710 (unsigned long)chan
);
1713 chan
->desc_pool
= NULL
;
1714 dma_cookie_init(&chan
->dma_chan
);
1716 /* Setup dma device capabilities and prep routines */
1717 xgene_dma_set_caps(chan
, dma_dev
);
1719 /* Initialize DMA device list head */
1720 INIT_LIST_HEAD(&dma_dev
->channels
);
1721 list_add_tail(&chan
->dma_chan
.device_node
, &dma_dev
->channels
);
1723 /* Register with Linux async DMA framework*/
1724 ret
= dma_async_device_register(dma_dev
);
1726 chan_err(chan
, "Failed to register async device %d", ret
);
1727 tasklet_kill(&chan
->tasklet
);
1732 /* DMA capability info */
1734 "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan
->dma_chan
),
1735 dma_has_cap(DMA_SG
, dma_dev
->cap_mask
) ? "SGCPY " : "",
1736 dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
) ? "XOR " : "",
1737 dma_has_cap(DMA_PQ
, dma_dev
->cap_mask
) ? "PQ " : "");
1742 static int xgene_dma_init_async(struct xgene_dma
*pdma
)
1746 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1747 ret
= xgene_dma_async_register(pdma
, i
);
1749 for (j
= 0; j
< i
; j
++) {
1750 dma_async_device_unregister(&pdma
->dma_dev
[j
]);
1751 tasklet_kill(&pdma
->chan
[j
].tasklet
);
1761 static void xgene_dma_async_unregister(struct xgene_dma
*pdma
)
1765 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++)
1766 dma_async_device_unregister(&pdma
->dma_dev
[i
]);
1769 static void xgene_dma_init_channels(struct xgene_dma
*pdma
)
1771 struct xgene_dma_chan
*chan
;
1774 pdma
->ring_num
= XGENE_DMA_RING_NUM
;
1776 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1777 chan
= &pdma
->chan
[i
];
1778 chan
->dev
= pdma
->dev
;
1781 snprintf(chan
->name
, sizeof(chan
->name
), "dmachan%d", chan
->id
);
1785 static int xgene_dma_get_resources(struct platform_device
*pdev
,
1786 struct xgene_dma
*pdma
)
1788 struct resource
*res
;
1791 /* Get DMA csr region */
1792 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1794 dev_err(&pdev
->dev
, "Failed to get csr region\n");
1798 pdma
->csr_dma
= devm_ioremap(&pdev
->dev
, res
->start
,
1799 resource_size(res
));
1800 if (!pdma
->csr_dma
) {
1801 dev_err(&pdev
->dev
, "Failed to ioremap csr region");
1805 /* Get DMA ring csr region */
1806 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1808 dev_err(&pdev
->dev
, "Failed to get ring csr region\n");
1812 pdma
->csr_ring
= devm_ioremap(&pdev
->dev
, res
->start
,
1813 resource_size(res
));
1814 if (!pdma
->csr_ring
) {
1815 dev_err(&pdev
->dev
, "Failed to ioremap ring csr region");
1819 /* Get DMA ring cmd csr region */
1820 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1822 dev_err(&pdev
->dev
, "Failed to get ring cmd csr region\n");
1826 pdma
->csr_ring_cmd
= devm_ioremap(&pdev
->dev
, res
->start
,
1827 resource_size(res
));
1828 if (!pdma
->csr_ring_cmd
) {
1829 dev_err(&pdev
->dev
, "Failed to ioremap ring cmd csr region");
1833 pdma
->csr_ring_cmd
+= XGENE_DMA_RING_CMD_SM_OFFSET
;
1835 /* Get efuse csr region */
1836 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
1838 dev_err(&pdev
->dev
, "Failed to get efuse csr region\n");
1842 pdma
->csr_efuse
= devm_ioremap(&pdev
->dev
, res
->start
,
1843 resource_size(res
));
1844 if (!pdma
->csr_efuse
) {
1845 dev_err(&pdev
->dev
, "Failed to ioremap efuse csr region");
1849 /* Get DMA error interrupt */
1850 irq
= platform_get_irq(pdev
, 0);
1852 dev_err(&pdev
->dev
, "Failed to get Error IRQ\n");
1856 pdma
->err_irq
= irq
;
1858 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1859 for (i
= 1; i
<= XGENE_DMA_MAX_CHANNEL
; i
++) {
1860 irq
= platform_get_irq(pdev
, i
);
1862 dev_err(&pdev
->dev
, "Failed to get Rx IRQ\n");
1866 pdma
->chan
[i
- 1].rx_irq
= irq
;
1872 static int xgene_dma_probe(struct platform_device
*pdev
)
1874 struct xgene_dma
*pdma
;
1877 pdma
= devm_kzalloc(&pdev
->dev
, sizeof(*pdma
), GFP_KERNEL
);
1881 pdma
->dev
= &pdev
->dev
;
1882 platform_set_drvdata(pdev
, pdma
);
1884 ret
= xgene_dma_get_resources(pdev
, pdma
);
1888 pdma
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1889 if (IS_ERR(pdma
->clk
) && !ACPI_COMPANION(&pdev
->dev
)) {
1890 dev_err(&pdev
->dev
, "Failed to get clk\n");
1891 return PTR_ERR(pdma
->clk
);
1894 /* Enable clk before accessing registers */
1895 if (!IS_ERR(pdma
->clk
)) {
1896 ret
= clk_prepare_enable(pdma
->clk
);
1898 dev_err(&pdev
->dev
, "Failed to enable clk %d\n", ret
);
1903 /* Remove DMA RAM out of shutdown */
1904 ret
= xgene_dma_init_mem(pdma
);
1906 goto err_clk_enable
;
1908 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(42));
1910 dev_err(&pdev
->dev
, "No usable DMA configuration\n");
1914 /* Initialize DMA channels software state */
1915 xgene_dma_init_channels(pdma
);
1917 /* Configue DMA rings */
1918 ret
= xgene_dma_init_rings(pdma
);
1920 goto err_clk_enable
;
1922 ret
= xgene_dma_request_irqs(pdma
);
1924 goto err_request_irq
;
1926 /* Configure and enable DMA engine */
1927 xgene_dma_init_hw(pdma
);
1929 /* Register DMA device with linux async framework */
1930 ret
= xgene_dma_init_async(pdma
);
1932 goto err_async_init
;
1937 xgene_dma_free_irqs(pdma
);
1940 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++)
1941 xgene_dma_delete_chan_rings(&pdma
->chan
[i
]);
1945 if (!IS_ERR(pdma
->clk
))
1946 clk_disable_unprepare(pdma
->clk
);
1951 static int xgene_dma_remove(struct platform_device
*pdev
)
1953 struct xgene_dma
*pdma
= platform_get_drvdata(pdev
);
1954 struct xgene_dma_chan
*chan
;
1957 xgene_dma_async_unregister(pdma
);
1959 /* Mask interrupts and disable DMA engine */
1960 xgene_dma_mask_interrupts(pdma
);
1961 xgene_dma_disable(pdma
);
1962 xgene_dma_free_irqs(pdma
);
1964 for (i
= 0; i
< XGENE_DMA_MAX_CHANNEL
; i
++) {
1965 chan
= &pdma
->chan
[i
];
1966 tasklet_kill(&chan
->tasklet
);
1967 xgene_dma_delete_chan_rings(chan
);
1970 if (!IS_ERR(pdma
->clk
))
1971 clk_disable_unprepare(pdma
->clk
);
1977 static const struct acpi_device_id xgene_dma_acpi_match_ptr
[] = {
1981 MODULE_DEVICE_TABLE(acpi
, xgene_dma_acpi_match_ptr
);
1984 static const struct of_device_id xgene_dma_of_match_ptr
[] = {
1985 {.compatible
= "apm,xgene-storm-dma",},
1988 MODULE_DEVICE_TABLE(of
, xgene_dma_of_match_ptr
);
1990 static struct platform_driver xgene_dma_driver
= {
1991 .probe
= xgene_dma_probe
,
1992 .remove
= xgene_dma_remove
,
1994 .name
= "X-Gene-DMA",
1995 .of_match_table
= xgene_dma_of_match_ptr
,
1996 .acpi_match_table
= ACPI_PTR(xgene_dma_acpi_match_ptr
),
2000 module_platform_driver(xgene_dma_driver
);
2002 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2003 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2004 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2005 MODULE_LICENSE("GPL");
2006 MODULE_VERSION("1.0");