drivers/edac/altera_edac.h

   1 /*
   2  *
   3  * Copyright (C) 2015 Altera Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef _ALTERA_EDAC_H
  19 #define _ALTERA_EDAC_H
  20
  21 #include <linux/edac.h>
  22 #include <linux/types.h>
  23
  24 /* SDRAM Controller CtrlCfg Register */
  25 #define CV_CTLCFG_OFST             0x00
  26
  27 /* SDRAM Controller CtrlCfg Register Bit Masks */
  28 #define CV_CTLCFG_ECC_EN           0x400
  29 #define CV_CTLCFG_ECC_CORR_EN      0x800
  30 #define CV_CTLCFG_GEN_SB_ERR       0x2000
  31 #define CV_CTLCFG_GEN_DB_ERR       0x4000
  32
  33 #define CV_CTLCFG_ECC_AUTO_EN     (CV_CTLCFG_ECC_EN)
  34
  35 /* SDRAM Controller Address Width Register */
  36 #define CV_DRAMADDRW_OFST          0x2C
  37
  38 /* SDRAM Controller Address Widths Field Register */
  39 #define DRAMADDRW_COLBIT_MASK      0x001F
  40 #define DRAMADDRW_COLBIT_SHIFT     0
  41 #define DRAMADDRW_ROWBIT_MASK      0x03E0
  42 #define DRAMADDRW_ROWBIT_SHIFT     5
  43 #define CV_DRAMADDRW_BANKBIT_MASK  0x1C00
  44 #define CV_DRAMADDRW_BANKBIT_SHIFT 10
  45 #define CV_DRAMADDRW_CSBIT_MASK    0xE000
  46 #define CV_DRAMADDRW_CSBIT_SHIFT   13
  47
  48 /* SDRAM Controller Interface Data Width Register */
  49 #define CV_DRAMIFWIDTH_OFST        0x30
  50
  51 /* SDRAM Controller Interface Data Width Defines */
  52 #define CV_DRAMIFWIDTH_16B_ECC     24
  53 #define CV_DRAMIFWIDTH_32B_ECC     40
  54
  55 /* SDRAM Controller DRAM Status Register */
  56 #define CV_DRAMSTS_OFST            0x38
  57
  58 /* SDRAM Controller DRAM Status Register Bit Masks */
  59 #define CV_DRAMSTS_SBEERR          0x04
  60 #define CV_DRAMSTS_DBEERR          0x08
  61 #define CV_DRAMSTS_CORR_DROP       0x10
  62
  63 /* SDRAM Controller DRAM IRQ Register */
  64 #define CV_DRAMINTR_OFST           0x3C
  65
  66 /* SDRAM Controller DRAM IRQ Register Bit Masks */
  67 #define CV_DRAMINTR_INTREN         0x01
  68 #define CV_DRAMINTR_SBEMASK        0x02
  69 #define CV_DRAMINTR_DBEMASK        0x04
  70 #define CV_DRAMINTR_CORRDROPMASK   0x08
  71 #define CV_DRAMINTR_INTRCLR        0x10
  72
  73 /* SDRAM Controller Single Bit Error Count Register */
  74 #define CV_SBECOUNT_OFST           0x40
  75
  76 /* SDRAM Controller Double Bit Error Count Register */
  77 #define CV_DBECOUNT_OFST           0x44
  78
  79 /* SDRAM Controller ECC Error Address Register */
  80 #define CV_ERRADDR_OFST            0x48
  81
  82 /*-----------------------------------------*/
  83
  84 /* SDRAM Controller EccCtrl Register */
  85 #define A10_ECCCTRL1_OFST          0x00
  86
  87 /* SDRAM Controller EccCtrl Register Bit Masks */
  88 #define A10_ECCCTRL1_ECC_EN        0x001
  89 #define A10_ECCCTRL1_CNT_RST       0x010
  90 #define A10_ECCCTRL1_AWB_CNT_RST   0x100
  91 #define A10_ECC_CNT_RESET_MASK     (A10_ECCCTRL1_CNT_RST | \
  92                                     A10_ECCCTRL1_AWB_CNT_RST)
  93
  94 /* SDRAM Controller Address Width Register */
  95 #define CV_DRAMADDRW               0xFFC2502C
  96 #define A10_DRAMADDRW              0xFFCFA0A8
  97
  98 /* SDRAM Controller Address Widths Field Register */
  99 #define DRAMADDRW_COLBIT_MASK      0x001F
 100 #define DRAMADDRW_COLBIT_SHIFT     0
 101 #define DRAMADDRW_ROWBIT_MASK      0x03E0
 102 #define DRAMADDRW_ROWBIT_SHIFT     5
 103 #define CV_DRAMADDRW_BANKBIT_MASK  0x1C00
 104 #define CV_DRAMADDRW_BANKBIT_SHIFT 10
 105 #define CV_DRAMADDRW_CSBIT_MASK    0xE000
 106 #define CV_DRAMADDRW_CSBIT_SHIFT   13
 107
 108 #define A10_DRAMADDRW_BANKBIT_MASK  0x3C00
 109 #define A10_DRAMADDRW_BANKBIT_SHIFT 10
 110 #define A10_DRAMADDRW_GRPBIT_MASK   0xC000
 111 #define A10_DRAMADDRW_GRPBIT_SHIFT  14
 112 #define A10_DRAMADDRW_CSBIT_MASK    0x70000
 113 #define A10_DRAMADDRW_CSBIT_SHIFT   16
 114
 115 /* SDRAM Controller Interface Data Width Register */
 116 #define CV_DRAMIFWIDTH             0xFFC25030
 117 #define A10_DRAMIFWIDTH            0xFFCFB008
 118
 119 /* SDRAM Controller Interface Data Width Defines */
 120 #define CV_DRAMIFWIDTH_16B_ECC     24
 121 #define CV_DRAMIFWIDTH_32B_ECC     40
 122
 123 #define A10_DRAMIFWIDTH_16B        0x0
 124 #define A10_DRAMIFWIDTH_32B        0x1
 125 #define A10_DRAMIFWIDTH_64B        0x2
 126
 127 /* SDRAM Controller DRAM IRQ Register */
 128 #define A10_ERRINTEN_OFST          0x10
 129
 130 /* SDRAM Controller DRAM IRQ Register Bit Masks */
 131 #define A10_ERRINTEN_SERRINTEN     0x01
 132 #define A10_ERRINTEN_DERRINTEN     0x02
 133 #define A10_ECC_IRQ_EN_MASK        (A10_ERRINTEN_SERRINTEN | \
 134                                     A10_ERRINTEN_DERRINTEN)
 135
 136 /* SDRAM Interrupt Mode Register */
 137 #define A10_INTMODE_OFST           0x1C
 138 #define A10_INTMODE_SB_INT         1
 139
 140 /* SDRAM Controller Error Status Register */
 141 #define A10_INTSTAT_OFST           0x20
 142
 143 /* SDRAM Controller Error Status Register Bit Masks */
 144 #define A10_INTSTAT_SBEERR         0x01
 145 #define A10_INTSTAT_DBEERR         0x02
 146
 147 /* SDRAM Controller ECC Error Address Register */
 148 #define A10_DERRADDR_OFST          0x2C
 149 #define A10_SERRADDR_OFST          0x30
 150
 151 /* SDRAM Controller ECC Diagnostic Register */
 152 #define A10_DIAGINTTEST_OFST       0x24
 153
 154 #define A10_DIAGINT_TSERRA_MASK    0x0001
 155 #define A10_DIAGINT_TDERRA_MASK    0x0100
 156
 157 #define A10_SBERR_IRQ              34
 158 #define A10_DBERR_IRQ              32
 159
 160 /* SDRAM Single Bit Error Count Compare Set Register */
 161 #define A10_SERRCNTREG_OFST        0x3C
 162
 163 #define A10_SYMAN_INTMASK_CLR      0xFFD06098
 164 #define A10_INTMASK_CLR_OFST       0x10
 165 #define A10_DDR0_IRQ_MASK          BIT(17)
 166
 167 struct altr_sdram_prv_data {
 168         int ecc_ctrl_offset;
 169         int ecc_ctl_en_mask;
 170         int ecc_cecnt_offset;
 171         int ecc_uecnt_offset;
 172         int ecc_stat_offset;
 173         int ecc_stat_ce_mask;
 174         int ecc_stat_ue_mask;
 175         int ecc_saddr_offset;
 176         int ecc_daddr_offset;
 177         int ecc_irq_en_offset;
 178         int ecc_irq_en_mask;
 179         int ecc_irq_clr_offset;
 180         int ecc_irq_clr_mask;
 181         int ecc_cnt_rst_offset;
 182         int ecc_cnt_rst_mask;
 183         struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
 184         int ecc_enable_mask;
 185         int ce_set_mask;
 186         int ue_set_mask;
 187         int ce_ue_trgr_offset;
 188 };
 189
 190 /* Altera SDRAM Memory Controller data */
 191 struct altr_sdram_mc_data {
 192         struct regmap *mc_vbase;
 193         int sb_irq;
 194         int db_irq;
 195         const struct altr_sdram_prv_data *data;
 196 };
 197
 198 /************************** EDAC Device Defines **************************/
 199 /***** General Device Trigger Defines *****/
 200 #define ALTR_UE_TRIGGER_CHAR            'U'   /* Trigger for UE */
 201 #define ALTR_TRIGGER_READ_WRD_CNT       32    /* Line size x 4 */
 202 #define ALTR_TRIG_OCRAM_BYTE_SIZE       128   /* Line size x 4 */
 203 #define ALTR_TRIG_L2C_BYTE_SIZE         4096  /* Full Page */
 204
 205 /******* Cyclone5 and Arria5 Defines *******/
 206 /* OCRAM ECC Management Group Defines */
 207 #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
 208 #define ALTR_OCR_ECC_REG_OFFSET         0x00
 209 #define ALTR_OCR_ECC_EN                 BIT(0)
 210 #define ALTR_OCR_ECC_INJS               BIT(1)
 211 #define ALTR_OCR_ECC_INJD               BIT(2)
 212 #define ALTR_OCR_ECC_SERR               BIT(3)
 213 #define ALTR_OCR_ECC_DERR               BIT(4)
 214
 215 /* L2 ECC Management Group Defines */
 216 #define ALTR_MAN_GRP_L2_ECC_OFFSET      0x00
 217 #define ALTR_L2_ECC_REG_OFFSET          0x00
 218 #define ALTR_L2_ECC_EN                  BIT(0)
 219 #define ALTR_L2_ECC_INJS                BIT(1)
 220 #define ALTR_L2_ECC_INJD                BIT(2)
 221
 222 /* Arria10 General ECC Block Module Defines */
 223 #define ALTR_A10_ECC_CTRL_OFST          0x08
 224 #define ALTR_A10_ECC_EN                 BIT(0)
 225 #define ALTR_A10_ECC_INITA              BIT(16)
 226 #define ALTR_A10_ECC_INITB              BIT(24)
 227
 228 #define ALTR_A10_ECC_INITSTAT_OFST      0x0C
 229 #define ALTR_A10_ECC_INITCOMPLETEA      BIT(0)
 230 #define ALTR_A10_ECC_INITCOMPLETEB      BIT(8)
 231
 232 #define ALTR_A10_ECC_ERRINTEN_OFST      0x10
 233 #define ALTR_A10_ECC_ERRINTENS_OFST     0x14
 234 #define ALTR_A10_ECC_ERRINTENR_OFST     0x18
 235 #define ALTR_A10_ECC_SERRINTEN          BIT(0)
 236
 237 #define ALTR_A10_ECC_INTMODE_OFST       0x1C
 238 #define ALTR_A10_ECC_INTMODE            BIT(0)
 239
 240 #define ALTR_A10_ECC_INTSTAT_OFST       0x20
 241 #define ALTR_A10_ECC_SERRPENA           BIT(0)
 242 #define ALTR_A10_ECC_DERRPENA           BIT(8)
 243 #define ALTR_A10_ECC_ERRPENA_MASK       (ALTR_A10_ECC_SERRPENA | \
 244                                          ALTR_A10_ECC_DERRPENA)
 245 #define ALTR_A10_ECC_SERRPENB           BIT(16)
 246 #define ALTR_A10_ECC_DERRPENB           BIT(24)
 247 #define ALTR_A10_ECC_ERRPENB_MASK       (ALTR_A10_ECC_SERRPENB | \
 248                                          ALTR_A10_ECC_DERRPENB)
 249
 250 #define ALTR_A10_ECC_INTTEST_OFST       0x24
 251 #define ALTR_A10_ECC_TSERRA             BIT(0)
 252 #define ALTR_A10_ECC_TDERRA             BIT(8)
 253 #define ALTR_A10_ECC_TSERRB             BIT(16)
 254 #define ALTR_A10_ECC_TDERRB             BIT(24)
 255
 256 /* ECC Manager Defines */
 257 #define A10_SYSMGR_ECC_INTMASK_SET_OFST   0x94
 258 #define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98
 259 #define A10_SYSMGR_ECC_INTMASK_OCRAM      BIT(1)
 260
 261 #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST  0x9C
 262 #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0
 263 #define A10_SYSMGR_ECC_INTSTAT_L2         BIT(0)
 264 #define A10_SYSMGR_ECC_INTSTAT_OCRAM      BIT(1)
 265
 266 #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST  0xA8
 267 #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB    BIT(15)
 268 #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB    BIT(31)
 269
 270 /* Arria 10 L2 ECC Management Group Defines */
 271 #define ALTR_A10_L2_ECC_CTL_OFST        0x0
 272 #define ALTR_A10_L2_ECC_EN_CTL          BIT(0)
 273
 274 #define ALTR_A10_L2_ECC_STATUS          0xFFD060A4
 275 #define ALTR_A10_L2_ECC_STAT_OFST       0xA4
 276 #define ALTR_A10_L2_ECC_SERR_PEND       BIT(0)
 277 #define ALTR_A10_L2_ECC_MERR_PEND       BIT(0)
 278
 279 #define ALTR_A10_L2_ECC_CLR_OFST        0x4
 280 #define ALTR_A10_L2_ECC_SERR_CLR        BIT(15)
 281 #define ALTR_A10_L2_ECC_MERR_CLR        BIT(31)
 282
 283 #define ALTR_A10_L2_ECC_INJ_OFST        ALTR_A10_L2_ECC_CTL_OFST
 284 #define ALTR_A10_L2_ECC_CE_INJ_MASK     0x00000101
 285 #define ALTR_A10_L2_ECC_UE_INJ_MASK     0x00010101
 286
 287 /* Arria 10 OCRAM ECC Management Group Defines */
 288 #define ALTR_A10_OCRAM_ECC_EN_CTL       (BIT(1) | BIT(0))
 289
 290 /* Arria 10 Ethernet ECC Management Group Defines */
 291 #define ALTR_A10_COMMON_ECC_EN_CTL      BIT(0)
 292
 293 /* Arria 10 SDMMC ECC Management Group Defines */
 294 #define ALTR_A10_SDMMC_IRQ_MASK         (BIT(16) | BIT(15))
 295
 296 /* A10 ECC Controller memory initialization timeout */
 297 #define ALTR_A10_ECC_INIT_WATCHDOG_10US      10000
 298
 299 struct altr_edac_device_dev;
 300
 301 struct edac_device_prv_data {
 302         int (*setup)(struct altr_edac_device_dev *device);
 303         int ce_clear_mask;
 304         int ue_clear_mask;
 305         int irq_status_mask;
 306         void * (*alloc_mem)(size_t size, void **other);
 307         void (*free_mem)(void *p, size_t size, void *other);
 308         int ecc_enable_mask;
 309         int ecc_en_ofst;
 310         int ce_set_mask;
 311         int ue_set_mask;
 312         int set_err_ofst;
 313         irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
 314         int trig_alloc_sz;
 315         const struct file_operations *inject_fops;
 316         bool panic;
 317 };
 318
 319 struct altr_edac_device_dev {
 320         struct list_head next;
 321         void __iomem *base;
 322         int sb_irq;
 323         int db_irq;
 324         const struct edac_device_prv_data *data;
 325         struct dentry *debugfs_dir;
 326         char *edac_dev_name;
 327         struct altr_arria10_edac *edac;
 328         struct edac_device_ctl_info *edac_dev;
 329         struct device ddev;
 330         int edac_idx;
 331 };
 332
 333 struct altr_arria10_edac {
 334         struct device           *dev;
 335         struct regmap           *ecc_mgr_map;
 336         int sb_irq;
 337         int db_irq;
 338         struct irq_domain       *domain;
 339         struct irq_chip         irq_chip;
 340         struct list_head        a10_ecc_devices;
 341 };
 342
 343 #endif  /* #ifndef _ALTERA_EDAC_H */