?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / gpio / gpio-tegra.c
blob661b0e34e0672eedba9e7896c742944aeda18477
1 /*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm.h>
33
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
37
38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
39 GPIO_PORT(x) * 4)
40
41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
51
52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
59
60 #define GPIO_INT_LVL_MASK 0x010101
61 #define GPIO_INT_LVL_EDGE_RISING 0x000101
62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
67 struct tegra_gpio_info;
68
69 struct tegra_gpio_bank {
70 int bank;
71 int irq;
72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74 #ifdef CONFIG_PM_SLEEP
75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
80 u32 wake_enb[4];
81 u32 dbc_enb[4];
82 #endif
83 u32 dbc_cnt[4];
84 struct tegra_gpio_info *tgi;
85 };
86
87 struct tegra_gpio_soc_config {
88 bool debounce_supported;
89 u32 bank_stride;
90 u32 upper_offset;
91 };
92
93 struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
101 u32 bank_count;
102 };
103
104 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
105 u32 val, u32 reg)
106 {
107 __raw_writel(val, tgi->regs + reg);
108 }
109
110 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
111 {
112 return __raw_readl(tgi->regs + reg);
113 }
114
115 static int tegra_gpio_compose(int bank, int port, int bit)
116 {
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
118 }
119
120 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
121 int gpio, int value)
122 {
123 u32 val;
124
125 val = 0x100 << GPIO_BIT(gpio);
126 if (value)
127 val |= 1 << GPIO_BIT(gpio);
128 tegra_gpio_writel(tgi, val, reg);
129 }
130
131 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
132 {
133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
134 }
135
136 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
137 {
138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
139 }
140
141 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
142 {
143 return pinctrl_request_gpio(offset);
144 }
145
146 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
147 {
148 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
149
150 pinctrl_free_gpio(offset);
151 tegra_gpio_disable(tgi, offset);
152 }
153
154 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
155 {
156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
157
158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
159 }
160
161 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
162 {
163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
164 int bval = BIT(GPIO_BIT(offset));
165
166 /* If gpio is in output mode then read from the out value */
167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
168 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
169
170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
171 }
172
173 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
174 {
175 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
176
177 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
178 tegra_gpio_enable(tgi, offset);
179 return 0;
180 }
181
182 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
183 int value)
184 {
185 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
186
187 tegra_gpio_set(chip, offset, value);
188 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
189 tegra_gpio_enable(tgi, offset);
190 return 0;
191 }
192
193 static int tegra_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
194 {
195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
196 u32 pin_mask = BIT(GPIO_BIT(offset));
197 u32 cnf, oe;
198
199 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
200 if (!(cnf & pin_mask))
201 return -EINVAL;
202
203 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
204
205 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
206 }
207
208 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
209 unsigned int debounce)
210 {
211 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
212 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
213 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
214 unsigned long flags;
215 int port;
216
217 if (!debounce_ms) {
218 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
219 offset, 0);
220 return 0;
221 }
222
223 debounce_ms = min(debounce_ms, 255U);
224 port = GPIO_PORT(offset);
225
226 /* There is only one debounce count register per port and hence
227 * set the maximum of current and requested debounce time.
228 */
229 spin_lock_irqsave(&bank->dbc_lock[port], flags);
230 if (bank->dbc_cnt[port] < debounce_ms) {
231 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
232 bank->dbc_cnt[port] = debounce_ms;
233 }
234 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
235
236 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
237
238 return 0;
239 }
240
241 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
242 {
243 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
244
245 return irq_find_mapping(tgi->irq_domain, offset);
246 }
247
248 static void tegra_gpio_irq_ack(struct irq_data *d)
249 {
250 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
251 struct tegra_gpio_info *tgi = bank->tgi;
252 int gpio = d->hwirq;
253
254 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
255 }
256
257 static void tegra_gpio_irq_mask(struct irq_data *d)
258 {
259 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
260 struct tegra_gpio_info *tgi = bank->tgi;
261 int gpio = d->hwirq;
262
263 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
264 }
265
266 static void tegra_gpio_irq_unmask(struct irq_data *d)
267 {
268 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
269 struct tegra_gpio_info *tgi = bank->tgi;
270 int gpio = d->hwirq;
271
272 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
273 }
274
275 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
276 {
277 int gpio = d->hwirq;
278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
279 struct tegra_gpio_info *tgi = bank->tgi;
280 int port = GPIO_PORT(gpio);
281 int lvl_type;
282 int val;
283 unsigned long flags;
284 int ret;
285
286 switch (type & IRQ_TYPE_SENSE_MASK) {
287 case IRQ_TYPE_EDGE_RISING:
288 lvl_type = GPIO_INT_LVL_EDGE_RISING;
289 break;
290
291 case IRQ_TYPE_EDGE_FALLING:
292 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
293 break;
294
295 case IRQ_TYPE_EDGE_BOTH:
296 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
297 break;
298
299 case IRQ_TYPE_LEVEL_HIGH:
300 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
301 break;
302
303 case IRQ_TYPE_LEVEL_LOW:
304 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
305 break;
306
307 default:
308 return -EINVAL;
309 }
310
311 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
312 if (ret) {
313 dev_err(tgi->dev,
314 "unable to lock Tegra GPIO %d as IRQ\n", gpio);
315 return ret;
316 }
317
318 spin_lock_irqsave(&bank->lvl_lock[port], flags);
319
320 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
321 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
322 val |= lvl_type << GPIO_BIT(gpio);
323 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
324
325 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
326
327 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
328 tegra_gpio_enable(tgi, gpio);
329
330 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
331 irq_set_handler_locked(d, handle_level_irq);
332 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
333 irq_set_handler_locked(d, handle_edge_irq);
334
335 return 0;
336 }
337
338 static void tegra_gpio_irq_shutdown(struct irq_data *d)
339 {
340 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
341 struct tegra_gpio_info *tgi = bank->tgi;
342 int gpio = d->hwirq;
343
344 gpiochip_unlock_as_irq(&tgi->gc, gpio);
345 }
346
347 static void tegra_gpio_irq_handler(struct irq_desc *desc)
348 {
349 int port;
350 int pin;
351 int unmasked = 0;
352 int gpio;
353 u32 lvl;
354 unsigned long sta;
355 struct irq_chip *chip = irq_desc_get_chip(desc);
356 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
357 struct tegra_gpio_info *tgi = bank->tgi;
358
359 chained_irq_enter(chip, desc);
360
361 for (port = 0; port < 4; port++) {
362 gpio = tegra_gpio_compose(bank->bank, port, 0);
363 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
364 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
365 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
366
367 for_each_set_bit(pin, &sta, 8) {
368 tegra_gpio_writel(tgi, 1 << pin,
369 GPIO_INT_CLR(tgi, gpio));
370
371 /* if gpio is edge triggered, clear condition
372 * before executing the handler so that we don't
373 * miss edges
374 */
375 if (lvl & (0x100 << pin)) {
376 unmasked = 1;
377 chained_irq_exit(chip, desc);
378 }
379
380 generic_handle_irq(gpio_to_irq(gpio + pin));
381 }
382 }
383
384 if (!unmasked)
385 chained_irq_exit(chip, desc);
386
387 }
388
389 #ifdef CONFIG_PM_SLEEP
390 static int tegra_gpio_resume(struct device *dev)
391 {
392 struct platform_device *pdev = to_platform_device(dev);
393 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
394 unsigned long flags;
395 int b;
396 int p;
397
398 local_irq_save(flags);
399
400 for (b = 0; b < tgi->bank_count; b++) {
401 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
402
403 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
404 unsigned int gpio = (b<<5) | (p<<3);
405 tegra_gpio_writel(tgi, bank->cnf[p],
406 GPIO_CNF(tgi, gpio));
407
408 if (tgi->soc->debounce_supported) {
409 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
410 GPIO_DBC_CNT(tgi, gpio));
411 tegra_gpio_writel(tgi, bank->dbc_enb[p],
412 GPIO_MSK_DBC_EN(tgi, gpio));
413 }
414
415 tegra_gpio_writel(tgi, bank->out[p],
416 GPIO_OUT(tgi, gpio));
417 tegra_gpio_writel(tgi, bank->oe[p],
418 GPIO_OE(tgi, gpio));
419 tegra_gpio_writel(tgi, bank->int_lvl[p],
420 GPIO_INT_LVL(tgi, gpio));
421 tegra_gpio_writel(tgi, bank->int_enb[p],
422 GPIO_INT_ENB(tgi, gpio));
423 }
424 }
425
426 local_irq_restore(flags);
427 return 0;
428 }
429
430 static int tegra_gpio_suspend(struct device *dev)
431 {
432 struct platform_device *pdev = to_platform_device(dev);
433 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
434 unsigned long flags;
435 int b;
436 int p;
437
438 local_irq_save(flags);
439 for (b = 0; b < tgi->bank_count; b++) {
440 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
441
442 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
443 unsigned int gpio = (b<<5) | (p<<3);
444 bank->cnf[p] = tegra_gpio_readl(tgi,
445 GPIO_CNF(tgi, gpio));
446 bank->out[p] = tegra_gpio_readl(tgi,
447 GPIO_OUT(tgi, gpio));
448 bank->oe[p] = tegra_gpio_readl(tgi,
449 GPIO_OE(tgi, gpio));
450 if (tgi->soc->debounce_supported) {
451 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
452 GPIO_MSK_DBC_EN(tgi, gpio));
453 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
454 bank->dbc_enb[p];
455 }
456
457 bank->int_enb[p] = tegra_gpio_readl(tgi,
458 GPIO_INT_ENB(tgi, gpio));
459 bank->int_lvl[p] = tegra_gpio_readl(tgi,
460 GPIO_INT_LVL(tgi, gpio));
461
462 /* Enable gpio irq for wake up source */
463 tegra_gpio_writel(tgi, bank->wake_enb[p],
464 GPIO_INT_ENB(tgi, gpio));
465 }
466 }
467 local_irq_restore(flags);
468 return 0;
469 }
470
471 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
472 {
473 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
474 int gpio = d->hwirq;
475 u32 port, bit, mask;
476
477 port = GPIO_PORT(gpio);
478 bit = GPIO_BIT(gpio);
479 mask = BIT(bit);
480
481 if (enable)
482 bank->wake_enb[port] |= mask;
483 else
484 bank->wake_enb[port] &= ~mask;
485
486 return irq_set_irq_wake(bank->irq, enable);
487 }
488 #endif
489
490 #ifdef CONFIG_DEBUG_FS
491
492 #include <linux/debugfs.h>
493 #include <linux/seq_file.h>
494
495 static int dbg_gpio_show(struct seq_file *s, void *unused)
496 {
497 struct tegra_gpio_info *tgi = s->private;
498 int i;
499 int j;
500
501 for (i = 0; i < tgi->bank_count; i++) {
502 for (j = 0; j < 4; j++) {
503 int gpio = tegra_gpio_compose(i, j, 0);
504 seq_printf(s,
505 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
506 i, j,
507 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
508 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
509 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
510 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
511 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
512 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
513 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
514 }
515 }
516 return 0;
517 }
518
519 static int dbg_gpio_open(struct inode *inode, struct file *file)
520 {
521 return single_open(file, dbg_gpio_show, inode->i_private);
522 }
523
524 static const struct file_operations debug_fops = {
525 .open = dbg_gpio_open,
526 .read = seq_read,
527 .llseek = seq_lseek,
528 .release = single_release,
529 };
530
531 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
532 {
533 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
534 NULL, tgi, &debug_fops);
535 }
536
537 #else
538
539 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
540 {
541 }
542
543 #endif
544
545 static const struct dev_pm_ops tegra_gpio_pm_ops = {
546 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
547 };
548
549 /*
550 * This lock class tells lockdep that GPIO irqs are in a different category
551 * than their parents, so it won't report false recursion.
552 */
553 static struct lock_class_key gpio_lock_class;
554
555 static int tegra_gpio_probe(struct platform_device *pdev)
556 {
557 const struct tegra_gpio_soc_config *config;
558 struct tegra_gpio_info *tgi;
559 struct resource *res;
560 struct tegra_gpio_bank *bank;
561 int ret;
562 int gpio;
563 int i;
564 int j;
565
566 config = of_device_get_match_data(&pdev->dev);
567 if (!config) {
568 dev_err(&pdev->dev, "Error: No device match found\n");
569 return -ENODEV;
570 }
571
572 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
573 if (!tgi)
574 return -ENODEV;
575
576 tgi->soc = config;
577 tgi->dev = &pdev->dev;
578
579 for (;;) {
580 res = platform_get_resource(pdev, IORESOURCE_IRQ,
581 tgi->bank_count);
582 if (!res)
583 break;
584 tgi->bank_count++;
585 }
586 if (!tgi->bank_count) {
587 dev_err(&pdev->dev, "Missing IRQ resource\n");
588 return -ENODEV;
589 }
590
591 tgi->gc.label = "tegra-gpio";
592 tgi->gc.request = tegra_gpio_request;
593 tgi->gc.free = tegra_gpio_free;
594 tgi->gc.direction_input = tegra_gpio_direction_input;
595 tgi->gc.get = tegra_gpio_get;
596 tgi->gc.direction_output = tegra_gpio_direction_output;
597 tgi->gc.set = tegra_gpio_set;
598 tgi->gc.get_direction = tegra_gpio_get_direction;
599 tgi->gc.to_irq = tegra_gpio_to_irq;
600 tgi->gc.base = 0;
601 tgi->gc.ngpio = tgi->bank_count * 32;
602 tgi->gc.parent = &pdev->dev;
603 tgi->gc.of_node = pdev->dev.of_node;
604
605 tgi->ic.name = "GPIO";
606 tgi->ic.irq_ack = tegra_gpio_irq_ack;
607 tgi->ic.irq_mask = tegra_gpio_irq_mask;
608 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
609 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
610 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
611 #ifdef CONFIG_PM_SLEEP
612 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
613 #endif
614
615 platform_set_drvdata(pdev, tgi);
616
617 if (config->debounce_supported)
618 tgi->gc.set_debounce = tegra_gpio_set_debounce;
619
620 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count *
621 sizeof(*tgi->bank_info), GFP_KERNEL);
622 if (!tgi->bank_info)
623 return -ENODEV;
624
625 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
626 tgi->gc.ngpio,
627 &irq_domain_simple_ops, NULL);
628 if (!tgi->irq_domain)
629 return -ENODEV;
630
631 for (i = 0; i < tgi->bank_count; i++) {
632 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
633 if (!res) {
634 dev_err(&pdev->dev, "Missing IRQ resource\n");
635 return -ENODEV;
636 }
637
638 bank = &tgi->bank_info[i];
639 bank->bank = i;
640 bank->irq = res->start;
641 bank->tgi = tgi;
642 }
643
644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
645 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
646 if (IS_ERR(tgi->regs))
647 return PTR_ERR(tgi->regs);
648
649 for (i = 0; i < tgi->bank_count; i++) {
650 for (j = 0; j < 4; j++) {
651 int gpio = tegra_gpio_compose(i, j, 0);
652 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
653 }
654 }
655
656 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
657 if (ret < 0) {
658 irq_domain_remove(tgi->irq_domain);
659 return ret;
660 }
661
662 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
663 int irq = irq_create_mapping(tgi->irq_domain, gpio);
664 /* No validity check; all Tegra GPIOs are valid IRQs */
665
666 bank = &tgi->bank_info[GPIO_BANK(gpio)];
667
668 irq_set_lockdep_class(irq, &gpio_lock_class);
669 irq_set_chip_data(irq, bank);
670 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
671 }
672
673 for (i = 0; i < tgi->bank_count; i++) {
674 bank = &tgi->bank_info[i];
675
676 irq_set_chained_handler_and_data(bank->irq,
677 tegra_gpio_irq_handler, bank);
678
679 for (j = 0; j < 4; j++) {
680 spin_lock_init(&bank->lvl_lock[j]);
681 spin_lock_init(&bank->dbc_lock[j]);
682 }
683 }
684
685 tegra_gpio_debuginit(tgi);
686
687 return 0;
688 }
689
690 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
691 .bank_stride = 0x80,
692 .upper_offset = 0x800,
693 };
694
695 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
696 .bank_stride = 0x100,
697 .upper_offset = 0x80,
698 };
699
700 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
701 .debounce_supported = true,
702 .bank_stride = 0x100,
703 .upper_offset = 0x80,
704 };
705
706 static const struct of_device_id tegra_gpio_of_match[] = {
707 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
708 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
709 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
710 { },
711 };
712
713 static struct platform_driver tegra_gpio_driver = {
714 .driver = {
715 .name = "tegra-gpio",
716 .pm = &tegra_gpio_pm_ops,
717 .of_match_table = tegra_gpio_of_match,
718 },
719 .probe = tegra_gpio_probe,
720 };
721
722 static int __init tegra_gpio_init(void)
723 {
724 return platform_driver_register(&tegra_gpio_driver);
725 }
726 postcore_initcall(tegra_gpio_init);
Linux with added FPC-III support