drivers/gpio/gpio-zynq.c

   1 /*
   2  * Xilinx Zynq GPIO device driver
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it under
   7  * the terms of the GNU General Public License as published by the Free Software
   8  * Foundation; either version 2 of the License, or (at your option) any later
   9  * version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/of.h>
  22
  23 #define DRIVER_NAME "zynq-gpio"
  24
  25 /* Maximum banks */
  26 #define ZYNQ_GPIO_MAX_BANK      4
  27 #define ZYNQMP_GPIO_MAX_BANK    6
  28
  29 #define ZYNQ_GPIO_BANK0_NGPIO   32
  30 #define ZYNQ_GPIO_BANK1_NGPIO   22
  31 #define ZYNQ_GPIO_BANK2_NGPIO   32
  32 #define ZYNQ_GPIO_BANK3_NGPIO   32
  33
  34 #define ZYNQMP_GPIO_BANK0_NGPIO 26
  35 #define ZYNQMP_GPIO_BANK1_NGPIO 26
  36 #define ZYNQMP_GPIO_BANK2_NGPIO 26
  37 #define ZYNQMP_GPIO_BANK3_NGPIO 32
  38 #define ZYNQMP_GPIO_BANK4_NGPIO 32
  39 #define ZYNQMP_GPIO_BANK5_NGPIO 32
  40
  41 #define ZYNQ_GPIO_NR_GPIOS      118
  42 #define ZYNQMP_GPIO_NR_GPIOS    174
  43
  44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str)    0
  45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str)    (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  46                                         ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str)    (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str)    (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  49                                         ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str)    (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str)    (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  52                                         ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str)    (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str)    (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  55                                         ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str)    (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str)    (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  58                                         ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str)    (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str)    (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  61                                         ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  62
  63
  64 /* Register offsets for the GPIO device */
  65 /* LSW Mask & Data -WO */
  66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  67 /* MSW Mask & Data -WO */
  68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  69 /* Data Register-RW */
  70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)  (0x060 + (4 * BANK))
  71 /* Direction mode reg-RW */
  72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK)     (0x204 + (0x40 * BANK))
  73 /* Output enable reg-RW */
  74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK)    (0x208 + (0x40 * BANK))
  75 /* Interrupt mask reg-RO */
  76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK)  (0x20C + (0x40 * BANK))
  77 /* Interrupt enable reg-WO */
  78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK)    (0x210 + (0x40 * BANK))
  79 /* Interrupt disable reg-WO */
  80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK)   (0x214 + (0x40 * BANK))
  81 /* Interrupt status reg-RO */
  82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK)   (0x218 + (0x40 * BANK))
  83 /* Interrupt type reg-RW */
  84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)  (0x21C + (0x40 * BANK))
  85 /* Interrupt polarity reg-RW */
  86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK)   (0x220 + (0x40 * BANK))
  87 /* Interrupt on any, reg-RW */
  88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK)   (0x224 + (0x40 * BANK))
  89
  90 /* Disable all interrupts mask */
  91 #define ZYNQ_GPIO_IXR_DISABLE_ALL       0xFFFFFFFF
  92
  93 /* Mid pin number of a bank */
  94 #define ZYNQ_GPIO_MID_PIN_NUM 16
  95
  96 /* GPIO upper 16 bit mask */
  97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  98
  99 /* For GPIO quirks */
 100 #define ZYNQ_GPIO_QUIRK_FOO     BIT(0)
 101
 102 /**
 103  * struct zynq_gpio - gpio device private data structure
 104  * @chip:       instance of the gpio_chip
 105  * @base_addr:  base address of the GPIO device
 106  * @clk:        clock resource for this controller
 107  * @irq:        interrupt for the GPIO device
 108  * @p_data:     pointer to platform data
 109  */
 110 struct zynq_gpio {
 111         struct gpio_chip chip;
 112         void __iomem *base_addr;
 113         struct clk *clk;
 114         int irq;
 115         const struct zynq_platform_data *p_data;
 116 };
 117
 118 /**
 119  * struct zynq_platform_data -  zynq gpio platform data structure
 120  * @label:      string to store in gpio->label
 121  * @ngpio:      max number of gpio pins
 122  * @max_bank:   maximum number of gpio banks
 123  * @bank_min:   this array represents bank's min pin
 124  * @bank_max:   this array represents bank's max pin
 125 */
 126 struct zynq_platform_data {
 127         const char *label;
 128         u32 quirks;
 129         u16 ngpio;
 130         int max_bank;
 131         int bank_min[ZYNQMP_GPIO_MAX_BANK];
 132         int bank_max[ZYNQMP_GPIO_MAX_BANK];
 133 };
 134
 135 static struct irq_chip zynq_gpio_level_irqchip;
 136 static struct irq_chip zynq_gpio_edge_irqchip;
 137
 138 /**
 139  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
 140  * for a given pin in the GPIO device
 141  * @pin_num:    gpio pin number within the device
 142  * @bank_num:   an output parameter used to return the bank number of the gpio
 143  *              pin
 144  * @bank_pin_num: an output parameter used to return pin number within a bank
 145  *                for the given gpio pin
 146  *
 147  * Returns the bank number and pin offset within the bank.
 148  */
 149 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 150                                           unsigned int *bank_num,
 151                                           unsigned int *bank_pin_num,
 152                                           struct zynq_gpio *gpio)
 153 {
 154         int bank;
 155
 156         for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
 157                 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
 158                         (pin_num <= gpio->p_data->bank_max[bank])) {
 159                                 *bank_num = bank;
 160                                 *bank_pin_num = pin_num -
 161                                                 gpio->p_data->bank_min[bank];
 162                                 return;
 163                 }
 164         }
 165
 166         /* default */
 167         WARN(true, "invalid GPIO pin number: %u", pin_num);
 168         *bank_num = 0;
 169         *bank_pin_num = 0;
 170 }
 171
 172 /**
 173  * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
 174  * @chip:       gpio_chip instance to be worked on
 175  * @pin:        gpio pin number within the device
 176  *
 177  * This function reads the state of the specified pin of the GPIO device.
 178  *
 179  * Return: 0 if the pin is low, 1 if pin is high.
 180  */
 181 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
 182 {
 183         u32 data;
 184         unsigned int bank_num, bank_pin_num;
 185         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 186
 187         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 188
 189         data = readl_relaxed(gpio->base_addr +
 190                              ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 191
 192         return (data >> bank_pin_num) & 1;
 193 }
 194
 195 /**
 196  * zynq_gpio_set_value - Modify the state of the pin with specified value
 197  * @chip:       gpio_chip instance to be worked on
 198  * @pin:        gpio pin number within the device
 199  * @state:      value used to modify the state of the specified pin
 200  *
 201  * This function calculates the register offset (i.e to lower 16 bits or
 202  * upper 16 bits) based on the given pin number and sets the state of a
 203  * gpio pin to the specified value. The state is either 0 or non-zero.
 204  */
 205 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
 206                                 int state)
 207 {
 208         unsigned int reg_offset, bank_num, bank_pin_num;
 209         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 210
 211         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 212
 213         if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
 214                 /* only 16 data bits in bit maskable reg */
 215                 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
 216                 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
 217         } else {
 218                 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
 219         }
 220
 221         /*
 222          * get the 32 bit value to be written to the mask/data register where
 223          * the upper 16 bits is the mask and lower 16 bits is the data
 224          */
 225         state = !!state;
 226         state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
 227                 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 228
 229         writel_relaxed(state, gpio->base_addr + reg_offset);
 230 }
 231
 232 /**
 233  * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
 234  * @chip:       gpio_chip instance to be worked on
 235  * @pin:        gpio pin number within the device
 236  *
 237  * This function uses the read-modify-write sequence to set the direction of
 238  * the gpio pin as input.
 239  *
 240  * Return: 0 always
 241  */
 242 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
 243 {
 244         u32 reg;
 245         bool is_zynq_gpio;
 246         unsigned int bank_num, bank_pin_num;
 247         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 248
 249         is_zynq_gpio = gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_FOO;
 250         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 251
 252         /*
 253          * On zynq bank 0 pins 7 and 8 are special and cannot be used
 254          * as inputs.
 255          */
 256         if (is_zynq_gpio && bank_num == 0 &&
 257                 (bank_pin_num == 7 || bank_pin_num == 8))
 258                 return -EINVAL;
 259
 260         /* clear the bit in direction mode reg to set the pin as input */
 261         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 262         reg &= ~BIT(bank_pin_num);
 263         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 264
 265         return 0;
 266 }
 267
 268 /**
 269  * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
 270  * @chip:       gpio_chip instance to be worked on
 271  * @pin:        gpio pin number within the device
 272  * @state:      value to be written to specified pin
 273  *
 274  * This function sets the direction of specified GPIO pin as output, configures
 275  * the Output Enable register for the pin and uses zynq_gpio_set to set
 276  * the state of the pin to the value specified.
 277  *
 278  * Return: 0 always
 279  */
 280 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
 281                              int state)
 282 {
 283         u32 reg;
 284         unsigned int bank_num, bank_pin_num;
 285         struct zynq_gpio *gpio = gpiochip_get_data(chip);
 286
 287         zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
 288
 289         /* set the GPIO pin as output */
 290         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 291         reg |= BIT(bank_pin_num);
 292         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 293
 294         /* configure the output enable reg for the pin */
 295         reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 296         reg |= BIT(bank_pin_num);
 297         writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 298
 299         /* set the state of the pin */
 300         zynq_gpio_set_value(chip, pin, state);
 301         return 0;
 302 }
 303
 304 /**
 305  * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
 306  * @irq_data:   per irq and chip data passed down to chip functions
 307  *
 308  * This function calculates gpio pin number from irq number and sets the
 309  * bit in the Interrupt Disable register of the corresponding bank to disable
 310  * interrupts for that pin.
 311  */
 312 static void zynq_gpio_irq_mask(struct irq_data *irq_data)
 313 {
 314         unsigned int device_pin_num, bank_num, bank_pin_num;
 315         struct zynq_gpio *gpio =
 316                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 317
 318         device_pin_num = irq_data->hwirq;
 319         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 320         writel_relaxed(BIT(bank_pin_num),
 321                        gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 322 }
 323
 324 /**
 325  * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
 326  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 327  *              to enable
 328  *
 329  * This function calculates the gpio pin number from irq number and sets the
 330  * bit in the Interrupt Enable register of the corresponding bank to enable
 331  * interrupts for that pin.
 332  */
 333 static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
 334 {
 335         unsigned int device_pin_num, bank_num, bank_pin_num;
 336         struct zynq_gpio *gpio =
 337                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 338
 339         device_pin_num = irq_data->hwirq;
 340         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 341         writel_relaxed(BIT(bank_pin_num),
 342                        gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
 343 }
 344
 345 /**
 346  * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
 347  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 348  *              to ack
 349  *
 350  * This function calculates gpio pin number from irq number and sets the bit
 351  * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
 352  */
 353 static void zynq_gpio_irq_ack(struct irq_data *irq_data)
 354 {
 355         unsigned int device_pin_num, bank_num, bank_pin_num;
 356         struct zynq_gpio *gpio =
 357                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 358
 359         device_pin_num = irq_data->hwirq;
 360         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 361         writel_relaxed(BIT(bank_pin_num),
 362                        gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 363 }
 364
 365 /**
 366  * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
 367  * @irq_data:   irq data containing irq number of gpio pin for the interrupt
 368  *              to enable
 369  *
 370  * Clears the INTSTS bit and unmasks the given interrupt.
 371  */
 372 static void zynq_gpio_irq_enable(struct irq_data *irq_data)
 373 {
 374         /*
 375          * The Zynq GPIO controller does not disable interrupt detection when
 376          * the interrupt is masked and only disables the propagation of the
 377          * interrupt. This means when the controller detects an interrupt
 378          * condition while the interrupt is logically disabled it will propagate
 379          * that interrupt event once the interrupt is enabled. This will cause
 380          * the interrupt consumer to see spurious interrupts to prevent this
 381          * first make sure that the interrupt is not asserted and then enable
 382          * it.
 383          */
 384         zynq_gpio_irq_ack(irq_data);
 385         zynq_gpio_irq_unmask(irq_data);
 386 }
 387
 388 /**
 389  * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
 390  * @irq_data:   irq data containing irq number of gpio pin
 391  * @type:       interrupt type that is to be set for the gpio pin
 392  *
 393  * This function gets the gpio pin number and its bank from the gpio pin number
 394  * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
 395  *
 396  * Return: 0, negative error otherwise.
 397  * TYPE-EDGE_RISING,  INT_TYPE - 1, INT_POLARITY - 1,  INT_ANY - 0;
 398  * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0,  INT_ANY - 0;
 399  * TYPE-EDGE_BOTH,    INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
 400  * TYPE-LEVEL_HIGH,   INT_TYPE - 0, INT_POLARITY - 1,  INT_ANY - NA;
 401  * TYPE-LEVEL_LOW,    INT_TYPE - 0, INT_POLARITY - 0,  INT_ANY - NA
 402  */
 403 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
 404 {
 405         u32 int_type, int_pol, int_any;
 406         unsigned int device_pin_num, bank_num, bank_pin_num;
 407         struct zynq_gpio *gpio =
 408                 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
 409
 410         device_pin_num = irq_data->hwirq;
 411         zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
 412
 413         int_type = readl_relaxed(gpio->base_addr +
 414                                  ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 415         int_pol = readl_relaxed(gpio->base_addr +
 416                                 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 417         int_any = readl_relaxed(gpio->base_addr +
 418                                 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 419
 420         /*
 421          * based on the type requested, configure the INT_TYPE, INT_POLARITY
 422          * and INT_ANY registers
 423          */
 424         switch (type) {
 425         case IRQ_TYPE_EDGE_RISING:
 426                 int_type |= BIT(bank_pin_num);
 427                 int_pol |= BIT(bank_pin_num);
 428                 int_any &= ~BIT(bank_pin_num);
 429                 break;
 430         case IRQ_TYPE_EDGE_FALLING:
 431                 int_type |= BIT(bank_pin_num);
 432                 int_pol &= ~BIT(bank_pin_num);
 433                 int_any &= ~BIT(bank_pin_num);
 434                 break;
 435         case IRQ_TYPE_EDGE_BOTH:
 436                 int_type |= BIT(bank_pin_num);
 437                 int_any |= BIT(bank_pin_num);
 438                 break;
 439         case IRQ_TYPE_LEVEL_HIGH:
 440                 int_type &= ~BIT(bank_pin_num);
 441                 int_pol |= BIT(bank_pin_num);
 442                 break;
 443         case IRQ_TYPE_LEVEL_LOW:
 444                 int_type &= ~BIT(bank_pin_num);
 445                 int_pol &= ~BIT(bank_pin_num);
 446                 break;
 447         default:
 448                 return -EINVAL;
 449         }
 450
 451         writel_relaxed(int_type,
 452                        gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
 453         writel_relaxed(int_pol,
 454                        gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
 455         writel_relaxed(int_any,
 456                        gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
 457
 458         if (type & IRQ_TYPE_LEVEL_MASK) {
 459                 irq_set_chip_handler_name_locked(irq_data,
 460                         &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
 461         } else {
 462                 irq_set_chip_handler_name_locked(irq_data,
 463                         &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
 470 {
 471         struct zynq_gpio *gpio =
 472                 gpiochip_get_data(irq_data_get_irq_chip_data(data));
 473
 474         irq_set_irq_wake(gpio->irq, on);
 475
 476         return 0;
 477 }
 478
 479 /* irq chip descriptor */
 480 static struct irq_chip zynq_gpio_level_irqchip = {
 481         .name           = DRIVER_NAME,
 482         .irq_enable     = zynq_gpio_irq_enable,
 483         .irq_eoi        = zynq_gpio_irq_ack,
 484         .irq_mask       = zynq_gpio_irq_mask,
 485         .irq_unmask     = zynq_gpio_irq_unmask,
 486         .irq_set_type   = zynq_gpio_set_irq_type,
 487         .irq_set_wake   = zynq_gpio_set_wake,
 488         .flags          = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
 489                           IRQCHIP_MASK_ON_SUSPEND,
 490 };
 491
 492 static struct irq_chip zynq_gpio_edge_irqchip = {
 493         .name           = DRIVER_NAME,
 494         .irq_enable     = zynq_gpio_irq_enable,
 495         .irq_ack        = zynq_gpio_irq_ack,
 496         .irq_mask       = zynq_gpio_irq_mask,
 497         .irq_unmask     = zynq_gpio_irq_unmask,
 498         .irq_set_type   = zynq_gpio_set_irq_type,
 499         .irq_set_wake   = zynq_gpio_set_wake,
 500         .flags          = IRQCHIP_MASK_ON_SUSPEND,
 501 };
 502
 503 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
 504                                       unsigned int bank_num,
 505                                       unsigned long pending)
 506 {
 507         unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
 508         struct irq_domain *irqdomain = gpio->chip.irqdomain;
 509         int offset;
 510
 511         if (!pending)
 512                 return;
 513
 514         for_each_set_bit(offset, &pending, 32) {
 515                 unsigned int gpio_irq;
 516
 517                 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
 518                 generic_handle_irq(gpio_irq);
 519         }
 520 }
 521
 522 /**
 523  * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
 524  * @irq:        irq number of the gpio bank where interrupt has occurred
 525  * @desc:       irq descriptor instance of the 'irq'
 526  *
 527  * This function reads the Interrupt Status Register of each bank to get the
 528  * gpio pin number which has triggered an interrupt. It then acks the triggered
 529  * interrupt and calls the pin specific handler set by the higher layer
 530  * application for that pin.
 531  * Note: A bug is reported if no handler is set for the gpio pin.
 532  */
 533 static void zynq_gpio_irqhandler(struct irq_desc *desc)
 534 {
 535         u32 int_sts, int_enb;
 536         unsigned int bank_num;
 537         struct zynq_gpio *gpio =
 538                 gpiochip_get_data(irq_desc_get_handler_data(desc));
 539         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 540
 541         chained_irq_enter(irqchip, desc);
 542
 543         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
 544                 int_sts = readl_relaxed(gpio->base_addr +
 545                                         ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
 546                 int_enb = readl_relaxed(gpio->base_addr +
 547                                         ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
 548                 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
 549         }
 550
 551         chained_irq_exit(irqchip, desc);
 552 }
 553
 554 static int __maybe_unused zynq_gpio_suspend(struct device *dev)
 555 {
 556         struct platform_device *pdev = to_platform_device(dev);
 557         int irq = platform_get_irq(pdev, 0);
 558         struct irq_data *data = irq_get_irq_data(irq);
 559
 560         if (!irqd_is_wakeup_set(data))
 561                 return pm_runtime_force_suspend(dev);
 562
 563         return 0;
 564 }
 565
 566 static int __maybe_unused zynq_gpio_resume(struct device *dev)
 567 {
 568         struct platform_device *pdev = to_platform_device(dev);
 569         int irq = platform_get_irq(pdev, 0);
 570         struct irq_data *data = irq_get_irq_data(irq);
 571
 572         if (!irqd_is_wakeup_set(data))
 573                 return pm_runtime_force_resume(dev);
 574
 575         return 0;
 576 }
 577
 578 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
 579 {
 580         struct platform_device *pdev = to_platform_device(dev);
 581         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 582
 583         clk_disable_unprepare(gpio->clk);
 584
 585         return 0;
 586 }
 587
 588 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
 589 {
 590         struct platform_device *pdev = to_platform_device(dev);
 591         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 592
 593         return clk_prepare_enable(gpio->clk);
 594 }
 595
 596 static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
 597 {
 598         int ret;
 599
 600         ret = pm_runtime_get_sync(chip->parent);
 601
 602         /*
 603          * If the device is already active pm_runtime_get() will return 1 on
 604          * success, but gpio_request still needs to return 0.
 605          */
 606         return ret < 0 ? ret : 0;
 607 }
 608
 609 static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
 610 {
 611         pm_runtime_put(chip->parent);
 612 }
 613
 614 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
 615         SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
 616         SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
 617                         zynq_gpio_runtime_resume, NULL)
 618 };
 619
 620 static const struct zynq_platform_data zynqmp_gpio_def = {
 621         .label = "zynqmp_gpio",
 622         .ngpio = ZYNQMP_GPIO_NR_GPIOS,
 623         .max_bank = ZYNQMP_GPIO_MAX_BANK,
 624         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
 625         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
 626         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
 627         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
 628         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
 629         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
 630         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
 631         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
 632         .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
 633         .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
 634         .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
 635         .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
 636 };
 637
 638 static const struct zynq_platform_data zynq_gpio_def = {
 639         .label = "zynq_gpio",
 640         .quirks = ZYNQ_GPIO_QUIRK_FOO,
 641         .ngpio = ZYNQ_GPIO_NR_GPIOS,
 642         .max_bank = ZYNQ_GPIO_MAX_BANK,
 643         .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
 644         .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
 645         .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
 646         .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
 647         .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
 648         .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
 649         .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
 650         .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
 651 };
 652
 653 static const struct of_device_id zynq_gpio_of_match[] = {
 654         { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
 655         { .compatible = "xlnx,zynqmp-gpio-1.0",
 656                                         .data = (void *)&zynqmp_gpio_def },
 657         { /* end of table */ }
 658 };
 659 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
 660
 661 /**
 662  * zynq_gpio_probe - Initialization method for a zynq_gpio device
 663  * @pdev:       platform device instance
 664  *
 665  * This function allocates memory resources for the gpio device and registers
 666  * all the banks of the device. It will also set up interrupts for the gpio
 667  * pins.
 668  * Note: Interrupts are disabled for all the banks during initialization.
 669  *
 670  * Return: 0 on success, negative error otherwise.
 671  */
 672 static int zynq_gpio_probe(struct platform_device *pdev)
 673 {
 674         int ret, bank_num;
 675         struct zynq_gpio *gpio;
 676         struct gpio_chip *chip;
 677         struct resource *res;
 678         const struct of_device_id *match;
 679
 680         gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 681         if (!gpio)
 682                 return -ENOMEM;
 683
 684         match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
 685         if (!match) {
 686                 dev_err(&pdev->dev, "of_match_node() failed\n");
 687                 return -EINVAL;
 688         }
 689         gpio->p_data = match->data;
 690         platform_set_drvdata(pdev, gpio);
 691
 692         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 693         gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
 694         if (IS_ERR(gpio->base_addr))
 695                 return PTR_ERR(gpio->base_addr);
 696
 697         gpio->irq = platform_get_irq(pdev, 0);
 698         if (gpio->irq < 0) {
 699                 dev_err(&pdev->dev, "invalid IRQ\n");
 700                 return gpio->irq;
 701         }
 702
 703         /* configure the gpio chip */
 704         chip = &gpio->chip;
 705         chip->label = gpio->p_data->label;
 706         chip->owner = THIS_MODULE;
 707         chip->parent = &pdev->dev;
 708         chip->get = zynq_gpio_get_value;
 709         chip->set = zynq_gpio_set_value;
 710         chip->request = zynq_gpio_request;
 711         chip->free = zynq_gpio_free;
 712         chip->direction_input = zynq_gpio_dir_in;
 713         chip->direction_output = zynq_gpio_dir_out;
 714         chip->base = -1;
 715         chip->ngpio = gpio->p_data->ngpio;
 716
 717         /* Retrieve GPIO clock */
 718         gpio->clk = devm_clk_get(&pdev->dev, NULL);
 719         if (IS_ERR(gpio->clk)) {
 720                 dev_err(&pdev->dev, "input clock not found.\n");
 721                 return PTR_ERR(gpio->clk);
 722         }
 723         ret = clk_prepare_enable(gpio->clk);
 724         if (ret) {
 725                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 726                 return ret;
 727         }
 728
 729         pm_runtime_set_active(&pdev->dev);
 730         pm_runtime_enable(&pdev->dev);
 731         ret = pm_runtime_get_sync(&pdev->dev);
 732         if (ret < 0)
 733                 goto err_pm_dis;
 734
 735         /* report a bug if gpio chip registration fails */
 736         ret = gpiochip_add_data(chip, gpio);
 737         if (ret) {
 738                 dev_err(&pdev->dev, "Failed to add gpio chip\n");
 739                 goto err_pm_put;
 740         }
 741
 742         /* disable interrupts for all banks */
 743         for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
 744                 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
 745                                ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
 746
 747         ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
 748                                    handle_level_irq, IRQ_TYPE_NONE);
 749         if (ret) {
 750                 dev_err(&pdev->dev, "Failed to add irq chip\n");
 751                 goto err_rm_gpiochip;
 752         }
 753
 754         gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
 755                                      zynq_gpio_irqhandler);
 756
 757         pm_runtime_put(&pdev->dev);
 758
 759         return 0;
 760
 761 err_rm_gpiochip:
 762         gpiochip_remove(chip);
 763 err_pm_put:
 764         pm_runtime_put(&pdev->dev);
 765 err_pm_dis:
 766         pm_runtime_disable(&pdev->dev);
 767         clk_disable_unprepare(gpio->clk);
 768
 769         return ret;
 770 }
 771
 772 /**
 773  * zynq_gpio_remove - Driver removal function
 774  * @pdev:       platform device instance
 775  *
 776  * Return: 0 always
 777  */
 778 static int zynq_gpio_remove(struct platform_device *pdev)
 779 {
 780         struct zynq_gpio *gpio = platform_get_drvdata(pdev);
 781
 782         pm_runtime_get_sync(&pdev->dev);
 783         gpiochip_remove(&gpio->chip);
 784         clk_disable_unprepare(gpio->clk);
 785         device_set_wakeup_capable(&pdev->dev, 0);
 786         pm_runtime_disable(&pdev->dev);
 787         return 0;
 788 }
 789
 790 static struct platform_driver zynq_gpio_driver = {
 791         .driver = {
 792                 .name = DRIVER_NAME,
 793                 .pm = &zynq_gpio_dev_pm_ops,
 794                 .of_match_table = zynq_gpio_of_match,
 795         },
 796         .probe = zynq_gpio_probe,
 797         .remove = zynq_gpio_remove,
 798 };
 799
 800 /**
 801  * zynq_gpio_init - Initial driver registration call
 802  *
 803  * Return: value from platform_driver_register
 804  */
 805 static int __init zynq_gpio_init(void)
 806 {
 807         return platform_driver_register(&zynq_gpio_driver);
 808 }
 809 postcore_initcall(zynq_gpio_init);
 810
 811 static void __exit zynq_gpio_exit(void)
 812 {
 813         platform_driver_unregister(&zynq_gpio_driver);
 814 }
 815 module_exit(zynq_gpio_exit);
 816
 817 MODULE_AUTHOR("Xilinx Inc.");
 818 MODULE_DESCRIPTION("Zynq GPIO driver");
 819 MODULE_LICENSE("GPL");