sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / gpu / host1x / hw / hw_host1x02_uclass.h
blob028e49d9bac9837132f3ccbcb10067a8514dea58
1 /*
2 * Copyright (c) 2013 NVIDIA Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 * Function naming determines intended use:
21 * <x>_r(void) : Returns the offset for register <x>.
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
51 #ifndef HOST1X_HW_HOST1X02_UCLASS_H
52 #define HOST1X_HW_HOST1X02_UCLASS_H
54 static inline u32 host1x_uclass_incr_syncpt_r(void)
56 return 0x0;
58 #define HOST1X_UCLASS_INCR_SYNCPT \
59 host1x_uclass_incr_syncpt_r()
60 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
62 return (v & 0xff) << 8;
64 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
65 host1x_uclass_incr_syncpt_cond_f(v)
66 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
68 return (v & 0xff) << 0;
70 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
71 host1x_uclass_incr_syncpt_indx_f(v)
72 static inline u32 host1x_uclass_wait_syncpt_r(void)
74 return 0x8;
76 #define HOST1X_UCLASS_WAIT_SYNCPT \
77 host1x_uclass_wait_syncpt_r()
78 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
80 return (v & 0xff) << 24;
82 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
83 host1x_uclass_wait_syncpt_indx_f(v)
84 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
86 return (v & 0xffffff) << 0;
88 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
89 host1x_uclass_wait_syncpt_thresh_f(v)
90 static inline u32 host1x_uclass_wait_syncpt_base_r(void)
92 return 0x9;
94 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
95 host1x_uclass_wait_syncpt_base_r()
96 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
98 return (v & 0xff) << 24;
100 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
101 host1x_uclass_wait_syncpt_base_indx_f(v)
102 static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
104 return (v & 0xff) << 16;
106 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
107 host1x_uclass_wait_syncpt_base_base_indx_f(v)
108 static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
110 return (v & 0xffff) << 0;
112 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
113 host1x_uclass_wait_syncpt_base_offset_f(v)
114 static inline u32 host1x_uclass_load_syncpt_base_r(void)
116 return 0xb;
118 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
119 host1x_uclass_load_syncpt_base_r()
120 static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
122 return (v & 0xff) << 24;
124 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
125 host1x_uclass_load_syncpt_base_base_indx_f(v)
126 static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
128 return (v & 0xffffff) << 0;
130 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
131 host1x_uclass_load_syncpt_base_value_f(v)
132 static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
134 return (v & 0xff) << 24;
136 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
137 host1x_uclass_incr_syncpt_base_base_indx_f(v)
138 static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
140 return (v & 0xffffff) << 0;
142 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
143 host1x_uclass_incr_syncpt_base_offset_f(v)
144 static inline u32 host1x_uclass_indoff_r(void)
146 return 0x2d;
148 #define HOST1X_UCLASS_INDOFF \
149 host1x_uclass_indoff_r()
150 static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
152 return (v & 0xf) << 28;
154 #define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
155 host1x_uclass_indoff_indbe_f(v)
156 static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
158 return (v & 0x1) << 27;
160 #define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
161 host1x_uclass_indoff_autoinc_f(v)
162 static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
164 return (v & 0xff) << 18;
166 #define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
167 host1x_uclass_indoff_indmodid_f(v)
168 static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
170 return (v & 0xffff) << 2;
172 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
173 host1x_uclass_indoff_indroffset_f(v)
174 static inline u32 host1x_uclass_indoff_rwn_read_v(void)
176 return 1;
178 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
179 host1x_uclass_indoff_indroffset_f(v)
181 #endif