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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / iio / adc / mxs-lradc.c
blobb84d37c80a944dd4080c1207b23e20e6489e010f
1 /*
2 * Freescale MXS LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/device.h>
22 #include <linux/err.h>
23 #include <linux/input.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/stmp_device.h>
34 #include <linux/sysfs.h>
35
36 #include <linux/iio/buffer.h>
37 #include <linux/iio/iio.h>
38 #include <linux/iio/trigger.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41 #include <linux/iio/sysfs.h>
42
43 #define DRIVER_NAME "mxs-lradc"
44
45 #define LRADC_MAX_DELAY_CHANS 4
46 #define LRADC_MAX_MAPPED_CHANS 8
47 #define LRADC_MAX_TOTAL_CHANS 16
48
49 #define LRADC_DELAY_TIMER_HZ 2000
50
51 /*
52 * Make this runtime configurable if necessary. Currently, if the buffered mode
53 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
54 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
55 * seconds. The result is that the samples arrive every 500mS.
56 */
57 #define LRADC_DELAY_TIMER_PER 200
58 #define LRADC_DELAY_TIMER_LOOP 5
59
60 /*
61 * Once the pen touches the touchscreen, the touchscreen switches from
62 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
63 * is realized by worker thread, which is called every 20 or so milliseconds.
64 * This gives the touchscreen enough fluency and does not strain the system
65 * too much.
66 */
67 #define LRADC_TS_SAMPLE_DELAY_MS 5
68
69 /*
70 * The LRADC reads the following amount of samples from each touchscreen
71 * channel and the driver then computes average of these.
72 */
73 #define LRADC_TS_SAMPLE_AMOUNT 4
74
75 enum mxs_lradc_id {
76 IMX23_LRADC,
77 IMX28_LRADC,
78 };
79
80 static const char * const mx23_lradc_irq_names[] = {
81 "mxs-lradc-touchscreen",
82 "mxs-lradc-channel0",
83 "mxs-lradc-channel1",
84 "mxs-lradc-channel2",
85 "mxs-lradc-channel3",
86 "mxs-lradc-channel4",
87 "mxs-lradc-channel5",
88 "mxs-lradc-channel6",
89 "mxs-lradc-channel7",
90 };
91
92 static const char * const mx28_lradc_irq_names[] = {
93 "mxs-lradc-touchscreen",
94 "mxs-lradc-thresh0",
95 "mxs-lradc-thresh1",
96 "mxs-lradc-channel0",
97 "mxs-lradc-channel1",
98 "mxs-lradc-channel2",
99 "mxs-lradc-channel3",
100 "mxs-lradc-channel4",
101 "mxs-lradc-channel5",
102 "mxs-lradc-channel6",
103 "mxs-lradc-channel7",
104 "mxs-lradc-button0",
105 "mxs-lradc-button1",
106 };
107
108 struct mxs_lradc_of_config {
109 const int irq_count;
110 const char * const *irq_name;
111 const u32 *vref_mv;
112 };
113
114 #define VREF_MV_BASE 1850
115
116 static const u32 mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
117 VREF_MV_BASE, /* CH0 */
118 VREF_MV_BASE, /* CH1 */
119 VREF_MV_BASE, /* CH2 */
120 VREF_MV_BASE, /* CH3 */
121 VREF_MV_BASE, /* CH4 */
122 VREF_MV_BASE, /* CH5 */
123 VREF_MV_BASE * 2, /* CH6 VDDIO */
124 VREF_MV_BASE * 4, /* CH7 VBATT */
125 VREF_MV_BASE, /* CH8 Temp sense 0 */
126 VREF_MV_BASE, /* CH9 Temp sense 1 */
127 VREF_MV_BASE, /* CH10 */
128 VREF_MV_BASE, /* CH11 */
129 VREF_MV_BASE, /* CH12 USB_DP */
130 VREF_MV_BASE, /* CH13 USB_DN */
131 VREF_MV_BASE, /* CH14 VBG */
132 VREF_MV_BASE * 4, /* CH15 VDD5V */
133 };
134
135 static const u32 mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
136 VREF_MV_BASE, /* CH0 */
137 VREF_MV_BASE, /* CH1 */
138 VREF_MV_BASE, /* CH2 */
139 VREF_MV_BASE, /* CH3 */
140 VREF_MV_BASE, /* CH4 */
141 VREF_MV_BASE, /* CH5 */
142 VREF_MV_BASE, /* CH6 */
143 VREF_MV_BASE * 4, /* CH7 VBATT */
144 VREF_MV_BASE, /* CH8 Temp sense 0 */
145 VREF_MV_BASE, /* CH9 Temp sense 1 */
146 VREF_MV_BASE * 2, /* CH10 VDDIO */
147 VREF_MV_BASE, /* CH11 VTH */
148 VREF_MV_BASE * 2, /* CH12 VDDA */
149 VREF_MV_BASE, /* CH13 VDDD */
150 VREF_MV_BASE, /* CH14 VBG */
151 VREF_MV_BASE * 4, /* CH15 VDD5V */
152 };
153
154 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
155 [IMX23_LRADC] = {
156 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
157 .irq_name = mx23_lradc_irq_names,
158 .vref_mv = mx23_vref_mv,
159 },
160 [IMX28_LRADC] = {
161 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
162 .irq_name = mx28_lradc_irq_names,
163 .vref_mv = mx28_vref_mv,
164 },
165 };
166
167 enum mxs_lradc_ts {
168 MXS_LRADC_TOUCHSCREEN_NONE = 0,
169 MXS_LRADC_TOUCHSCREEN_4WIRE,
170 MXS_LRADC_TOUCHSCREEN_5WIRE,
171 };
172
173 /*
174 * Touchscreen handling
175 */
176 enum lradc_ts_plate {
177 LRADC_TOUCH = 0,
178 LRADC_SAMPLE_X,
179 LRADC_SAMPLE_Y,
180 LRADC_SAMPLE_PRESSURE,
181 LRADC_SAMPLE_VALID,
182 };
183
184 enum mxs_lradc_divbytwo {
185 MXS_LRADC_DIV_DISABLED = 0,
186 MXS_LRADC_DIV_ENABLED,
187 };
188
189 struct mxs_lradc_scale {
190 unsigned int integer;
191 unsigned int nano;
192 };
193
194 struct mxs_lradc {
195 struct device *dev;
196 void __iomem *base;
197 int irq[13];
198
199 struct clk *clk;
200
201 u32 *buffer;
202 struct iio_trigger *trig;
203
204 struct mutex lock;
205
206 struct completion completion;
207
208 const u32 *vref_mv;
209 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
210 unsigned long is_divided;
211
212 /*
213 * When the touchscreen is enabled, we give it two private virtual
214 * channels: #6 and #7. This means that only 6 virtual channels (instead
215 * of 8) will be available for buffered capture.
216 */
217 #define TOUCHSCREEN_VCHANNEL1 7
218 #define TOUCHSCREEN_VCHANNEL2 6
219 #define BUFFER_VCHANS_LIMITED 0x3f
220 #define BUFFER_VCHANS_ALL 0xff
221 u8 buffer_vchans;
222
223 /*
224 * Furthermore, certain LRADC channels are shared between touchscreen
225 * and/or touch-buttons and generic LRADC block. Therefore when using
226 * either of these, these channels are not available for the regular
227 * sampling. The shared channels are as follows:
228 *
229 * CH0 -- Touch button #0
230 * CH1 -- Touch button #1
231 * CH2 -- Touch screen XPUL
232 * CH3 -- Touch screen YPLL
233 * CH4 -- Touch screen XNUL
234 * CH5 -- Touch screen YNLR
235 * CH6 -- Touch screen WIPER (5-wire only)
236 *
237 * The bit fields below represents which parts of the LRADC block are
238 * switched into special mode of operation. These channels can not
239 * be sampled as regular LRADC channels. The driver will refuse any
240 * attempt to sample these channels.
241 */
242 #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
243 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
244 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
245 enum mxs_lradc_ts use_touchscreen;
246 bool use_touchbutton;
247
248 struct input_dev *ts_input;
249
250 enum mxs_lradc_id soc;
251 enum lradc_ts_plate cur_plate; /* state machine */
252 bool ts_valid;
253 unsigned ts_x_pos;
254 unsigned ts_y_pos;
255 unsigned ts_pressure;
256
257 /* handle touchscreen's physical behaviour */
258 /* samples per coordinate */
259 unsigned over_sample_cnt;
260 /* time clocks between samples */
261 unsigned over_sample_delay;
262 /* time in clocks to wait after the plates where switched */
263 unsigned settling_delay;
264 };
265
266 #define LRADC_CTRL0 0x00
267 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
268 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
269 # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
270 # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
271 # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
272 # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
273 # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
274 # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
275
276 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
277 # define LRADC_CTRL0_MX23_YM BIT(19)
278 # define LRADC_CTRL0_MX23_XM BIT(18)
279 # define LRADC_CTRL0_MX23_YP BIT(17)
280 # define LRADC_CTRL0_MX23_XP BIT(16)
281
282 # define LRADC_CTRL0_MX28_PLATE_MASK \
283 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
284 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
285 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
286 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
287
288 # define LRADC_CTRL0_MX23_PLATE_MASK \
289 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
290 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
291 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
292
293 #define LRADC_CTRL1 0x10
294 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
295 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
296 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
297 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
298 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
299 #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
300 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
301 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
302 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
303 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
304
305 #define LRADC_CTRL2 0x20
306 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
307 #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
308
309 #define LRADC_STATUS 0x40
310 #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
311
312 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
313 #define LRADC_CH_ACCUMULATE BIT(29)
314 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
315 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
316 #define LRADC_CH_NUM_SAMPLES(x) \
317 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
318 #define LRADC_CH_VALUE_MASK 0x3ffff
319 #define LRADC_CH_VALUE_OFFSET 0
320
321 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
322 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24)
323 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
324 #define LRADC_DELAY_TRIGGER(x) \
325 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
326 LRADC_DELAY_TRIGGER_LRADCS_MASK)
327 #define LRADC_DELAY_KICK BIT(20)
328 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
329 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
330 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
331 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
332 LRADC_DELAY_TRIGGER_DELAYS_MASK)
333 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
334 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
335 #define LRADC_DELAY_LOOP(x) \
336 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
337 LRADC_DELAY_LOOP_COUNT_MASK)
338 #define LRADC_DELAY_DELAY_MASK 0x7ff
339 #define LRADC_DELAY_DELAY_OFFSET 0
340 #define LRADC_DELAY_DELAY(x) \
341 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
342 LRADC_DELAY_DELAY_MASK)
343
344 #define LRADC_CTRL4 0x140
345 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
346 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
347 #define LRADC_CTRL4_LRADCSELECT(n, x) \
348 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
349 LRADC_CTRL4_LRADCSELECT_MASK(n))
350
351 #define LRADC_RESOLUTION 12
352 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
353
354 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
357 }
358
359 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361 writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
362 }
363
364 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
365 {
366 writel(val, lradc->base + reg);
367 }
368
369 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
370 {
371 if (lradc->soc == IMX23_LRADC)
372 return LRADC_CTRL0_MX23_PLATE_MASK;
373 return LRADC_CTRL0_MX28_PLATE_MASK;
374 }
375
376 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
377 {
378 if (lradc->soc == IMX23_LRADC)
379 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
380 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
381 }
382
383 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
384 {
385 if (lradc->soc == IMX23_LRADC)
386 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
387 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
388 }
389
390 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
391 {
392 if (lradc->soc == IMX23_LRADC)
393 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
394 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
395 }
396
397 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
398 {
399 if (lradc->soc == IMX23_LRADC)
400 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
401 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
402 }
403
404 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
405 {
406 if (lradc->soc == IMX23_LRADC)
407 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
408 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
409 }
410
411 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
412 {
413 return !!(readl(lradc->base + LRADC_STATUS) &
414 LRADC_STATUS_TOUCH_DETECT_RAW);
415 }
416
417 static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
418 unsigned ch)
419 {
420 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
421 LRADC_CTRL4);
422 mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
423 }
424
425 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
426 {
427 /*
428 * prepare for oversampling conversion
429 *
430 * from the datasheet:
431 * "The ACCUMULATE bit in the appropriate channel register
432 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
433 * otherwise, the IRQs will not fire."
434 */
435 mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
436 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
437 LRADC_CH(ch));
438
439 /*
440 * from the datasheet:
441 * "Software must clear this register in preparation for a
442 * multi-cycle accumulation.
443 */
444 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
445
446 /*
447 * prepare the delay/loop unit according to the oversampling count
448 *
449 * from the datasheet:
450 * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1,
451 * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise,
452 * the LRADC will not trigger the delay group."
453 */
454 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
455 LRADC_DELAY_TRIGGER_DELAYS(0) |
456 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
457 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
458 LRADC_DELAY(3));
459
460 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
461
462 /*
463 * after changing the touchscreen plates setting
464 * the signals need some initial time to settle. Start the
465 * SoC's delay unit and start the conversion later
466 * and automatically.
467 */
468 mxs_lradc_reg_wrt(
469 lradc,
470 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
471 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
472 LRADC_DELAY_KICK |
473 LRADC_DELAY_DELAY(lradc->settling_delay),
474 LRADC_DELAY(2));
475 }
476
477 /*
478 * Pressure detection is special:
479 * We want to do both required measurements for the pressure detection in
480 * one turn. Use the hardware features to chain both conversions and let the
481 * hardware report one interrupt if both conversions are done
482 */
483 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
484 unsigned ch2)
485 {
486 u32 reg;
487
488 /*
489 * prepare for oversampling conversion
490 *
491 * from the datasheet:
492 * "The ACCUMULATE bit in the appropriate channel register
493 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
494 * otherwise, the IRQs will not fire."
495 */
496 reg = LRADC_CH_ACCUMULATE |
497 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
498 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
499 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
500
501 /*
502 * from the datasheet:
503 * "Software must clear this register in preparation for a
504 * multi-cycle accumulation.
505 */
506 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
507 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
508
509 /* prepare the delay/loop unit according to the oversampling count */
510 mxs_lradc_reg_wrt(
511 lradc,
512 LRADC_DELAY_TRIGGER(1 << ch1) |
513 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
514 LRADC_DELAY_TRIGGER_DELAYS(0) |
515 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
516 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
517 LRADC_DELAY(3));
518
519 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
520
521 /*
522 * after changing the touchscreen plates setting
523 * the signals need some initial time to settle. Start the
524 * SoC's delay unit and start the conversion later
525 * and automatically.
526 */
527 mxs_lradc_reg_wrt(
528 lradc,
529 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
530 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
531 LRADC_DELAY_KICK |
532 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
533 }
534
535 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
536 unsigned channel)
537 {
538 u32 reg;
539 unsigned num_samples, val;
540
541 reg = readl(lradc->base + LRADC_CH(channel));
542 if (reg & LRADC_CH_ACCUMULATE)
543 num_samples = lradc->over_sample_cnt;
544 else
545 num_samples = 1;
546
547 val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
548 return val / num_samples;
549 }
550
551 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
552 unsigned ch1, unsigned ch2)
553 {
554 u32 reg, mask;
555 unsigned pressure, m1, m2;
556
557 mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
558 reg = readl(lradc->base + LRADC_CTRL1) & mask;
559
560 while (reg != mask) {
561 reg = readl(lradc->base + LRADC_CTRL1) & mask;
562 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
563 }
564
565 m1 = mxs_lradc_read_raw_channel(lradc, ch1);
566 m2 = mxs_lradc_read_raw_channel(lradc, ch2);
567
568 if (m2 == 0) {
569 dev_warn(lradc->dev, "Cannot calculate pressure\n");
570 return 1 << (LRADC_RESOLUTION - 1);
571 }
572
573 /* simply scale the value from 0 ... max ADC resolution */
574 pressure = m1;
575 pressure *= (1 << LRADC_RESOLUTION);
576 pressure /= m2;
577
578 dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
579 return pressure;
580 }
581
582 #define TS_CH_XP 2
583 #define TS_CH_YP 3
584 #define TS_CH_XM 4
585 #define TS_CH_YM 5
586
587 /*
588 * YP(open)--+-------------+
589 * | |--+
590 * | | |
591 * YM(-)--+-------------+ |
592 * +--------------+
593 * | |
594 * XP(weak+) XM(open)
595 *
596 * "weak+" means 200k Ohm VDDIO
597 * (-) means GND
598 */
599 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
600 {
601 /*
602 * In order to detect a touch event the 'touch detect enable' bit
603 * enables:
604 * - a weak pullup to the X+ connector
605 * - a strong ground at the Y- connector
606 */
607 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
608 mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
609 LRADC_CTRL0);
610 }
611
612 /*
613 * YP(meas)--+-------------+
614 * | |--+
615 * | | |
616 * YM(open)--+-------------+ |
617 * +--------------+
618 * | |
619 * XP(+) XM(-)
620 *
621 * (+) means here 1.85 V
622 * (-) means here GND
623 */
624 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
625 {
626 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
627 mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
628
629 lradc->cur_plate = LRADC_SAMPLE_X;
630 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
631 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
632 }
633
634 /*
635 * YP(+)--+-------------+
636 * | |--+
637 * | | |
638 * YM(-)--+-------------+ |
639 * +--------------+
640 * | |
641 * XP(open) XM(meas)
642 *
643 * (+) means here 1.85 V
644 * (-) means here GND
645 */
646 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
647 {
648 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
649 mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
650
651 lradc->cur_plate = LRADC_SAMPLE_Y;
652 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
653 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
654 }
655
656 /*
657 * YP(+)--+-------------+
658 * | |--+
659 * | | |
660 * YM(meas)--+-------------+ |
661 * +--------------+
662 * | |
663 * XP(meas) XM(-)
664 *
665 * (+) means here 1.85 V
666 * (-) means here GND
667 */
668 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
669 {
670 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
671 mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
672
673 lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
674 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
675 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
676 mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
677 TOUCHSCREEN_VCHANNEL1);
678 }
679
680 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
681 {
682 /* Configure the touchscreen type */
683 if (lradc->soc == IMX28_LRADC) {
684 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
685 LRADC_CTRL0);
686
687 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
688 mxs_lradc_reg_set(lradc,
689 LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
690 LRADC_CTRL0);
691 }
692
693 mxs_lradc_setup_touch_detection(lradc);
694
695 lradc->cur_plate = LRADC_TOUCH;
696 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
697 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
698 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
699 }
700
701 static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
702 {
703 mxs_lradc_reg_clear(lradc,
704 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
705 LRADC_CTRL1);
706 mxs_lradc_reg_set(lradc,
707 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1),
708 LRADC_CTRL1);
709 /*
710 * start with the Y-pos, because it uses nearly the same plate
711 * settings like the touch detection
712 */
713 mxs_lradc_prepare_y_pos(lradc);
714 }
715
716 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
717 {
718 input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
719 input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
720 input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
721 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
722 input_sync(lradc->ts_input);
723 }
724
725 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
726 {
727 mxs_lradc_setup_touch_detection(lradc);
728 lradc->cur_plate = LRADC_SAMPLE_VALID;
729 /*
730 * start a dummy conversion to burn time to settle the signals
731 * note: we are not interested in the conversion's value
732 */
733 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
734 mxs_lradc_reg_clear(lradc,
735 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
736 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2),
737 LRADC_CTRL1);
738 mxs_lradc_reg_wrt(
739 lradc,
740 LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
741 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
742 LRADC_DELAY(2));
743 }
744
745 /*
746 * in order to avoid false measurements, report only samples where
747 * the surface is still touched after the position measurement
748 */
749 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
750 {
751 /* if it is still touched, report the sample */
752 if (valid && mxs_lradc_check_touch_event(lradc)) {
753 lradc->ts_valid = true;
754 mxs_lradc_report_ts_event(lradc);
755 }
756
757 /* if it is even still touched, continue with the next measurement */
758 if (mxs_lradc_check_touch_event(lradc)) {
759 mxs_lradc_prepare_y_pos(lradc);
760 return;
761 }
762
763 if (lradc->ts_valid) {
764 /* signal the release */
765 lradc->ts_valid = false;
766 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
767 input_sync(lradc->ts_input);
768 }
769
770 /* if it is released, wait for the next touch via IRQ */
771 lradc->cur_plate = LRADC_TOUCH;
772 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
773 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
774 mxs_lradc_reg_clear(lradc,
775 LRADC_CTRL1_TOUCH_DETECT_IRQ |
776 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
777 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1),
778 LRADC_CTRL1);
779 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
780 }
781
782 /* touchscreen's state machine */
783 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
784 {
785 switch (lradc->cur_plate) {
786 case LRADC_TOUCH:
787 if (mxs_lradc_check_touch_event(lradc))
788 mxs_lradc_start_touch_event(lradc);
789 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
790 LRADC_CTRL1);
791 return;
792
793 case LRADC_SAMPLE_Y:
794 lradc->ts_y_pos =
795 mxs_lradc_read_raw_channel(lradc,
796 TOUCHSCREEN_VCHANNEL1);
797 mxs_lradc_prepare_x_pos(lradc);
798 return;
799
800 case LRADC_SAMPLE_X:
801 lradc->ts_x_pos =
802 mxs_lradc_read_raw_channel(lradc,
803 TOUCHSCREEN_VCHANNEL1);
804 mxs_lradc_prepare_pressure(lradc);
805 return;
806
807 case LRADC_SAMPLE_PRESSURE:
808 lradc->ts_pressure =
809 mxs_lradc_read_ts_pressure(lradc,
810 TOUCHSCREEN_VCHANNEL2,
811 TOUCHSCREEN_VCHANNEL1);
812 mxs_lradc_complete_touch_event(lradc);
813 return;
814
815 case LRADC_SAMPLE_VALID:
816 mxs_lradc_finish_touch_event(lradc, 1);
817 break;
818 }
819 }
820
821 /*
822 * Raw I/O operations
823 */
824 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
825 {
826 struct mxs_lradc *lradc = iio_priv(iio_dev);
827 int ret;
828
829 /*
830 * See if there is no buffered operation in progress. If there is, simply
831 * bail out. This can be improved to support both buffered and raw IO at
832 * the same time, yet the code becomes horribly complicated. Therefore I
833 * applied KISS principle here.
834 */
835 ret = mutex_trylock(&lradc->lock);
836 if (!ret)
837 return -EBUSY;
838
839 reinit_completion(&lradc->completion);
840
841 /*
842 * No buffered operation in progress, map the channel and trigger it.
843 * Virtual channel 0 is always used here as the others are always not
844 * used if doing raw sampling.
845 */
846 if (lradc->soc == IMX28_LRADC)
847 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
848 LRADC_CTRL1);
849 mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0);
850
851 /* Enable / disable the divider per requirement */
852 if (test_bit(chan, &lradc->is_divided))
853 mxs_lradc_reg_set(lradc,
854 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
855 LRADC_CTRL2);
856 else
857 mxs_lradc_reg_clear(lradc,
858 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
859 LRADC_CTRL2);
860
861 /* Clean the slot's previous content, then set new one. */
862 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
863 LRADC_CTRL4);
864 mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
865
866 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
867
868 /* Enable the IRQ and start sampling the channel. */
869 mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
870 mxs_lradc_reg_set(lradc, BIT(0), LRADC_CTRL0);
871
872 /* Wait for completion on the channel, 1 second max. */
873 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
874 if (!ret)
875 ret = -ETIMEDOUT;
876 if (ret < 0)
877 goto err;
878
879 /* Read the data. */
880 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
881 ret = IIO_VAL_INT;
882
883 err:
884 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
885
886 mutex_unlock(&lradc->lock);
887
888 return ret;
889 }
890
891 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
892 {
893 int ret, min, max;
894
895 ret = mxs_lradc_read_single(iio_dev, 8, &min);
896 if (ret != IIO_VAL_INT)
897 return ret;
898
899 ret = mxs_lradc_read_single(iio_dev, 9, &max);
900 if (ret != IIO_VAL_INT)
901 return ret;
902
903 *val = max - min;
904
905 return IIO_VAL_INT;
906 }
907
908 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
909 const struct iio_chan_spec *chan,
910 int *val, int *val2, long m)
911 {
912 struct mxs_lradc *lradc = iio_priv(iio_dev);
913
914 switch (m) {
915 case IIO_CHAN_INFO_RAW:
916 if (chan->type == IIO_TEMP)
917 return mxs_lradc_read_temp(iio_dev, val);
918
919 return mxs_lradc_read_single(iio_dev, chan->channel, val);
920
921 case IIO_CHAN_INFO_SCALE:
922 if (chan->type == IIO_TEMP) {
923 /*
924 * From the datasheet, we have to multiply by 1.012 and
925 * divide by 4
926 */
927 *val = 0;
928 *val2 = 253000;
929 return IIO_VAL_INT_PLUS_MICRO;
930 }
931
932 *val = lradc->vref_mv[chan->channel];
933 *val2 = chan->scan_type.realbits -
934 test_bit(chan->channel, &lradc->is_divided);
935 return IIO_VAL_FRACTIONAL_LOG2;
936
937 case IIO_CHAN_INFO_OFFSET:
938 if (chan->type == IIO_TEMP) {
939 /*
940 * The calculated value from the ADC is in Kelvin, we
941 * want Celsius for hwmon so the offset is -273.15
942 * The offset is applied before scaling so it is
943 * actually -213.15 * 4 / 1.012 = -1079.644268
944 */
945 *val = -1079;
946 *val2 = 644268;
947
948 return IIO_VAL_INT_PLUS_MICRO;
949 }
950
951 return -EINVAL;
952
953 default:
954 break;
955 }
956
957 return -EINVAL;
958 }
959
960 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
961 const struct iio_chan_spec *chan,
962 int val, int val2, long m)
963 {
964 struct mxs_lradc *lradc = iio_priv(iio_dev);
965 struct mxs_lradc_scale *scale_avail =
966 lradc->scale_avail[chan->channel];
967 int ret;
968
969 ret = mutex_trylock(&lradc->lock);
970 if (!ret)
971 return -EBUSY;
972
973 switch (m) {
974 case IIO_CHAN_INFO_SCALE:
975 ret = -EINVAL;
976 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
977 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
978 /* divider by two disabled */
979 clear_bit(chan->channel, &lradc->is_divided);
980 ret = 0;
981 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
982 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
983 /* divider by two enabled */
984 set_bit(chan->channel, &lradc->is_divided);
985 ret = 0;
986 }
987
988 break;
989 default:
990 ret = -EINVAL;
991 break;
992 }
993
994 mutex_unlock(&lradc->lock);
995
996 return ret;
997 }
998
999 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
1000 const struct iio_chan_spec *chan,
1001 long m)
1002 {
1003 return IIO_VAL_INT_PLUS_NANO;
1004 }
1005
1006 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
1007 struct device_attribute *attr,
1008 char *buf,
1009 int ch)
1010 {
1011 struct iio_dev *iio = dev_to_iio_dev(dev);
1012 struct mxs_lradc *lradc = iio_priv(iio);
1013 int i, len = 0;
1014
1015 for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
1016 len += sprintf(buf + len, "%u.%09u ",
1017 lradc->scale_avail[ch][i].integer,
1018 lradc->scale_avail[ch][i].nano);
1019
1020 len += sprintf(buf + len, "\n");
1021
1022 return len;
1023 }
1024
1025 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1026 struct device_attribute *attr,
1027 char *buf)
1028 {
1029 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1030
1031 return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1032 iio_attr->address);
1033 }
1034
1035 #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
1036 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
1037 mxs_lradc_show_scale_available, NULL, ch)
1038
1039 SHOW_SCALE_AVAILABLE_ATTR(0);
1040 SHOW_SCALE_AVAILABLE_ATTR(1);
1041 SHOW_SCALE_AVAILABLE_ATTR(2);
1042 SHOW_SCALE_AVAILABLE_ATTR(3);
1043 SHOW_SCALE_AVAILABLE_ATTR(4);
1044 SHOW_SCALE_AVAILABLE_ATTR(5);
1045 SHOW_SCALE_AVAILABLE_ATTR(6);
1046 SHOW_SCALE_AVAILABLE_ATTR(7);
1047 SHOW_SCALE_AVAILABLE_ATTR(10);
1048 SHOW_SCALE_AVAILABLE_ATTR(11);
1049 SHOW_SCALE_AVAILABLE_ATTR(12);
1050 SHOW_SCALE_AVAILABLE_ATTR(13);
1051 SHOW_SCALE_AVAILABLE_ATTR(14);
1052 SHOW_SCALE_AVAILABLE_ATTR(15);
1053
1054 static struct attribute *mxs_lradc_attributes[] = {
1055 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1056 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1057 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1058 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1059 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1060 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1061 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1062 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1063 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1064 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1065 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1066 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1067 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1068 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1069 NULL
1070 };
1071
1072 static const struct attribute_group mxs_lradc_attribute_group = {
1073 .attrs = mxs_lradc_attributes,
1074 };
1075
1076 static const struct iio_info mxs_lradc_iio_info = {
1077 .driver_module = THIS_MODULE,
1078 .read_raw = mxs_lradc_read_raw,
1079 .write_raw = mxs_lradc_write_raw,
1080 .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
1081 .attrs = &mxs_lradc_attribute_group,
1082 };
1083
1084 static int mxs_lradc_ts_open(struct input_dev *dev)
1085 {
1086 struct mxs_lradc *lradc = input_get_drvdata(dev);
1087
1088 /* Enable the touch-detect circuitry. */
1089 mxs_lradc_enable_touch_detection(lradc);
1090
1091 return 0;
1092 }
1093
1094 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1095 {
1096 /* stop all interrupts from firing */
1097 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1098 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
1099 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
1100
1101 /* Power-down touchscreen touch-detect circuitry. */
1102 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1103 }
1104
1105 static void mxs_lradc_ts_close(struct input_dev *dev)
1106 {
1107 struct mxs_lradc *lradc = input_get_drvdata(dev);
1108
1109 mxs_lradc_disable_ts(lradc);
1110 }
1111
1112 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1113 {
1114 struct input_dev *input;
1115 struct device *dev = lradc->dev;
1116
1117 if (!lradc->use_touchscreen)
1118 return 0;
1119
1120 input = devm_input_allocate_device(dev);
1121 if (!input)
1122 return -ENOMEM;
1123
1124 input->name = DRIVER_NAME;
1125 input->id.bustype = BUS_HOST;
1126 input->open = mxs_lradc_ts_open;
1127 input->close = mxs_lradc_ts_close;
1128
1129 __set_bit(EV_ABS, input->evbit);
1130 __set_bit(EV_KEY, input->evbit);
1131 __set_bit(BTN_TOUCH, input->keybit);
1132 __set_bit(INPUT_PROP_DIRECT, input->propbit);
1133 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1134 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1135 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1136 0, 0);
1137
1138 lradc->ts_input = input;
1139 input_set_drvdata(input, lradc);
1140
1141 return input_register_device(input);
1142 }
1143
1144 /*
1145 * IRQ Handling
1146 */
1147 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1148 {
1149 struct iio_dev *iio = data;
1150 struct mxs_lradc *lradc = iio_priv(iio);
1151 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1152 u32 clr_irq = mxs_lradc_irq_mask(lradc);
1153 const u32 ts_irq_mask =
1154 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1155 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1156 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
1157
1158 if (!(reg & mxs_lradc_irq_mask(lradc)))
1159 return IRQ_NONE;
1160
1161 if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
1162 mxs_lradc_handle_touch(lradc);
1163
1164 /* Make sure we don't clear the next conversion's interrupt. */
1165 clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1166 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
1167 }
1168
1169 if (iio_buffer_enabled(iio)) {
1170 if (reg & lradc->buffer_vchans)
1171 iio_trigger_poll(iio->trig);
1172 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
1173 complete(&lradc->completion);
1174 }
1175
1176 mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
1177
1178 return IRQ_HANDLED;
1179 }
1180
1181 /*
1182 * Trigger handling
1183 */
1184 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1185 {
1186 struct iio_poll_func *pf = p;
1187 struct iio_dev *iio = pf->indio_dev;
1188 struct mxs_lradc *lradc = iio_priv(iio);
1189 const u32 chan_value = LRADC_CH_ACCUMULATE |
1190 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1191 unsigned int i, j = 0;
1192
1193 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1194 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1195 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1196 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1197 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1198 j++;
1199 }
1200
1201 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1202
1203 iio_trigger_notify_done(iio->trig);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1209 {
1210 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1211 struct mxs_lradc *lradc = iio_priv(iio);
1212 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1213
1214 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1215
1216 return 0;
1217 }
1218
1219 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1220 .owner = THIS_MODULE,
1221 .set_trigger_state = &mxs_lradc_configure_trigger,
1222 };
1223
1224 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1225 {
1226 int ret;
1227 struct iio_trigger *trig;
1228 struct mxs_lradc *lradc = iio_priv(iio);
1229
1230 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1231 if (!trig)
1232 return -ENOMEM;
1233
1234 trig->dev.parent = lradc->dev;
1235 iio_trigger_set_drvdata(trig, iio);
1236 trig->ops = &mxs_lradc_trigger_ops;
1237
1238 ret = iio_trigger_register(trig);
1239 if (ret) {
1240 iio_trigger_free(trig);
1241 return ret;
1242 }
1243
1244 lradc->trig = trig;
1245
1246 return 0;
1247 }
1248
1249 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1250 {
1251 struct mxs_lradc *lradc = iio_priv(iio);
1252
1253 iio_trigger_unregister(lradc->trig);
1254 iio_trigger_free(lradc->trig);
1255 }
1256
1257 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1258 {
1259 struct mxs_lradc *lradc = iio_priv(iio);
1260 int ret = 0, chan, ofs = 0;
1261 unsigned long enable = 0;
1262 u32 ctrl4_set = 0;
1263 u32 ctrl4_clr = 0;
1264 u32 ctrl1_irq = 0;
1265 const u32 chan_value = LRADC_CH_ACCUMULATE |
1266 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1267 const int len = bitmap_weight(iio->active_scan_mask,
1268 LRADC_MAX_TOTAL_CHANS);
1269
1270 if (!len)
1271 return -EINVAL;
1272
1273 /*
1274 * Lock the driver so raw access can not be done during buffered
1275 * operation. This simplifies the code a lot.
1276 */
1277 ret = mutex_trylock(&lradc->lock);
1278 if (!ret)
1279 return -EBUSY;
1280
1281 lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1282 if (!lradc->buffer) {
1283 ret = -ENOMEM;
1284 goto err_mem;
1285 }
1286
1287 if (lradc->soc == IMX28_LRADC)
1288 mxs_lradc_reg_clear(
1289 lradc,
1290 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1291 LRADC_CTRL1);
1292 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1293
1294 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1295 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1296 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1297 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1298 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1299 bitmap_set(&enable, ofs, 1);
1300 ofs++;
1301 }
1302
1303 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1304 LRADC_DELAY_KICK, LRADC_DELAY(0));
1305 mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1306 mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1307 mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1308 mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1309 LRADC_DELAY(0));
1310
1311 return 0;
1312
1313 err_mem:
1314 mutex_unlock(&lradc->lock);
1315 return ret;
1316 }
1317
1318 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1319 {
1320 struct mxs_lradc *lradc = iio_priv(iio);
1321
1322 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1323 LRADC_DELAY_KICK, LRADC_DELAY(0));
1324
1325 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1326 if (lradc->soc == IMX28_LRADC)
1327 mxs_lradc_reg_clear(
1328 lradc,
1329 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1330 LRADC_CTRL1);
1331
1332 kfree(lradc->buffer);
1333 mutex_unlock(&lradc->lock);
1334
1335 return 0;
1336 }
1337
1338 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1339 const unsigned long *mask)
1340 {
1341 struct mxs_lradc *lradc = iio_priv(iio);
1342 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1343 int rsvd_chans = 0;
1344 unsigned long rsvd_mask = 0;
1345
1346 if (lradc->use_touchbutton)
1347 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1348 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1349 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1350 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1351 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1352
1353 if (lradc->use_touchbutton)
1354 rsvd_chans++;
1355 if (lradc->use_touchscreen)
1356 rsvd_chans += 2;
1357
1358 /* Test for attempts to map channels with special mode of operation. */
1359 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1360 return false;
1361
1362 /* Test for attempts to map more channels then available slots. */
1363 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1364 return false;
1365
1366 return true;
1367 }
1368
1369 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1370 .preenable = &mxs_lradc_buffer_preenable,
1371 .postenable = &iio_triggered_buffer_postenable,
1372 .predisable = &iio_triggered_buffer_predisable,
1373 .postdisable = &mxs_lradc_buffer_postdisable,
1374 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1375 };
1376
1377 /*
1378 * Driver initialization
1379 */
1380
1381 #define MXS_ADC_CHAN(idx, chan_type, name) { \
1382 .type = (chan_type), \
1383 .indexed = 1, \
1384 .scan_index = (idx), \
1385 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1386 BIT(IIO_CHAN_INFO_SCALE), \
1387 .channel = (idx), \
1388 .address = (idx), \
1389 .scan_type = { \
1390 .sign = 'u', \
1391 .realbits = LRADC_RESOLUTION, \
1392 .storagebits = 32, \
1393 }, \
1394 .datasheet_name = (name), \
1395 }
1396
1397 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
1398 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
1399 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
1400 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
1401 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
1402 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
1403 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
1404 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
1405 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
1406 /* Combined Temperature sensors */
1407 {
1408 .type = IIO_TEMP,
1409 .indexed = 1,
1410 .scan_index = 8,
1411 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1412 BIT(IIO_CHAN_INFO_OFFSET) |
1413 BIT(IIO_CHAN_INFO_SCALE),
1414 .channel = 8,
1415 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1416 .datasheet_name = "TEMP_DIE",
1417 },
1418 /* Hidden channel to keep indexes */
1419 {
1420 .type = IIO_TEMP,
1421 .indexed = 1,
1422 .scan_index = -1,
1423 .channel = 9,
1424 },
1425 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
1426 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
1427 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
1428 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
1429 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
1430 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
1431 };
1432
1433 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
1434 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
1435 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
1436 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
1437 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
1438 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
1439 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
1440 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
1441 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
1442 /* Combined Temperature sensors */
1443 {
1444 .type = IIO_TEMP,
1445 .indexed = 1,
1446 .scan_index = 8,
1447 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1448 BIT(IIO_CHAN_INFO_OFFSET) |
1449 BIT(IIO_CHAN_INFO_SCALE),
1450 .channel = 8,
1451 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1452 .datasheet_name = "TEMP_DIE",
1453 },
1454 /* Hidden channel to keep indexes */
1455 {
1456 .type = IIO_TEMP,
1457 .indexed = 1,
1458 .scan_index = -1,
1459 .channel = 9,
1460 },
1461 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
1462 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
1463 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
1464 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
1465 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
1466 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
1467 };
1468
1469 static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
1470 {
1471 /* The ADC always uses DELAY CHANNEL 0. */
1472 const u32 adc_cfg =
1473 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1474 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1475
1476 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1477 mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1478
1479 /* Disable remaining DELAY CHANNELs */
1480 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1481 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1482 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1483
1484 /* Start internal temperature sensing. */
1485 mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1486 }
1487
1488 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1489 {
1490 int i;
1491
1492 mxs_lradc_reg_clear(lradc,
1493 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1494 LRADC_CTRL1);
1495
1496 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1497 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1498 }
1499
1500 static const struct of_device_id mxs_lradc_dt_ids[] = {
1501 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1502 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1503 { /* sentinel */ }
1504 };
1505 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1506
1507 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1508 struct device_node *lradc_node)
1509 {
1510 int ret;
1511 u32 ts_wires = 0, adapt;
1512
1513 ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1514 &ts_wires);
1515 if (ret)
1516 return -ENODEV; /* touchscreen feature disabled */
1517
1518 switch (ts_wires) {
1519 case 4:
1520 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1521 break;
1522 case 5:
1523 if (lradc->soc == IMX28_LRADC) {
1524 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1525 break;
1526 }
1527 /* fall through an error message for i.MX23 */
1528 default:
1529 dev_err(lradc->dev,
1530 "Unsupported number of touchscreen wires (%d)\n",
1531 ts_wires);
1532 return -EINVAL;
1533 }
1534
1535 if (of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt)) {
1536 lradc->over_sample_cnt = 4;
1537 } else {
1538 if (adapt < 1 || adapt > 32) {
1539 dev_err(lradc->dev, "Invalid sample count (%u)\n",
1540 adapt);
1541 return -EINVAL;
1542 }
1543 lradc->over_sample_cnt = adapt;
1544 }
1545
1546 if (of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt)) {
1547 lradc->over_sample_delay = 2;
1548 } else {
1549 if (adapt < 2 || adapt > LRADC_DELAY_DELAY_MASK + 1) {
1550 dev_err(lradc->dev, "Invalid sample delay (%u)\n",
1551 adapt);
1552 return -EINVAL;
1553 }
1554 lradc->over_sample_delay = adapt;
1555 }
1556
1557 if (of_property_read_u32(lradc_node, "fsl,settling", &adapt)) {
1558 lradc->settling_delay = 10;
1559 } else {
1560 if (adapt < 1 || adapt > LRADC_DELAY_DELAY_MASK) {
1561 dev_err(lradc->dev, "Invalid settling delay (%u)\n",
1562 adapt);
1563 return -EINVAL;
1564 }
1565 lradc->settling_delay = adapt;
1566 }
1567
1568 return 0;
1569 }
1570
1571 static int mxs_lradc_probe(struct platform_device *pdev)
1572 {
1573 const struct of_device_id *of_id =
1574 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1575 const struct mxs_lradc_of_config *of_cfg =
1576 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1577 struct device *dev = &pdev->dev;
1578 struct device_node *node = dev->of_node;
1579 struct mxs_lradc *lradc;
1580 struct iio_dev *iio;
1581 struct resource *iores;
1582 int ret = 0, touch_ret;
1583 int i, s;
1584 u64 scale_uv;
1585
1586 /* Allocate the IIO device. */
1587 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1588 if (!iio) {
1589 dev_err(dev, "Failed to allocate IIO device\n");
1590 return -ENOMEM;
1591 }
1592
1593 lradc = iio_priv(iio);
1594 lradc->soc = (enum mxs_lradc_id)of_id->data;
1595
1596 /* Grab the memory area */
1597 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1598 lradc->dev = &pdev->dev;
1599 lradc->base = devm_ioremap_resource(dev, iores);
1600 if (IS_ERR(lradc->base))
1601 return PTR_ERR(lradc->base);
1602
1603 lradc->clk = devm_clk_get(&pdev->dev, NULL);
1604 if (IS_ERR(lradc->clk)) {
1605 dev_err(dev, "Failed to get the delay unit clock\n");
1606 return PTR_ERR(lradc->clk);
1607 }
1608 ret = clk_prepare_enable(lradc->clk);
1609 if (ret != 0) {
1610 dev_err(dev, "Failed to enable the delay unit clock\n");
1611 return ret;
1612 }
1613
1614 touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1615
1616 if (touch_ret == 0)
1617 lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
1618 else
1619 lradc->buffer_vchans = BUFFER_VCHANS_ALL;
1620
1621 /* Grab all IRQ sources */
1622 for (i = 0; i < of_cfg->irq_count; i++) {
1623 lradc->irq[i] = platform_get_irq(pdev, i);
1624 if (lradc->irq[i] < 0) {
1625 ret = lradc->irq[i];
1626 goto err_clk;
1627 }
1628
1629 ret = devm_request_irq(dev, lradc->irq[i],
1630 mxs_lradc_handle_irq, 0,
1631 of_cfg->irq_name[i], iio);
1632 if (ret)
1633 goto err_clk;
1634 }
1635
1636 lradc->vref_mv = of_cfg->vref_mv;
1637
1638 platform_set_drvdata(pdev, iio);
1639
1640 init_completion(&lradc->completion);
1641 mutex_init(&lradc->lock);
1642
1643 iio->name = pdev->name;
1644 iio->dev.parent = &pdev->dev;
1645 iio->info = &mxs_lradc_iio_info;
1646 iio->modes = INDIO_DIRECT_MODE;
1647 iio->masklength = LRADC_MAX_TOTAL_CHANS;
1648
1649 if (lradc->soc == IMX23_LRADC) {
1650 iio->channels = mx23_lradc_chan_spec;
1651 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
1652 } else {
1653 iio->channels = mx28_lradc_chan_spec;
1654 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
1655 }
1656
1657 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1658 &mxs_lradc_trigger_handler,
1659 &mxs_lradc_buffer_ops);
1660 if (ret)
1661 goto err_clk;
1662
1663 ret = mxs_lradc_trigger_init(iio);
1664 if (ret)
1665 goto err_trig;
1666
1667 /* Populate available ADC input ranges */
1668 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1669 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1670 /*
1671 * [s=0] = optional divider by two disabled (default)
1672 * [s=1] = optional divider by two enabled
1673 *
1674 * The scale is calculated by doing:
1675 * Vref >> (realbits - s)
1676 * which multiplies by two on the second component
1677 * of the array.
1678 */
1679 scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1680 (LRADC_RESOLUTION - s);
1681 lradc->scale_avail[i][s].nano =
1682 do_div(scale_uv, 100000000) * 10;
1683 lradc->scale_avail[i][s].integer = scale_uv;
1684 }
1685 }
1686
1687 ret = stmp_reset_block(lradc->base);
1688 if (ret)
1689 goto err_dev;
1690
1691 /* Configure the hardware. */
1692 mxs_lradc_hw_init(lradc);
1693
1694 /* Register the touchscreen input device. */
1695 if (touch_ret == 0) {
1696 ret = mxs_lradc_ts_register(lradc);
1697 if (ret)
1698 goto err_ts_register;
1699 }
1700
1701 /* Register IIO device. */
1702 ret = iio_device_register(iio);
1703 if (ret) {
1704 dev_err(dev, "Failed to register IIO device\n");
1705 return ret;
1706 }
1707
1708 return 0;
1709
1710 err_ts_register:
1711 mxs_lradc_hw_stop(lradc);
1712 err_dev:
1713 mxs_lradc_trigger_remove(iio);
1714 err_trig:
1715 iio_triggered_buffer_cleanup(iio);
1716 err_clk:
1717 clk_disable_unprepare(lradc->clk);
1718 return ret;
1719 }
1720
1721 static int mxs_lradc_remove(struct platform_device *pdev)
1722 {
1723 struct iio_dev *iio = platform_get_drvdata(pdev);
1724 struct mxs_lradc *lradc = iio_priv(iio);
1725
1726 iio_device_unregister(iio);
1727 mxs_lradc_hw_stop(lradc);
1728 mxs_lradc_trigger_remove(iio);
1729 iio_triggered_buffer_cleanup(iio);
1730
1731 clk_disable_unprepare(lradc->clk);
1732
1733 return 0;
1734 }
1735
1736 static struct platform_driver mxs_lradc_driver = {
1737 .driver = {
1738 .name = DRIVER_NAME,
1739 .of_match_table = mxs_lradc_dt_ids,
1740 },
1741 .probe = mxs_lradc_probe,
1742 .remove = mxs_lradc_remove,
1743 };
1744
1745 module_platform_driver(mxs_lradc_driver);
1746
1747 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1748 MODULE_DESCRIPTION("Freescale MXS LRADC driver");
1749 MODULE_LICENSE("GPL v2");
1750 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support