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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / isdn / hardware / mISDN / hfcmulti.c
blob480c2d7794ebdcfbcb38667a0807a156a1b2fac3
1 /*
2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
3 *
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
7 *
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * Thanks to Cologne Chip AG for this great controller!
29 */
30
31 /*
32 * module parameters:
33 * type:
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
41 * Bit 10 = spare
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
44 * Bit 13 = spare
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
49 * Bit 18 = spare
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
53 * bus (PCM master)
54 *
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
64 *
65 * HFC-E1 only bits:
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
73 * mode instead.
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
77 * (E1 only)
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
79 * for default.
80 * (all other bits are reserved and shall be 0)
81 *
82 * debug:
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
85 *
86 * poll:
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
92 *
93 * pcm:
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
105 *
106 * dmask and bmask:
107 * NOTE: One dmask value must be given for every HFC-E1 card.
108 * If omitted, the E1 card has D-channel on time slot 16, which is default.
109 * dmask is a 32 bit mask. The bit must be set for an alternate time slot.
110 * If multiple bits are set, multiple virtual card fragments are created.
111 * For each bit set, a bmask value must be given. Each bit on the bmask
112 * value stands for a B-channel. The bmask may not overlap with dmask or
113 * with other bmask values for that card.
114 * Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
115 * This will create one fragment with D-channel on slot 1 with
116 * B-channels on slots 2..15, and a second fragment with D-channel
117 * on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
118 * If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
119 * not function.
120 * Example: dmask=0x00000001 bmask=0xfffffffe
121 * This will create a port with all 31 usable timeslots as
122 * B-channels.
123 * If no bits are set on bmask, no B-channel is created for that fragment.
124 * Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
125 * This will create 31 ports with one D-channel only.
126 * If you don't know how to use it, you don't need it!
127 *
128 * iomode:
129 * NOTE: only one mode value must be given for every card.
130 * -> See hfc_multi.h for HFC_IO_MODE_* values
131 * By default, the IO mode is pci memory IO (MEMIO).
132 * Some cards require specific IO mode, so it cannot be changed.
133 * It may be useful to set IO mode to register io (REGIO) to solve
134 * PCI bridge problems.
135 * If unsure, don't give this parameter.
136 *
137 * clockdelay_nt:
138 * NOTE: only one clockdelay_nt value must be given once for all cards.
139 * Give the value of the clock control register (A_ST_CLK_DLY)
140 * of the S/T interfaces in NT mode.
141 * This register is needed for the TBR3 certification, so don't change it.
142 *
143 * clockdelay_te:
144 * NOTE: only one clockdelay_te value must be given once
145 * Give the value of the clock control register (A_ST_CLK_DLY)
146 * of the S/T interfaces in TE mode.
147 * This register is needed for the TBR3 certification, so don't change it.
148 *
149 * clock:
150 * NOTE: only one clock value must be given once
151 * Selects interface with clock source for mISDN and applications.
152 * Set to card number starting with 1. Set to -1 to disable.
153 * By default, the first card is used as clock source.
154 *
155 * hwid:
156 * NOTE: only one hwid value must be given once
157 * Enable special embedded devices with XHFC controllers.
158 */
159
160 /*
161 * debug register access (never use this, it will flood your system log)
162 * #define HFC_REGISTER_DEBUG
163 */
164
165 #define HFC_MULTI_VERSION "2.03"
166
167 #include <linux/interrupt.h>
168 #include <linux/module.h>
169 #include <linux/slab.h>
170 #include <linux/pci.h>
171 #include <linux/delay.h>
172 #include <linux/mISDNhw.h>
173 #include <linux/mISDNdsp.h>
174
175 /*
176 #define IRQCOUNT_DEBUG
177 #define IRQ_DEBUG
178 */
179
180 #include "hfc_multi.h"
181 #ifdef ECHOPREP
182 #include "gaintab.h"
183 #endif
184
185 #define MAX_CARDS 8
186 #define MAX_PORTS (8 * MAX_CARDS)
187 #define MAX_FRAGS (32 * MAX_CARDS)
188
189 static LIST_HEAD(HFClist);
190 static spinlock_t HFClock; /* global hfc list lock */
191
192 static void ph_state_change(struct dchannel *);
193
194 static struct hfc_multi *syncmaster;
195 static int plxsd_master; /* if we have a master card (yet) */
196 static spinlock_t plx_lock; /* may not acquire other lock inside */
197
198 #define TYP_E1 1
199 #define TYP_4S 4
200 #define TYP_8S 8
201
202 static int poll_timer = 6; /* default = 128 samples = 16ms */
203 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
204 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
205 #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
206 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode
207 (0x60 MUST be included!) */
208
209 #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
210 #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
211 #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
212
213 /*
214 * module stuff
215 */
216
217 static uint type[MAX_CARDS];
218 static int pcm[MAX_CARDS];
219 static uint dmask[MAX_CARDS];
220 static uint bmask[MAX_FRAGS];
221 static uint iomode[MAX_CARDS];
222 static uint port[MAX_PORTS];
223 static uint debug;
224 static uint poll;
225 static int clock;
226 static uint timer;
227 static uint clockdelay_te = CLKDEL_TE;
228 static uint clockdelay_nt = CLKDEL_NT;
229 #define HWID_NONE 0
230 #define HWID_MINIP4 1
231 #define HWID_MINIP8 2
232 #define HWID_MINIP16 3
233 static uint hwid = HWID_NONE;
234
235 static int HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
236
237 MODULE_AUTHOR("Andreas Eversberg");
238 MODULE_LICENSE("GPL");
239 MODULE_VERSION(HFC_MULTI_VERSION);
240 module_param(debug, uint, S_IRUGO | S_IWUSR);
241 module_param(poll, uint, S_IRUGO | S_IWUSR);
242 module_param(clock, int, S_IRUGO | S_IWUSR);
243 module_param(timer, uint, S_IRUGO | S_IWUSR);
244 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
245 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
246 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
247 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
248 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
249 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
250 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
251 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
252 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
253
254 #ifdef HFC_REGISTER_DEBUG
255 #define HFC_outb(hc, reg, val) \
256 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
257 #define HFC_outb_nodebug(hc, reg, val) \
258 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
259 #define HFC_inb(hc, reg) \
260 (hc->HFC_inb(hc, reg, __func__, __LINE__))
261 #define HFC_inb_nodebug(hc, reg) \
262 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
263 #define HFC_inw(hc, reg) \
264 (hc->HFC_inw(hc, reg, __func__, __LINE__))
265 #define HFC_inw_nodebug(hc, reg) \
266 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
267 #define HFC_wait(hc) \
268 (hc->HFC_wait(hc, __func__, __LINE__))
269 #define HFC_wait_nodebug(hc) \
270 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
271 #else
272 #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
273 #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
274 #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
275 #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
276 #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
277 #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
278 #define HFC_wait(hc) (hc->HFC_wait(hc))
279 #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
280 #endif
281
282 #ifdef CONFIG_MISDN_HFCMULTI_8xx
283 #include "hfc_multi_8xx.h"
284 #endif
285
286 /* HFC_IO_MODE_PCIMEM */
287 static void
288 #ifdef HFC_REGISTER_DEBUG
289 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
290 const char *function, int line)
291 #else
292 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
293 #endif
294 {
295 writeb(val, hc->pci_membase + reg);
296 }
297 static u_char
298 #ifdef HFC_REGISTER_DEBUG
299 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
300 #else
301 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
302 #endif
303 {
304 return readb(hc->pci_membase + reg);
305 }
306 static u_short
307 #ifdef HFC_REGISTER_DEBUG
308 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
309 #else
310 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
311 #endif
312 {
313 return readw(hc->pci_membase + reg);
314 }
315 static void
316 #ifdef HFC_REGISTER_DEBUG
317 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
318 #else
319 HFC_wait_pcimem(struct hfc_multi *hc)
320 #endif
321 {
322 while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
323 cpu_relax();
324 }
325
326 /* HFC_IO_MODE_REGIO */
327 static void
328 #ifdef HFC_REGISTER_DEBUG
329 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
330 const char *function, int line)
331 #else
332 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
333 #endif
334 {
335 outb(reg, hc->pci_iobase + 4);
336 outb(val, hc->pci_iobase);
337 }
338 static u_char
339 #ifdef HFC_REGISTER_DEBUG
340 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
341 #else
342 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
343 #endif
344 {
345 outb(reg, hc->pci_iobase + 4);
346 return inb(hc->pci_iobase);
347 }
348 static u_short
349 #ifdef HFC_REGISTER_DEBUG
350 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
351 #else
352 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
353 #endif
354 {
355 outb(reg, hc->pci_iobase + 4);
356 return inw(hc->pci_iobase);
357 }
358 static void
359 #ifdef HFC_REGISTER_DEBUG
360 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
361 #else
362 HFC_wait_regio(struct hfc_multi *hc)
363 #endif
364 {
365 outb(R_STATUS, hc->pci_iobase + 4);
366 while (inb(hc->pci_iobase) & V_BUSY)
367 cpu_relax();
368 }
369
370 #ifdef HFC_REGISTER_DEBUG
371 static void
372 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
373 const char *function, int line)
374 {
375 char regname[256] = "", bits[9] = "xxxxxxxx";
376 int i;
377
378 i = -1;
379 while (hfc_register_names[++i].name) {
380 if (hfc_register_names[i].reg == reg)
381 strcat(regname, hfc_register_names[i].name);
382 }
383 if (regname[0] == '\0')
384 strcpy(regname, "register");
385
386 bits[7] = '0' + (!!(val & 1));
387 bits[6] = '0' + (!!(val & 2));
388 bits[5] = '0' + (!!(val & 4));
389 bits[4] = '0' + (!!(val & 8));
390 bits[3] = '0' + (!!(val & 16));
391 bits[2] = '0' + (!!(val & 32));
392 bits[1] = '0' + (!!(val & 64));
393 bits[0] = '0' + (!!(val & 128));
394 printk(KERN_DEBUG
395 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
396 hc->id, reg, regname, val, bits, function, line);
397 HFC_outb_nodebug(hc, reg, val);
398 }
399 static u_char
400 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
401 {
402 char regname[256] = "", bits[9] = "xxxxxxxx";
403 u_char val = HFC_inb_nodebug(hc, reg);
404 int i;
405
406 i = 0;
407 while (hfc_register_names[i++].name)
408 ;
409 while (hfc_register_names[++i].name) {
410 if (hfc_register_names[i].reg == reg)
411 strcat(regname, hfc_register_names[i].name);
412 }
413 if (regname[0] == '\0')
414 strcpy(regname, "register");
415
416 bits[7] = '0' + (!!(val & 1));
417 bits[6] = '0' + (!!(val & 2));
418 bits[5] = '0' + (!!(val & 4));
419 bits[4] = '0' + (!!(val & 8));
420 bits[3] = '0' + (!!(val & 16));
421 bits[2] = '0' + (!!(val & 32));
422 bits[1] = '0' + (!!(val & 64));
423 bits[0] = '0' + (!!(val & 128));
424 printk(KERN_DEBUG
425 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
426 hc->id, reg, regname, val, bits, function, line);
427 return val;
428 }
429 static u_short
430 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
431 {
432 char regname[256] = "";
433 u_short val = HFC_inw_nodebug(hc, reg);
434 int i;
435
436 i = 0;
437 while (hfc_register_names[i++].name)
438 ;
439 while (hfc_register_names[++i].name) {
440 if (hfc_register_names[i].reg == reg)
441 strcat(regname, hfc_register_names[i].name);
442 }
443 if (regname[0] == '\0')
444 strcpy(regname, "register");
445
446 printk(KERN_DEBUG
447 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
448 hc->id, reg, regname, val, function, line);
449 return val;
450 }
451 static void
452 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
453 {
454 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
455 hc->id, function, line);
456 HFC_wait_nodebug(hc);
457 }
458 #endif
459
460 /* write fifo data (REGIO) */
461 static void
462 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
463 {
464 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
465 while (len >> 2) {
466 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
467 data += 4;
468 len -= 4;
469 }
470 while (len >> 1) {
471 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
472 data += 2;
473 len -= 2;
474 }
475 while (len) {
476 outb(*data, hc->pci_iobase);
477 data++;
478 len--;
479 }
480 }
481 /* write fifo data (PCIMEM) */
482 static void
483 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
484 {
485 while (len >> 2) {
486 writel(cpu_to_le32(*(u32 *)data),
487 hc->pci_membase + A_FIFO_DATA0);
488 data += 4;
489 len -= 4;
490 }
491 while (len >> 1) {
492 writew(cpu_to_le16(*(u16 *)data),
493 hc->pci_membase + A_FIFO_DATA0);
494 data += 2;
495 len -= 2;
496 }
497 while (len) {
498 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
499 data++;
500 len--;
501 }
502 }
503
504 /* read fifo data (REGIO) */
505 static void
506 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
507 {
508 outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
509 while (len >> 2) {
510 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
511 data += 4;
512 len -= 4;
513 }
514 while (len >> 1) {
515 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
516 data += 2;
517 len -= 2;
518 }
519 while (len) {
520 *data = inb(hc->pci_iobase);
521 data++;
522 len--;
523 }
524 }
525
526 /* read fifo data (PCIMEM) */
527 static void
528 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
529 {
530 while (len >> 2) {
531 *(u32 *)data =
532 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
533 data += 4;
534 len -= 4;
535 }
536 while (len >> 1) {
537 *(u16 *)data =
538 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
539 data += 2;
540 len -= 2;
541 }
542 while (len) {
543 *data = readb(hc->pci_membase + A_FIFO_DATA0);
544 data++;
545 len--;
546 }
547 }
548
549 static void
550 enable_hwirq(struct hfc_multi *hc)
551 {
552 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
553 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
554 }
555
556 static void
557 disable_hwirq(struct hfc_multi *hc)
558 {
559 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
560 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
561 }
562
563 #define NUM_EC 2
564 #define MAX_TDM_CHAN 32
565
566
567 static inline void
568 enablepcibridge(struct hfc_multi *c)
569 {
570 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
571 }
572
573 static inline void
574 disablepcibridge(struct hfc_multi *c)
575 {
576 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
577 }
578
579 static inline unsigned char
580 readpcibridge(struct hfc_multi *hc, unsigned char address)
581 {
582 unsigned short cipv;
583 unsigned char data;
584
585 if (!hc->pci_iobase)
586 return 0;
587
588 /* slow down a PCI read access by 1 PCI clock cycle */
589 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
590
591 if (address == 0)
592 cipv = 0x4000;
593 else
594 cipv = 0x5800;
595
596 /* select local bridge port address by writing to CIP port */
597 /* data = HFC_inb(c, cipv); * was _io before */
598 outw(cipv, hc->pci_iobase + 4);
599 data = inb(hc->pci_iobase);
600
601 /* restore R_CTRL for normal PCI read cycle speed */
602 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
603
604 return data;
605 }
606
607 static inline void
608 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
609 {
610 unsigned short cipv;
611 unsigned int datav;
612
613 if (!hc->pci_iobase)
614 return;
615
616 if (address == 0)
617 cipv = 0x4000;
618 else
619 cipv = 0x5800;
620
621 /* select local bridge port address by writing to CIP port */
622 outw(cipv, hc->pci_iobase + 4);
623 /* define a 32 bit dword with 4 identical bytes for write sequence */
624 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
625 ((__u32) data << 24);
626
627 /*
628 * write this 32 bit dword to the bridge data port
629 * this will initiate a write sequence of up to 4 writes to the same
630 * address on the local bus interface the number of write accesses
631 * is undefined but >=1 and depends on the next PCI transaction
632 * during write sequence on the local bus
633 */
634 outl(datav, hc->pci_iobase);
635 }
636
637 static inline void
638 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
639 {
640 /* Do data pin read low byte */
641 HFC_outb(hc, R_GPIO_OUT1, reg);
642 }
643
644 static inline void
645 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
646 {
647 cpld_set_reg(hc, reg);
648
649 enablepcibridge(hc);
650 writepcibridge(hc, 1, val);
651 disablepcibridge(hc);
652
653 return;
654 }
655
656 static inline unsigned char
657 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
658 {
659 unsigned char bytein;
660
661 cpld_set_reg(hc, reg);
662
663 /* Do data pin read low byte */
664 HFC_outb(hc, R_GPIO_OUT1, reg);
665
666 enablepcibridge(hc);
667 bytein = readpcibridge(hc, 1);
668 disablepcibridge(hc);
669
670 return bytein;
671 }
672
673 static inline void
674 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
675 {
676 cpld_write_reg(hc, 0, 0xff & addr);
677 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
678 }
679
680 static inline unsigned short
681 vpm_read_address(struct hfc_multi *c)
682 {
683 unsigned short addr;
684 unsigned short highbit;
685
686 addr = cpld_read_reg(c, 0);
687 highbit = cpld_read_reg(c, 1);
688
689 addr = addr | (highbit << 8);
690
691 return addr & 0x1ff;
692 }
693
694 static inline unsigned char
695 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
696 {
697 unsigned char res;
698
699 vpm_write_address(c, addr);
700
701 if (!which)
702 cpld_set_reg(c, 2);
703 else
704 cpld_set_reg(c, 3);
705
706 enablepcibridge(c);
707 res = readpcibridge(c, 1);
708 disablepcibridge(c);
709
710 cpld_set_reg(c, 0);
711
712 return res;
713 }
714
715 static inline void
716 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
717 unsigned char data)
718 {
719 vpm_write_address(c, addr);
720
721 enablepcibridge(c);
722
723 if (!which)
724 cpld_set_reg(c, 2);
725 else
726 cpld_set_reg(c, 3);
727
728 writepcibridge(c, 1, data);
729
730 cpld_set_reg(c, 0);
731
732 disablepcibridge(c);
733
734 {
735 unsigned char regin;
736 regin = vpm_in(c, which, addr);
737 if (regin != data)
738 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
739 "0x%x\n", data, addr, regin);
740 }
741
742 }
743
744
745 static void
746 vpm_init(struct hfc_multi *wc)
747 {
748 unsigned char reg;
749 unsigned int mask;
750 unsigned int i, x, y;
751 unsigned int ver;
752
753 for (x = 0; x < NUM_EC; x++) {
754 /* Setup GPIO's */
755 if (!x) {
756 ver = vpm_in(wc, x, 0x1a0);
757 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
758 }
759
760 for (y = 0; y < 4; y++) {
761 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
762 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
763 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
764 }
765
766 /* Setup TDM path - sets fsync and tdm_clk as inputs */
767 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
768 vpm_out(wc, x, 0x1a3, reg & ~2);
769
770 /* Setup Echo length (256 taps) */
771 vpm_out(wc, x, 0x022, 1);
772 vpm_out(wc, x, 0x023, 0xff);
773
774 /* Setup timeslots */
775 vpm_out(wc, x, 0x02f, 0x00);
776 mask = 0x02020202 << (x * 4);
777
778 /* Setup the tdm channel masks for all chips */
779 for (i = 0; i < 4; i++)
780 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
781
782 /* Setup convergence rate */
783 printk(KERN_DEBUG "VPM: A-law mode\n");
784 reg = 0x00 | 0x10 | 0x01;
785 vpm_out(wc, x, 0x20, reg);
786 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
787 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
788
789 vpm_out(wc, x, 0x24, 0x02);
790 reg = vpm_in(wc, x, 0x24);
791 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
792
793 /* Initialize echo cans */
794 for (i = 0; i < MAX_TDM_CHAN; i++) {
795 if (mask & (0x00000001 << i))
796 vpm_out(wc, x, i, 0x00);
797 }
798
799 /*
800 * ARM arch at least disallows a udelay of
801 * more than 2ms... it gives a fake "__bad_udelay"
802 * reference at link-time.
803 * long delays in kernel code are pretty sucky anyway
804 * for now work around it using 5 x 2ms instead of 1 x 10ms
805 */
806
807 udelay(2000);
808 udelay(2000);
809 udelay(2000);
810 udelay(2000);
811 udelay(2000);
812
813 /* Put in bypass mode */
814 for (i = 0; i < MAX_TDM_CHAN; i++) {
815 if (mask & (0x00000001 << i))
816 vpm_out(wc, x, i, 0x01);
817 }
818
819 /* Enable bypass */
820 for (i = 0; i < MAX_TDM_CHAN; i++) {
821 if (mask & (0x00000001 << i))
822 vpm_out(wc, x, 0x78 + i, 0x01);
823 }
824
825 }
826 }
827
828 #ifdef UNUSED
829 static void
830 vpm_check(struct hfc_multi *hctmp)
831 {
832 unsigned char gpi2;
833
834 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
835
836 if ((gpi2 & 0x3) != 0x3)
837 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
838 }
839 #endif /* UNUSED */
840
841
842 /*
843 * Interface to enable/disable the HW Echocan
844 *
845 * these functions are called within a spin_lock_irqsave on
846 * the channel instance lock, so we are not disturbed by irqs
847 *
848 * we can later easily change the interface to make other
849 * things configurable, for now we configure the taps
850 *
851 */
852
853 static void
854 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
855 {
856 unsigned int timeslot;
857 unsigned int unit;
858 struct bchannel *bch = hc->chan[ch].bch;
859 #ifdef TXADJ
860 int txadj = -4;
861 struct sk_buff *skb;
862 #endif
863 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
864 return;
865
866 if (!bch)
867 return;
868
869 #ifdef TXADJ
870 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
871 sizeof(int), &txadj, GFP_ATOMIC);
872 if (skb)
873 recv_Bchannel_skb(bch, skb);
874 #endif
875
876 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
877 unit = ch % 4;
878
879 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
880 taps, timeslot);
881
882 vpm_out(hc, unit, timeslot, 0x7e);
883 }
884
885 static void
886 vpm_echocan_off(struct hfc_multi *hc, int ch)
887 {
888 unsigned int timeslot;
889 unsigned int unit;
890 struct bchannel *bch = hc->chan[ch].bch;
891 #ifdef TXADJ
892 int txadj = 0;
893 struct sk_buff *skb;
894 #endif
895
896 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
897 return;
898
899 if (!bch)
900 return;
901
902 #ifdef TXADJ
903 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
904 sizeof(int), &txadj, GFP_ATOMIC);
905 if (skb)
906 recv_Bchannel_skb(bch, skb);
907 #endif
908
909 timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
910 unit = ch % 4;
911
912 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
913 timeslot);
914 /* FILLME */
915 vpm_out(hc, unit, timeslot, 0x01);
916 }
917
918
919 /*
920 * Speech Design resync feature
921 * NOTE: This is called sometimes outside interrupt handler.
922 * We must lock irqsave, so no other interrupt (other card) will occur!
923 * Also multiple interrupts may nest, so must lock each access (lists, card)!
924 */
925 static inline void
926 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
927 {
928 struct hfc_multi *hc, *next, *pcmmaster = NULL;
929 void __iomem *plx_acc_32;
930 u_int pv;
931 u_long flags;
932
933 spin_lock_irqsave(&HFClock, flags);
934 spin_lock(&plx_lock); /* must be locked inside other locks */
935
936 if (debug & DEBUG_HFCMULTI_PLXSD)
937 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
938 __func__, syncmaster);
939
940 /* select new master */
941 if (newmaster) {
942 if (debug & DEBUG_HFCMULTI_PLXSD)
943 printk(KERN_DEBUG "using provided controller\n");
944 } else {
945 list_for_each_entry_safe(hc, next, &HFClist, list) {
946 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
947 if (hc->syncronized) {
948 newmaster = hc;
949 break;
950 }
951 }
952 }
953 }
954
955 /* Disable sync of all cards */
956 list_for_each_entry_safe(hc, next, &HFClist, list) {
957 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
958 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
959 pv = readl(plx_acc_32);
960 pv &= ~PLX_SYNC_O_EN;
961 writel(pv, plx_acc_32);
962 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
963 pcmmaster = hc;
964 if (hc->ctype == HFC_TYPE_E1) {
965 if (debug & DEBUG_HFCMULTI_PLXSD)
966 printk(KERN_DEBUG
967 "Schedule SYNC_I\n");
968 hc->e1_resync |= 1; /* get SYNC_I */
969 }
970 }
971 }
972 }
973
974 if (newmaster) {
975 hc = newmaster;
976 if (debug & DEBUG_HFCMULTI_PLXSD)
977 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
978 "interface.\n", hc->id, hc);
979 /* Enable new sync master */
980 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
981 pv = readl(plx_acc_32);
982 pv |= PLX_SYNC_O_EN;
983 writel(pv, plx_acc_32);
984 /* switch to jatt PLL, if not disabled by RX_SYNC */
985 if (hc->ctype == HFC_TYPE_E1
986 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
987 if (debug & DEBUG_HFCMULTI_PLXSD)
988 printk(KERN_DEBUG "Schedule jatt PLL\n");
989 hc->e1_resync |= 2; /* switch to jatt */
990 }
991 } else {
992 if (pcmmaster) {
993 hc = pcmmaster;
994 if (debug & DEBUG_HFCMULTI_PLXSD)
995 printk(KERN_DEBUG
996 "id=%d (0x%p) = PCM master syncronized "
997 "with QUARTZ\n", hc->id, hc);
998 if (hc->ctype == HFC_TYPE_E1) {
999 /* Use the crystal clock for the PCM
1000 master card */
1001 if (debug & DEBUG_HFCMULTI_PLXSD)
1002 printk(KERN_DEBUG
1003 "Schedule QUARTZ for HFC-E1\n");
1004 hc->e1_resync |= 4; /* switch quartz */
1005 } else {
1006 if (debug & DEBUG_HFCMULTI_PLXSD)
1007 printk(KERN_DEBUG
1008 "QUARTZ is automatically "
1009 "enabled by HFC-%dS\n", hc->ctype);
1010 }
1011 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1012 pv = readl(plx_acc_32);
1013 pv |= PLX_SYNC_O_EN;
1014 writel(pv, plx_acc_32);
1015 } else
1016 if (!rm)
1017 printk(KERN_ERR "%s no pcm master, this MUST "
1018 "not happen!\n", __func__);
1019 }
1020 syncmaster = newmaster;
1021
1022 spin_unlock(&plx_lock);
1023 spin_unlock_irqrestore(&HFClock, flags);
1024 }
1025
1026 /* This must be called AND hc must be locked irqsave!!! */
1027 static inline void
1028 plxsd_checksync(struct hfc_multi *hc, int rm)
1029 {
1030 if (hc->syncronized) {
1031 if (syncmaster == NULL) {
1032 if (debug & DEBUG_HFCMULTI_PLXSD)
1033 printk(KERN_DEBUG "%s: GOT sync on card %d"
1034 " (id=%d)\n", __func__, hc->id + 1,
1035 hc->id);
1036 hfcmulti_resync(hc, hc, rm);
1037 }
1038 } else {
1039 if (syncmaster == hc) {
1040 if (debug & DEBUG_HFCMULTI_PLXSD)
1041 printk(KERN_DEBUG "%s: LOST sync on card %d"
1042 " (id=%d)\n", __func__, hc->id + 1,
1043 hc->id);
1044 hfcmulti_resync(hc, NULL, rm);
1045 }
1046 }
1047 }
1048
1049
1050 /*
1051 * free hardware resources used by driver
1052 */
1053 static void
1054 release_io_hfcmulti(struct hfc_multi *hc)
1055 {
1056 void __iomem *plx_acc_32;
1057 u_int pv;
1058 u_long plx_flags;
1059
1060 if (debug & DEBUG_HFCMULTI_INIT)
1061 printk(KERN_DEBUG "%s: entered\n", __func__);
1062
1063 /* soft reset also masks all interrupts */
1064 hc->hw.r_cirm |= V_SRES;
1065 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1066 udelay(1000);
1067 hc->hw.r_cirm &= ~V_SRES;
1068 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1069 udelay(1000); /* instead of 'wait' that may cause locking */
1070
1071 /* release Speech Design card, if PLX was initialized */
1072 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1073 if (debug & DEBUG_HFCMULTI_PLXSD)
1074 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1075 __func__, hc->id + 1);
1076 spin_lock_irqsave(&plx_lock, plx_flags);
1077 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1078 writel(PLX_GPIOC_INIT, plx_acc_32);
1079 pv = readl(plx_acc_32);
1080 /* Termination off */
1081 pv &= ~PLX_TERM_ON;
1082 /* Disconnect the PCM */
1083 pv |= PLX_SLAVE_EN_N;
1084 pv &= ~PLX_MASTER_EN;
1085 pv &= ~PLX_SYNC_O_EN;
1086 /* Put the DSP in Reset */
1087 pv &= ~PLX_DSP_RES_N;
1088 writel(pv, plx_acc_32);
1089 if (debug & DEBUG_HFCMULTI_INIT)
1090 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1091 __func__, pv);
1092 spin_unlock_irqrestore(&plx_lock, plx_flags);
1093 }
1094
1095 /* disable memory mapped ports / io ports */
1096 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1097 if (hc->pci_dev)
1098 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1099 if (hc->pci_membase)
1100 iounmap(hc->pci_membase);
1101 if (hc->plx_membase)
1102 iounmap(hc->plx_membase);
1103 if (hc->pci_iobase)
1104 release_region(hc->pci_iobase, 8);
1105 if (hc->xhfc_membase)
1106 iounmap((void *)hc->xhfc_membase);
1107
1108 if (hc->pci_dev) {
1109 pci_disable_device(hc->pci_dev);
1110 pci_set_drvdata(hc->pci_dev, NULL);
1111 }
1112 if (debug & DEBUG_HFCMULTI_INIT)
1113 printk(KERN_DEBUG "%s: done\n", __func__);
1114 }
1115
1116 /*
1117 * function called to reset the HFC chip. A complete software reset of chip
1118 * and fifos is done. All configuration of the chip is done.
1119 */
1120
1121 static int
1122 init_chip(struct hfc_multi *hc)
1123 {
1124 u_long flags, val, val2 = 0, rev;
1125 int i, err = 0;
1126 u_char r_conf_en, rval;
1127 void __iomem *plx_acc_32;
1128 u_int pv;
1129 u_long plx_flags, hfc_flags;
1130 int plx_count;
1131 struct hfc_multi *pos, *next, *plx_last_hc;
1132
1133 spin_lock_irqsave(&hc->lock, flags);
1134 /* reset all registers */
1135 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1136
1137 /* revision check */
1138 if (debug & DEBUG_HFCMULTI_INIT)
1139 printk(KERN_DEBUG "%s: entered\n", __func__);
1140 val = HFC_inb(hc, R_CHIP_ID);
1141 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1142 (val >> 1) != 0x31) {
1143 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1144 err = -EIO;
1145 goto out;
1146 }
1147 rev = HFC_inb(hc, R_CHIP_RV);
1148 printk(KERN_INFO
1149 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1150 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1151 " (old FIFO handling)" : "");
1152 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1153 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1154 printk(KERN_WARNING
1155 "HFC_multi: NOTE: Your chip is revision 0, "
1156 "ask Cologne Chip for update. Newer chips "
1157 "have a better FIFO handling. Old chips "
1158 "still work but may have slightly lower "
1159 "HDLC transmit performance.\n");
1160 }
1161 if (rev > 1) {
1162 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1163 "consider chip revision = %ld. The chip / "
1164 "bridge may not work.\n", rev);
1165 }
1166
1167 /* set s-ram size */
1168 hc->Flen = 0x10;
1169 hc->Zmin = 0x80;
1170 hc->Zlen = 384;
1171 hc->DTMFbase = 0x1000;
1172 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1173 if (debug & DEBUG_HFCMULTI_INIT)
1174 printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1175 __func__);
1176 hc->hw.r_ctrl |= V_EXT_RAM;
1177 hc->hw.r_ram_sz = 1;
1178 hc->Flen = 0x20;
1179 hc->Zmin = 0xc0;
1180 hc->Zlen = 1856;
1181 hc->DTMFbase = 0x2000;
1182 }
1183 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1184 if (debug & DEBUG_HFCMULTI_INIT)
1185 printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1186 __func__);
1187 hc->hw.r_ctrl |= V_EXT_RAM;
1188 hc->hw.r_ram_sz = 2;
1189 hc->Flen = 0x20;
1190 hc->Zmin = 0xc0;
1191 hc->Zlen = 8000;
1192 hc->DTMFbase = 0x2000;
1193 }
1194 if (hc->ctype == HFC_TYPE_XHFC) {
1195 hc->Flen = 0x8;
1196 hc->Zmin = 0x0;
1197 hc->Zlen = 64;
1198 hc->DTMFbase = 0x0;
1199 }
1200 hc->max_trans = poll << 1;
1201 if (hc->max_trans > hc->Zlen)
1202 hc->max_trans = hc->Zlen;
1203
1204 /* Speech Design PLX bridge */
1205 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1206 if (debug & DEBUG_HFCMULTI_PLXSD)
1207 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1208 __func__, hc->id + 1);
1209 spin_lock_irqsave(&plx_lock, plx_flags);
1210 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1211 writel(PLX_GPIOC_INIT, plx_acc_32);
1212 pv = readl(plx_acc_32);
1213 /* The first and the last cards are terminating the PCM bus */
1214 pv |= PLX_TERM_ON; /* hc is currently the last */
1215 /* Disconnect the PCM */
1216 pv |= PLX_SLAVE_EN_N;
1217 pv &= ~PLX_MASTER_EN;
1218 pv &= ~PLX_SYNC_O_EN;
1219 /* Put the DSP in Reset */
1220 pv &= ~PLX_DSP_RES_N;
1221 writel(pv, plx_acc_32);
1222 spin_unlock_irqrestore(&plx_lock, plx_flags);
1223 if (debug & DEBUG_HFCMULTI_INIT)
1224 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1225 __func__, pv);
1226 /*
1227 * If we are the 3rd PLXSD card or higher, we must turn
1228 * termination of last PLXSD card off.
1229 */
1230 spin_lock_irqsave(&HFClock, hfc_flags);
1231 plx_count = 0;
1232 plx_last_hc = NULL;
1233 list_for_each_entry_safe(pos, next, &HFClist, list) {
1234 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1235 plx_count++;
1236 if (pos != hc)
1237 plx_last_hc = pos;
1238 }
1239 }
1240 if (plx_count >= 3) {
1241 if (debug & DEBUG_HFCMULTI_PLXSD)
1242 printk(KERN_DEBUG "%s: card %d is between, so "
1243 "we disable termination\n",
1244 __func__, plx_last_hc->id + 1);
1245 spin_lock_irqsave(&plx_lock, plx_flags);
1246 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1247 pv = readl(plx_acc_32);
1248 pv &= ~PLX_TERM_ON;
1249 writel(pv, plx_acc_32);
1250 spin_unlock_irqrestore(&plx_lock, plx_flags);
1251 if (debug & DEBUG_HFCMULTI_INIT)
1252 printk(KERN_DEBUG
1253 "%s: term off: PLX_GPIO=%x\n",
1254 __func__, pv);
1255 }
1256 spin_unlock_irqrestore(&HFClock, hfc_flags);
1257 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1258 }
1259
1260 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1261 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1262
1263 /* we only want the real Z2 read-pointer for revision > 0 */
1264 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1265 hc->hw.r_ram_sz |= V_FZ_MD;
1266
1267 /* select pcm mode */
1268 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1269 if (debug & DEBUG_HFCMULTI_INIT)
1270 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1271 __func__);
1272 } else
1273 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1274 if (debug & DEBUG_HFCMULTI_INIT)
1275 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1276 __func__);
1277 hc->hw.r_pcm_md0 |= V_PCM_MD;
1278 } else {
1279 if (debug & DEBUG_HFCMULTI_INIT)
1280 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1281 __func__);
1282 }
1283
1284 /* soft reset */
1285 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1286 if (hc->ctype == HFC_TYPE_XHFC)
1287 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1288 0x11 /* 16 Bytes TX/RX */);
1289 else
1290 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1291 HFC_outb(hc, R_FIFO_MD, 0);
1292 if (hc->ctype == HFC_TYPE_XHFC)
1293 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1294 else
1295 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1296 | V_RLD_EPR;
1297 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1298 udelay(100);
1299 hc->hw.r_cirm = 0;
1300 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1301 udelay(100);
1302 if (hc->ctype != HFC_TYPE_XHFC)
1303 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1304
1305 /* Speech Design PLX bridge pcm and sync mode */
1306 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1307 spin_lock_irqsave(&plx_lock, plx_flags);
1308 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1309 pv = readl(plx_acc_32);
1310 /* Connect PCM */
1311 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1312 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1313 pv |= PLX_SYNC_O_EN;
1314 if (debug & DEBUG_HFCMULTI_INIT)
1315 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1316 __func__, pv);
1317 } else {
1318 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1319 pv &= ~PLX_SYNC_O_EN;
1320 if (debug & DEBUG_HFCMULTI_INIT)
1321 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1322 __func__, pv);
1323 }
1324 writel(pv, plx_acc_32);
1325 spin_unlock_irqrestore(&plx_lock, plx_flags);
1326 }
1327
1328 /* PCM setup */
1329 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1330 if (hc->slots == 32)
1331 HFC_outb(hc, R_PCM_MD1, 0x00);
1332 if (hc->slots == 64)
1333 HFC_outb(hc, R_PCM_MD1, 0x10);
1334 if (hc->slots == 128)
1335 HFC_outb(hc, R_PCM_MD1, 0x20);
1336 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1337 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1338 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1339 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1340 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1341 else
1342 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1343 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1344 for (i = 0; i < 256; i++) {
1345 HFC_outb_nodebug(hc, R_SLOT, i);
1346 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1347 if (hc->ctype != HFC_TYPE_XHFC)
1348 HFC_outb_nodebug(hc, A_CONF, 0);
1349 hc->slot_owner[i] = -1;
1350 }
1351
1352 /* set clock speed */
1353 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1354 if (debug & DEBUG_HFCMULTI_INIT)
1355 printk(KERN_DEBUG
1356 "%s: setting double clock\n", __func__);
1357 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1358 }
1359
1360 if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1361 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1362
1363 /* B410P GPIO */
1364 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1365 printk(KERN_NOTICE "Setting GPIOs\n");
1366 HFC_outb(hc, R_GPIO_SEL, 0x30);
1367 HFC_outb(hc, R_GPIO_EN1, 0x3);
1368 udelay(1000);
1369 printk(KERN_NOTICE "calling vpm_init\n");
1370 vpm_init(hc);
1371 }
1372
1373 /* check if R_F0_CNT counts (8 kHz frame count) */
1374 val = HFC_inb(hc, R_F0_CNTL);
1375 val += HFC_inb(hc, R_F0_CNTH) << 8;
1376 if (debug & DEBUG_HFCMULTI_INIT)
1377 printk(KERN_DEBUG
1378 "HFC_multi F0_CNT %ld after reset\n", val);
1379 spin_unlock_irqrestore(&hc->lock, flags);
1380 set_current_state(TASK_UNINTERRUPTIBLE);
1381 schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1382 spin_lock_irqsave(&hc->lock, flags);
1383 val2 = HFC_inb(hc, R_F0_CNTL);
1384 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1385 if (debug & DEBUG_HFCMULTI_INIT)
1386 printk(KERN_DEBUG
1387 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1388 val2);
1389 if (val2 >= val + 8) { /* 1 ms */
1390 /* it counts, so we keep the pcm mode */
1391 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1392 printk(KERN_INFO "controller is PCM bus MASTER\n");
1393 else
1394 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1395 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1396 else {
1397 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1398 printk(KERN_INFO "controller is PCM bus SLAVE "
1399 "(auto detected)\n");
1400 }
1401 } else {
1402 /* does not count */
1403 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1404 controller_fail:
1405 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1406 "pulse. Seems that controller fails.\n");
1407 err = -EIO;
1408 goto out;
1409 }
1410 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1411 printk(KERN_INFO "controller is PCM bus SLAVE "
1412 "(ignoring missing PCM clock)\n");
1413 } else {
1414 /* only one pcm master */
1415 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1416 && plxsd_master) {
1417 printk(KERN_ERR "HFC_multi ERROR, no clock "
1418 "on another Speech Design card found. "
1419 "Please be sure to connect PCM cable.\n");
1420 err = -EIO;
1421 goto out;
1422 }
1423 /* retry with master clock */
1424 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1425 spin_lock_irqsave(&plx_lock, plx_flags);
1426 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1427 pv = readl(plx_acc_32);
1428 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1429 pv |= PLX_SYNC_O_EN;
1430 writel(pv, plx_acc_32);
1431 spin_unlock_irqrestore(&plx_lock, plx_flags);
1432 if (debug & DEBUG_HFCMULTI_INIT)
1433 printk(KERN_DEBUG "%s: master: "
1434 "PLX_GPIO=%x\n", __func__, pv);
1435 }
1436 hc->hw.r_pcm_md0 |= V_PCM_MD;
1437 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1438 spin_unlock_irqrestore(&hc->lock, flags);
1439 set_current_state(TASK_UNINTERRUPTIBLE);
1440 schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1441 spin_lock_irqsave(&hc->lock, flags);
1442 val2 = HFC_inb(hc, R_F0_CNTL);
1443 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1444 if (debug & DEBUG_HFCMULTI_INIT)
1445 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1446 "10 ms (2nd try)\n", val2);
1447 if (val2 >= val + 8) { /* 1 ms */
1448 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1449 &hc->chip);
1450 printk(KERN_INFO "controller is PCM bus MASTER "
1451 "(auto detected)\n");
1452 } else
1453 goto controller_fail;
1454 }
1455 }
1456
1457 /* Release the DSP Reset */
1458 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1459 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1460 plxsd_master = 1;
1461 spin_lock_irqsave(&plx_lock, plx_flags);
1462 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1463 pv = readl(plx_acc_32);
1464 pv |= PLX_DSP_RES_N;
1465 writel(pv, plx_acc_32);
1466 spin_unlock_irqrestore(&plx_lock, plx_flags);
1467 if (debug & DEBUG_HFCMULTI_INIT)
1468 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1469 __func__, pv);
1470 }
1471
1472 /* pcm id */
1473 if (hc->pcm)
1474 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1475 hc->pcm);
1476 else {
1477 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1478 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1479 PCM_cnt++; /* SD has proprietary bridging */
1480 }
1481 hc->pcm = PCM_cnt;
1482 printk(KERN_INFO "controller has PCM BUS ID %d "
1483 "(auto selected)\n", hc->pcm);
1484 }
1485
1486 /* set up timer */
1487 HFC_outb(hc, R_TI_WD, poll_timer);
1488 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1489
1490 /* set E1 state machine IRQ */
1491 if (hc->ctype == HFC_TYPE_E1)
1492 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1493
1494 /* set DTMF detection */
1495 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1496 if (debug & DEBUG_HFCMULTI_INIT)
1497 printk(KERN_DEBUG "%s: enabling DTMF detection "
1498 "for all B-channel\n", __func__);
1499 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1500 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1501 hc->hw.r_dtmf |= V_ULAW_SEL;
1502 HFC_outb(hc, R_DTMF_N, 102 - 1);
1503 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1504 }
1505
1506 /* conference engine */
1507 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1508 r_conf_en = V_CONF_EN | V_ULAW;
1509 else
1510 r_conf_en = V_CONF_EN;
1511 if (hc->ctype != HFC_TYPE_XHFC)
1512 HFC_outb(hc, R_CONF_EN, r_conf_en);
1513
1514 /* setting leds */
1515 switch (hc->leds) {
1516 case 1: /* HFC-E1 OEM */
1517 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1518 HFC_outb(hc, R_GPIO_SEL, 0x32);
1519 else
1520 HFC_outb(hc, R_GPIO_SEL, 0x30);
1521
1522 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1523 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1524
1525 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1526 break;
1527
1528 case 2: /* HFC-4S OEM */
1529 case 3:
1530 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1531 HFC_outb(hc, R_GPIO_EN1, 0xff);
1532 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1533 break;
1534 }
1535
1536 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1537 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1538 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1539 }
1540
1541 /* set master clock */
1542 if (hc->masterclk >= 0) {
1543 if (debug & DEBUG_HFCMULTI_INIT)
1544 printk(KERN_DEBUG "%s: setting ST master clock "
1545 "to port %d (0..%d)\n",
1546 __func__, hc->masterclk, hc->ports - 1);
1547 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1548 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1549 }
1550
1551
1552
1553 /* setting misc irq */
1554 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1555 if (debug & DEBUG_HFCMULTI_INIT)
1556 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1557 hc->hw.r_irqmsk_misc);
1558
1559 /* RAM access test */
1560 HFC_outb(hc, R_RAM_ADDR0, 0);
1561 HFC_outb(hc, R_RAM_ADDR1, 0);
1562 HFC_outb(hc, R_RAM_ADDR2, 0);
1563 for (i = 0; i < 256; i++) {
1564 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1565 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1566 }
1567 for (i = 0; i < 256; i++) {
1568 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1569 HFC_inb_nodebug(hc, R_RAM_DATA);
1570 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1571 if (rval != ((i * 3) & 0xff)) {
1572 printk(KERN_DEBUG
1573 "addr:%x val:%x should:%x\n", i, rval,
1574 (i * 3) & 0xff);
1575 err++;
1576 }
1577 }
1578 if (err) {
1579 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1580 err = -EIO;
1581 goto out;
1582 }
1583
1584 if (debug & DEBUG_HFCMULTI_INIT)
1585 printk(KERN_DEBUG "%s: done\n", __func__);
1586 out:
1587 spin_unlock_irqrestore(&hc->lock, flags);
1588 return err;
1589 }
1590
1591
1592 /*
1593 * control the watchdog
1594 */
1595 static void
1596 hfcmulti_watchdog(struct hfc_multi *hc)
1597 {
1598 hc->wdcount++;
1599
1600 if (hc->wdcount > 10) {
1601 hc->wdcount = 0;
1602 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1603 V_GPIO_OUT3 : V_GPIO_OUT2;
1604
1605 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1606 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1607 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1608 }
1609 }
1610
1611
1612
1613 /*
1614 * output leds
1615 */
1616 static void
1617 hfcmulti_leds(struct hfc_multi *hc)
1618 {
1619 unsigned long lled;
1620 unsigned long leddw;
1621 int i, state, active, leds;
1622 struct dchannel *dch;
1623 int led[4];
1624
1625 switch (hc->leds) {
1626 case 1: /* HFC-E1 OEM */
1627 /* 2 red steady: LOS
1628 * 1 red steady: L1 not active
1629 * 2 green steady: L1 active
1630 * 1st green flashing: activity on TX
1631 * 2nd green flashing: activity on RX
1632 */
1633 led[0] = 0;
1634 led[1] = 0;
1635 led[2] = 0;
1636 led[3] = 0;
1637 dch = hc->chan[hc->dnum[0]].dch;
1638 if (dch) {
1639 if (hc->chan[hc->dnum[0]].los)
1640 led[1] = 1;
1641 if (hc->e1_state != 1) {
1642 led[0] = 1;
1643 hc->flash[2] = 0;
1644 hc->flash[3] = 0;
1645 } else {
1646 led[2] = 1;
1647 led[3] = 1;
1648 if (!hc->flash[2] && hc->activity_tx)
1649 hc->flash[2] = poll;
1650 if (!hc->flash[3] && hc->activity_rx)
1651 hc->flash[3] = poll;
1652 if (hc->flash[2] && hc->flash[2] < 1024)
1653 led[2] = 0;
1654 if (hc->flash[3] && hc->flash[3] < 1024)
1655 led[3] = 0;
1656 if (hc->flash[2] >= 2048)
1657 hc->flash[2] = 0;
1658 if (hc->flash[3] >= 2048)
1659 hc->flash[3] = 0;
1660 if (hc->flash[2])
1661 hc->flash[2] += poll;
1662 if (hc->flash[3])
1663 hc->flash[3] += poll;
1664 }
1665 }
1666 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1667 /* leds are inverted */
1668 if (leds != (int)hc->ledstate) {
1669 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1670 hc->ledstate = leds;
1671 }
1672 break;
1673
1674 case 2: /* HFC-4S OEM */
1675 /* red steady: PH_DEACTIVATE
1676 * green steady: PH_ACTIVATE
1677 * green flashing: activity on TX
1678 */
1679 for (i = 0; i < 4; i++) {
1680 state = 0;
1681 active = -1;
1682 dch = hc->chan[(i << 2) | 2].dch;
1683 if (dch) {
1684 state = dch->state;
1685 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1686 active = 3;
1687 else
1688 active = 7;
1689 }
1690 if (state) {
1691 if (state == active) {
1692 led[i] = 1; /* led green */
1693 hc->activity_tx |= hc->activity_rx;
1694 if (!hc->flash[i] &&
1695 (hc->activity_tx & (1 << i)))
1696 hc->flash[i] = poll;
1697 if (hc->flash[i] && hc->flash[i] < 1024)
1698 led[i] = 0; /* led off */
1699 if (hc->flash[i] >= 2048)
1700 hc->flash[i] = 0;
1701 if (hc->flash[i])
1702 hc->flash[i] += poll;
1703 } else {
1704 led[i] = 2; /* led red */
1705 hc->flash[i] = 0;
1706 }
1707 } else
1708 led[i] = 0; /* led off */
1709 }
1710 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1711 leds = 0;
1712 for (i = 0; i < 4; i++) {
1713 if (led[i] == 1) {
1714 /*green*/
1715 leds |= (0x2 << (i * 2));
1716 } else if (led[i] == 2) {
1717 /*red*/
1718 leds |= (0x1 << (i * 2));
1719 }
1720 }
1721 if (leds != (int)hc->ledstate) {
1722 vpm_out(hc, 0, 0x1a8 + 3, leds);
1723 hc->ledstate = leds;
1724 }
1725 } else {
1726 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1727 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1728 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1729 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1730 if (leds != (int)hc->ledstate) {
1731 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1732 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1733 hc->ledstate = leds;
1734 }
1735 }
1736 break;
1737
1738 case 3: /* HFC 1S/2S Beronet */
1739 /* red steady: PH_DEACTIVATE
1740 * green steady: PH_ACTIVATE
1741 * green flashing: activity on TX
1742 */
1743 for (i = 0; i < 2; i++) {
1744 state = 0;
1745 active = -1;
1746 dch = hc->chan[(i << 2) | 2].dch;
1747 if (dch) {
1748 state = dch->state;
1749 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1750 active = 3;
1751 else
1752 active = 7;
1753 }
1754 if (state) {
1755 if (state == active) {
1756 led[i] = 1; /* led green */
1757 hc->activity_tx |= hc->activity_rx;
1758 if (!hc->flash[i] &&
1759 (hc->activity_tx & (1 << i)))
1760 hc->flash[i] = poll;
1761 if (hc->flash[i] < 1024)
1762 led[i] = 0; /* led off */
1763 if (hc->flash[i] >= 2048)
1764 hc->flash[i] = 0;
1765 if (hc->flash[i])
1766 hc->flash[i] += poll;
1767 } else {
1768 led[i] = 2; /* led red */
1769 hc->flash[i] = 0;
1770 }
1771 } else
1772 led[i] = 0; /* led off */
1773 }
1774 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1775 | ((led[1]&1) << 3);
1776 if (leds != (int)hc->ledstate) {
1777 HFC_outb_nodebug(hc, R_GPIO_EN1,
1778 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1779 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1780 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1781 hc->ledstate = leds;
1782 }
1783 break;
1784 case 8: /* HFC 8S+ Beronet */
1785 /* off: PH_DEACTIVATE
1786 * steady: PH_ACTIVATE
1787 * flashing: activity on TX
1788 */
1789 lled = 0xff; /* leds off */
1790 for (i = 0; i < 8; i++) {
1791 state = 0;
1792 active = -1;
1793 dch = hc->chan[(i << 2) | 2].dch;
1794 if (dch) {
1795 state = dch->state;
1796 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1797 active = 3;
1798 else
1799 active = 7;
1800 }
1801 if (state) {
1802 if (state == active) {
1803 lled &= ~(1 << i); /* led on */
1804 hc->activity_tx |= hc->activity_rx;
1805 if (!hc->flash[i] &&
1806 (hc->activity_tx & (1 << i)))
1807 hc->flash[i] = poll;
1808 if (hc->flash[i] < 1024)
1809 lled |= 1 << i; /* led off */
1810 if (hc->flash[i] >= 2048)
1811 hc->flash[i] = 0;
1812 if (hc->flash[i])
1813 hc->flash[i] += poll;
1814 } else
1815 hc->flash[i] = 0;
1816 }
1817 }
1818 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1819 if (leddw != hc->ledstate) {
1820 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1821 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1822 /* was _io before */
1823 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1824 outw(0x4000, hc->pci_iobase + 4);
1825 outl(leddw, hc->pci_iobase);
1826 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1827 hc->ledstate = leddw;
1828 }
1829 break;
1830 }
1831 hc->activity_tx = 0;
1832 hc->activity_rx = 0;
1833 }
1834 /*
1835 * read dtmf coefficients
1836 */
1837
1838 static void
1839 hfcmulti_dtmf(struct hfc_multi *hc)
1840 {
1841 s32 *coeff;
1842 u_int mantissa;
1843 int co, ch;
1844 struct bchannel *bch = NULL;
1845 u8 exponent;
1846 int dtmf = 0;
1847 int addr;
1848 u16 w_float;
1849 struct sk_buff *skb;
1850 struct mISDNhead *hh;
1851
1852 if (debug & DEBUG_HFCMULTI_DTMF)
1853 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1854 for (ch = 0; ch <= 31; ch++) {
1855 /* only process enabled B-channels */
1856 bch = hc->chan[ch].bch;
1857 if (!bch)
1858 continue;
1859 if (!hc->created[hc->chan[ch].port])
1860 continue;
1861 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1862 continue;
1863 if (debug & DEBUG_HFCMULTI_DTMF)
1864 printk(KERN_DEBUG "%s: dtmf channel %d:",
1865 __func__, ch);
1866 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1867 dtmf = 1;
1868 for (co = 0; co < 8; co++) {
1869 /* read W(n-1) coefficient */
1870 addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1871 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1872 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1873 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1874 | V_ADDR_INC);
1875 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1876 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1877 if (debug & DEBUG_HFCMULTI_DTMF)
1878 printk(" %04x", w_float);
1879
1880 /* decode float (see chip doc) */
1881 mantissa = w_float & 0x0fff;
1882 if (w_float & 0x8000)
1883 mantissa |= 0xfffff000;
1884 exponent = (w_float >> 12) & 0x7;
1885 if (exponent) {
1886 mantissa ^= 0x1000;
1887 mantissa <<= (exponent - 1);
1888 }
1889
1890 /* store coefficient */
1891 coeff[co << 1] = mantissa;
1892
1893 /* read W(n) coefficient */
1894 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1895 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1896 if (debug & DEBUG_HFCMULTI_DTMF)
1897 printk(" %04x", w_float);
1898
1899 /* decode float (see chip doc) */
1900 mantissa = w_float & 0x0fff;
1901 if (w_float & 0x8000)
1902 mantissa |= 0xfffff000;
1903 exponent = (w_float >> 12) & 0x7;
1904 if (exponent) {
1905 mantissa ^= 0x1000;
1906 mantissa <<= (exponent - 1);
1907 }
1908
1909 /* store coefficient */
1910 coeff[(co << 1) | 1] = mantissa;
1911 }
1912 if (debug & DEBUG_HFCMULTI_DTMF)
1913 printk(" DTMF ready %08x %08x %08x %08x "
1914 "%08x %08x %08x %08x\n",
1915 coeff[0], coeff[1], coeff[2], coeff[3],
1916 coeff[4], coeff[5], coeff[6], coeff[7]);
1917 hc->chan[ch].coeff_count++;
1918 if (hc->chan[ch].coeff_count == 8) {
1919 hc->chan[ch].coeff_count = 0;
1920 skb = mI_alloc_skb(512, GFP_ATOMIC);
1921 if (!skb) {
1922 printk(KERN_DEBUG "%s: No memory for skb\n",
1923 __func__);
1924 continue;
1925 }
1926 hh = mISDN_HEAD_P(skb);
1927 hh->prim = PH_CONTROL_IND;
1928 hh->id = DTMF_HFC_COEF;
1929 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1930 recv_Bchannel_skb(bch, skb);
1931 }
1932 }
1933
1934 /* restart DTMF processing */
1935 hc->dtmf = dtmf;
1936 if (dtmf)
1937 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1938 }
1939
1940
1941 /*
1942 * fill fifo as much as possible
1943 */
1944
1945 static void
1946 hfcmulti_tx(struct hfc_multi *hc, int ch)
1947 {
1948 int i, ii, temp, len = 0;
1949 int Zspace, z1, z2; /* must be int for calculation */
1950 int Fspace, f1, f2;
1951 u_char *d;
1952 int *txpending, slot_tx;
1953 struct bchannel *bch;
1954 struct dchannel *dch;
1955 struct sk_buff **sp = NULL;
1956 int *idxp;
1957
1958 bch = hc->chan[ch].bch;
1959 dch = hc->chan[ch].dch;
1960 if ((!dch) && (!bch))
1961 return;
1962
1963 txpending = &hc->chan[ch].txpending;
1964 slot_tx = hc->chan[ch].slot_tx;
1965 if (dch) {
1966 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1967 return;
1968 sp = &dch->tx_skb;
1969 idxp = &dch->tx_idx;
1970 } else {
1971 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1972 return;
1973 sp = &bch->tx_skb;
1974 idxp = &bch->tx_idx;
1975 }
1976 if (*sp)
1977 len = (*sp)->len;
1978
1979 if ((!len) && *txpending != 1)
1980 return; /* no data */
1981
1982 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1983 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1984 (hc->chan[ch].slot_rx < 0) &&
1985 (hc->chan[ch].slot_tx < 0))
1986 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1987 else
1988 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1989 HFC_wait_nodebug(hc);
1990
1991 if (*txpending == 2) {
1992 /* reset fifo */
1993 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1994 HFC_wait_nodebug(hc);
1995 HFC_outb(hc, A_SUBCH_CFG, 0);
1996 *txpending = 1;
1997 }
1998 next_frame:
1999 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2000 f1 = HFC_inb_nodebug(hc, A_F1);
2001 f2 = HFC_inb_nodebug(hc, A_F2);
2002 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
2003 if (debug & DEBUG_HFCMULTI_FIFO)
2004 printk(KERN_DEBUG
2005 "%s(card %d): reread f2 because %d!=%d\n",
2006 __func__, hc->id + 1, temp, f2);
2007 f2 = temp; /* repeat until F2 is equal */
2008 }
2009 Fspace = f2 - f1 - 1;
2010 if (Fspace < 0)
2011 Fspace += hc->Flen;
2012 /*
2013 * Old FIFO handling doesn't give us the current Z2 read
2014 * pointer, so we cannot send the next frame before the fifo
2015 * is empty. It makes no difference except for a slightly
2016 * lower performance.
2017 */
2018 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2019 if (f1 != f2)
2020 Fspace = 0;
2021 else
2022 Fspace = 1;
2023 }
2024 /* one frame only for ST D-channels, to allow resending */
2025 if (hc->ctype != HFC_TYPE_E1 && dch) {
2026 if (f1 != f2)
2027 Fspace = 0;
2028 }
2029 /* F-counter full condition */
2030 if (Fspace == 0)
2031 return;
2032 }
2033 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2034 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2035 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2036 if (debug & DEBUG_HFCMULTI_FIFO)
2037 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2038 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2039 z2 = temp; /* repeat unti Z2 is equal */
2040 }
2041 hc->chan[ch].Zfill = z1 - z2;
2042 if (hc->chan[ch].Zfill < 0)
2043 hc->chan[ch].Zfill += hc->Zlen;
2044 Zspace = z2 - z1;
2045 if (Zspace <= 0)
2046 Zspace += hc->Zlen;
2047 Zspace -= 4; /* keep not too full, so pointers will not overrun */
2048 /* fill transparent data only to maxinum transparent load (minus 4) */
2049 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2050 Zspace = Zspace - hc->Zlen + hc->max_trans;
2051 if (Zspace <= 0) /* no space of 4 bytes */
2052 return;
2053
2054 /* if no data */
2055 if (!len) {
2056 if (z1 == z2) { /* empty */
2057 /* if done with FIFO audio data during PCM connection */
2058 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2059 *txpending && slot_tx >= 0) {
2060 if (debug & DEBUG_HFCMULTI_MODE)
2061 printk(KERN_DEBUG
2062 "%s: reconnecting PCM due to no "
2063 "more FIFO data: channel %d "
2064 "slot_tx %d\n",
2065 __func__, ch, slot_tx);
2066 /* connect slot */
2067 if (hc->ctype == HFC_TYPE_XHFC)
2068 HFC_outb(hc, A_CON_HDLC, 0xc0
2069 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2070 /* Enable FIFO, no interrupt */
2071 else
2072 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2073 V_HDLC_TRP | V_IFF);
2074 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2075 HFC_wait_nodebug(hc);
2076 if (hc->ctype == HFC_TYPE_XHFC)
2077 HFC_outb(hc, A_CON_HDLC, 0xc0
2078 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2079 /* Enable FIFO, no interrupt */
2080 else
2081 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2082 V_HDLC_TRP | V_IFF);
2083 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2084 HFC_wait_nodebug(hc);
2085 }
2086 *txpending = 0;
2087 }
2088 return; /* no data */
2089 }
2090
2091 /* "fill fifo if empty" feature */
2092 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2093 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2094 if (debug & DEBUG_HFCMULTI_FILL)
2095 printk(KERN_DEBUG "%s: buffer empty, so we have "
2096 "underrun\n", __func__);
2097 /* fill buffer, to prevent future underrun */
2098 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2099 Zspace -= (poll >> 1);
2100 }
2101
2102 /* if audio data and connected slot */
2103 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2104 && slot_tx >= 0) {
2105 if (debug & DEBUG_HFCMULTI_MODE)
2106 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2107 "FIFO data: channel %d slot_tx %d\n",
2108 __func__, ch, slot_tx);
2109 /* disconnect slot */
2110 if (hc->ctype == HFC_TYPE_XHFC)
2111 HFC_outb(hc, A_CON_HDLC, 0x80
2112 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2113 /* Enable FIFO, no interrupt */
2114 else
2115 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2116 V_HDLC_TRP | V_IFF);
2117 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2118 HFC_wait_nodebug(hc);
2119 if (hc->ctype == HFC_TYPE_XHFC)
2120 HFC_outb(hc, A_CON_HDLC, 0x80
2121 | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2122 /* Enable FIFO, no interrupt */
2123 else
2124 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2125 V_HDLC_TRP | V_IFF);
2126 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2127 HFC_wait_nodebug(hc);
2128 }
2129 *txpending = 1;
2130
2131 /* show activity */
2132 if (dch)
2133 hc->activity_tx |= 1 << hc->chan[ch].port;
2134
2135 /* fill fifo to what we have left */
2136 ii = len;
2137 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2138 temp = 1;
2139 else
2140 temp = 0;
2141 i = *idxp;
2142 d = (*sp)->data + i;
2143 if (ii - i > Zspace)
2144 ii = Zspace + i;
2145 if (debug & DEBUG_HFCMULTI_FIFO)
2146 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2147 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2148 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2149 temp ? "HDLC" : "TRANS");
2150
2151 /* Have to prep the audio data */
2152 hc->write_fifo(hc, d, ii - i);
2153 hc->chan[ch].Zfill += ii - i;
2154 *idxp = ii;
2155
2156 /* if not all data has been written */
2157 if (ii != len) {
2158 /* NOTE: fifo is started by the calling function */
2159 return;
2160 }
2161
2162 /* if all data has been written, terminate frame */
2163 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2164 /* increment f-counter */
2165 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2166 HFC_wait_nodebug(hc);
2167 }
2168
2169 dev_kfree_skb(*sp);
2170 /* check for next frame */
2171 if (bch && get_next_bframe(bch)) {
2172 len = (*sp)->len;
2173 goto next_frame;
2174 }
2175 if (dch && get_next_dframe(dch)) {
2176 len = (*sp)->len;
2177 goto next_frame;
2178 }
2179
2180 /*
2181 * now we have no more data, so in case of transparent,
2182 * we set the last byte in fifo to 'silence' in case we will get
2183 * no more data at all. this prevents sending an undefined value.
2184 */
2185 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2186 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2187 }
2188
2189
2190 /* NOTE: only called if E1 card is in active state */
2191 static void
2192 hfcmulti_rx(struct hfc_multi *hc, int ch)
2193 {
2194 int temp;
2195 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2196 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2197 int again = 0;
2198 struct bchannel *bch;
2199 struct dchannel *dch = NULL;
2200 struct sk_buff *skb, **sp = NULL;
2201 int maxlen;
2202
2203 bch = hc->chan[ch].bch;
2204 if (bch) {
2205 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2206 return;
2207 } else if (hc->chan[ch].dch) {
2208 dch = hc->chan[ch].dch;
2209 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2210 return;
2211 } else {
2212 return;
2213 }
2214 next_frame:
2215 /* on first AND before getting next valid frame, R_FIFO must be written
2216 to. */
2217 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2218 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2219 (hc->chan[ch].slot_rx < 0) &&
2220 (hc->chan[ch].slot_tx < 0))
2221 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2222 else
2223 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2224 HFC_wait_nodebug(hc);
2225
2226 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2227 if (hc->chan[ch].rx_off) {
2228 if (bch)
2229 bch->dropcnt += poll; /* not exact but fair enough */
2230 return;
2231 }
2232
2233 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2234 f1 = HFC_inb_nodebug(hc, A_F1);
2235 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2236 if (debug & DEBUG_HFCMULTI_FIFO)
2237 printk(KERN_DEBUG
2238 "%s(card %d): reread f1 because %d!=%d\n",
2239 __func__, hc->id + 1, temp, f1);
2240 f1 = temp; /* repeat until F1 is equal */
2241 }
2242 f2 = HFC_inb_nodebug(hc, A_F2);
2243 }
2244 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2245 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2246 if (debug & DEBUG_HFCMULTI_FIFO)
2247 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2248 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2249 z1 = temp; /* repeat until Z1 is equal */
2250 }
2251 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2252 Zsize = z1 - z2;
2253 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2254 /* complete hdlc frame */
2255 Zsize++;
2256 if (Zsize < 0)
2257 Zsize += hc->Zlen;
2258 /* if buffer is empty */
2259 if (Zsize <= 0)
2260 return;
2261
2262 if (bch) {
2263 maxlen = bchannel_get_rxbuf(bch, Zsize);
2264 if (maxlen < 0) {
2265 pr_warning("card%d.B%d: No bufferspace for %d bytes\n",
2266 hc->id + 1, bch->nr, Zsize);
2267 return;
2268 }
2269 sp = &bch->rx_skb;
2270 maxlen = bch->maxlen;
2271 } else { /* Dchannel */
2272 sp = &dch->rx_skb;
2273 maxlen = dch->maxlen + 3;
2274 if (*sp == NULL) {
2275 *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2276 if (*sp == NULL) {
2277 pr_warning("card%d: No mem for dch rx_skb\n",
2278 hc->id + 1);
2279 return;
2280 }
2281 }
2282 }
2283 /* show activity */
2284 if (dch)
2285 hc->activity_rx |= 1 << hc->chan[ch].port;
2286
2287 /* empty fifo with what we have */
2288 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2289 if (debug & DEBUG_HFCMULTI_FIFO)
2290 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2291 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2292 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2293 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2294 f1, f2, Zsize + (*sp)->len, again);
2295 /* HDLC */
2296 if ((Zsize + (*sp)->len) > maxlen) {
2297 if (debug & DEBUG_HFCMULTI_FIFO)
2298 printk(KERN_DEBUG
2299 "%s(card %d): hdlc-frame too large.\n",
2300 __func__, hc->id + 1);
2301 skb_trim(*sp, 0);
2302 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2303 HFC_wait_nodebug(hc);
2304 return;
2305 }
2306
2307 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2308
2309 if (f1 != f2) {
2310 /* increment Z2,F2-counter */
2311 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2312 HFC_wait_nodebug(hc);
2313 /* check size */
2314 if ((*sp)->len < 4) {
2315 if (debug & DEBUG_HFCMULTI_FIFO)
2316 printk(KERN_DEBUG
2317 "%s(card %d): Frame below minimum "
2318 "size\n", __func__, hc->id + 1);
2319 skb_trim(*sp, 0);
2320 goto next_frame;
2321 }
2322 /* there is at least one complete frame, check crc */
2323 if ((*sp)->data[(*sp)->len - 1]) {
2324 if (debug & DEBUG_HFCMULTI_CRC)
2325 printk(KERN_DEBUG
2326 "%s: CRC-error\n", __func__);
2327 skb_trim(*sp, 0);
2328 goto next_frame;
2329 }
2330 skb_trim(*sp, (*sp)->len - 3);
2331 if ((*sp)->len < MISDN_COPY_SIZE) {
2332 skb = *sp;
2333 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2334 if (*sp) {
2335 memcpy(skb_put(*sp, skb->len),
2336 skb->data, skb->len);
2337 skb_trim(skb, 0);
2338 } else {
2339 printk(KERN_DEBUG "%s: No mem\n",
2340 __func__);
2341 *sp = skb;
2342 skb = NULL;
2343 }
2344 } else {
2345 skb = NULL;
2346 }
2347 if (debug & DEBUG_HFCMULTI_FIFO) {
2348 printk(KERN_DEBUG "%s(card %d):",
2349 __func__, hc->id + 1);
2350 temp = 0;
2351 while (temp < (*sp)->len)
2352 printk(" %02x", (*sp)->data[temp++]);
2353 printk("\n");
2354 }
2355 if (dch)
2356 recv_Dchannel(dch);
2357 else
2358 recv_Bchannel(bch, MISDN_ID_ANY, false);
2359 *sp = skb;
2360 again++;
2361 goto next_frame;
2362 }
2363 /* there is an incomplete frame */
2364 } else {
2365 /* transparent */
2366 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2367 if (debug & DEBUG_HFCMULTI_FIFO)
2368 printk(KERN_DEBUG
2369 "%s(card %d): fifo(%d) reading %d bytes "
2370 "(z1=%04x, z2=%04x) TRANS\n",
2371 __func__, hc->id + 1, ch, Zsize, z1, z2);
2372 /* only bch is transparent */
2373 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2374 }
2375 }
2376
2377
2378 /*
2379 * Interrupt handler
2380 */
2381 static void
2382 signal_state_up(struct dchannel *dch, int info, char *msg)
2383 {
2384 struct sk_buff *skb;
2385 int id, data = info;
2386
2387 if (debug & DEBUG_HFCMULTI_STATE)
2388 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2389
2390 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2391
2392 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2393 GFP_ATOMIC);
2394 if (!skb)
2395 return;
2396 recv_Dchannel_skb(dch, skb);
2397 }
2398
2399 static inline void
2400 handle_timer_irq(struct hfc_multi *hc)
2401 {
2402 int ch, temp;
2403 struct dchannel *dch;
2404 u_long flags;
2405
2406 /* process queued resync jobs */
2407 if (hc->e1_resync) {
2408 /* lock, so e1_resync gets not changed */
2409 spin_lock_irqsave(&HFClock, flags);
2410 if (hc->e1_resync & 1) {
2411 if (debug & DEBUG_HFCMULTI_PLXSD)
2412 printk(KERN_DEBUG "Enable SYNC_I\n");
2413 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2414 /* disable JATT, if RX_SYNC is set */
2415 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2416 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2417 }
2418 if (hc->e1_resync & 2) {
2419 if (debug & DEBUG_HFCMULTI_PLXSD)
2420 printk(KERN_DEBUG "Enable jatt PLL\n");
2421 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2422 }
2423 if (hc->e1_resync & 4) {
2424 if (debug & DEBUG_HFCMULTI_PLXSD)
2425 printk(KERN_DEBUG
2426 "Enable QUARTZ for HFC-E1\n");
2427 /* set jatt to quartz */
2428 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2429 | V_JATT_OFF);
2430 /* switch to JATT, in case it is not already */
2431 HFC_outb(hc, R_SYNC_OUT, 0);
2432 }
2433 hc->e1_resync = 0;
2434 spin_unlock_irqrestore(&HFClock, flags);
2435 }
2436
2437 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2438 for (ch = 0; ch <= 31; ch++) {
2439 if (hc->created[hc->chan[ch].port]) {
2440 hfcmulti_tx(hc, ch);
2441 /* fifo is started when switching to rx-fifo */
2442 hfcmulti_rx(hc, ch);
2443 if (hc->chan[ch].dch &&
2444 hc->chan[ch].nt_timer > -1) {
2445 dch = hc->chan[ch].dch;
2446 if (!(--hc->chan[ch].nt_timer)) {
2447 schedule_event(dch,
2448 FLG_PHCHANGE);
2449 if (debug &
2450 DEBUG_HFCMULTI_STATE)
2451 printk(KERN_DEBUG
2452 "%s: nt_timer at "
2453 "state %x\n",
2454 __func__,
2455 dch->state);
2456 }
2457 }
2458 }
2459 }
2460 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2461 dch = hc->chan[hc->dnum[0]].dch;
2462 /* LOS */
2463 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2464 hc->chan[hc->dnum[0]].los = temp;
2465 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2466 if (!temp && hc->chan[hc->dnum[0]].los)
2467 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2468 "LOS detected");
2469 if (temp && !hc->chan[hc->dnum[0]].los)
2470 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2471 "LOS gone");
2472 }
2473 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2474 /* AIS */
2475 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2476 if (!temp && hc->chan[hc->dnum[0]].ais)
2477 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2478 "AIS detected");
2479 if (temp && !hc->chan[hc->dnum[0]].ais)
2480 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2481 "AIS gone");
2482 hc->chan[hc->dnum[0]].ais = temp;
2483 }
2484 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2485 /* SLIP */
2486 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2487 if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2488 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2489 " bit SLIP detected RX");
2490 hc->chan[hc->dnum[0]].slip_rx = temp;
2491 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2492 if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2493 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2494 " bit SLIP detected TX");
2495 hc->chan[hc->dnum[0]].slip_tx = temp;
2496 }
2497 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2498 /* RDI */
2499 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2500 if (!temp && hc->chan[hc->dnum[0]].rdi)
2501 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2502 "RDI detected");
2503 if (temp && !hc->chan[hc->dnum[0]].rdi)
2504 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2505 "RDI gone");
2506 hc->chan[hc->dnum[0]].rdi = temp;
2507 }
2508 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2509 switch (hc->chan[hc->dnum[0]].sync) {
2510 case 0:
2511 if ((temp & 0x60) == 0x60) {
2512 if (debug & DEBUG_HFCMULTI_SYNC)
2513 printk(KERN_DEBUG
2514 "%s: (id=%d) E1 now "
2515 "in clock sync\n",
2516 __func__, hc->id);
2517 HFC_outb(hc, R_RX_OFF,
2518 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2519 HFC_outb(hc, R_TX_OFF,
2520 hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2521 hc->chan[hc->dnum[0]].sync = 1;
2522 goto check_framesync;
2523 }
2524 break;
2525 case 1:
2526 if ((temp & 0x60) != 0x60) {
2527 if (debug & DEBUG_HFCMULTI_SYNC)
2528 printk(KERN_DEBUG
2529 "%s: (id=%d) E1 "
2530 "lost clock sync\n",
2531 __func__, hc->id);
2532 hc->chan[hc->dnum[0]].sync = 0;
2533 break;
2534 }
2535 check_framesync:
2536 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2537 if (temp == 0x27) {
2538 if (debug & DEBUG_HFCMULTI_SYNC)
2539 printk(KERN_DEBUG
2540 "%s: (id=%d) E1 "
2541 "now in frame sync\n",
2542 __func__, hc->id);
2543 hc->chan[hc->dnum[0]].sync = 2;
2544 }
2545 break;
2546 case 2:
2547 if ((temp & 0x60) != 0x60) {
2548 if (debug & DEBUG_HFCMULTI_SYNC)
2549 printk(KERN_DEBUG
2550 "%s: (id=%d) E1 lost "
2551 "clock & frame sync\n",
2552 __func__, hc->id);
2553 hc->chan[hc->dnum[0]].sync = 0;
2554 break;
2555 }
2556 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2557 if (temp != 0x27) {
2558 if (debug & DEBUG_HFCMULTI_SYNC)
2559 printk(KERN_DEBUG
2560 "%s: (id=%d) E1 "
2561 "lost frame sync\n",
2562 __func__, hc->id);
2563 hc->chan[hc->dnum[0]].sync = 1;
2564 }
2565 break;
2566 }
2567 }
2568
2569 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2570 hfcmulti_watchdog(hc);
2571
2572 if (hc->leds)
2573 hfcmulti_leds(hc);
2574 }
2575
2576 static void
2577 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2578 {
2579 struct dchannel *dch;
2580 int ch;
2581 int active;
2582 u_char st_status, temp;
2583
2584 /* state machine */
2585 for (ch = 0; ch <= 31; ch++) {
2586 if (hc->chan[ch].dch) {
2587 dch = hc->chan[ch].dch;
2588 if (r_irq_statech & 1) {
2589 HFC_outb_nodebug(hc, R_ST_SEL,
2590 hc->chan[ch].port);
2591 /* undocumented: delay after R_ST_SEL */
2592 udelay(1);
2593 /* undocumented: status changes during read */
2594 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2595 while (st_status != (temp =
2596 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2597 if (debug & DEBUG_HFCMULTI_STATE)
2598 printk(KERN_DEBUG "%s: reread "
2599 "STATE because %d!=%d\n",
2600 __func__, temp,
2601 st_status);
2602 st_status = temp; /* repeat */
2603 }
2604
2605 /* Speech Design TE-sync indication */
2606 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2607 dch->dev.D.protocol == ISDN_P_TE_S0) {
2608 if (st_status & V_FR_SYNC_ST)
2609 hc->syncronized |=
2610 (1 << hc->chan[ch].port);
2611 else
2612 hc->syncronized &=
2613 ~(1 << hc->chan[ch].port);
2614 }
2615 dch->state = st_status & 0x0f;
2616 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2617 active = 3;
2618 else
2619 active = 7;
2620 if (dch->state == active) {
2621 HFC_outb_nodebug(hc, R_FIFO,
2622 (ch << 1) | 1);
2623 HFC_wait_nodebug(hc);
2624 HFC_outb_nodebug(hc,
2625 R_INC_RES_FIFO, V_RES_F);
2626 HFC_wait_nodebug(hc);
2627 dch->tx_idx = 0;
2628 }
2629 schedule_event(dch, FLG_PHCHANGE);
2630 if (debug & DEBUG_HFCMULTI_STATE)
2631 printk(KERN_DEBUG
2632 "%s: S/T newstate %x port %d\n",
2633 __func__, dch->state,
2634 hc->chan[ch].port);
2635 }
2636 r_irq_statech >>= 1;
2637 }
2638 }
2639 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2640 plxsd_checksync(hc, 0);
2641 }
2642
2643 static void
2644 fifo_irq(struct hfc_multi *hc, int block)
2645 {
2646 int ch, j;
2647 struct dchannel *dch;
2648 struct bchannel *bch;
2649 u_char r_irq_fifo_bl;
2650
2651 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2652 j = 0;
2653 while (j < 8) {
2654 ch = (block << 2) + (j >> 1);
2655 dch = hc->chan[ch].dch;
2656 bch = hc->chan[ch].bch;
2657 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2658 j += 2;
2659 continue;
2660 }
2661 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2662 test_bit(FLG_ACTIVE, &dch->Flags)) {
2663 hfcmulti_tx(hc, ch);
2664 /* start fifo */
2665 HFC_outb_nodebug(hc, R_FIFO, 0);
2666 HFC_wait_nodebug(hc);
2667 }
2668 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2669 test_bit(FLG_ACTIVE, &bch->Flags)) {
2670 hfcmulti_tx(hc, ch);
2671 /* start fifo */
2672 HFC_outb_nodebug(hc, R_FIFO, 0);
2673 HFC_wait_nodebug(hc);
2674 }
2675 j++;
2676 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2677 test_bit(FLG_ACTIVE, &dch->Flags)) {
2678 hfcmulti_rx(hc, ch);
2679 }
2680 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2681 test_bit(FLG_ACTIVE, &bch->Flags)) {
2682 hfcmulti_rx(hc, ch);
2683 }
2684 j++;
2685 }
2686 }
2687
2688 #ifdef IRQ_DEBUG
2689 int irqsem;
2690 #endif
2691 static irqreturn_t
2692 hfcmulti_interrupt(int intno, void *dev_id)
2693 {
2694 #ifdef IRQCOUNT_DEBUG
2695 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2696 iq5 = 0, iq6 = 0, iqcnt = 0;
2697 #endif
2698 struct hfc_multi *hc = dev_id;
2699 struct dchannel *dch;
2700 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2701 int i;
2702 void __iomem *plx_acc;
2703 u_short wval;
2704 u_char e1_syncsta, temp, temp2;
2705 u_long flags;
2706
2707 if (!hc) {
2708 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2709 return IRQ_NONE;
2710 }
2711
2712 spin_lock(&hc->lock);
2713
2714 #ifdef IRQ_DEBUG
2715 if (irqsem)
2716 printk(KERN_ERR "irq for card %d during irq from "
2717 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2718 irqsem = hc->id + 1;
2719 #endif
2720 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2721 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2722 goto irq_notforus;
2723 #endif
2724 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2725 spin_lock_irqsave(&plx_lock, flags);
2726 plx_acc = hc->plx_membase + PLX_INTCSR;
2727 wval = readw(plx_acc);
2728 spin_unlock_irqrestore(&plx_lock, flags);
2729 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2730 goto irq_notforus;
2731 }
2732
2733 status = HFC_inb_nodebug(hc, R_STATUS);
2734 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2735 #ifdef IRQCOUNT_DEBUG
2736 if (r_irq_statech)
2737 iq1++;
2738 if (status & V_DTMF_STA)
2739 iq2++;
2740 if (status & V_LOST_STA)
2741 iq3++;
2742 if (status & V_EXT_IRQSTA)
2743 iq4++;
2744 if (status & V_MISC_IRQSTA)
2745 iq5++;
2746 if (status & V_FR_IRQSTA)
2747 iq6++;
2748 if (iqcnt++ > 5000) {
2749 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2750 iq1, iq2, iq3, iq4, iq5, iq6);
2751 iqcnt = 0;
2752 }
2753 #endif
2754
2755 if (!r_irq_statech &&
2756 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2757 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2758 /* irq is not for us */
2759 goto irq_notforus;
2760 }
2761 hc->irqcnt++;
2762 if (r_irq_statech) {
2763 if (hc->ctype != HFC_TYPE_E1)
2764 ph_state_irq(hc, r_irq_statech);
2765 }
2766 if (status & V_EXT_IRQSTA)
2767 ; /* external IRQ */
2768 if (status & V_LOST_STA) {
2769 /* LOST IRQ */
2770 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2771 }
2772 if (status & V_MISC_IRQSTA) {
2773 /* misc IRQ */
2774 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2775 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2776 if (r_irq_misc & V_STA_IRQ) {
2777 if (hc->ctype == HFC_TYPE_E1) {
2778 /* state machine */
2779 dch = hc->chan[hc->dnum[0]].dch;
2780 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2781 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2782 && hc->e1_getclock) {
2783 if (e1_syncsta & V_FR_SYNC_E1)
2784 hc->syncronized = 1;
2785 else
2786 hc->syncronized = 0;
2787 }
2788 /* undocumented: status changes during read */
2789 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2790 while (temp != (temp2 =
2791 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2792 if (debug & DEBUG_HFCMULTI_STATE)
2793 printk(KERN_DEBUG "%s: reread "
2794 "STATE because %d!=%d\n",
2795 __func__, temp, temp2);
2796 temp = temp2; /* repeat */
2797 }
2798 /* broadcast state change to all fragments */
2799 if (debug & DEBUG_HFCMULTI_STATE)
2800 printk(KERN_DEBUG
2801 "%s: E1 (id=%d) newstate %x\n",
2802 __func__, hc->id, temp & 0x7);
2803 for (i = 0; i < hc->ports; i++) {
2804 dch = hc->chan[hc->dnum[i]].dch;
2805 dch->state = temp & 0x7;
2806 schedule_event(dch, FLG_PHCHANGE);
2807 }
2808
2809 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2810 plxsd_checksync(hc, 0);
2811 }
2812 }
2813 if (r_irq_misc & V_TI_IRQ) {
2814 if (hc->iclock_on)
2815 mISDN_clock_update(hc->iclock, poll, NULL);
2816 handle_timer_irq(hc);
2817 }
2818
2819 if (r_irq_misc & V_DTMF_IRQ)
2820 hfcmulti_dtmf(hc);
2821
2822 if (r_irq_misc & V_IRQ_PROC) {
2823 static int irq_proc_cnt;
2824 if (!irq_proc_cnt++)
2825 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2826 " this should not happen\n", __func__);
2827 }
2828
2829 }
2830 if (status & V_FR_IRQSTA) {
2831 /* FIFO IRQ */
2832 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2833 for (i = 0; i < 8; i++) {
2834 if (r_irq_oview & (1 << i))
2835 fifo_irq(hc, i);
2836 }
2837 }
2838
2839 #ifdef IRQ_DEBUG
2840 irqsem = 0;
2841 #endif
2842 spin_unlock(&hc->lock);
2843 return IRQ_HANDLED;
2844
2845 irq_notforus:
2846 #ifdef IRQ_DEBUG
2847 irqsem = 0;
2848 #endif
2849 spin_unlock(&hc->lock);
2850 return IRQ_NONE;
2851 }
2852
2853
2854 /*
2855 * timer callback for D-chan busy resolution. Currently no function
2856 */
2857
2858 static void
2859 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2860 {
2861 }
2862
2863
2864 /*
2865 * activate/deactivate hardware for selected channels and mode
2866 *
2867 * configure B-channel with the given protocol
2868 * ch eqals to the HFC-channel (0-31)
2869 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2870 * for S/T, 1-31 for E1)
2871 * the hdlc interrupts will be set/unset
2872 */
2873 static int
2874 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2875 int bank_tx, int slot_rx, int bank_rx)
2876 {
2877 int flow_tx = 0, flow_rx = 0, routing = 0;
2878 int oslot_tx, oslot_rx;
2879 int conf;
2880
2881 if (ch < 0 || ch > 31)
2882 return -EINVAL;
2883 oslot_tx = hc->chan[ch].slot_tx;
2884 oslot_rx = hc->chan[ch].slot_rx;
2885 conf = hc->chan[ch].conf;
2886
2887 if (debug & DEBUG_HFCMULTI_MODE)
2888 printk(KERN_DEBUG
2889 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2890 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2891 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2892 bank_tx, oslot_rx, slot_rx, bank_rx);
2893
2894 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2895 /* remove from slot */
2896 if (debug & DEBUG_HFCMULTI_MODE)
2897 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2898 __func__, oslot_tx);
2899 if (hc->slot_owner[oslot_tx << 1] == ch) {
2900 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2901 HFC_outb(hc, A_SL_CFG, 0);
2902 if (hc->ctype != HFC_TYPE_XHFC)
2903 HFC_outb(hc, A_CONF, 0);
2904 hc->slot_owner[oslot_tx << 1] = -1;
2905 } else {
2906 if (debug & DEBUG_HFCMULTI_MODE)
2907 printk(KERN_DEBUG
2908 "%s: we are not owner of this tx slot "
2909 "anymore, channel %d is.\n",
2910 __func__, hc->slot_owner[oslot_tx << 1]);
2911 }
2912 }
2913
2914 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2915 /* remove from slot */
2916 if (debug & DEBUG_HFCMULTI_MODE)
2917 printk(KERN_DEBUG
2918 "%s: remove from slot %d (RX)\n",
2919 __func__, oslot_rx);
2920 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2921 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2922 HFC_outb(hc, A_SL_CFG, 0);
2923 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2924 } else {
2925 if (debug & DEBUG_HFCMULTI_MODE)
2926 printk(KERN_DEBUG
2927 "%s: we are not owner of this rx slot "
2928 "anymore, channel %d is.\n",
2929 __func__,
2930 hc->slot_owner[(oslot_rx << 1) | 1]);
2931 }
2932 }
2933
2934 if (slot_tx < 0) {
2935 flow_tx = 0x80; /* FIFO->ST */
2936 /* disable pcm slot */
2937 hc->chan[ch].slot_tx = -1;
2938 hc->chan[ch].bank_tx = 0;
2939 } else {
2940 /* set pcm slot */
2941 if (hc->chan[ch].txpending)
2942 flow_tx = 0x80; /* FIFO->ST */
2943 else
2944 flow_tx = 0xc0; /* PCM->ST */
2945 /* put on slot */
2946 routing = bank_tx ? 0xc0 : 0x80;
2947 if (conf >= 0 || bank_tx > 1)
2948 routing = 0x40; /* loop */
2949 if (debug & DEBUG_HFCMULTI_MODE)
2950 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2951 " %d flow %02x routing %02x conf %d (TX)\n",
2952 __func__, ch, slot_tx, bank_tx,
2953 flow_tx, routing, conf);
2954 HFC_outb(hc, R_SLOT, slot_tx << 1);
2955 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2956 if (hc->ctype != HFC_TYPE_XHFC)
2957 HFC_outb(hc, A_CONF,
2958 (conf < 0) ? 0 : (conf | V_CONF_SL));
2959 hc->slot_owner[slot_tx << 1] = ch;
2960 hc->chan[ch].slot_tx = slot_tx;
2961 hc->chan[ch].bank_tx = bank_tx;
2962 }
2963 if (slot_rx < 0) {
2964 /* disable pcm slot */
2965 flow_rx = 0x80; /* ST->FIFO */
2966 hc->chan[ch].slot_rx = -1;
2967 hc->chan[ch].bank_rx = 0;
2968 } else {
2969 /* set pcm slot */
2970 if (hc->chan[ch].txpending)
2971 flow_rx = 0x80; /* ST->FIFO */
2972 else
2973 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2974 /* put on slot */
2975 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2976 if (conf >= 0 || bank_rx > 1)
2977 routing = 0x40; /* loop */
2978 if (debug & DEBUG_HFCMULTI_MODE)
2979 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2980 " %d flow %02x routing %02x conf %d (RX)\n",
2981 __func__, ch, slot_rx, bank_rx,
2982 flow_rx, routing, conf);
2983 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2984 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2985 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2986 hc->chan[ch].slot_rx = slot_rx;
2987 hc->chan[ch].bank_rx = bank_rx;
2988 }
2989
2990 switch (protocol) {
2991 case (ISDN_P_NONE):
2992 /* disable TX fifo */
2993 HFC_outb(hc, R_FIFO, ch << 1);
2994 HFC_wait(hc);
2995 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2996 HFC_outb(hc, A_SUBCH_CFG, 0);
2997 HFC_outb(hc, A_IRQ_MSK, 0);
2998 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2999 HFC_wait(hc);
3000 /* disable RX fifo */
3001 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3002 HFC_wait(hc);
3003 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
3004 HFC_outb(hc, A_SUBCH_CFG, 0);
3005 HFC_outb(hc, A_IRQ_MSK, 0);
3006 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3007 HFC_wait(hc);
3008 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
3009 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
3010 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
3011 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3012 /* undocumented: delay after R_ST_SEL */
3013 udelay(1);
3014 HFC_outb(hc, A_ST_CTRL0,
3015 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3016 }
3017 if (hc->chan[ch].bch) {
3018 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3019 test_and_clear_bit(FLG_TRANSPARENT,
3020 &hc->chan[ch].bch->Flags);
3021 }
3022 break;
3023 case (ISDN_P_B_RAW): /* B-channel */
3024
3025 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3026 (hc->chan[ch].slot_rx < 0) &&
3027 (hc->chan[ch].slot_tx < 0)) {
3028
3029 printk(KERN_DEBUG
3030 "Setting B-channel %d to echo cancelable "
3031 "state on PCM slot %d\n", ch,
3032 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3033 printk(KERN_DEBUG
3034 "Enabling pass through for channel\n");
3035 vpm_out(hc, ch, ((ch / 4) * 8) +
3036 ((ch % 4) * 4) + 1, 0x01);
3037 /* rx path */
3038 /* S/T -> PCM */
3039 HFC_outb(hc, R_FIFO, (ch << 1));
3040 HFC_wait(hc);
3041 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3042 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3043 ((ch % 4) * 4) + 1) << 1);
3044 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3045
3046 /* PCM -> FIFO */
3047 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3048 HFC_wait(hc);
3049 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3050 HFC_outb(hc, A_SUBCH_CFG, 0);
3051 HFC_outb(hc, A_IRQ_MSK, 0);
3052 if (hc->chan[ch].protocol != protocol) {
3053 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3054 HFC_wait(hc);
3055 }
3056 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3057 ((ch % 4) * 4) + 1) << 1) | 1);
3058 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3059
3060 /* tx path */
3061 /* PCM -> S/T */
3062 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3063 HFC_wait(hc);
3064 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3065 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3066 ((ch % 4) * 4)) << 1) | 1);
3067 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3068
3069 /* FIFO -> PCM */
3070 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3071 HFC_wait(hc);
3072 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3073 HFC_outb(hc, A_SUBCH_CFG, 0);
3074 HFC_outb(hc, A_IRQ_MSK, 0);
3075 if (hc->chan[ch].protocol != protocol) {
3076 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3077 HFC_wait(hc);
3078 }
3079 /* tx silence */
3080 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3081 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3082 ((ch % 4) * 4)) << 1);
3083 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3084 } else {
3085 /* enable TX fifo */
3086 HFC_outb(hc, R_FIFO, ch << 1);
3087 HFC_wait(hc);
3088 if (hc->ctype == HFC_TYPE_XHFC)
3089 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3090 V_HDLC_TRP | V_IFF);
3091 /* Enable FIFO, no interrupt */
3092 else
3093 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3094 V_HDLC_TRP | V_IFF);
3095 HFC_outb(hc, A_SUBCH_CFG, 0);
3096 HFC_outb(hc, A_IRQ_MSK, 0);
3097 if (hc->chan[ch].protocol != protocol) {
3098 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3099 HFC_wait(hc);
3100 }
3101 /* tx silence */
3102 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3103 /* enable RX fifo */
3104 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3105 HFC_wait(hc);
3106 if (hc->ctype == HFC_TYPE_XHFC)
3107 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3108 V_HDLC_TRP);
3109 /* Enable FIFO, no interrupt*/
3110 else
3111 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3112 V_HDLC_TRP);
3113 HFC_outb(hc, A_SUBCH_CFG, 0);
3114 HFC_outb(hc, A_IRQ_MSK, 0);
3115 if (hc->chan[ch].protocol != protocol) {
3116 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3117 HFC_wait(hc);
3118 }
3119 }
3120 if (hc->ctype != HFC_TYPE_E1) {
3121 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3122 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3123 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3124 /* undocumented: delay after R_ST_SEL */
3125 udelay(1);
3126 HFC_outb(hc, A_ST_CTRL0,
3127 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3128 }
3129 if (hc->chan[ch].bch)
3130 test_and_set_bit(FLG_TRANSPARENT,
3131 &hc->chan[ch].bch->Flags);
3132 break;
3133 case (ISDN_P_B_HDLC): /* B-channel */
3134 case (ISDN_P_TE_S0): /* D-channel */
3135 case (ISDN_P_NT_S0):
3136 case (ISDN_P_TE_E1):
3137 case (ISDN_P_NT_E1):
3138 /* enable TX fifo */
3139 HFC_outb(hc, R_FIFO, ch << 1);
3140 HFC_wait(hc);
3141 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3142 /* E1 or B-channel */
3143 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3144 HFC_outb(hc, A_SUBCH_CFG, 0);
3145 } else {
3146 /* D-Channel without HDLC fill flags */
3147 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3148 HFC_outb(hc, A_SUBCH_CFG, 2);
3149 }
3150 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3151 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3152 HFC_wait(hc);
3153 /* enable RX fifo */
3154 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3155 HFC_wait(hc);
3156 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3157 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3158 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3159 else
3160 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3161 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3162 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3163 HFC_wait(hc);
3164 if (hc->chan[ch].bch) {
3165 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3166 if (hc->ctype != HFC_TYPE_E1) {
3167 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3168 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3169 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3170 /* undocumented: delay after R_ST_SEL */
3171 udelay(1);
3172 HFC_outb(hc, A_ST_CTRL0,
3173 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3174 }
3175 }
3176 break;
3177 default:
3178 printk(KERN_DEBUG "%s: protocol not known %x\n",
3179 __func__, protocol);
3180 hc->chan[ch].protocol = ISDN_P_NONE;
3181 return -ENOPROTOOPT;
3182 }
3183 hc->chan[ch].protocol = protocol;
3184 return 0;
3185 }
3186
3187
3188 /*
3189 * connect/disconnect PCM
3190 */
3191
3192 static void
3193 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3194 int slot_rx, int bank_rx)
3195 {
3196 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3197 /* disable PCM */
3198 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3199 return;
3200 }
3201
3202 /* enable pcm */
3203 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3204 slot_rx, bank_rx);
3205 }
3206
3207 /*
3208 * set/disable conference
3209 */
3210
3211 static void
3212 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3213 {
3214 if (num >= 0 && num <= 7)
3215 hc->chan[ch].conf = num;
3216 else
3217 hc->chan[ch].conf = -1;
3218 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3219 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3220 hc->chan[ch].bank_rx);
3221 }
3222
3223
3224 /*
3225 * set/disable sample loop
3226 */
3227
3228 /* NOTE: this function is experimental and therefore disabled */
3229
3230 /*
3231 * Layer 1 callback function
3232 */
3233 static int
3234 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3235 {
3236 struct hfc_multi *hc = dch->hw;
3237 u_long flags;
3238
3239 switch (cmd) {
3240 case INFO3_P8:
3241 case INFO3_P10:
3242 break;
3243 case HW_RESET_REQ:
3244 /* start activation */
3245 spin_lock_irqsave(&hc->lock, flags);
3246 if (hc->ctype == HFC_TYPE_E1) {
3247 if (debug & DEBUG_HFCMULTI_MSG)
3248 printk(KERN_DEBUG
3249 "%s: HW_RESET_REQ no BRI\n",
3250 __func__);
3251 } else {
3252 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3253 /* undocumented: delay after R_ST_SEL */
3254 udelay(1);
3255 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3256 udelay(6); /* wait at least 5,21us */
3257 HFC_outb(hc, A_ST_WR_STATE, 3);
3258 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3259 /* activate */
3260 }
3261 spin_unlock_irqrestore(&hc->lock, flags);
3262 l1_event(dch->l1, HW_POWERUP_IND);
3263 break;
3264 case HW_DEACT_REQ:
3265 /* start deactivation */
3266 spin_lock_irqsave(&hc->lock, flags);
3267 if (hc->ctype == HFC_TYPE_E1) {
3268 if (debug & DEBUG_HFCMULTI_MSG)
3269 printk(KERN_DEBUG
3270 "%s: HW_DEACT_REQ no BRI\n",
3271 __func__);
3272 } else {
3273 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3274 /* undocumented: delay after R_ST_SEL */
3275 udelay(1);
3276 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3277 /* deactivate */
3278 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3279 hc->syncronized &=
3280 ~(1 << hc->chan[dch->slot].port);
3281 plxsd_checksync(hc, 0);
3282 }
3283 }
3284 skb_queue_purge(&dch->squeue);
3285 if (dch->tx_skb) {
3286 dev_kfree_skb(dch->tx_skb);
3287 dch->tx_skb = NULL;
3288 }
3289 dch->tx_idx = 0;
3290 if (dch->rx_skb) {
3291 dev_kfree_skb(dch->rx_skb);
3292 dch->rx_skb = NULL;
3293 }
3294 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3295 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3296 del_timer(&dch->timer);
3297 spin_unlock_irqrestore(&hc->lock, flags);
3298 break;
3299 case HW_POWERUP_REQ:
3300 spin_lock_irqsave(&hc->lock, flags);
3301 if (hc->ctype == HFC_TYPE_E1) {
3302 if (debug & DEBUG_HFCMULTI_MSG)
3303 printk(KERN_DEBUG
3304 "%s: HW_POWERUP_REQ no BRI\n",
3305 __func__);
3306 } else {
3307 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3308 /* undocumented: delay after R_ST_SEL */
3309 udelay(1);
3310 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3311 udelay(6); /* wait at least 5,21us */
3312 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3313 }
3314 spin_unlock_irqrestore(&hc->lock, flags);
3315 break;
3316 case PH_ACTIVATE_IND:
3317 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3318 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3319 GFP_ATOMIC);
3320 break;
3321 case PH_DEACTIVATE_IND:
3322 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3323 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3324 GFP_ATOMIC);
3325 break;
3326 default:
3327 if (dch->debug & DEBUG_HW)
3328 printk(KERN_DEBUG "%s: unknown command %x\n",
3329 __func__, cmd);
3330 return -1;
3331 }
3332 return 0;
3333 }
3334
3335 /*
3336 * Layer2 -> Layer 1 Transfer
3337 */
3338
3339 static int
3340 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3341 {
3342 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3343 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3344 struct hfc_multi *hc = dch->hw;
3345 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3346 int ret = -EINVAL;
3347 unsigned int id;
3348 u_long flags;
3349
3350 switch (hh->prim) {
3351 case PH_DATA_REQ:
3352 if (skb->len < 1)
3353 break;
3354 spin_lock_irqsave(&hc->lock, flags);
3355 ret = dchannel_senddata(dch, skb);
3356 if (ret > 0) { /* direct TX */
3357 id = hh->id; /* skb can be freed */
3358 hfcmulti_tx(hc, dch->slot);
3359 ret = 0;
3360 /* start fifo */
3361 HFC_outb(hc, R_FIFO, 0);
3362 HFC_wait(hc);
3363 spin_unlock_irqrestore(&hc->lock, flags);
3364 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3365 } else
3366 spin_unlock_irqrestore(&hc->lock, flags);
3367 return ret;
3368 case PH_ACTIVATE_REQ:
3369 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3370 spin_lock_irqsave(&hc->lock, flags);
3371 ret = 0;
3372 if (debug & DEBUG_HFCMULTI_MSG)
3373 printk(KERN_DEBUG
3374 "%s: PH_ACTIVATE port %d (0..%d)\n",
3375 __func__, hc->chan[dch->slot].port,
3376 hc->ports - 1);
3377 /* start activation */
3378 if (hc->ctype == HFC_TYPE_E1) {
3379 ph_state_change(dch);
3380 if (debug & DEBUG_HFCMULTI_STATE)
3381 printk(KERN_DEBUG
3382 "%s: E1 report state %x \n",
3383 __func__, dch->state);
3384 } else {
3385 HFC_outb(hc, R_ST_SEL,
3386 hc->chan[dch->slot].port);
3387 /* undocumented: delay after R_ST_SEL */
3388 udelay(1);
3389 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3390 /* G1 */
3391 udelay(6); /* wait at least 5,21us */
3392 HFC_outb(hc, A_ST_WR_STATE, 1);
3393 HFC_outb(hc, A_ST_WR_STATE, 1 |
3394 (V_ST_ACT * 3)); /* activate */
3395 dch->state = 1;
3396 }
3397 spin_unlock_irqrestore(&hc->lock, flags);
3398 } else
3399 ret = l1_event(dch->l1, hh->prim);
3400 break;
3401 case PH_DEACTIVATE_REQ:
3402 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3403 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3404 spin_lock_irqsave(&hc->lock, flags);
3405 if (debug & DEBUG_HFCMULTI_MSG)
3406 printk(KERN_DEBUG
3407 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3408 __func__, hc->chan[dch->slot].port,
3409 hc->ports - 1);
3410 /* start deactivation */
3411 if (hc->ctype == HFC_TYPE_E1) {
3412 if (debug & DEBUG_HFCMULTI_MSG)
3413 printk(KERN_DEBUG
3414 "%s: PH_DEACTIVATE no BRI\n",
3415 __func__);
3416 } else {
3417 HFC_outb(hc, R_ST_SEL,
3418 hc->chan[dch->slot].port);
3419 /* undocumented: delay after R_ST_SEL */
3420 udelay(1);
3421 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3422 /* deactivate */
3423 dch->state = 1;
3424 }
3425 skb_queue_purge(&dch->squeue);
3426 if (dch->tx_skb) {
3427 dev_kfree_skb(dch->tx_skb);
3428 dch->tx_skb = NULL;
3429 }
3430 dch->tx_idx = 0;
3431 if (dch->rx_skb) {
3432 dev_kfree_skb(dch->rx_skb);
3433 dch->rx_skb = NULL;
3434 }
3435 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3436 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3437 del_timer(&dch->timer);
3438 #ifdef FIXME
3439 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3440 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3441 #endif
3442 ret = 0;
3443 spin_unlock_irqrestore(&hc->lock, flags);
3444 } else
3445 ret = l1_event(dch->l1, hh->prim);
3446 break;
3447 }
3448 if (!ret)
3449 dev_kfree_skb(skb);
3450 return ret;
3451 }
3452
3453 static void
3454 deactivate_bchannel(struct bchannel *bch)
3455 {
3456 struct hfc_multi *hc = bch->hw;
3457 u_long flags;
3458
3459 spin_lock_irqsave(&hc->lock, flags);
3460 mISDN_clear_bchannel(bch);
3461 hc->chan[bch->slot].coeff_count = 0;
3462 hc->chan[bch->slot].rx_off = 0;
3463 hc->chan[bch->slot].conf = -1;
3464 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3465 spin_unlock_irqrestore(&hc->lock, flags);
3466 }
3467
3468 static int
3469 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3470 {
3471 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3472 struct hfc_multi *hc = bch->hw;
3473 int ret = -EINVAL;
3474 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3475 unsigned long flags;
3476
3477 switch (hh->prim) {
3478 case PH_DATA_REQ:
3479 if (!skb->len)
3480 break;
3481 spin_lock_irqsave(&hc->lock, flags);
3482 ret = bchannel_senddata(bch, skb);
3483 if (ret > 0) { /* direct TX */
3484 hfcmulti_tx(hc, bch->slot);
3485 ret = 0;
3486 /* start fifo */
3487 HFC_outb_nodebug(hc, R_FIFO, 0);
3488 HFC_wait_nodebug(hc);
3489 }
3490 spin_unlock_irqrestore(&hc->lock, flags);
3491 return ret;
3492 case PH_ACTIVATE_REQ:
3493 if (debug & DEBUG_HFCMULTI_MSG)
3494 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3495 __func__, bch->slot);
3496 spin_lock_irqsave(&hc->lock, flags);
3497 /* activate B-channel if not already activated */
3498 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3499 hc->chan[bch->slot].txpending = 0;
3500 ret = mode_hfcmulti(hc, bch->slot,
3501 ch->protocol,
3502 hc->chan[bch->slot].slot_tx,
3503 hc->chan[bch->slot].bank_tx,
3504 hc->chan[bch->slot].slot_rx,
3505 hc->chan[bch->slot].bank_rx);
3506 if (!ret) {
3507 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3508 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3509 /* start decoder */
3510 hc->dtmf = 1;
3511 if (debug & DEBUG_HFCMULTI_DTMF)
3512 printk(KERN_DEBUG
3513 "%s: start dtmf decoder\n",
3514 __func__);
3515 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3516 V_RST_DTMF);
3517 }
3518 }
3519 } else
3520 ret = 0;
3521 spin_unlock_irqrestore(&hc->lock, flags);
3522 if (!ret)
3523 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3524 GFP_KERNEL);
3525 break;
3526 case PH_CONTROL_REQ:
3527 spin_lock_irqsave(&hc->lock, flags);
3528 switch (hh->id) {
3529 case HFC_SPL_LOOP_ON: /* set sample loop */
3530 if (debug & DEBUG_HFCMULTI_MSG)
3531 printk(KERN_DEBUG
3532 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3533 __func__, skb->len);
3534 ret = 0;
3535 break;
3536 case HFC_SPL_LOOP_OFF: /* set silence */
3537 if (debug & DEBUG_HFCMULTI_MSG)
3538 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3539 __func__);
3540 ret = 0;
3541 break;
3542 default:
3543 printk(KERN_ERR
3544 "%s: unknown PH_CONTROL_REQ info %x\n",
3545 __func__, hh->id);
3546 ret = -EINVAL;
3547 }
3548 spin_unlock_irqrestore(&hc->lock, flags);
3549 break;
3550 case PH_DEACTIVATE_REQ:
3551 deactivate_bchannel(bch); /* locked there */
3552 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3553 GFP_KERNEL);
3554 ret = 0;
3555 break;
3556 }
3557 if (!ret)
3558 dev_kfree_skb(skb);
3559 return ret;
3560 }
3561
3562 /*
3563 * bchannel control function
3564 */
3565 static int
3566 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3567 {
3568 int ret = 0;
3569 struct dsp_features *features =
3570 (struct dsp_features *)(*((u_long *)&cq->p1));
3571 struct hfc_multi *hc = bch->hw;
3572 int slot_tx;
3573 int bank_tx;
3574 int slot_rx;
3575 int bank_rx;
3576 int num;
3577
3578 switch (cq->op) {
3579 case MISDN_CTRL_GETOP:
3580 ret = mISDN_ctrl_bchannel(bch, cq);
3581 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3582 break;
3583 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3584 ret = mISDN_ctrl_bchannel(bch, cq);
3585 hc->chan[bch->slot].rx_off = !!cq->p1;
3586 if (!hc->chan[bch->slot].rx_off) {
3587 /* reset fifo on rx on */
3588 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3589 HFC_wait_nodebug(hc);
3590 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3591 HFC_wait_nodebug(hc);
3592 }
3593 if (debug & DEBUG_HFCMULTI_MSG)
3594 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3595 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3596 break;
3597 case MISDN_CTRL_FILL_EMPTY:
3598 ret = mISDN_ctrl_bchannel(bch, cq);
3599 hc->silence = bch->fill[0];
3600 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3601 break;
3602 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3603 if (debug & DEBUG_HFCMULTI_MSG)
3604 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3605 __func__);
3606 /* create confirm */
3607 features->hfc_id = hc->id;
3608 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3609 features->hfc_dtmf = 1;
3610 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3611 features->hfc_conf = 1;
3612 features->hfc_loops = 0;
3613 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3614 features->hfc_echocanhw = 1;
3615 } else {
3616 features->pcm_id = hc->pcm;
3617 features->pcm_slots = hc->slots;
3618 features->pcm_banks = 2;
3619 }
3620 break;
3621 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3622 slot_tx = cq->p1 & 0xff;
3623 bank_tx = cq->p1 >> 8;
3624 slot_rx = cq->p2 & 0xff;
3625 bank_rx = cq->p2 >> 8;
3626 if (debug & DEBUG_HFCMULTI_MSG)
3627 printk(KERN_DEBUG
3628 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3629 "slot %d bank %d (RX)\n",
3630 __func__, slot_tx, bank_tx,
3631 slot_rx, bank_rx);
3632 if (slot_tx < hc->slots && bank_tx <= 2 &&
3633 slot_rx < hc->slots && bank_rx <= 2)
3634 hfcmulti_pcm(hc, bch->slot,
3635 slot_tx, bank_tx, slot_rx, bank_rx);
3636 else {
3637 printk(KERN_WARNING
3638 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3639 "slot %d bank %d (RX) out of range\n",
3640 __func__, slot_tx, bank_tx,
3641 slot_rx, bank_rx);
3642 ret = -EINVAL;
3643 }
3644 break;
3645 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3646 if (debug & DEBUG_HFCMULTI_MSG)
3647 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3648 __func__);
3649 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3650 break;
3651 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3652 num = cq->p1 & 0xff;
3653 if (debug & DEBUG_HFCMULTI_MSG)
3654 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3655 __func__, num);
3656 if (num <= 7)
3657 hfcmulti_conf(hc, bch->slot, num);
3658 else {
3659 printk(KERN_WARNING
3660 "%s: HW_CONF_JOIN conf %d out of range\n",
3661 __func__, num);
3662 ret = -EINVAL;
3663 }
3664 break;
3665 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3666 if (debug & DEBUG_HFCMULTI_MSG)
3667 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3668 hfcmulti_conf(hc, bch->slot, -1);
3669 break;
3670 case MISDN_CTRL_HFC_ECHOCAN_ON:
3671 if (debug & DEBUG_HFCMULTI_MSG)
3672 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3673 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3674 vpm_echocan_on(hc, bch->slot, cq->p1);
3675 else
3676 ret = -EINVAL;
3677 break;
3678
3679 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3680 if (debug & DEBUG_HFCMULTI_MSG)
3681 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3682 __func__);
3683 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3684 vpm_echocan_off(hc, bch->slot);
3685 else
3686 ret = -EINVAL;
3687 break;
3688 default:
3689 ret = mISDN_ctrl_bchannel(bch, cq);
3690 break;
3691 }
3692 return ret;
3693 }
3694
3695 static int
3696 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3697 {
3698 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3699 struct hfc_multi *hc = bch->hw;
3700 int err = -EINVAL;
3701 u_long flags;
3702
3703 if (bch->debug & DEBUG_HW)
3704 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3705 __func__, cmd, arg);
3706 switch (cmd) {
3707 case CLOSE_CHANNEL:
3708 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3709 deactivate_bchannel(bch); /* locked there */
3710 ch->protocol = ISDN_P_NONE;
3711 ch->peer = NULL;
3712 module_put(THIS_MODULE);
3713 err = 0;
3714 break;
3715 case CONTROL_CHANNEL:
3716 spin_lock_irqsave(&hc->lock, flags);
3717 err = channel_bctrl(bch, arg);
3718 spin_unlock_irqrestore(&hc->lock, flags);
3719 break;
3720 default:
3721 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3722 __func__, cmd);
3723 }
3724 return err;
3725 }
3726
3727 /*
3728 * handle D-channel events
3729 *
3730 * handle state change event
3731 */
3732 static void
3733 ph_state_change(struct dchannel *dch)
3734 {
3735 struct hfc_multi *hc;
3736 int ch, i;
3737
3738 if (!dch) {
3739 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3740 return;
3741 }
3742 hc = dch->hw;
3743 ch = dch->slot;
3744
3745 if (hc->ctype == HFC_TYPE_E1) {
3746 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3747 if (debug & DEBUG_HFCMULTI_STATE)
3748 printk(KERN_DEBUG
3749 "%s: E1 TE (id=%d) newstate %x\n",
3750 __func__, hc->id, dch->state);
3751 } else {
3752 if (debug & DEBUG_HFCMULTI_STATE)
3753 printk(KERN_DEBUG
3754 "%s: E1 NT (id=%d) newstate %x\n",
3755 __func__, hc->id, dch->state);
3756 }
3757 switch (dch->state) {
3758 case (1):
3759 if (hc->e1_state != 1) {
3760 for (i = 1; i <= 31; i++) {
3761 /* reset fifos on e1 activation */
3762 HFC_outb_nodebug(hc, R_FIFO,
3763 (i << 1) | 1);
3764 HFC_wait_nodebug(hc);
3765 HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3766 V_RES_F);
3767 HFC_wait_nodebug(hc);
3768 }
3769 }
3770 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3771 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3772 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3773 break;
3774
3775 default:
3776 if (hc->e1_state != 1)
3777 return;
3778 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3779 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3780 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3781 }
3782 hc->e1_state = dch->state;
3783 } else {
3784 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3785 if (debug & DEBUG_HFCMULTI_STATE)
3786 printk(KERN_DEBUG
3787 "%s: S/T TE newstate %x\n",
3788 __func__, dch->state);
3789 switch (dch->state) {
3790 case (0):
3791 l1_event(dch->l1, HW_RESET_IND);
3792 break;
3793 case (3):
3794 l1_event(dch->l1, HW_DEACT_IND);
3795 break;
3796 case (5):
3797 case (8):
3798 l1_event(dch->l1, ANYSIGNAL);
3799 break;
3800 case (6):
3801 l1_event(dch->l1, INFO2);
3802 break;
3803 case (7):
3804 l1_event(dch->l1, INFO4_P8);
3805 break;
3806 }
3807 } else {
3808 if (debug & DEBUG_HFCMULTI_STATE)
3809 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3810 __func__, dch->state);
3811 switch (dch->state) {
3812 case (2):
3813 if (hc->chan[ch].nt_timer == 0) {
3814 hc->chan[ch].nt_timer = -1;
3815 HFC_outb(hc, R_ST_SEL,
3816 hc->chan[ch].port);
3817 /* undocumented: delay after R_ST_SEL */
3818 udelay(1);
3819 HFC_outb(hc, A_ST_WR_STATE, 4 |
3820 V_ST_LD_STA); /* G4 */
3821 udelay(6); /* wait at least 5,21us */
3822 HFC_outb(hc, A_ST_WR_STATE, 4);
3823 dch->state = 4;
3824 } else {
3825 /* one extra count for the next event */
3826 hc->chan[ch].nt_timer =
3827 nt_t1_count[poll_timer] + 1;
3828 HFC_outb(hc, R_ST_SEL,
3829 hc->chan[ch].port);
3830 /* undocumented: delay after R_ST_SEL */
3831 udelay(1);
3832 /* allow G2 -> G3 transition */
3833 HFC_outb(hc, A_ST_WR_STATE, 2 |
3834 V_SET_G2_G3);
3835 }
3836 break;
3837 case (1):
3838 hc->chan[ch].nt_timer = -1;
3839 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3840 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3841 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3842 break;
3843 case (4):
3844 hc->chan[ch].nt_timer = -1;
3845 break;
3846 case (3):
3847 hc->chan[ch].nt_timer = -1;
3848 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3849 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3850 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3851 break;
3852 }
3853 }
3854 }
3855 }
3856
3857 /*
3858 * called for card mode init message
3859 */
3860
3861 static void
3862 hfcmulti_initmode(struct dchannel *dch)
3863 {
3864 struct hfc_multi *hc = dch->hw;
3865 u_char a_st_wr_state, r_e1_wr_sta;
3866 int i, pt;
3867
3868 if (debug & DEBUG_HFCMULTI_INIT)
3869 printk(KERN_DEBUG "%s: entered\n", __func__);
3870
3871 i = dch->slot;
3872 pt = hc->chan[i].port;
3873 if (hc->ctype == HFC_TYPE_E1) {
3874 /* E1 */
3875 hc->chan[hc->dnum[pt]].slot_tx = -1;
3876 hc->chan[hc->dnum[pt]].slot_rx = -1;
3877 hc->chan[hc->dnum[pt]].conf = -1;
3878 if (hc->dnum[pt]) {
3879 mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3880 -1, 0, -1, 0);
3881 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3882 dch->timer.data = (long) dch;
3883 init_timer(&dch->timer);
3884 }
3885 for (i = 1; i <= 31; i++) {
3886 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3887 continue;
3888 hc->chan[i].slot_tx = -1;
3889 hc->chan[i].slot_rx = -1;
3890 hc->chan[i].conf = -1;
3891 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3892 }
3893 }
3894 if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3895 /* E1, port 0 */
3896 dch = hc->chan[hc->dnum[0]].dch;
3897 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3898 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3899 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3900 }
3901 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3902 HFC_outb(hc, R_RX0, 0);
3903 hc->hw.r_tx0 = 0 | V_OUT_EN;
3904 } else {
3905 HFC_outb(hc, R_RX0, 1);
3906 hc->hw.r_tx0 = 1 | V_OUT_EN;
3907 }
3908 hc->hw.r_tx1 = V_ATX | V_NTRI;
3909 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3910 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3911 HFC_outb(hc, R_TX_FR0, 0x00);
3912 HFC_outb(hc, R_TX_FR1, 0xf8);
3913
3914 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3915 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3916
3917 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3918
3919 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3920 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3921
3922 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3923 if (debug & DEBUG_HFCMULTI_INIT)
3924 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3925 __func__);
3926 r_e1_wr_sta = 0; /* G0 */
3927 hc->e1_getclock = 0;
3928 } else {
3929 if (debug & DEBUG_HFCMULTI_INIT)
3930 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3931 __func__);
3932 r_e1_wr_sta = 0; /* F0 */
3933 hc->e1_getclock = 1;
3934 }
3935 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3936 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3937 else
3938 HFC_outb(hc, R_SYNC_OUT, 0);
3939 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3940 hc->e1_getclock = 1;
3941 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3942 hc->e1_getclock = 0;
3943 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3944 /* SLAVE (clock master) */
3945 if (debug & DEBUG_HFCMULTI_INIT)
3946 printk(KERN_DEBUG
3947 "%s: E1 port is clock master "
3948 "(clock from PCM)\n", __func__);
3949 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3950 } else {
3951 if (hc->e1_getclock) {
3952 /* MASTER (clock slave) */
3953 if (debug & DEBUG_HFCMULTI_INIT)
3954 printk(KERN_DEBUG
3955 "%s: E1 port is clock slave "
3956 "(clock to PCM)\n", __func__);
3957 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3958 } else {
3959 /* MASTER (clock master) */
3960 if (debug & DEBUG_HFCMULTI_INIT)
3961 printk(KERN_DEBUG "%s: E1 port is "
3962 "clock master "
3963 "(clock from QUARTZ)\n",
3964 __func__);
3965 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3966 V_PCM_SYNC | V_JATT_OFF);
3967 HFC_outb(hc, R_SYNC_OUT, 0);
3968 }
3969 }
3970 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3971 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3972 HFC_outb(hc, R_PWM0, 0x50);
3973 HFC_outb(hc, R_PWM1, 0xff);
3974 /* state machine setup */
3975 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3976 udelay(6); /* wait at least 5,21us */
3977 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3978 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3979 hc->syncronized = 0;
3980 plxsd_checksync(hc, 0);
3981 }
3982 }
3983 if (hc->ctype != HFC_TYPE_E1) {
3984 /* ST */
3985 hc->chan[i].slot_tx = -1;
3986 hc->chan[i].slot_rx = -1;
3987 hc->chan[i].conf = -1;
3988 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3989 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3990 dch->timer.data = (long) dch;
3991 init_timer(&dch->timer);
3992 hc->chan[i - 2].slot_tx = -1;
3993 hc->chan[i - 2].slot_rx = -1;
3994 hc->chan[i - 2].conf = -1;
3995 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3996 hc->chan[i - 1].slot_tx = -1;
3997 hc->chan[i - 1].slot_rx = -1;
3998 hc->chan[i - 1].conf = -1;
3999 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
4000 /* select interface */
4001 HFC_outb(hc, R_ST_SEL, pt);
4002 /* undocumented: delay after R_ST_SEL */
4003 udelay(1);
4004 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
4005 if (debug & DEBUG_HFCMULTI_INIT)
4006 printk(KERN_DEBUG
4007 "%s: ST port %d is NT-mode\n",
4008 __func__, pt);
4009 /* clock delay */
4010 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
4011 a_st_wr_state = 1; /* G1 */
4012 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
4013 } else {
4014 if (debug & DEBUG_HFCMULTI_INIT)
4015 printk(KERN_DEBUG
4016 "%s: ST port %d is TE-mode\n",
4017 __func__, pt);
4018 /* clock delay */
4019 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4020 a_st_wr_state = 2; /* F2 */
4021 hc->hw.a_st_ctrl0[pt] = 0;
4022 }
4023 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4024 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4025 if (hc->ctype == HFC_TYPE_XHFC) {
4026 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4027 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4028 0x7c << 1 /* V_ST_PULSE */);
4029 }
4030 /* line setup */
4031 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4032 /* disable E-channel */
4033 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4034 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4035 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4036 else
4037 HFC_outb(hc, A_ST_CTRL1, 0);
4038 /* enable B-channel receive */
4039 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
4040 /* state machine setup */
4041 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4042 udelay(6); /* wait at least 5,21us */
4043 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4044 hc->hw.r_sci_msk |= 1 << pt;
4045 /* state machine interrupts */
4046 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4047 /* unset sync on port */
4048 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4049 hc->syncronized &=
4050 ~(1 << hc->chan[dch->slot].port);
4051 plxsd_checksync(hc, 0);
4052 }
4053 }
4054 if (debug & DEBUG_HFCMULTI_INIT)
4055 printk("%s: done\n", __func__);
4056 }
4057
4058
4059 static int
4060 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4061 struct channel_req *rq)
4062 {
4063 int err = 0;
4064 u_long flags;
4065
4066 if (debug & DEBUG_HW_OPEN)
4067 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4068 dch->dev.id, __builtin_return_address(0));
4069 if (rq->protocol == ISDN_P_NONE)
4070 return -EINVAL;
4071 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4072 (dch->dev.D.protocol != rq->protocol)) {
4073 if (debug & DEBUG_HFCMULTI_MODE)
4074 printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4075 __func__, dch->dev.D.protocol, rq->protocol);
4076 }
4077 if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4078 (rq->protocol != ISDN_P_TE_S0))
4079 l1_event(dch->l1, CLOSE_CHANNEL);
4080 if (dch->dev.D.protocol != rq->protocol) {
4081 if (rq->protocol == ISDN_P_TE_S0) {
4082 err = create_l1(dch, hfcm_l1callback);
4083 if (err)
4084 return err;
4085 }
4086 dch->dev.D.protocol = rq->protocol;
4087 spin_lock_irqsave(&hc->lock, flags);
4088 hfcmulti_initmode(dch);
4089 spin_unlock_irqrestore(&hc->lock, flags);
4090 }
4091 if (test_bit(FLG_ACTIVE, &dch->Flags))
4092 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4093 0, NULL, GFP_KERNEL);
4094 rq->ch = &dch->dev.D;
4095 if (!try_module_get(THIS_MODULE))
4096 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4097 return 0;
4098 }
4099
4100 static int
4101 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4102 struct channel_req *rq)
4103 {
4104 struct bchannel *bch;
4105 int ch;
4106
4107 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4108 return -EINVAL;
4109 if (rq->protocol == ISDN_P_NONE)
4110 return -EINVAL;
4111 if (hc->ctype == HFC_TYPE_E1)
4112 ch = rq->adr.channel;
4113 else
4114 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4115 bch = hc->chan[ch].bch;
4116 if (!bch) {
4117 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4118 __func__, ch);
4119 return -EINVAL;
4120 }
4121 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4122 return -EBUSY; /* b-channel can be only open once */
4123 bch->ch.protocol = rq->protocol;
4124 hc->chan[ch].rx_off = 0;
4125 rq->ch = &bch->ch;
4126 if (!try_module_get(THIS_MODULE))
4127 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4128 return 0;
4129 }
4130
4131 /*
4132 * device control function
4133 */
4134 static int
4135 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4136 {
4137 struct hfc_multi *hc = dch->hw;
4138 int ret = 0;
4139 int wd_mode, wd_cnt;
4140
4141 switch (cq->op) {
4142 case MISDN_CTRL_GETOP:
4143 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4144 break;
4145 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4146 wd_cnt = cq->p1 & 0xf;
4147 wd_mode = !!(cq->p1 >> 4);
4148 if (debug & DEBUG_HFCMULTI_MSG)
4149 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4150 ", counter 0x%x\n", __func__,
4151 wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4152 /* set the watchdog timer */
4153 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4154 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4155 if (hc->ctype == HFC_TYPE_XHFC)
4156 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4157 /* init the watchdog register and reset the counter */
4158 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4159 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4160 /* enable the watchdog output for Speech-Design */
4161 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4162 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4163 HFC_outb(hc, R_GPIO_OUT1, 0);
4164 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4165 }
4166 break;
4167 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4168 if (debug & DEBUG_HFCMULTI_MSG)
4169 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4170 __func__);
4171 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4172 break;
4173 case MISDN_CTRL_L1_TIMER3:
4174 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4175 break;
4176 default:
4177 printk(KERN_WARNING "%s: unknown Op %x\n",
4178 __func__, cq->op);
4179 ret = -EINVAL;
4180 break;
4181 }
4182 return ret;
4183 }
4184
4185 static int
4186 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4187 {
4188 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4189 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4190 struct hfc_multi *hc = dch->hw;
4191 struct channel_req *rq;
4192 int err = 0;
4193 u_long flags;
4194
4195 if (dch->debug & DEBUG_HW)
4196 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4197 __func__, cmd, arg);
4198 switch (cmd) {
4199 case OPEN_CHANNEL:
4200 rq = arg;
4201 switch (rq->protocol) {
4202 case ISDN_P_TE_S0:
4203 case ISDN_P_NT_S0:
4204 if (hc->ctype == HFC_TYPE_E1) {
4205 err = -EINVAL;
4206 break;
4207 }
4208 err = open_dchannel(hc, dch, rq); /* locked there */
4209 break;
4210 case ISDN_P_TE_E1:
4211 case ISDN_P_NT_E1:
4212 if (hc->ctype != HFC_TYPE_E1) {
4213 err = -EINVAL;
4214 break;
4215 }
4216 err = open_dchannel(hc, dch, rq); /* locked there */
4217 break;
4218 default:
4219 spin_lock_irqsave(&hc->lock, flags);
4220 err = open_bchannel(hc, dch, rq);
4221 spin_unlock_irqrestore(&hc->lock, flags);
4222 }
4223 break;
4224 case CLOSE_CHANNEL:
4225 if (debug & DEBUG_HW_OPEN)
4226 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4227 __func__, dch->dev.id,
4228 __builtin_return_address(0));
4229 module_put(THIS_MODULE);
4230 break;
4231 case CONTROL_CHANNEL:
4232 spin_lock_irqsave(&hc->lock, flags);
4233 err = channel_dctrl(dch, arg);
4234 spin_unlock_irqrestore(&hc->lock, flags);
4235 break;
4236 default:
4237 if (dch->debug & DEBUG_HW)
4238 printk(KERN_DEBUG "%s: unknown command %x\n",
4239 __func__, cmd);
4240 err = -EINVAL;
4241 }
4242 return err;
4243 }
4244
4245 static int
4246 clockctl(void *priv, int enable)
4247 {
4248 struct hfc_multi *hc = priv;
4249
4250 hc->iclock_on = enable;
4251 return 0;
4252 }
4253
4254 /*
4255 * initialize the card
4256 */
4257
4258 /*
4259 * start timer irq, wait some time and check if we have interrupts.
4260 * if not, reset chip and try again.
4261 */
4262 static int
4263 init_card(struct hfc_multi *hc)
4264 {
4265 int err = -EIO;
4266 u_long flags;
4267 void __iomem *plx_acc;
4268 u_long plx_flags;
4269
4270 if (debug & DEBUG_HFCMULTI_INIT)
4271 printk(KERN_DEBUG "%s: entered\n", __func__);
4272
4273 spin_lock_irqsave(&hc->lock, flags);
4274 /* set interrupts but leave global interrupt disabled */
4275 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4276 disable_hwirq(hc);
4277 spin_unlock_irqrestore(&hc->lock, flags);
4278
4279 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4280 "HFC-multi", hc)) {
4281 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4282 hc->irq);
4283 hc->irq = 0;
4284 return -EIO;
4285 }
4286
4287 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4288 spin_lock_irqsave(&plx_lock, plx_flags);
4289 plx_acc = hc->plx_membase + PLX_INTCSR;
4290 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4291 plx_acc); /* enable PCI & LINT1 irq */
4292 spin_unlock_irqrestore(&plx_lock, plx_flags);
4293 }
4294
4295 if (debug & DEBUG_HFCMULTI_INIT)
4296 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4297 __func__, hc->irq, hc->irqcnt);
4298 err = init_chip(hc);
4299 if (err)
4300 goto error;
4301 /*
4302 * Finally enable IRQ output
4303 * this is only allowed, if an IRQ routine is already
4304 * established for this HFC, so don't do that earlier
4305 */
4306 spin_lock_irqsave(&hc->lock, flags);
4307 enable_hwirq(hc);
4308 spin_unlock_irqrestore(&hc->lock, flags);
4309 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4310 set_current_state(TASK_UNINTERRUPTIBLE);
4311 schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4312 /* turn IRQ off until chip is completely initialized */
4313 spin_lock_irqsave(&hc->lock, flags);
4314 disable_hwirq(hc);
4315 spin_unlock_irqrestore(&hc->lock, flags);
4316 if (debug & DEBUG_HFCMULTI_INIT)
4317 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4318 __func__, hc->irq, hc->irqcnt);
4319 if (hc->irqcnt) {
4320 if (debug & DEBUG_HFCMULTI_INIT)
4321 printk(KERN_DEBUG "%s: done\n", __func__);
4322
4323 return 0;
4324 }
4325 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4326 printk(KERN_INFO "ignoring missing interrupts\n");
4327 return 0;
4328 }
4329
4330 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4331 hc->irq);
4332
4333 err = -EIO;
4334
4335 error:
4336 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4337 spin_lock_irqsave(&plx_lock, plx_flags);
4338 plx_acc = hc->plx_membase + PLX_INTCSR;
4339 writew(0x00, plx_acc); /*disable IRQs*/
4340 spin_unlock_irqrestore(&plx_lock, plx_flags);
4341 }
4342
4343 if (debug & DEBUG_HFCMULTI_INIT)
4344 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4345 if (hc->irq) {
4346 free_irq(hc->irq, hc);
4347 hc->irq = 0;
4348 }
4349
4350 if (debug & DEBUG_HFCMULTI_INIT)
4351 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4352 return err;
4353 }
4354
4355 /*
4356 * find pci device and set it up
4357 */
4358
4359 static int
4360 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4361 const struct pci_device_id *ent)
4362 {
4363 struct hm_map *m = (struct hm_map *)ent->driver_data;
4364
4365 printk(KERN_INFO
4366 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4367 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4368
4369 hc->pci_dev = pdev;
4370 if (m->clock2)
4371 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4372
4373 if (ent->device == 0xB410) {
4374 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4375 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4376 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4377 hc->slots = 32;
4378 }
4379
4380 if (hc->pci_dev->irq <= 0) {
4381 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4382 return -EIO;
4383 }
4384 if (pci_enable_device(hc->pci_dev)) {
4385 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4386 return -EIO;
4387 }
4388 hc->leds = m->leds;
4389 hc->ledstate = 0xAFFEAFFE;
4390 hc->opticalsupport = m->opticalsupport;
4391
4392 hc->pci_iobase = 0;
4393 hc->pci_membase = NULL;
4394 hc->plx_membase = NULL;
4395
4396 /* set memory access methods */
4397 if (m->io_mode) /* use mode from card config */
4398 hc->io_mode = m->io_mode;
4399 switch (hc->io_mode) {
4400 case HFC_IO_MODE_PLXSD:
4401 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4402 hc->slots = 128; /* required */
4403 hc->HFC_outb = HFC_outb_pcimem;
4404 hc->HFC_inb = HFC_inb_pcimem;
4405 hc->HFC_inw = HFC_inw_pcimem;
4406 hc->HFC_wait = HFC_wait_pcimem;
4407 hc->read_fifo = read_fifo_pcimem;
4408 hc->write_fifo = write_fifo_pcimem;
4409 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4410 /* MEMBASE 1 is PLX PCI Bridge */
4411
4412 if (!hc->plx_origmembase) {
4413 printk(KERN_WARNING
4414 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4415 pci_disable_device(hc->pci_dev);
4416 return -EIO;
4417 }
4418
4419 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4420 if (!hc->plx_membase) {
4421 printk(KERN_WARNING
4422 "HFC-multi: failed to remap plx address space. "
4423 "(internal error)\n");
4424 pci_disable_device(hc->pci_dev);
4425 return -EIO;
4426 }
4427 printk(KERN_INFO
4428 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4429 (u_long)hc->plx_membase, hc->plx_origmembase);
4430
4431 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4432 /* MEMBASE 1 is PLX PCI Bridge */
4433 if (!hc->pci_origmembase) {
4434 printk(KERN_WARNING
4435 "HFC-multi: No IO-Memory for PCI card found\n");
4436 pci_disable_device(hc->pci_dev);
4437 return -EIO;
4438 }
4439
4440 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4441 if (!hc->pci_membase) {
4442 printk(KERN_WARNING "HFC-multi: failed to remap io "
4443 "address space. (internal error)\n");
4444 pci_disable_device(hc->pci_dev);
4445 return -EIO;
4446 }
4447
4448 printk(KERN_INFO
4449 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4450 "leds-type %d\n",
4451 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4452 hc->pci_dev->irq, HZ, hc->leds);
4453 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4454 break;
4455 case HFC_IO_MODE_PCIMEM:
4456 hc->HFC_outb = HFC_outb_pcimem;
4457 hc->HFC_inb = HFC_inb_pcimem;
4458 hc->HFC_inw = HFC_inw_pcimem;
4459 hc->HFC_wait = HFC_wait_pcimem;
4460 hc->read_fifo = read_fifo_pcimem;
4461 hc->write_fifo = write_fifo_pcimem;
4462 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4463 if (!hc->pci_origmembase) {
4464 printk(KERN_WARNING
4465 "HFC-multi: No IO-Memory for PCI card found\n");
4466 pci_disable_device(hc->pci_dev);
4467 return -EIO;
4468 }
4469
4470 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4471 if (!hc->pci_membase) {
4472 printk(KERN_WARNING
4473 "HFC-multi: failed to remap io address space. "
4474 "(internal error)\n");
4475 pci_disable_device(hc->pci_dev);
4476 return -EIO;
4477 }
4478 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4479 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4480 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4481 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4482 break;
4483 case HFC_IO_MODE_REGIO:
4484 hc->HFC_outb = HFC_outb_regio;
4485 hc->HFC_inb = HFC_inb_regio;
4486 hc->HFC_inw = HFC_inw_regio;
4487 hc->HFC_wait = HFC_wait_regio;
4488 hc->read_fifo = read_fifo_regio;
4489 hc->write_fifo = write_fifo_regio;
4490 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4491 if (!hc->pci_iobase) {
4492 printk(KERN_WARNING
4493 "HFC-multi: No IO for PCI card found\n");
4494 pci_disable_device(hc->pci_dev);
4495 return -EIO;
4496 }
4497
4498 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4499 printk(KERN_WARNING "HFC-multi: failed to request "
4500 "address space at 0x%08lx (internal error)\n",
4501 hc->pci_iobase);
4502 pci_disable_device(hc->pci_dev);
4503 return -EIO;
4504 }
4505
4506 printk(KERN_INFO
4507 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4508 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4509 hc->pci_dev->irq, HZ, hc->leds);
4510 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4511 break;
4512 default:
4513 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4514 pci_disable_device(hc->pci_dev);
4515 return -EIO;
4516 }
4517
4518 pci_set_drvdata(hc->pci_dev, hc);
4519
4520 /* At this point the needed PCI config is done */
4521 /* fifos are still not enabled */
4522 return 0;
4523 }
4524
4525
4526 /*
4527 * remove port
4528 */
4529
4530 static void
4531 release_port(struct hfc_multi *hc, struct dchannel *dch)
4532 {
4533 int pt, ci, i = 0;
4534 u_long flags;
4535 struct bchannel *pb;
4536
4537 ci = dch->slot;
4538 pt = hc->chan[ci].port;
4539
4540 if (debug & DEBUG_HFCMULTI_INIT)
4541 printk(KERN_DEBUG "%s: entered for port %d\n",
4542 __func__, pt + 1);
4543
4544 if (pt >= hc->ports) {
4545 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4546 __func__, pt + 1);
4547 return;
4548 }
4549
4550 if (debug & DEBUG_HFCMULTI_INIT)
4551 printk(KERN_DEBUG "%s: releasing port=%d\n",
4552 __func__, pt + 1);
4553
4554 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4555 l1_event(dch->l1, CLOSE_CHANNEL);
4556
4557 hc->chan[ci].dch = NULL;
4558
4559 if (hc->created[pt]) {
4560 hc->created[pt] = 0;
4561 mISDN_unregister_device(&dch->dev);
4562 }
4563
4564 spin_lock_irqsave(&hc->lock, flags);
4565
4566 if (dch->timer.function) {
4567 del_timer(&dch->timer);
4568 dch->timer.function = NULL;
4569 }
4570
4571 if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4572 /* remove sync */
4573 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4574 hc->syncronized = 0;
4575 plxsd_checksync(hc, 1);
4576 }
4577 /* free channels */
4578 for (i = 0; i <= 31; i++) {
4579 if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4580 continue;
4581 if (hc->chan[i].bch) {
4582 if (debug & DEBUG_HFCMULTI_INIT)
4583 printk(KERN_DEBUG
4584 "%s: free port %d channel %d\n",
4585 __func__, hc->chan[i].port + 1, i);
4586 pb = hc->chan[i].bch;
4587 hc->chan[i].bch = NULL;
4588 spin_unlock_irqrestore(&hc->lock, flags);
4589 mISDN_freebchannel(pb);
4590 kfree(pb);
4591 kfree(hc->chan[i].coeff);
4592 spin_lock_irqsave(&hc->lock, flags);
4593 }
4594 }
4595 } else {
4596 /* remove sync */
4597 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4598 hc->syncronized &=
4599 ~(1 << hc->chan[ci].port);
4600 plxsd_checksync(hc, 1);
4601 }
4602 /* free channels */
4603 if (hc->chan[ci - 2].bch) {
4604 if (debug & DEBUG_HFCMULTI_INIT)
4605 printk(KERN_DEBUG
4606 "%s: free port %d channel %d\n",
4607 __func__, hc->chan[ci - 2].port + 1,
4608 ci - 2);
4609 pb = hc->chan[ci - 2].bch;
4610 hc->chan[ci - 2].bch = NULL;
4611 spin_unlock_irqrestore(&hc->lock, flags);
4612 mISDN_freebchannel(pb);
4613 kfree(pb);
4614 kfree(hc->chan[ci - 2].coeff);
4615 spin_lock_irqsave(&hc->lock, flags);
4616 }
4617 if (hc->chan[ci - 1].bch) {
4618 if (debug & DEBUG_HFCMULTI_INIT)
4619 printk(KERN_DEBUG
4620 "%s: free port %d channel %d\n",
4621 __func__, hc->chan[ci - 1].port + 1,
4622 ci - 1);
4623 pb = hc->chan[ci - 1].bch;
4624 hc->chan[ci - 1].bch = NULL;
4625 spin_unlock_irqrestore(&hc->lock, flags);
4626 mISDN_freebchannel(pb);
4627 kfree(pb);
4628 kfree(hc->chan[ci - 1].coeff);
4629 spin_lock_irqsave(&hc->lock, flags);
4630 }
4631 }
4632
4633 spin_unlock_irqrestore(&hc->lock, flags);
4634
4635 if (debug & DEBUG_HFCMULTI_INIT)
4636 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4637 pt+1, ci);
4638 mISDN_freedchannel(dch);
4639 kfree(dch);
4640
4641 if (debug & DEBUG_HFCMULTI_INIT)
4642 printk(KERN_DEBUG "%s: done!\n", __func__);
4643 }
4644
4645 static void
4646 release_card(struct hfc_multi *hc)
4647 {
4648 u_long flags;
4649 int ch;
4650
4651 if (debug & DEBUG_HFCMULTI_INIT)
4652 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4653 __func__, hc->id);
4654
4655 /* unregister clock source */
4656 if (hc->iclock)
4657 mISDN_unregister_clock(hc->iclock);
4658
4659 /* disable and free irq */
4660 spin_lock_irqsave(&hc->lock, flags);
4661 disable_hwirq(hc);
4662 spin_unlock_irqrestore(&hc->lock, flags);
4663 udelay(1000);
4664 if (hc->irq) {
4665 if (debug & DEBUG_HFCMULTI_INIT)
4666 printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4667 __func__, hc->irq, hc);
4668 free_irq(hc->irq, hc);
4669 hc->irq = 0;
4670
4671 }
4672
4673 /* disable D-channels & B-channels */
4674 if (debug & DEBUG_HFCMULTI_INIT)
4675 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4676 __func__);
4677 for (ch = 0; ch <= 31; ch++) {
4678 if (hc->chan[ch].dch)
4679 release_port(hc, hc->chan[ch].dch);
4680 }
4681
4682 /* dimm leds */
4683 if (hc->leds)
4684 hfcmulti_leds(hc);
4685
4686 /* release hardware */
4687 release_io_hfcmulti(hc);
4688
4689 if (debug & DEBUG_HFCMULTI_INIT)
4690 printk(KERN_DEBUG "%s: remove instance from list\n",
4691 __func__);
4692 list_del(&hc->list);
4693
4694 if (debug & DEBUG_HFCMULTI_INIT)
4695 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4696 if (hc == syncmaster)
4697 syncmaster = NULL;
4698 kfree(hc);
4699 if (debug & DEBUG_HFCMULTI_INIT)
4700 printk(KERN_DEBUG "%s: card successfully removed\n",
4701 __func__);
4702 }
4703
4704 static void
4705 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4706 {
4707 /* set optical line type */
4708 if (port[Port_cnt] & 0x001) {
4709 if (!m->opticalsupport) {
4710 printk(KERN_INFO
4711 "This board has no optical "
4712 "support\n");
4713 } else {
4714 if (debug & DEBUG_HFCMULTI_INIT)
4715 printk(KERN_DEBUG
4716 "%s: PORT set optical "
4717 "interfacs: card(%d) "
4718 "port(%d)\n",
4719 __func__,
4720 HFC_cnt + 1, 1);
4721 test_and_set_bit(HFC_CFG_OPTICAL,
4722 &hc->chan[hc->dnum[0]].cfg);
4723 }
4724 }
4725 /* set LOS report */
4726 if (port[Port_cnt] & 0x004) {
4727 if (debug & DEBUG_HFCMULTI_INIT)
4728 printk(KERN_DEBUG "%s: PORT set "
4729 "LOS report: card(%d) port(%d)\n",
4730 __func__, HFC_cnt + 1, 1);
4731 test_and_set_bit(HFC_CFG_REPORT_LOS,
4732 &hc->chan[hc->dnum[0]].cfg);
4733 }
4734 /* set AIS report */
4735 if (port[Port_cnt] & 0x008) {
4736 if (debug & DEBUG_HFCMULTI_INIT)
4737 printk(KERN_DEBUG "%s: PORT set "
4738 "AIS report: card(%d) port(%d)\n",
4739 __func__, HFC_cnt + 1, 1);
4740 test_and_set_bit(HFC_CFG_REPORT_AIS,
4741 &hc->chan[hc->dnum[0]].cfg);
4742 }
4743 /* set SLIP report */
4744 if (port[Port_cnt] & 0x010) {
4745 if (debug & DEBUG_HFCMULTI_INIT)
4746 printk(KERN_DEBUG
4747 "%s: PORT set SLIP report: "
4748 "card(%d) port(%d)\n",
4749 __func__, HFC_cnt + 1, 1);
4750 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4751 &hc->chan[hc->dnum[0]].cfg);
4752 }
4753 /* set RDI report */
4754 if (port[Port_cnt] & 0x020) {
4755 if (debug & DEBUG_HFCMULTI_INIT)
4756 printk(KERN_DEBUG
4757 "%s: PORT set RDI report: "
4758 "card(%d) port(%d)\n",
4759 __func__, HFC_cnt + 1, 1);
4760 test_and_set_bit(HFC_CFG_REPORT_RDI,
4761 &hc->chan[hc->dnum[0]].cfg);
4762 }
4763 /* set CRC-4 Mode */
4764 if (!(port[Port_cnt] & 0x100)) {
4765 if (debug & DEBUG_HFCMULTI_INIT)
4766 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4767 " card(%d) port(%d)\n",
4768 __func__, HFC_cnt + 1, 1);
4769 test_and_set_bit(HFC_CFG_CRC4,
4770 &hc->chan[hc->dnum[0]].cfg);
4771 } else {
4772 if (debug & DEBUG_HFCMULTI_INIT)
4773 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4774 " report: card(%d) port(%d)\n",
4775 __func__, HFC_cnt + 1, 1);
4776 }
4777 /* set forced clock */
4778 if (port[Port_cnt] & 0x0200) {
4779 if (debug & DEBUG_HFCMULTI_INIT)
4780 printk(KERN_DEBUG "%s: PORT force getting clock from "
4781 "E1: card(%d) port(%d)\n",
4782 __func__, HFC_cnt + 1, 1);
4783 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4784 } else
4785 if (port[Port_cnt] & 0x0400) {
4786 if (debug & DEBUG_HFCMULTI_INIT)
4787 printk(KERN_DEBUG "%s: PORT force putting clock to "
4788 "E1: card(%d) port(%d)\n",
4789 __func__, HFC_cnt + 1, 1);
4790 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4791 }
4792 /* set JATT PLL */
4793 if (port[Port_cnt] & 0x0800) {
4794 if (debug & DEBUG_HFCMULTI_INIT)
4795 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4796 "E1: card(%d) port(%d)\n",
4797 __func__, HFC_cnt + 1, 1);
4798 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4799 }
4800 /* set elastic jitter buffer */
4801 if (port[Port_cnt] & 0x3000) {
4802 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4803 if (debug & DEBUG_HFCMULTI_INIT)
4804 printk(KERN_DEBUG
4805 "%s: PORT set elastic "
4806 "buffer to %d: card(%d) port(%d)\n",
4807 __func__, hc->chan[hc->dnum[0]].jitter,
4808 HFC_cnt + 1, 1);
4809 } else
4810 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4811 }
4812
4813 static int
4814 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4815 {
4816 struct dchannel *dch;
4817 struct bchannel *bch;
4818 int ch, ret = 0;
4819 char name[MISDN_MAX_IDLEN];
4820 int bcount = 0;
4821
4822 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4823 if (!dch)
4824 return -ENOMEM;
4825 dch->debug = debug;
4826 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4827 dch->hw = hc;
4828 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4829 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4830 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4831 dch->dev.D.send = handle_dmsg;
4832 dch->dev.D.ctrl = hfcm_dctrl;
4833 dch->slot = hc->dnum[pt];
4834 hc->chan[hc->dnum[pt]].dch = dch;
4835 hc->chan[hc->dnum[pt]].port = pt;
4836 hc->chan[hc->dnum[pt]].nt_timer = -1;
4837 for (ch = 1; ch <= 31; ch++) {
4838 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4839 continue;
4840 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4841 if (!bch) {
4842 printk(KERN_ERR "%s: no memory for bchannel\n",
4843 __func__);
4844 ret = -ENOMEM;
4845 goto free_chan;
4846 }
4847 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4848 if (!hc->chan[ch].coeff) {
4849 printk(KERN_ERR "%s: no memory for coeffs\n",
4850 __func__);
4851 ret = -ENOMEM;
4852 kfree(bch);
4853 goto free_chan;
4854 }
4855 bch->nr = ch;
4856 bch->slot = ch;
4857 bch->debug = debug;
4858 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4859 bch->hw = hc;
4860 bch->ch.send = handle_bmsg;
4861 bch->ch.ctrl = hfcm_bctrl;
4862 bch->ch.nr = ch;
4863 list_add(&bch->ch.list, &dch->dev.bchannels);
4864 hc->chan[ch].bch = bch;
4865 hc->chan[ch].port = pt;
4866 set_channelmap(bch->nr, dch->dev.channelmap);
4867 bcount++;
4868 }
4869 dch->dev.nrbchan = bcount;
4870 if (pt == 0)
4871 init_e1_port_hw(hc, m);
4872 if (hc->ports > 1)
4873 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4874 HFC_cnt + 1, pt+1);
4875 else
4876 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4877 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4878 if (ret)
4879 goto free_chan;
4880 hc->created[pt] = 1;
4881 return ret;
4882 free_chan:
4883 release_port(hc, dch);
4884 return ret;
4885 }
4886
4887 static int
4888 init_multi_port(struct hfc_multi *hc, int pt)
4889 {
4890 struct dchannel *dch;
4891 struct bchannel *bch;
4892 int ch, i, ret = 0;
4893 char name[MISDN_MAX_IDLEN];
4894
4895 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4896 if (!dch)
4897 return -ENOMEM;
4898 dch->debug = debug;
4899 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4900 dch->hw = hc;
4901 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4902 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4903 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4904 dch->dev.D.send = handle_dmsg;
4905 dch->dev.D.ctrl = hfcm_dctrl;
4906 dch->dev.nrbchan = 2;
4907 i = pt << 2;
4908 dch->slot = i + 2;
4909 hc->chan[i + 2].dch = dch;
4910 hc->chan[i + 2].port = pt;
4911 hc->chan[i + 2].nt_timer = -1;
4912 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4913 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4914 if (!bch) {
4915 printk(KERN_ERR "%s: no memory for bchannel\n",
4916 __func__);
4917 ret = -ENOMEM;
4918 goto free_chan;
4919 }
4920 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4921 if (!hc->chan[i + ch].coeff) {
4922 printk(KERN_ERR "%s: no memory for coeffs\n",
4923 __func__);
4924 ret = -ENOMEM;
4925 kfree(bch);
4926 goto free_chan;
4927 }
4928 bch->nr = ch + 1;
4929 bch->slot = i + ch;
4930 bch->debug = debug;
4931 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4932 bch->hw = hc;
4933 bch->ch.send = handle_bmsg;
4934 bch->ch.ctrl = hfcm_bctrl;
4935 bch->ch.nr = ch + 1;
4936 list_add(&bch->ch.list, &dch->dev.bchannels);
4937 hc->chan[i + ch].bch = bch;
4938 hc->chan[i + ch].port = pt;
4939 set_channelmap(bch->nr, dch->dev.channelmap);
4940 }
4941 /* set master clock */
4942 if (port[Port_cnt] & 0x001) {
4943 if (debug & DEBUG_HFCMULTI_INIT)
4944 printk(KERN_DEBUG
4945 "%s: PROTOCOL set master clock: "
4946 "card(%d) port(%d)\n",
4947 __func__, HFC_cnt + 1, pt + 1);
4948 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4949 printk(KERN_ERR "Error: Master clock "
4950 "for port(%d) of card(%d) is only"
4951 " possible with TE-mode\n",
4952 pt + 1, HFC_cnt + 1);
4953 ret = -EINVAL;
4954 goto free_chan;
4955 }
4956 if (hc->masterclk >= 0) {
4957 printk(KERN_ERR "Error: Master clock "
4958 "for port(%d) of card(%d) already "
4959 "defined for port(%d)\n",
4960 pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4961 ret = -EINVAL;
4962 goto free_chan;
4963 }
4964 hc->masterclk = pt;
4965 }
4966 /* set transmitter line to non capacitive */
4967 if (port[Port_cnt] & 0x002) {
4968 if (debug & DEBUG_HFCMULTI_INIT)
4969 printk(KERN_DEBUG
4970 "%s: PROTOCOL set non capacitive "
4971 "transmitter: card(%d) port(%d)\n",
4972 __func__, HFC_cnt + 1, pt + 1);
4973 test_and_set_bit(HFC_CFG_NONCAP_TX,
4974 &hc->chan[i + 2].cfg);
4975 }
4976 /* disable E-channel */
4977 if (port[Port_cnt] & 0x004) {
4978 if (debug & DEBUG_HFCMULTI_INIT)
4979 printk(KERN_DEBUG
4980 "%s: PROTOCOL disable E-channel: "
4981 "card(%d) port(%d)\n",
4982 __func__, HFC_cnt + 1, pt + 1);
4983 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4984 &hc->chan[i + 2].cfg);
4985 }
4986 if (hc->ctype == HFC_TYPE_XHFC) {
4987 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4988 HFC_cnt + 1, pt + 1);
4989 ret = mISDN_register_device(&dch->dev, NULL, name);
4990 } else {
4991 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4992 hc->ctype, HFC_cnt + 1, pt + 1);
4993 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4994 }
4995 if (ret)
4996 goto free_chan;
4997 hc->created[pt] = 1;
4998 return ret;
4999 free_chan:
5000 release_port(hc, dch);
5001 return ret;
5002 }
5003
5004 static int
5005 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
5006 const struct pci_device_id *ent)
5007 {
5008 int ret_err = 0;
5009 int pt;
5010 struct hfc_multi *hc;
5011 u_long flags;
5012 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
5013 int i, ch;
5014 u_int maskcheck;
5015
5016 if (HFC_cnt >= MAX_CARDS) {
5017 printk(KERN_ERR "too many cards (max=%d).\n",
5018 MAX_CARDS);
5019 return -EINVAL;
5020 }
5021 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5022 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
5023 "type[%d] %d was supplied as module parameter\n",
5024 m->vendor_name, m->card_name, m->type, HFC_cnt,
5025 type[HFC_cnt] & 0xff);
5026 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
5027 "first, to see cards and their types.");
5028 return -EINVAL;
5029 }
5030 if (debug & DEBUG_HFCMULTI_INIT)
5031 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
5032 __func__, m->vendor_name, m->card_name, m->type,
5033 type[HFC_cnt]);
5034
5035 /* allocate card+fifo structure */
5036 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5037 if (!hc) {
5038 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5039 return -ENOMEM;
5040 }
5041 spin_lock_init(&hc->lock);
5042 hc->mtyp = m;
5043 hc->ctype = m->type;
5044 hc->ports = m->ports;
5045 hc->id = HFC_cnt;
5046 hc->pcm = pcm[HFC_cnt];
5047 hc->io_mode = iomode[HFC_cnt];
5048 if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5049 /* fragment card */
5050 pt = 0;
5051 maskcheck = 0;
5052 for (ch = 0; ch <= 31; ch++) {
5053 if (!((1 << ch) & dmask[E1_cnt]))
5054 continue;
5055 hc->dnum[pt] = ch;
5056 hc->bmask[pt] = bmask[bmask_cnt++];
5057 if ((maskcheck & hc->bmask[pt])
5058 || (dmask[E1_cnt] & hc->bmask[pt])) {
5059 printk(KERN_INFO
5060 "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5061 E1_cnt + 1, pt);
5062 kfree(hc);
5063 return -EINVAL;
5064 }
5065 maskcheck |= hc->bmask[pt];
5066 printk(KERN_INFO
5067 "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5068 E1_cnt + 1, ch, hc->bmask[pt]);
5069 pt++;
5070 }
5071 hc->ports = pt;
5072 }
5073 if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5074 /* default card layout */
5075 hc->dnum[0] = 16;
5076 hc->bmask[0] = 0xfffefffe;
5077 hc->ports = 1;
5078 }
5079
5080 /* set chip specific features */
5081 hc->masterclk = -1;
5082 if (type[HFC_cnt] & 0x100) {
5083 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5084 hc->silence = 0xff; /* ulaw silence */
5085 } else
5086 hc->silence = 0x2a; /* alaw silence */
5087 if ((poll >> 1) > sizeof(hc->silence_data)) {
5088 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5089 "please fix\n");
5090 kfree(hc);
5091 return -EINVAL;
5092 }
5093 for (i = 0; i < (poll >> 1); i++)
5094 hc->silence_data[i] = hc->silence;
5095
5096 if (hc->ctype != HFC_TYPE_XHFC) {
5097 if (!(type[HFC_cnt] & 0x200))
5098 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5099 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5100 }
5101
5102 if (type[HFC_cnt] & 0x800)
5103 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5104 if (type[HFC_cnt] & 0x1000) {
5105 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5106 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5107 }
5108 if (type[HFC_cnt] & 0x4000)
5109 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5110 if (type[HFC_cnt] & 0x8000)
5111 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5112 hc->slots = 32;
5113 if (type[HFC_cnt] & 0x10000)
5114 hc->slots = 64;
5115 if (type[HFC_cnt] & 0x20000)
5116 hc->slots = 128;
5117 if (type[HFC_cnt] & 0x80000) {
5118 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5119 hc->wdcount = 0;
5120 hc->wdbyte = V_GPIO_OUT2;
5121 printk(KERN_NOTICE "Watchdog enabled\n");
5122 }
5123
5124 if (pdev && ent)
5125 /* setup pci, hc->slots may change due to PLXSD */
5126 ret_err = setup_pci(hc, pdev, ent);
5127 else
5128 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5129 ret_err = setup_embedded(hc, m);
5130 #else
5131 {
5132 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5133 ret_err = -EIO;
5134 }
5135 #endif
5136 if (ret_err) {
5137 if (hc == syncmaster)
5138 syncmaster = NULL;
5139 kfree(hc);
5140 return ret_err;
5141 }
5142
5143 hc->HFC_outb_nodebug = hc->HFC_outb;
5144 hc->HFC_inb_nodebug = hc->HFC_inb;
5145 hc->HFC_inw_nodebug = hc->HFC_inw;
5146 hc->HFC_wait_nodebug = hc->HFC_wait;
5147 #ifdef HFC_REGISTER_DEBUG
5148 hc->HFC_outb = HFC_outb_debug;
5149 hc->HFC_inb = HFC_inb_debug;
5150 hc->HFC_inw = HFC_inw_debug;
5151 hc->HFC_wait = HFC_wait_debug;
5152 #endif
5153 /* create channels */
5154 for (pt = 0; pt < hc->ports; pt++) {
5155 if (Port_cnt >= MAX_PORTS) {
5156 printk(KERN_ERR "too many ports (max=%d).\n",
5157 MAX_PORTS);
5158 ret_err = -EINVAL;
5159 goto free_card;
5160 }
5161 if (hc->ctype == HFC_TYPE_E1)
5162 ret_err = init_e1_port(hc, m, pt);
5163 else
5164 ret_err = init_multi_port(hc, pt);
5165 if (debug & DEBUG_HFCMULTI_INIT)
5166 printk(KERN_DEBUG
5167 "%s: Registering D-channel, card(%d) port(%d) "
5168 "result %d\n",
5169 __func__, HFC_cnt + 1, pt + 1, ret_err);
5170
5171 if (ret_err) {
5172 while (pt) { /* release already registered ports */
5173 pt--;
5174 if (hc->ctype == HFC_TYPE_E1)
5175 release_port(hc,
5176 hc->chan[hc->dnum[pt]].dch);
5177 else
5178 release_port(hc,
5179 hc->chan[(pt << 2) + 2].dch);
5180 }
5181 goto free_card;
5182 }
5183 if (hc->ctype != HFC_TYPE_E1)
5184 Port_cnt++; /* for each S0 port */
5185 }
5186 if (hc->ctype == HFC_TYPE_E1) {
5187 Port_cnt++; /* for each E1 port */
5188 E1_cnt++;
5189 }
5190
5191 /* disp switches */
5192 switch (m->dip_type) {
5193 case DIP_4S:
5194 /*
5195 * Get DIP setting for beroNet 1S/2S/4S cards
5196 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5197 * GPI 19/23 (R_GPI_IN2))
5198 */
5199 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5200 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5201 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5202
5203 /* Port mode (TE/NT) jumpers */
5204 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5205
5206 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5207 pmj = ~pmj & 0xf;
5208
5209 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5210 m->vendor_name, m->card_name, dips, pmj);
5211 break;
5212 case DIP_8S:
5213 /*
5214 * Get DIP Setting for beroNet 8S0+ cards
5215 * Enable PCI auxbridge function
5216 */
5217 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5218 /* prepare access to auxport */
5219 outw(0x4000, hc->pci_iobase + 4);
5220 /*
5221 * some dummy reads are required to
5222 * read valid DIP switch data
5223 */
5224 dips = inb(hc->pci_iobase);
5225 dips = inb(hc->pci_iobase);
5226 dips = inb(hc->pci_iobase);
5227 dips = ~inb(hc->pci_iobase) & 0x3F;
5228 outw(0x0, hc->pci_iobase + 4);
5229 /* disable PCI auxbridge function */
5230 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5231 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5232 m->vendor_name, m->card_name, dips);
5233 break;
5234 case DIP_E1:
5235 /*
5236 * get DIP Setting for beroNet E1 cards
5237 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5238 */
5239 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5240 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5241 m->vendor_name, m->card_name, dips);
5242 break;
5243 }
5244
5245 /* add to list */
5246 spin_lock_irqsave(&HFClock, flags);
5247 list_add_tail(&hc->list, &HFClist);
5248 spin_unlock_irqrestore(&HFClock, flags);
5249
5250 /* use as clock source */
5251 if (clock == HFC_cnt + 1)
5252 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5253
5254 /* initialize hardware */
5255 hc->irq = (m->irq) ? : hc->pci_dev->irq;
5256 ret_err = init_card(hc);
5257 if (ret_err) {
5258 printk(KERN_ERR "init card returns %d\n", ret_err);
5259 release_card(hc);
5260 return ret_err;
5261 }
5262
5263 /* start IRQ and return */
5264 spin_lock_irqsave(&hc->lock, flags);
5265 enable_hwirq(hc);
5266 spin_unlock_irqrestore(&hc->lock, flags);
5267 return 0;
5268
5269 free_card:
5270 release_io_hfcmulti(hc);
5271 if (hc == syncmaster)
5272 syncmaster = NULL;
5273 kfree(hc);
5274 return ret_err;
5275 }
5276
5277 static void hfc_remove_pci(struct pci_dev *pdev)
5278 {
5279 struct hfc_multi *card = pci_get_drvdata(pdev);
5280 u_long flags;
5281
5282 if (debug)
5283 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5284 "device:%x subvendor:%x subdevice:%x\n",
5285 pdev->vendor, pdev->device,
5286 pdev->subsystem_vendor, pdev->subsystem_device);
5287
5288 if (card) {
5289 spin_lock_irqsave(&HFClock, flags);
5290 release_card(card);
5291 spin_unlock_irqrestore(&HFClock, flags);
5292 } else {
5293 if (debug)
5294 printk(KERN_DEBUG "%s: drvdata already removed\n",
5295 __func__);
5296 }
5297 }
5298
5299 #define VENDOR_CCD "Cologne Chip AG"
5300 #define VENDOR_BN "beroNet GmbH"
5301 #define VENDOR_DIG "Digium Inc."
5302 #define VENDOR_JH "Junghanns.NET GmbH"
5303 #define VENDOR_PRIM "PrimuX"
5304
5305 static const struct hm_map hfcm_map[] = {
5306 /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5307 /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5308 /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5309 /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5310 /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5311 /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5312 /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5313 /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5314 /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5315 /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5316 /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5317 /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5318
5319 /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5320 /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5321 HFC_IO_MODE_REGIO, 0},
5322 /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5323 /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5324
5325 /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5326 /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5327 /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5328
5329 /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5330 /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5331 /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5332 /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5333
5334 /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5335 /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5336 /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5337
5338 /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5339 HFC_IO_MODE_PLXSD, 0},
5340 /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5341 HFC_IO_MODE_PLXSD, 0},
5342 /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5343 /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5344 /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5345 /*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5346 HFC_IO_MODE_EMBSD, XHFC_IRQ},
5347 /*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5348 /*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5349 /*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5350 };
5351
5352 #undef H
5353 #define H(x) ((unsigned long)&hfcm_map[x])
5354 static struct pci_device_id hfmultipci_ids[] = {
5355
5356 /* Cards with HFC-4S Chip */
5357 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5358 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5359 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5360 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5361 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5362 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5363 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5364 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5365 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5366 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5367 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5368 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5369 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5370 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5371 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5372 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5373 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5374 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5375 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5376 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5377 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5378 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5379 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5380 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5381 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5382 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5383 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5384 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5385 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5386 0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5387 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5388 0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5389
5390 /* Cards with HFC-8S Chip */
5391 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5392 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5393 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5394 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5395 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5396 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5397 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5398 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5399 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5400 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5401 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5402 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5403 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5404 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5405 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5406 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5407 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5408 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */
5409
5410
5411 /* Cards with HFC-E1 Chip */
5412 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5413 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5414 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5415 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5416 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5417 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5418 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5419 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5420
5421 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5422 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5423 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5424 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5425 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5426 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5427
5428 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5429 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5430 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5431 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5432
5433 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5434 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5435
5436 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5437 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5438 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5439 {0, }
5440 };
5441 #undef H
5442
5443 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5444
5445 static int
5446 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5447 {
5448 struct hm_map *m = (struct hm_map *)ent->driver_data;
5449 int ret;
5450
5451 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5452 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5453 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5454 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5455 printk(KERN_ERR
5456 "Unknown HFC multiport controller (vendor:%04x device:%04x "
5457 "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5458 pdev->device, pdev->subsystem_vendor,
5459 pdev->subsystem_device);
5460 printk(KERN_ERR
5461 "Please contact the driver maintainer for support.\n");
5462 return -ENODEV;
5463 }
5464 ret = hfcmulti_init(m, pdev, ent);
5465 if (ret)
5466 return ret;
5467 HFC_cnt++;
5468 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5469 return 0;
5470 }
5471
5472 static struct pci_driver hfcmultipci_driver = {
5473 .name = "hfc_multi",
5474 .probe = hfcmulti_probe,
5475 .remove = hfc_remove_pci,
5476 .id_table = hfmultipci_ids,
5477 };
5478
5479 static void __exit
5480 HFCmulti_cleanup(void)
5481 {
5482 struct hfc_multi *card, *next;
5483
5484 /* get rid of all devices of this driver */
5485 list_for_each_entry_safe(card, next, &HFClist, list)
5486 release_card(card);
5487 pci_unregister_driver(&hfcmultipci_driver);
5488 }
5489
5490 static int __init
5491 HFCmulti_init(void)
5492 {
5493 int err;
5494 int i, xhfc = 0;
5495 struct hm_map m;
5496
5497 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5498
5499 #ifdef IRQ_DEBUG
5500 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5501 #endif
5502
5503 spin_lock_init(&HFClock);
5504 spin_lock_init(&plx_lock);
5505
5506 if (debug & DEBUG_HFCMULTI_INIT)
5507 printk(KERN_DEBUG "%s: init entered\n", __func__);
5508
5509 switch (poll) {
5510 case 0:
5511 poll_timer = 6;
5512 poll = 128;
5513 break;
5514 case 8:
5515 poll_timer = 2;
5516 break;
5517 case 16:
5518 poll_timer = 3;
5519 break;
5520 case 32:
5521 poll_timer = 4;
5522 break;
5523 case 64:
5524 poll_timer = 5;
5525 break;
5526 case 128:
5527 poll_timer = 6;
5528 break;
5529 case 256:
5530 poll_timer = 7;
5531 break;
5532 default:
5533 printk(KERN_ERR
5534 "%s: Wrong poll value (%d).\n", __func__, poll);
5535 err = -EINVAL;
5536 return err;
5537
5538 }
5539
5540 if (!clock)
5541 clock = 1;
5542
5543 /* Register the embedded devices.
5544 * This should be done before the PCI cards registration */
5545 switch (hwid) {
5546 case HWID_MINIP4:
5547 xhfc = 1;
5548 m = hfcm_map[31];
5549 break;
5550 case HWID_MINIP8:
5551 xhfc = 2;
5552 m = hfcm_map[31];
5553 break;
5554 case HWID_MINIP16:
5555 xhfc = 4;
5556 m = hfcm_map[31];
5557 break;
5558 default:
5559 xhfc = 0;
5560 }
5561
5562 for (i = 0; i < xhfc; ++i) {
5563 err = hfcmulti_init(&m, NULL, NULL);
5564 if (err) {
5565 printk(KERN_ERR "error registering embedded driver: "
5566 "%x\n", err);
5567 return err;
5568 }
5569 HFC_cnt++;
5570 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5571 }
5572
5573 /* Register the PCI cards */
5574 err = pci_register_driver(&hfcmultipci_driver);
5575 if (err < 0) {
5576 printk(KERN_ERR "error registering pci driver: %x\n", err);
5577 return err;
5578 }
5579
5580 return 0;
5581 }
5582
5583
5584 module_init(HFCmulti_init);
5585 module_exit(HFCmulti_cleanup);
Linux with added FPC-III support