?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / dvb-frontends / af9033.c
blobf8818028752e126ea53fd7399212a2a1698436f4
1 /*
2 * Afatech AF9033 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22 #include "af9033_priv.h"
23
24 /* Max transfer size done by I2C transfer functions */
25 #define MAX_XFER_SIZE 64
26
27 struct af9033_dev {
28 struct i2c_client *client;
29 struct dvb_frontend fe;
30 struct af9033_config cfg;
31 bool is_af9035;
32 bool is_it9135;
33
34 u32 bandwidth_hz;
35 bool ts_mode_parallel;
36 bool ts_mode_serial;
37
38 enum fe_status fe_status;
39 u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
40 u64 post_bit_error;
41 u64 post_bit_count;
42 u64 error_block_count;
43 u64 total_block_count;
44 };
45
46 /* write multiple registers */
47 static int af9033_wr_regs(struct af9033_dev *dev, u32 reg, const u8 *val,
48 int len)
49 {
50 int ret;
51 u8 buf[MAX_XFER_SIZE];
52 struct i2c_msg msg[1] = {
53 {
54 .addr = dev->client->addr,
55 .flags = 0,
56 .len = 3 + len,
57 .buf = buf,
58 }
59 };
60
61 if (3 + len > sizeof(buf)) {
62 dev_warn(&dev->client->dev,
63 "i2c wr reg=%04x: len=%d is too big!\n",
64 reg, len);
65 return -EINVAL;
66 }
67
68 buf[0] = (reg >> 16) & 0xff;
69 buf[1] = (reg >> 8) & 0xff;
70 buf[2] = (reg >> 0) & 0xff;
71 memcpy(&buf[3], val, len);
72
73 ret = i2c_transfer(dev->client->adapter, msg, 1);
74 if (ret == 1) {
75 ret = 0;
76 } else {
77 dev_warn(&dev->client->dev, "i2c wr failed=%d reg=%06x len=%d\n",
78 ret, reg, len);
79 ret = -EREMOTEIO;
80 }
81
82 return ret;
83 }
84
85 /* read multiple registers */
86 static int af9033_rd_regs(struct af9033_dev *dev, u32 reg, u8 *val, int len)
87 {
88 int ret;
89 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
90 (reg >> 0) & 0xff };
91 struct i2c_msg msg[2] = {
92 {
93 .addr = dev->client->addr,
94 .flags = 0,
95 .len = sizeof(buf),
96 .buf = buf
97 }, {
98 .addr = dev->client->addr,
99 .flags = I2C_M_RD,
100 .len = len,
101 .buf = val
102 }
103 };
104
105 ret = i2c_transfer(dev->client->adapter, msg, 2);
106 if (ret == 2) {
107 ret = 0;
108 } else {
109 dev_warn(&dev->client->dev, "i2c rd failed=%d reg=%06x len=%d\n",
110 ret, reg, len);
111 ret = -EREMOTEIO;
112 }
113
114 return ret;
115 }
116
117
118 /* write single register */
119 static int af9033_wr_reg(struct af9033_dev *dev, u32 reg, u8 val)
120 {
121 return af9033_wr_regs(dev, reg, &val, 1);
122 }
123
124 /* read single register */
125 static int af9033_rd_reg(struct af9033_dev *dev, u32 reg, u8 *val)
126 {
127 return af9033_rd_regs(dev, reg, val, 1);
128 }
129
130 /* write single register with mask */
131 static int af9033_wr_reg_mask(struct af9033_dev *dev, u32 reg, u8 val,
132 u8 mask)
133 {
134 int ret;
135 u8 tmp;
136
137 /* no need for read if whole reg is written */
138 if (mask != 0xff) {
139 ret = af9033_rd_regs(dev, reg, &tmp, 1);
140 if (ret)
141 return ret;
142
143 val &= mask;
144 tmp &= ~mask;
145 val |= tmp;
146 }
147
148 return af9033_wr_regs(dev, reg, &val, 1);
149 }
150
151 /* read single register with mask */
152 static int af9033_rd_reg_mask(struct af9033_dev *dev, u32 reg, u8 *val,
153 u8 mask)
154 {
155 int ret, i;
156 u8 tmp;
157
158 ret = af9033_rd_regs(dev, reg, &tmp, 1);
159 if (ret)
160 return ret;
161
162 tmp &= mask;
163
164 /* find position of the first bit */
165 for (i = 0; i < 8; i++) {
166 if ((mask >> i) & 0x01)
167 break;
168 }
169 *val = tmp >> i;
170
171 return 0;
172 }
173
174 /* write reg val table using reg addr auto increment */
175 static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
176 const struct reg_val *tab, int tab_len)
177 {
178 #define MAX_TAB_LEN 212
179 int ret, i, j;
180 u8 buf[1 + MAX_TAB_LEN];
181
182 dev_dbg(&dev->client->dev, "tab_len=%d\n", tab_len);
183
184 if (tab_len > sizeof(buf)) {
185 dev_warn(&dev->client->dev, "tab len %d is too big\n", tab_len);
186 return -EINVAL;
187 }
188
189 for (i = 0, j = 0; i < tab_len; i++) {
190 buf[j] = tab[i].val;
191
192 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
193 ret = af9033_wr_regs(dev, tab[i].reg - j, buf, j + 1);
194 if (ret < 0)
195 goto err;
196
197 j = 0;
198 } else {
199 j++;
200 }
201 }
202
203 return 0;
204
205 err:
206 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
207
208 return ret;
209 }
210
211 static u32 af9033_div(struct af9033_dev *dev, u32 a, u32 b, u32 x)
212 {
213 u32 r = 0, c = 0, i;
214
215 dev_dbg(&dev->client->dev, "a=%d b=%d x=%d\n", a, b, x);
216
217 if (a > b) {
218 c = a / b;
219 a = a - c * b;
220 }
221
222 for (i = 0; i < x; i++) {
223 if (a >= b) {
224 r += 1;
225 a -= b;
226 }
227 a <<= 1;
228 r <<= 1;
229 }
230 r = (c << (u32)x) + r;
231
232 dev_dbg(&dev->client->dev, "a=%d b=%d x=%d r=%d r=%x\n", a, b, x, r, r);
233
234 return r;
235 }
236
237 static int af9033_init(struct dvb_frontend *fe)
238 {
239 struct af9033_dev *dev = fe->demodulator_priv;
240 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
241 int ret, i, len;
242 const struct reg_val *init;
243 u8 buf[4];
244 u32 adc_cw, clock_cw;
245 struct reg_val_mask tab[] = {
246 { 0x80fb24, 0x00, 0x08 },
247 { 0x80004c, 0x00, 0xff },
248 { 0x00f641, dev->cfg.tuner, 0xff },
249 { 0x80f5ca, 0x01, 0x01 },
250 { 0x80f715, 0x01, 0x01 },
251 { 0x00f41f, 0x04, 0x04 },
252 { 0x00f41a, 0x01, 0x01 },
253 { 0x80f731, 0x00, 0x01 },
254 { 0x00d91e, 0x00, 0x01 },
255 { 0x00d919, 0x00, 0x01 },
256 { 0x80f732, 0x00, 0x01 },
257 { 0x00d91f, 0x00, 0x01 },
258 { 0x00d91a, 0x00, 0x01 },
259 { 0x80f730, 0x00, 0x01 },
260 { 0x80f778, 0x00, 0xff },
261 { 0x80f73c, 0x01, 0x01 },
262 { 0x80f776, 0x00, 0x01 },
263 { 0x00d8fd, 0x01, 0xff },
264 { 0x00d830, 0x01, 0xff },
265 { 0x00d831, 0x00, 0xff },
266 { 0x00d832, 0x00, 0xff },
267 { 0x80f985, dev->ts_mode_serial, 0x01 },
268 { 0x80f986, dev->ts_mode_parallel, 0x01 },
269 { 0x00d827, 0x00, 0xff },
270 { 0x00d829, 0x00, 0xff },
271 { 0x800045, dev->cfg.adc_multiplier, 0xff },
272 };
273
274 /* program clock control */
275 clock_cw = af9033_div(dev, dev->cfg.clock, 1000000ul, 19ul);
276 buf[0] = (clock_cw >> 0) & 0xff;
277 buf[1] = (clock_cw >> 8) & 0xff;
278 buf[2] = (clock_cw >> 16) & 0xff;
279 buf[3] = (clock_cw >> 24) & 0xff;
280
281 dev_dbg(&dev->client->dev, "clock=%d clock_cw=%08x\n",
282 dev->cfg.clock, clock_cw);
283
284 ret = af9033_wr_regs(dev, 0x800025, buf, 4);
285 if (ret < 0)
286 goto err;
287
288 /* program ADC control */
289 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
290 if (clock_adc_lut[i].clock == dev->cfg.clock)
291 break;
292 }
293 if (i == ARRAY_SIZE(clock_adc_lut)) {
294 dev_err(&dev->client->dev,
295 "Couldn't find ADC config for clock=%d\n",
296 dev->cfg.clock);
297 goto err;
298 }
299
300 adc_cw = af9033_div(dev, clock_adc_lut[i].adc, 1000000ul, 19ul);
301 buf[0] = (adc_cw >> 0) & 0xff;
302 buf[1] = (adc_cw >> 8) & 0xff;
303 buf[2] = (adc_cw >> 16) & 0xff;
304
305 dev_dbg(&dev->client->dev, "adc=%d adc_cw=%06x\n",
306 clock_adc_lut[i].adc, adc_cw);
307
308 ret = af9033_wr_regs(dev, 0x80f1cd, buf, 3);
309 if (ret < 0)
310 goto err;
311
312 /* program register table */
313 for (i = 0; i < ARRAY_SIZE(tab); i++) {
314 ret = af9033_wr_reg_mask(dev, tab[i].reg, tab[i].val,
315 tab[i].mask);
316 if (ret < 0)
317 goto err;
318 }
319
320 /* clock output */
321 if (dev->cfg.dyn0_clk) {
322 ret = af9033_wr_reg(dev, 0x80fba8, 0x00);
323 if (ret < 0)
324 goto err;
325 }
326
327 /* settings for TS interface */
328 if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
329 ret = af9033_wr_reg_mask(dev, 0x80f9a5, 0x00, 0x01);
330 if (ret < 0)
331 goto err;
332
333 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x01, 0x01);
334 if (ret < 0)
335 goto err;
336 } else {
337 ret = af9033_wr_reg_mask(dev, 0x80f990, 0x00, 0x01);
338 if (ret < 0)
339 goto err;
340
341 ret = af9033_wr_reg_mask(dev, 0x80f9b5, 0x00, 0x01);
342 if (ret < 0)
343 goto err;
344 }
345
346 /* load OFSM settings */
347 dev_dbg(&dev->client->dev, "load ofsm settings\n");
348 switch (dev->cfg.tuner) {
349 case AF9033_TUNER_IT9135_38:
350 case AF9033_TUNER_IT9135_51:
351 case AF9033_TUNER_IT9135_52:
352 len = ARRAY_SIZE(ofsm_init_it9135_v1);
353 init = ofsm_init_it9135_v1;
354 break;
355 case AF9033_TUNER_IT9135_60:
356 case AF9033_TUNER_IT9135_61:
357 case AF9033_TUNER_IT9135_62:
358 len = ARRAY_SIZE(ofsm_init_it9135_v2);
359 init = ofsm_init_it9135_v2;
360 break;
361 default:
362 len = ARRAY_SIZE(ofsm_init);
363 init = ofsm_init;
364 break;
365 }
366
367 ret = af9033_wr_reg_val_tab(dev, init, len);
368 if (ret < 0)
369 goto err;
370
371 /* load tuner specific settings */
372 dev_dbg(&dev->client->dev, "load tuner specific settings\n");
373 switch (dev->cfg.tuner) {
374 case AF9033_TUNER_TUA9001:
375 len = ARRAY_SIZE(tuner_init_tua9001);
376 init = tuner_init_tua9001;
377 break;
378 case AF9033_TUNER_FC0011:
379 len = ARRAY_SIZE(tuner_init_fc0011);
380 init = tuner_init_fc0011;
381 break;
382 case AF9033_TUNER_MXL5007T:
383 len = ARRAY_SIZE(tuner_init_mxl5007t);
384 init = tuner_init_mxl5007t;
385 break;
386 case AF9033_TUNER_TDA18218:
387 len = ARRAY_SIZE(tuner_init_tda18218);
388 init = tuner_init_tda18218;
389 break;
390 case AF9033_TUNER_FC2580:
391 len = ARRAY_SIZE(tuner_init_fc2580);
392 init = tuner_init_fc2580;
393 break;
394 case AF9033_TUNER_FC0012:
395 len = ARRAY_SIZE(tuner_init_fc0012);
396 init = tuner_init_fc0012;
397 break;
398 case AF9033_TUNER_IT9135_38:
399 len = ARRAY_SIZE(tuner_init_it9135_38);
400 init = tuner_init_it9135_38;
401 break;
402 case AF9033_TUNER_IT9135_51:
403 len = ARRAY_SIZE(tuner_init_it9135_51);
404 init = tuner_init_it9135_51;
405 break;
406 case AF9033_TUNER_IT9135_52:
407 len = ARRAY_SIZE(tuner_init_it9135_52);
408 init = tuner_init_it9135_52;
409 break;
410 case AF9033_TUNER_IT9135_60:
411 len = ARRAY_SIZE(tuner_init_it9135_60);
412 init = tuner_init_it9135_60;
413 break;
414 case AF9033_TUNER_IT9135_61:
415 len = ARRAY_SIZE(tuner_init_it9135_61);
416 init = tuner_init_it9135_61;
417 break;
418 case AF9033_TUNER_IT9135_62:
419 len = ARRAY_SIZE(tuner_init_it9135_62);
420 init = tuner_init_it9135_62;
421 break;
422 default:
423 dev_dbg(&dev->client->dev, "unsupported tuner ID=%d\n",
424 dev->cfg.tuner);
425 ret = -ENODEV;
426 goto err;
427 }
428
429 ret = af9033_wr_reg_val_tab(dev, init, len);
430 if (ret < 0)
431 goto err;
432
433 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
434 ret = af9033_wr_reg_mask(dev, 0x00d91c, 0x01, 0x01);
435 if (ret < 0)
436 goto err;
437
438 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
439 if (ret < 0)
440 goto err;
441
442 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x00, 0x01);
443 if (ret < 0)
444 goto err;
445 }
446
447 switch (dev->cfg.tuner) {
448 case AF9033_TUNER_IT9135_60:
449 case AF9033_TUNER_IT9135_61:
450 case AF9033_TUNER_IT9135_62:
451 ret = af9033_wr_reg(dev, 0x800000, 0x01);
452 if (ret < 0)
453 goto err;
454 }
455
456 dev->bandwidth_hz = 0; /* force to program all parameters */
457 /* init stats here in order signal app which stats are supported */
458 c->strength.len = 1;
459 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
460 c->cnr.len = 1;
461 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
462 c->block_count.len = 1;
463 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
464 c->block_error.len = 1;
465 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
466 c->post_bit_count.len = 1;
467 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
468 c->post_bit_error.len = 1;
469 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
470
471 return 0;
472
473 err:
474 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
475
476 return ret;
477 }
478
479 static int af9033_sleep(struct dvb_frontend *fe)
480 {
481 struct af9033_dev *dev = fe->demodulator_priv;
482 int ret, i;
483 u8 tmp;
484
485 ret = af9033_wr_reg(dev, 0x80004c, 1);
486 if (ret < 0)
487 goto err;
488
489 ret = af9033_wr_reg(dev, 0x800000, 0);
490 if (ret < 0)
491 goto err;
492
493 for (i = 100, tmp = 1; i && tmp; i--) {
494 ret = af9033_rd_reg(dev, 0x80004c, &tmp);
495 if (ret < 0)
496 goto err;
497
498 usleep_range(200, 10000);
499 }
500
501 dev_dbg(&dev->client->dev, "loop=%d\n", i);
502
503 if (i == 0) {
504 ret = -ETIMEDOUT;
505 goto err;
506 }
507
508 ret = af9033_wr_reg_mask(dev, 0x80fb24, 0x08, 0x08);
509 if (ret < 0)
510 goto err;
511
512 /* prevent current leak (?) */
513 if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
514 /* enable parallel TS */
515 ret = af9033_wr_reg_mask(dev, 0x00d917, 0x00, 0x01);
516 if (ret < 0)
517 goto err;
518
519 ret = af9033_wr_reg_mask(dev, 0x00d916, 0x01, 0x01);
520 if (ret < 0)
521 goto err;
522 }
523
524 return 0;
525
526 err:
527 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
528
529 return ret;
530 }
531
532 static int af9033_get_tune_settings(struct dvb_frontend *fe,
533 struct dvb_frontend_tune_settings *fesettings)
534 {
535 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
536 fesettings->min_delay_ms = 2000;
537 fesettings->step_size = 0;
538 fesettings->max_drift = 0;
539
540 return 0;
541 }
542
543 static int af9033_set_frontend(struct dvb_frontend *fe)
544 {
545 struct af9033_dev *dev = fe->demodulator_priv;
546 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
547 int ret, i, spec_inv, sampling_freq;
548 u8 tmp, buf[3], bandwidth_reg_val;
549 u32 if_frequency, freq_cw, adc_freq;
550
551 dev_dbg(&dev->client->dev, "frequency=%d bandwidth_hz=%d\n",
552 c->frequency, c->bandwidth_hz);
553
554 /* check bandwidth */
555 switch (c->bandwidth_hz) {
556 case 6000000:
557 bandwidth_reg_val = 0x00;
558 break;
559 case 7000000:
560 bandwidth_reg_val = 0x01;
561 break;
562 case 8000000:
563 bandwidth_reg_val = 0x02;
564 break;
565 default:
566 dev_dbg(&dev->client->dev, "invalid bandwidth_hz\n");
567 ret = -EINVAL;
568 goto err;
569 }
570
571 /* program tuner */
572 if (fe->ops.tuner_ops.set_params)
573 fe->ops.tuner_ops.set_params(fe);
574
575 /* program CFOE coefficients */
576 if (c->bandwidth_hz != dev->bandwidth_hz) {
577 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
578 if (coeff_lut[i].clock == dev->cfg.clock &&
579 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
580 break;
581 }
582 }
583 if (i == ARRAY_SIZE(coeff_lut)) {
584 dev_err(&dev->client->dev,
585 "Couldn't find LUT config for clock=%d\n",
586 dev->cfg.clock);
587 ret = -EINVAL;
588 goto err;
589 }
590
591 ret = af9033_wr_regs(dev, 0x800001,
592 coeff_lut[i].val, sizeof(coeff_lut[i].val));
593 }
594
595 /* program frequency control */
596 if (c->bandwidth_hz != dev->bandwidth_hz) {
597 spec_inv = dev->cfg.spec_inv ? -1 : 1;
598
599 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
600 if (clock_adc_lut[i].clock == dev->cfg.clock)
601 break;
602 }
603 if (i == ARRAY_SIZE(clock_adc_lut)) {
604 dev_err(&dev->client->dev,
605 "Couldn't find ADC clock for clock=%d\n",
606 dev->cfg.clock);
607 ret = -EINVAL;
608 goto err;
609 }
610 adc_freq = clock_adc_lut[i].adc;
611
612 /* get used IF frequency */
613 if (fe->ops.tuner_ops.get_if_frequency)
614 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
615 else
616 if_frequency = 0;
617
618 sampling_freq = if_frequency;
619
620 while (sampling_freq > (adc_freq / 2))
621 sampling_freq -= adc_freq;
622
623 if (sampling_freq >= 0)
624 spec_inv *= -1;
625 else
626 sampling_freq *= -1;
627
628 freq_cw = af9033_div(dev, sampling_freq, adc_freq, 23ul);
629
630 if (spec_inv == -1)
631 freq_cw = 0x800000 - freq_cw;
632
633 if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
634 freq_cw /= 2;
635
636 buf[0] = (freq_cw >> 0) & 0xff;
637 buf[1] = (freq_cw >> 8) & 0xff;
638 buf[2] = (freq_cw >> 16) & 0x7f;
639
640 /* FIXME: there seems to be calculation error here... */
641 if (if_frequency == 0)
642 buf[2] = 0;
643
644 ret = af9033_wr_regs(dev, 0x800029, buf, 3);
645 if (ret < 0)
646 goto err;
647
648 dev->bandwidth_hz = c->bandwidth_hz;
649 }
650
651 ret = af9033_wr_reg_mask(dev, 0x80f904, bandwidth_reg_val, 0x03);
652 if (ret < 0)
653 goto err;
654
655 ret = af9033_wr_reg(dev, 0x800040, 0x00);
656 if (ret < 0)
657 goto err;
658
659 ret = af9033_wr_reg(dev, 0x800047, 0x00);
660 if (ret < 0)
661 goto err;
662
663 ret = af9033_wr_reg_mask(dev, 0x80f999, 0x00, 0x01);
664 if (ret < 0)
665 goto err;
666
667 if (c->frequency <= 230000000)
668 tmp = 0x00; /* VHF */
669 else
670 tmp = 0x01; /* UHF */
671
672 ret = af9033_wr_reg(dev, 0x80004b, tmp);
673 if (ret < 0)
674 goto err;
675
676 ret = af9033_wr_reg(dev, 0x800000, 0x00);
677 if (ret < 0)
678 goto err;
679
680 return 0;
681
682 err:
683 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
684
685 return ret;
686 }
687
688 static int af9033_get_frontend(struct dvb_frontend *fe,
689 struct dtv_frontend_properties *c)
690 {
691 struct af9033_dev *dev = fe->demodulator_priv;
692 int ret;
693 u8 buf[8];
694
695 dev_dbg(&dev->client->dev, "\n");
696
697 /* read all needed registers */
698 ret = af9033_rd_regs(dev, 0x80f900, buf, sizeof(buf));
699 if (ret < 0)
700 goto err;
701
702 switch ((buf[0] >> 0) & 3) {
703 case 0:
704 c->transmission_mode = TRANSMISSION_MODE_2K;
705 break;
706 case 1:
707 c->transmission_mode = TRANSMISSION_MODE_8K;
708 break;
709 }
710
711 switch ((buf[1] >> 0) & 3) {
712 case 0:
713 c->guard_interval = GUARD_INTERVAL_1_32;
714 break;
715 case 1:
716 c->guard_interval = GUARD_INTERVAL_1_16;
717 break;
718 case 2:
719 c->guard_interval = GUARD_INTERVAL_1_8;
720 break;
721 case 3:
722 c->guard_interval = GUARD_INTERVAL_1_4;
723 break;
724 }
725
726 switch ((buf[2] >> 0) & 7) {
727 case 0:
728 c->hierarchy = HIERARCHY_NONE;
729 break;
730 case 1:
731 c->hierarchy = HIERARCHY_1;
732 break;
733 case 2:
734 c->hierarchy = HIERARCHY_2;
735 break;
736 case 3:
737 c->hierarchy = HIERARCHY_4;
738 break;
739 }
740
741 switch ((buf[3] >> 0) & 3) {
742 case 0:
743 c->modulation = QPSK;
744 break;
745 case 1:
746 c->modulation = QAM_16;
747 break;
748 case 2:
749 c->modulation = QAM_64;
750 break;
751 }
752
753 switch ((buf[4] >> 0) & 3) {
754 case 0:
755 c->bandwidth_hz = 6000000;
756 break;
757 case 1:
758 c->bandwidth_hz = 7000000;
759 break;
760 case 2:
761 c->bandwidth_hz = 8000000;
762 break;
763 }
764
765 switch ((buf[6] >> 0) & 7) {
766 case 0:
767 c->code_rate_HP = FEC_1_2;
768 break;
769 case 1:
770 c->code_rate_HP = FEC_2_3;
771 break;
772 case 2:
773 c->code_rate_HP = FEC_3_4;
774 break;
775 case 3:
776 c->code_rate_HP = FEC_5_6;
777 break;
778 case 4:
779 c->code_rate_HP = FEC_7_8;
780 break;
781 case 5:
782 c->code_rate_HP = FEC_NONE;
783 break;
784 }
785
786 switch ((buf[7] >> 0) & 7) {
787 case 0:
788 c->code_rate_LP = FEC_1_2;
789 break;
790 case 1:
791 c->code_rate_LP = FEC_2_3;
792 break;
793 case 2:
794 c->code_rate_LP = FEC_3_4;
795 break;
796 case 3:
797 c->code_rate_LP = FEC_5_6;
798 break;
799 case 4:
800 c->code_rate_LP = FEC_7_8;
801 break;
802 case 5:
803 c->code_rate_LP = FEC_NONE;
804 break;
805 }
806
807 return 0;
808
809 err:
810 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
811
812 return ret;
813 }
814
815 static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
816 {
817 struct af9033_dev *dev = fe->demodulator_priv;
818 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
819 int ret, i, tmp = 0;
820 u8 u8tmp, buf[7];
821
822 dev_dbg(&dev->client->dev, "\n");
823
824 *status = 0;
825
826 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
827 ret = af9033_rd_reg(dev, 0x800047, &u8tmp);
828 if (ret < 0)
829 goto err;
830
831 /* has signal */
832 if (u8tmp == 0x01)
833 *status |= FE_HAS_SIGNAL;
834
835 if (u8tmp != 0x02) {
836 /* TPS lock */
837 ret = af9033_rd_reg_mask(dev, 0x80f5a9, &u8tmp, 0x01);
838 if (ret < 0)
839 goto err;
840
841 if (u8tmp)
842 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
843 FE_HAS_VITERBI;
844
845 /* full lock */
846 ret = af9033_rd_reg_mask(dev, 0x80f999, &u8tmp, 0x01);
847 if (ret < 0)
848 goto err;
849
850 if (u8tmp)
851 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
852 FE_HAS_VITERBI | FE_HAS_SYNC |
853 FE_HAS_LOCK;
854 }
855
856 dev->fe_status = *status;
857
858 /* signal strength */
859 if (dev->fe_status & FE_HAS_SIGNAL) {
860 if (dev->is_af9035) {
861 ret = af9033_rd_reg(dev, 0x80004a, &u8tmp);
862 if (ret)
863 goto err;
864 tmp = -u8tmp * 1000;
865 } else {
866 ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp);
867 if (ret)
868 goto err;
869 tmp = (u8tmp - 100) * 1000;
870 }
871
872 c->strength.len = 1;
873 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
874 c->strength.stat[0].svalue = tmp;
875 } else {
876 c->strength.len = 1;
877 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
878 }
879
880 /* CNR */
881 if (dev->fe_status & FE_HAS_VITERBI) {
882 u32 snr_val, snr_lut_size;
883 const struct val_snr *snr_lut = NULL;
884
885 /* read value */
886 ret = af9033_rd_regs(dev, 0x80002c, buf, 3);
887 if (ret)
888 goto err;
889
890 snr_val = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
891
892 /* read superframe number */
893 ret = af9033_rd_reg(dev, 0x80f78b, &u8tmp);
894 if (ret)
895 goto err;
896
897 if (u8tmp)
898 snr_val /= u8tmp;
899
900 /* read current transmission mode */
901 ret = af9033_rd_reg(dev, 0x80f900, &u8tmp);
902 if (ret)
903 goto err;
904
905 switch ((u8tmp >> 0) & 3) {
906 case 0:
907 snr_val *= 4;
908 break;
909 case 1:
910 snr_val *= 1;
911 break;
912 case 2:
913 snr_val *= 2;
914 break;
915 default:
916 snr_val *= 0;
917 break;
918 }
919
920 /* read current modulation */
921 ret = af9033_rd_reg(dev, 0x80f903, &u8tmp);
922 if (ret)
923 goto err;
924
925 switch ((u8tmp >> 0) & 3) {
926 case 0:
927 snr_lut_size = ARRAY_SIZE(qpsk_snr_lut);
928 snr_lut = qpsk_snr_lut;
929 break;
930 case 1:
931 snr_lut_size = ARRAY_SIZE(qam16_snr_lut);
932 snr_lut = qam16_snr_lut;
933 break;
934 case 2:
935 snr_lut_size = ARRAY_SIZE(qam64_snr_lut);
936 snr_lut = qam64_snr_lut;
937 break;
938 default:
939 snr_lut_size = 0;
940 tmp = 0;
941 break;
942 }
943
944 for (i = 0; i < snr_lut_size; i++) {
945 tmp = snr_lut[i].snr * 1000;
946 if (snr_val < snr_lut[i].val)
947 break;
948 }
949
950 c->cnr.len = 1;
951 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
952 c->cnr.stat[0].svalue = tmp;
953 } else {
954 c->cnr.len = 1;
955 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
956 }
957
958 /* UCB/PER/BER */
959 if (dev->fe_status & FE_HAS_LOCK) {
960 /* outer FEC, 204 byte packets */
961 u16 abort_packet_count, rsd_packet_count;
962 /* inner FEC, bits */
963 u32 rsd_bit_err_count;
964
965 /*
966 * Packet count used for measurement is 10000
967 * (rsd_packet_count). Maybe it should be increased?
968 */
969
970 ret = af9033_rd_regs(dev, 0x800032, buf, 7);
971 if (ret)
972 goto err;
973
974 abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
975 rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
976 rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
977
978 dev->error_block_count += abort_packet_count;
979 dev->total_block_count += rsd_packet_count;
980 dev->post_bit_error += rsd_bit_err_count;
981 dev->post_bit_count += rsd_packet_count * 204 * 8;
982
983 c->block_count.len = 1;
984 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
985 c->block_count.stat[0].uvalue = dev->total_block_count;
986
987 c->block_error.len = 1;
988 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
989 c->block_error.stat[0].uvalue = dev->error_block_count;
990
991 c->post_bit_count.len = 1;
992 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
993 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
994
995 c->post_bit_error.len = 1;
996 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
997 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
998 }
999
1000 return 0;
1001
1002 err:
1003 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1004
1005 return ret;
1006 }
1007
1008 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
1009 {
1010 struct af9033_dev *dev = fe->demodulator_priv;
1011 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
1012 int ret;
1013 u8 u8tmp;
1014
1015 /* use DVBv5 CNR */
1016 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
1017 /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
1018 if (dev->is_af9035) {
1019 /* 1000x => 10x (0.1 dB) */
1020 *snr = div_s64(c->cnr.stat[0].svalue, 100);
1021 } else {
1022 /* 1000x => 1x (1 dB) */
1023 *snr = div_s64(c->cnr.stat[0].svalue, 1000);
1024
1025 /* read current modulation */
1026 ret = af9033_rd_reg(dev, 0x80f903, &u8tmp);
1027 if (ret)
1028 goto err;
1029
1030 /* scale value to 0x0000-0xffff */
1031 switch ((u8tmp >> 0) & 3) {
1032 case 0:
1033 *snr = *snr * 0xffff / 23;
1034 break;
1035 case 1:
1036 *snr = *snr * 0xffff / 26;
1037 break;
1038 case 2:
1039 *snr = *snr * 0xffff / 32;
1040 break;
1041 default:
1042 goto err;
1043 }
1044 }
1045 } else {
1046 *snr = 0;
1047 }
1048
1049 return 0;
1050
1051 err:
1052 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1053
1054 return ret;
1055 }
1056
1057 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1058 {
1059 struct af9033_dev *dev = fe->demodulator_priv;
1060 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
1061 int ret, tmp, power_real;
1062 u8 u8tmp, gain_offset, buf[7];
1063
1064 if (dev->is_af9035) {
1065 /* read signal strength of 0-100 scale */
1066 ret = af9033_rd_reg(dev, 0x800048, &u8tmp);
1067 if (ret < 0)
1068 goto err;
1069
1070 /* scale value to 0x0000-0xffff */
1071 *strength = u8tmp * 0xffff / 100;
1072 } else {
1073 ret = af9033_rd_reg(dev, 0x8000f7, &u8tmp);
1074 if (ret < 0)
1075 goto err;
1076
1077 ret = af9033_rd_regs(dev, 0x80f900, buf, 7);
1078 if (ret < 0)
1079 goto err;
1080
1081 if (c->frequency <= 300000000)
1082 gain_offset = 7; /* VHF */
1083 else
1084 gain_offset = 4; /* UHF */
1085
1086 power_real = (u8tmp - 100 - gain_offset) -
1087 power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
1088
1089 if (power_real < -15)
1090 tmp = 0;
1091 else if ((power_real >= -15) && (power_real < 0))
1092 tmp = (2 * (power_real + 15)) / 3;
1093 else if ((power_real >= 0) && (power_real < 20))
1094 tmp = 4 * power_real + 10;
1095 else if ((power_real >= 20) && (power_real < 35))
1096 tmp = (2 * (power_real - 20)) / 3 + 90;
1097 else
1098 tmp = 100;
1099
1100 /* scale value to 0x0000-0xffff */
1101 *strength = tmp * 0xffff / 100;
1102 }
1103
1104 return 0;
1105
1106 err:
1107 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1108
1109 return ret;
1110 }
1111
1112 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
1113 {
1114 struct af9033_dev *dev = fe->demodulator_priv;
1115
1116 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
1117 dev->post_bit_error_prev = dev->post_bit_error;
1118
1119 return 0;
1120 }
1121
1122 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1123 {
1124 struct af9033_dev *dev = fe->demodulator_priv;
1125
1126 *ucblocks = dev->error_block_count;
1127 return 0;
1128 }
1129
1130 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1131 {
1132 struct af9033_dev *dev = fe->demodulator_priv;
1133 int ret;
1134
1135 dev_dbg(&dev->client->dev, "enable=%d\n", enable);
1136
1137 ret = af9033_wr_reg_mask(dev, 0x00fa04, enable, 0x01);
1138 if (ret < 0)
1139 goto err;
1140
1141 return 0;
1142
1143 err:
1144 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1145
1146 return ret;
1147 }
1148
1149 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1150 {
1151 struct af9033_dev *dev = fe->demodulator_priv;
1152 int ret;
1153
1154 dev_dbg(&dev->client->dev, "onoff=%d\n", onoff);
1155
1156 ret = af9033_wr_reg_mask(dev, 0x80f993, onoff, 0x01);
1157 if (ret < 0)
1158 goto err;
1159
1160 return 0;
1161
1162 err:
1163 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1164
1165 return ret;
1166 }
1167
1168 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
1169 int onoff)
1170 {
1171 struct af9033_dev *dev = fe->demodulator_priv;
1172 int ret;
1173 u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
1174
1175 dev_dbg(&dev->client->dev, "index=%d pid=%04x onoff=%d\n",
1176 index, pid, onoff);
1177
1178 if (pid > 0x1fff)
1179 return 0;
1180
1181 ret = af9033_wr_regs(dev, 0x80f996, wbuf, 2);
1182 if (ret < 0)
1183 goto err;
1184
1185 ret = af9033_wr_reg(dev, 0x80f994, onoff);
1186 if (ret < 0)
1187 goto err;
1188
1189 ret = af9033_wr_reg(dev, 0x80f995, index);
1190 if (ret < 0)
1191 goto err;
1192
1193 return 0;
1194
1195 err:
1196 dev_dbg(&dev->client->dev, "failed=%d\n", ret);
1197
1198 return ret;
1199 }
1200
1201 static const struct dvb_frontend_ops af9033_ops = {
1202 .delsys = { SYS_DVBT },
1203 .info = {
1204 .name = "Afatech AF9033 (DVB-T)",
1205 .frequency_min = 174000000,
1206 .frequency_max = 862000000,
1207 .frequency_stepsize = 250000,
1208 .frequency_tolerance = 0,
1209 .caps = FE_CAN_FEC_1_2 |
1210 FE_CAN_FEC_2_3 |
1211 FE_CAN_FEC_3_4 |
1212 FE_CAN_FEC_5_6 |
1213 FE_CAN_FEC_7_8 |
1214 FE_CAN_FEC_AUTO |
1215 FE_CAN_QPSK |
1216 FE_CAN_QAM_16 |
1217 FE_CAN_QAM_64 |
1218 FE_CAN_QAM_AUTO |
1219 FE_CAN_TRANSMISSION_MODE_AUTO |
1220 FE_CAN_GUARD_INTERVAL_AUTO |
1221 FE_CAN_HIERARCHY_AUTO |
1222 FE_CAN_RECOVER |
1223 FE_CAN_MUTE_TS
1224 },
1225
1226 .init = af9033_init,
1227 .sleep = af9033_sleep,
1228
1229 .get_tune_settings = af9033_get_tune_settings,
1230 .set_frontend = af9033_set_frontend,
1231 .get_frontend = af9033_get_frontend,
1232
1233 .read_status = af9033_read_status,
1234 .read_snr = af9033_read_snr,
1235 .read_signal_strength = af9033_read_signal_strength,
1236 .read_ber = af9033_read_ber,
1237 .read_ucblocks = af9033_read_ucblocks,
1238
1239 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1240 };
1241
1242 static int af9033_probe(struct i2c_client *client,
1243 const struct i2c_device_id *id)
1244 {
1245 struct af9033_config *cfg = client->dev.platform_data;
1246 struct af9033_dev *dev;
1247 int ret;
1248 u8 buf[8];
1249 u32 reg;
1250
1251 /* allocate memory for the internal state */
1252 dev = kzalloc(sizeof(struct af9033_dev), GFP_KERNEL);
1253 if (dev == NULL) {
1254 ret = -ENOMEM;
1255 dev_err(&client->dev, "Could not allocate memory for state\n");
1256 goto err;
1257 }
1258
1259 /* setup the state */
1260 dev->client = client;
1261 memcpy(&dev->cfg, cfg, sizeof(struct af9033_config));
1262
1263 if (dev->cfg.clock != 12000000) {
1264 ret = -ENODEV;
1265 dev_err(&dev->client->dev,
1266 "unsupported clock %d Hz, only 12000000 Hz is supported currently\n",
1267 dev->cfg.clock);
1268 goto err_kfree;
1269 }
1270
1271 /* firmware version */
1272 switch (dev->cfg.tuner) {
1273 case AF9033_TUNER_IT9135_38:
1274 case AF9033_TUNER_IT9135_51:
1275 case AF9033_TUNER_IT9135_52:
1276 case AF9033_TUNER_IT9135_60:
1277 case AF9033_TUNER_IT9135_61:
1278 case AF9033_TUNER_IT9135_62:
1279 dev->is_it9135 = true;
1280 reg = 0x004bfc;
1281 break;
1282 default:
1283 dev->is_af9035 = true;
1284 reg = 0x0083e9;
1285 break;
1286 }
1287
1288 ret = af9033_rd_regs(dev, reg, &buf[0], 4);
1289 if (ret < 0)
1290 goto err_kfree;
1291
1292 ret = af9033_rd_regs(dev, 0x804191, &buf[4], 4);
1293 if (ret < 0)
1294 goto err_kfree;
1295
1296 dev_info(&dev->client->dev,
1297 "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1298 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
1299 buf[7]);
1300
1301 /* sleep */
1302 switch (dev->cfg.tuner) {
1303 case AF9033_TUNER_IT9135_38:
1304 case AF9033_TUNER_IT9135_51:
1305 case AF9033_TUNER_IT9135_52:
1306 case AF9033_TUNER_IT9135_60:
1307 case AF9033_TUNER_IT9135_61:
1308 case AF9033_TUNER_IT9135_62:
1309 /* IT9135 did not like to sleep at that early */
1310 break;
1311 default:
1312 ret = af9033_wr_reg(dev, 0x80004c, 1);
1313 if (ret < 0)
1314 goto err_kfree;
1315
1316 ret = af9033_wr_reg(dev, 0x800000, 0);
1317 if (ret < 0)
1318 goto err_kfree;
1319 }
1320
1321 /* configure internal TS mode */
1322 switch (dev->cfg.ts_mode) {
1323 case AF9033_TS_MODE_PARALLEL:
1324 dev->ts_mode_parallel = true;
1325 break;
1326 case AF9033_TS_MODE_SERIAL:
1327 dev->ts_mode_serial = true;
1328 break;
1329 case AF9033_TS_MODE_USB:
1330 /* usb mode for AF9035 */
1331 default:
1332 break;
1333 }
1334
1335 /* create dvb_frontend */
1336 memcpy(&dev->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
1337 dev->fe.demodulator_priv = dev;
1338 *cfg->fe = &dev->fe;
1339 if (cfg->ops) {
1340 cfg->ops->pid_filter = af9033_pid_filter;
1341 cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
1342 }
1343 i2c_set_clientdata(client, dev);
1344
1345 dev_info(&dev->client->dev, "Afatech AF9033 successfully attached\n");
1346 return 0;
1347 err_kfree:
1348 kfree(dev);
1349 err:
1350 dev_dbg(&client->dev, "failed=%d\n", ret);
1351 return ret;
1352 }
1353
1354 static int af9033_remove(struct i2c_client *client)
1355 {
1356 struct af9033_dev *dev = i2c_get_clientdata(client);
1357
1358 dev_dbg(&dev->client->dev, "\n");
1359
1360 dev->fe.ops.release = NULL;
1361 dev->fe.demodulator_priv = NULL;
1362 kfree(dev);
1363
1364 return 0;
1365 }
1366
1367 static const struct i2c_device_id af9033_id_table[] = {
1368 {"af9033", 0},
1369 {}
1370 };
1371 MODULE_DEVICE_TABLE(i2c, af9033_id_table);
1372
1373 static struct i2c_driver af9033_driver = {
1374 .driver = {
1375 .name = "af9033",
1376 .suppress_bind_attrs = true,
1377 },
1378 .probe = af9033_probe,
1379 .remove = af9033_remove,
1380 .id_table = af9033_id_table,
1381 };
1382
1383 module_i2c_driver(af9033_driver);
1384
1385 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1386 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1387 MODULE_LICENSE("GPL");
Linux with added FPC-III support