drivers/media/dvb-frontends/au8522_decoder.c

   1 /*
   2  * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
   3  *
   4  * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
   5  * Copyright (C) 2005-2008 Auvitek International, Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * As published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA.
  21  */
  22
  23 /* Developer notes:
  24  *
  25  * VBI support is not yet working
  26  * Enough is implemented here for CVBS and S-Video inputs, but the actual
  27  *  analog demodulator code isn't implemented (not needed for xc5000 since it
  28  *  has its own demodulator and outputs CVBS)
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/slab.h>
  34 #include <linux/videodev2.h>
  35 #include <linux/i2c.h>
  36 #include <linux/delay.h>
  37 #include <media/v4l2-common.h>
  38 #include <media/v4l2-device.h>
  39 #include "au8522.h"
  40 #include "au8522_priv.h"
  41
  42 MODULE_AUTHOR("Devin Heitmueller");
  43 MODULE_LICENSE("GPL");
  44
  45 static int au8522_analog_debug;
  46
  47
  48 module_param_named(analog_debug, au8522_analog_debug, int, 0644);
  49
  50 MODULE_PARM_DESC(analog_debug,
  51                  "Analog debugging messages [0=Off (default) 1=On]");
  52
  53 struct au8522_register_config {
  54         u16 reg_name;
  55         u8 reg_val[8];
  56 };
  57
  58
  59 /* Video Decoder Filter Coefficients
  60    The values are as follows from left to right
  61    0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
  62 */
  63 static const struct au8522_register_config filter_coef[] = {
  64         {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
  65         {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
  66         {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
  67         {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
  68         {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
  69         {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
  70         {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
  71         {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
  72         {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
  73         {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
  74         {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
  75         {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
  76         {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
  77         {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
  78         {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
  79         {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
  80         {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
  81         {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
  82         {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
  83         {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
  84         {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
  85         {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
  86         {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
  87         {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
  88         {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
  89         {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
  90         {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
  91         {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
  92         {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
  93         {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
  94
  95 };
  96 #define NUM_FILTER_COEF (sizeof(filter_coef)\
  97                          / sizeof(struct au8522_register_config))
  98
  99
 100 /* Registers 0x060b through 0x0652 are the LP Filter coefficients
 101    The values are as follows from left to right
 102    0="SIF" 1="ATVRF/ATVRF13"
 103    Note: the "ATVRF/ATVRF13" mode has never been tested
 104 */
 105 static const struct au8522_register_config lpfilter_coef[] = {
 106         {0x060b, {0x21, 0x0b} },
 107         {0x060c, {0xad, 0xad} },
 108         {0x060d, {0x70, 0xf0} },
 109         {0x060e, {0xea, 0xe9} },
 110         {0x060f, {0xdd, 0xdd} },
 111         {0x0610, {0x08, 0x64} },
 112         {0x0611, {0x60, 0x60} },
 113         {0x0612, {0xf8, 0xb2} },
 114         {0x0613, {0x01, 0x02} },
 115         {0x0614, {0xe4, 0xb4} },
 116         {0x0615, {0x19, 0x02} },
 117         {0x0616, {0xae, 0x2e} },
 118         {0x0617, {0xee, 0xc5} },
 119         {0x0618, {0x56, 0x56} },
 120         {0x0619, {0x30, 0x58} },
 121         {0x061a, {0xf9, 0xf8} },
 122         {0x061b, {0x24, 0x64} },
 123         {0x061c, {0x07, 0x07} },
 124         {0x061d, {0x30, 0x30} },
 125         {0x061e, {0xa9, 0xed} },
 126         {0x061f, {0x09, 0x0b} },
 127         {0x0620, {0x42, 0xc2} },
 128         {0x0621, {0x1d, 0x2a} },
 129         {0x0622, {0xd6, 0x56} },
 130         {0x0623, {0x95, 0x8b} },
 131         {0x0624, {0x2b, 0x2b} },
 132         {0x0625, {0x30, 0x24} },
 133         {0x0626, {0x3e, 0x3e} },
 134         {0x0627, {0x62, 0xe2} },
 135         {0x0628, {0xe9, 0xf5} },
 136         {0x0629, {0x99, 0x19} },
 137         {0x062a, {0xd4, 0x11} },
 138         {0x062b, {0x03, 0x04} },
 139         {0x062c, {0xb5, 0x85} },
 140         {0x062d, {0x1e, 0x20} },
 141         {0x062e, {0x2a, 0xea} },
 142         {0x062f, {0xd7, 0xd2} },
 143         {0x0630, {0x15, 0x15} },
 144         {0x0631, {0xa3, 0xa9} },
 145         {0x0632, {0x1f, 0x1f} },
 146         {0x0633, {0xf9, 0xd1} },
 147         {0x0634, {0xc0, 0xc3} },
 148         {0x0635, {0x4d, 0x8d} },
 149         {0x0636, {0x21, 0x31} },
 150         {0x0637, {0x83, 0x83} },
 151         {0x0638, {0x08, 0x8c} },
 152         {0x0639, {0x19, 0x19} },
 153         {0x063a, {0x45, 0xa5} },
 154         {0x063b, {0xef, 0xec} },
 155         {0x063c, {0x8a, 0x8a} },
 156         {0x063d, {0xf4, 0xf6} },
 157         {0x063e, {0x8f, 0x8f} },
 158         {0x063f, {0x44, 0x0c} },
 159         {0x0640, {0xef, 0xf0} },
 160         {0x0641, {0x66, 0x66} },
 161         {0x0642, {0xcc, 0xd2} },
 162         {0x0643, {0x41, 0x41} },
 163         {0x0644, {0x63, 0x93} },
 164         {0x0645, {0x8e, 0x8e} },
 165         {0x0646, {0xa2, 0x42} },
 166         {0x0647, {0x7b, 0x7b} },
 167         {0x0648, {0x04, 0x04} },
 168         {0x0649, {0x00, 0x00} },
 169         {0x064a, {0x40, 0x40} },
 170         {0x064b, {0x8c, 0x98} },
 171         {0x064c, {0x00, 0x00} },
 172         {0x064d, {0x63, 0xc3} },
 173         {0x064e, {0x04, 0x04} },
 174         {0x064f, {0x20, 0x20} },
 175         {0x0650, {0x00, 0x00} },
 176         {0x0651, {0x40, 0x40} },
 177         {0x0652, {0x01, 0x01} },
 178 };
 179 #define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
 180                            / sizeof(struct au8522_register_config))
 181
 182 static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
 183 {
 184         return container_of(sd, struct au8522_state, sd);
 185 }
 186
 187 static void setup_vbi(struct au8522_state *state, int aud_input)
 188 {
 189         int i;
 190
 191         /* These are set to zero regardless of what mode we're in */
 192         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
 193         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
 194         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
 195         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
 196         au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
 197         au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
 198         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
 199         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
 200         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
 201         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
 202                         0x00);
 203         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
 204                         0x00);
 205         au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
 206                         0x00);
 207
 208         /* Setup the VBI registers */
 209         for (i = 0x30; i < 0x60; i++)
 210                 au8522_writereg(state, i, 0x40);
 211
 212         /* For some reason, every register is 0x40 except register 0x44
 213            (confirmed via the HVR-950q USB capture) */
 214         au8522_writereg(state, 0x44, 0x60);
 215
 216         /* Enable VBI (we always do this regardless of whether the user is
 217            viewing closed caption info) */
 218         au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
 219                         AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON);
 220
 221 }
 222
 223 static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
 224 {
 225         int i;
 226         int filter_coef_type;
 227
 228         /* Provide reasonable defaults for picture tuning values */
 229         au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
 230         au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
 231         au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
 232         au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
 233         au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
 234         au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
 235         au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
 236
 237         /* Other decoder registers */
 238         au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
 239
 240         if (is_svideo)
 241                 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
 242         else
 243                 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
 244
 245         au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
 246                         AU8522_TVDEC_PGA_REG012H_CVBS);
 247         au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
 248                         AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
 249         au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
 250                         AU8522_TVDED_DBG_MODE_REG060H_CVBS);
 251
 252         if (state->std == V4L2_STD_PAL_M) {
 253                 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
 254                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
 255                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
 256                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
 257                 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
 258                                 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
 259         } else {
 260                 /* NTSC */
 261                 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
 262                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
 263                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
 264                                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
 265                 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
 266                                 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
 267         }
 268         au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
 269                         AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
 270         au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
 271                         AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
 272         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
 273                         AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
 274         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
 275                         AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
 276         au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
 277                         AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
 278         au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
 279                         AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
 280         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
 281                         AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
 282         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
 283                         AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
 284         au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
 285                         AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
 286         if (is_svideo) {
 287                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 288                                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
 289                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 290                                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
 291         } else {
 292                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
 293                                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
 294                 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
 295                                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
 296         }
 297         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
 298                         AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
 299         au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
 300                         AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
 301         au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
 302                         AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
 303         au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
 304         au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
 305         au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
 306                         AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
 307         au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
 308         au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
 309         au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
 310                         AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
 311         au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
 312                         AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
 313         au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
 314                         AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
 315         au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
 316                         AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
 317         au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
 318                         AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
 319         au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
 320                         AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
 321         au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
 322                         AU8522_TOREGAAGC_REG0E5H_CVBS);
 323         au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
 324
 325         setup_vbi(state, 0);
 326
 327         if (is_svideo) {
 328                 /* Despite what the table says, for the HVR-950q we still need
 329                    to be in CVBS mode for the S-Video input (reason unknown). */
 330                 /* filter_coef_type = 3; */
 331                 filter_coef_type = 5;
 332         } else {
 333                 filter_coef_type = 5;
 334         }
 335
 336         /* Load the Video Decoder Filter Coefficients */
 337         for (i = 0; i < NUM_FILTER_COEF; i++) {
 338                 au8522_writereg(state, filter_coef[i].reg_name,
 339                                 filter_coef[i].reg_val[filter_coef_type]);
 340         }
 341
 342         /* It's not clear what these registers are for, but they are always
 343            set to the same value regardless of what mode we're in */
 344         au8522_writereg(state, AU8522_REG42EH, 0x87);
 345         au8522_writereg(state, AU8522_REG42FH, 0xa2);
 346         au8522_writereg(state, AU8522_REG430H, 0xbf);
 347         au8522_writereg(state, AU8522_REG431H, 0xcb);
 348         au8522_writereg(state, AU8522_REG432H, 0xa1);
 349         au8522_writereg(state, AU8522_REG433H, 0x41);
 350         au8522_writereg(state, AU8522_REG434H, 0x88);
 351         au8522_writereg(state, AU8522_REG435H, 0xc2);
 352         au8522_writereg(state, AU8522_REG436H, 0x3c);
 353 }
 354
 355 static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
 356 {
 357         /* here we're going to try the pre-programmed route */
 358         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 359                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 360
 361         /* PGA in automatic mode */
 362         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 363
 364         /* Enable clamping control */
 365         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 366
 367         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
 368
 369         setup_decoder_defaults(state, false);
 370
 371         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 372                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 373 }
 374
 375 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
 376                                          u8 input_mode)
 377 {
 378         /* here we're going to try the pre-programmed route */
 379         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 380                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
 381
 382         /* It's not clear why we have to have the PGA in automatic mode while
 383            enabling clamp control, but it's what Windows does */
 384         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 385
 386         /* Enable clamping control */
 387         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
 388
 389         /* Disable automatic PGA (since the CVBS is coming from the tuner) */
 390         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
 391
 392         /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
 393         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
 394
 395         setup_decoder_defaults(state, false);
 396
 397         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 398                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 399 }
 400
 401 static void au8522_setup_svideo_mode(struct au8522_state *state,
 402                                      u8 input_mode)
 403 {
 404         au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
 405                         AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
 406
 407         /* Set input to Y on Channe1, C on Channel 3 */
 408         au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
 409
 410         /* PGA in automatic mode */
 411         au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
 412
 413         /* Enable clamping control */
 414         au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
 415
 416         setup_decoder_defaults(state, true);
 417
 418         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 419                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 420 }
 421
 422 /* ----------------------------------------------------------------------- */
 423
 424 static void disable_audio_input(struct au8522_state *state)
 425 {
 426         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 427         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 428         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 429
 430         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
 431         au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
 432
 433         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 434                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
 435 }
 436
 437 /* 0=disable, 1=SIF */
 438 static void set_audio_input(struct au8522_state *state)
 439 {
 440         int aud_input = state->aud_input;
 441         int i;
 442
 443         /* Note that this function needs to be used in conjunction with setting
 444            the input routing via register 0x81 */
 445
 446         if (aud_input == AU8522_AUDIO_NONE) {
 447                 disable_audio_input(state);
 448                 return;
 449         }
 450
 451         if (aud_input != AU8522_AUDIO_SIF) {
 452                 /* The caller asked for a mode we don't currently support */
 453                 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
 454                        aud_input);
 455                 return;
 456         }
 457
 458         /* Load the Audio Decoder Filter Coefficients */
 459         for (i = 0; i < NUM_LPFILTER_COEF; i++) {
 460                 au8522_writereg(state, lpfilter_coef[i].reg_name,
 461                                 lpfilter_coef[i].reg_val[0]);
 462         }
 463
 464         /* Setup audio */
 465         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
 466         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
 467         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
 468         au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
 469         au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
 470         msleep(150);
 471         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
 472         msleep(10);
 473         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 474                         AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
 475         msleep(50);
 476         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 477         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 478         au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
 479         msleep(80);
 480         au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
 481         au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
 482         au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
 483         au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
 484         msleep(70);
 485         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
 486         au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
 487         au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
 488 }
 489
 490 /* ----------------------------------------------------------------------- */
 491
 492 static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
 493 {
 494         struct au8522_state *state =
 495                 container_of(ctrl->handler, struct au8522_state, hdl);
 496
 497         switch (ctrl->id) {
 498         case V4L2_CID_BRIGHTNESS:
 499                 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
 500                                 ctrl->val - 128);
 501                 break;
 502         case V4L2_CID_CONTRAST:
 503                 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
 504                                 ctrl->val);
 505                 break;
 506         case V4L2_CID_SATURATION:
 507                 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
 508                                 ctrl->val);
 509                 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
 510                                 ctrl->val);
 511                 break;
 512         case V4L2_CID_HUE:
 513                 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
 514                                 ctrl->val >> 8);
 515                 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
 516                                 ctrl->val & 0xFF);
 517                 break;
 518         default:
 519                 return -EINVAL;
 520         }
 521
 522         return 0;
 523 }
 524
 525 /* ----------------------------------------------------------------------- */
 526
 527 #ifdef CONFIG_VIDEO_ADV_DEBUG
 528 static int au8522_g_register(struct v4l2_subdev *sd,
 529                              struct v4l2_dbg_register *reg)
 530 {
 531         struct au8522_state *state = to_state(sd);
 532
 533         reg->val = au8522_readreg(state, reg->reg & 0xffff);
 534         return 0;
 535 }
 536
 537 static int au8522_s_register(struct v4l2_subdev *sd,
 538                              const struct v4l2_dbg_register *reg)
 539 {
 540         struct au8522_state *state = to_state(sd);
 541
 542         au8522_writereg(state, reg->reg, reg->val & 0xff);
 543         return 0;
 544 }
 545 #endif
 546
 547 static void au8522_video_set(struct au8522_state *state)
 548 {
 549         u8 input_mode;
 550
 551         au8522_writereg(state, 0xa4, 1 << 5);
 552
 553         switch (state->vid_input) {
 554         case AU8522_COMPOSITE_CH1:
 555                 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
 556                 au8522_setup_cvbs_mode(state, input_mode);
 557                 break;
 558         case AU8522_COMPOSITE_CH2:
 559                 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
 560                 au8522_setup_cvbs_mode(state, input_mode);
 561                 break;
 562         case AU8522_COMPOSITE_CH3:
 563                 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
 564                 au8522_setup_cvbs_mode(state, input_mode);
 565                 break;
 566         case AU8522_COMPOSITE_CH4:
 567                 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
 568                 au8522_setup_cvbs_mode(state, input_mode);
 569                 break;
 570         case AU8522_SVIDEO_CH13:
 571                 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
 572                 au8522_setup_svideo_mode(state, input_mode);
 573                 break;
 574         case AU8522_SVIDEO_CH24:
 575                 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
 576                 au8522_setup_svideo_mode(state, input_mode);
 577                 break;
 578         default:
 579         case AU8522_COMPOSITE_CH4_SIF:
 580                 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
 581                 au8522_setup_cvbs_tuner_mode(state, input_mode);
 582                 break;
 583         }
 584 }
 585
 586 static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
 587 {
 588         struct au8522_state *state = to_state(sd);
 589
 590         if (enable) {
 591                 /*
 592                  * Clear out any state associated with the digital side of the
 593                  * chip, so that when it gets powered back up it won't think
 594                  * that it is already tuned
 595                  */
 596                 state->current_frequency = 0;
 597
 598                 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 599                                 0x01);
 600                 msleep(10);
 601
 602                 au8522_video_set(state);
 603                 set_audio_input(state);
 604
 605                 state->operational_mode = AU8522_ANALOG_MODE;
 606         } else {
 607                 /* This does not completely power down the device
 608                    (it only reduces it from around 140ma to 80ma) */
 609                 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
 610                                 1 << 5);
 611                 state->operational_mode = AU8522_SUSPEND_MODE;
 612         }
 613         return 0;
 614 }
 615
 616 static int au8522_s_video_routing(struct v4l2_subdev *sd,
 617                                         u32 input, u32 output, u32 config)
 618 {
 619         struct au8522_state *state = to_state(sd);
 620
 621         switch(input) {
 622         case AU8522_COMPOSITE_CH1:
 623         case AU8522_SVIDEO_CH13:
 624         case AU8522_COMPOSITE_CH4_SIF:
 625                 state->vid_input = input;
 626                 break;
 627         default:
 628                 printk(KERN_ERR "au8522 mode not currently supported\n");
 629                 return -EINVAL;
 630         }
 631
 632         if (state->operational_mode == AU8522_ANALOG_MODE)
 633                 au8522_video_set(state);
 634
 635         return 0;
 636 }
 637
 638 static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
 639 {
 640         struct au8522_state *state = to_state(sd);
 641
 642         if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
 643                 return -EINVAL;
 644
 645         state->std = std;
 646
 647         if (state->operational_mode == AU8522_ANALOG_MODE)
 648                 au8522_video_set(state);
 649
 650         return 0;
 651 }
 652
 653 static int au8522_s_audio_routing(struct v4l2_subdev *sd,
 654                                         u32 input, u32 output, u32 config)
 655 {
 656         struct au8522_state *state = to_state(sd);
 657
 658         state->aud_input = input;
 659
 660         if (state->operational_mode == AU8522_ANALOG_MODE)
 661                 set_audio_input(state);
 662
 663         return 0;
 664 }
 665
 666 static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
 667 {
 668         int val = 0;
 669         struct au8522_state *state = to_state(sd);
 670         u8 lock_status;
 671
 672         /* Interrogate the decoder to see if we are getting a real signal */
 673         lock_status = au8522_readreg(state, 0x00);
 674         if (lock_status == 0xa2)
 675                 vt->signal = 0xffff;
 676         else
 677                 vt->signal = 0x00;
 678
 679         vt->capability |=
 680                 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
 681                 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
 682
 683         val = V4L2_TUNER_SUB_MONO;
 684         vt->rxsubchans = val;
 685         vt->audmode = V4L2_TUNER_MODE_STEREO;
 686         return 0;
 687 }
 688
 689 /* ----------------------------------------------------------------------- */
 690
 691 static const struct v4l2_subdev_core_ops au8522_core_ops = {
 692         .log_status = v4l2_ctrl_subdev_log_status,
 693 #ifdef CONFIG_VIDEO_ADV_DEBUG
 694         .g_register = au8522_g_register,
 695         .s_register = au8522_s_register,
 696 #endif
 697 };
 698
 699 static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
 700         .g_tuner = au8522_g_tuner,
 701 };
 702
 703 static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
 704         .s_routing = au8522_s_audio_routing,
 705 };
 706
 707 static const struct v4l2_subdev_video_ops au8522_video_ops = {
 708         .s_routing = au8522_s_video_routing,
 709         .s_stream = au8522_s_stream,
 710         .s_std = au8522_s_std,
 711 };
 712
 713 static const struct v4l2_subdev_ops au8522_ops = {
 714         .core = &au8522_core_ops,
 715         .tuner = &au8522_tuner_ops,
 716         .audio = &au8522_audio_ops,
 717         .video = &au8522_video_ops,
 718 };
 719
 720 static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
 721         .s_ctrl = au8522_s_ctrl,
 722 };
 723
 724 /* ----------------------------------------------------------------------- */
 725
 726 static int au8522_probe(struct i2c_client *client,
 727                         const struct i2c_device_id *did)
 728 {
 729         struct au8522_state *state;
 730         struct v4l2_ctrl_handler *hdl;
 731         struct v4l2_subdev *sd;
 732         int instance;
 733 #ifdef CONFIG_MEDIA_CONTROLLER
 734         int ret;
 735 #endif
 736
 737         /* Check if the adapter supports the needed features */
 738         if (!i2c_check_functionality(client->adapter,
 739                                      I2C_FUNC_SMBUS_BYTE_DATA)) {
 740                 return -EIO;
 741         }
 742
 743         /* allocate memory for the internal state */
 744         instance = au8522_get_state(&state, client->adapter, client->addr);
 745         switch (instance) {
 746         case 0:
 747                 printk(KERN_ERR "au8522_decoder allocation failed\n");
 748                 return -EIO;
 749         case 1:
 750                 /* new demod instance */
 751                 printk(KERN_INFO "au8522_decoder creating new instance...\n");
 752                 break;
 753         default:
 754                 /* existing demod instance */
 755                 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
 756                 break;
 757         }
 758
 759         state->config.demod_address = 0x8e >> 1;
 760         state->i2c = client->adapter;
 761
 762         sd = &state->sd;
 763         v4l2_i2c_subdev_init(sd, client, &au8522_ops);
 764 #if defined(CONFIG_MEDIA_CONTROLLER)
 765
 766         state->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
 767         state->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
 768         state->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
 769         state->pads[DEMOD_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
 770         sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
 771
 772         ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
 773                                 state->pads);
 774         if (ret < 0) {
 775                 v4l_info(client, "failed to initialize media entity!\n");
 776                 return ret;
 777         }
 778 #endif
 779
 780         hdl = &state->hdl;
 781         v4l2_ctrl_handler_init(hdl, 4);
 782         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 783                         V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
 784         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 785                         V4L2_CID_CONTRAST, 0, 255, 1,
 786                         AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
 787         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 788                         V4L2_CID_SATURATION, 0, 255, 1, 128);
 789         v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
 790                         V4L2_CID_HUE, -32768, 32767, 1, 0);
 791         sd->ctrl_handler = hdl;
 792         if (hdl->error) {
 793                 int err = hdl->error;
 794
 795                 v4l2_ctrl_handler_free(hdl);
 796                 au8522_release_state(state);
 797                 return err;
 798         }
 799
 800         state->c = client;
 801         state->std = V4L2_STD_NTSC_M;
 802         state->vid_input = AU8522_COMPOSITE_CH1;
 803         state->aud_input = AU8522_AUDIO_NONE;
 804         state->id = 8522;
 805         state->rev = 0;
 806
 807         /* Jam open the i2c gate to the tuner */
 808         au8522_writereg(state, 0x106, 1);
 809
 810         return 0;
 811 }
 812
 813 static int au8522_remove(struct i2c_client *client)
 814 {
 815         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 816         v4l2_device_unregister_subdev(sd);
 817         v4l2_ctrl_handler_free(sd->ctrl_handler);
 818         au8522_release_state(to_state(sd));
 819         return 0;
 820 }
 821
 822 static const struct i2c_device_id au8522_id[] = {
 823         {"au8522", 0},
 824         {}
 825 };
 826
 827 MODULE_DEVICE_TABLE(i2c, au8522_id);
 828
 829 static struct i2c_driver au8522_driver = {
 830         .driver = {
 831                 .name   = "au8522",
 832         },
 833         .probe          = au8522_probe,
 834         .remove         = au8522_remove,
 835         .id_table       = au8522_id,
 836 };
 837
 838 module_i2c_driver(au8522_driver);