drivers/media/dvb-frontends/au8522_priv.h

   1 /*
   2     Auvitek AU8522 QAM/8VSB demodulator driver
   3
   4     Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
   5     Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
   6     Copyright (C) 2005-2008 Auvitek International, Ltd.
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/string.h>
  28 #include <linux/slab.h>
  29 #include <linux/delay.h>
  30 #include <linux/videodev2.h>
  31 #include <media/v4l2-device.h>
  32 #include <media/v4l2-ctrls.h>
  33 #include <media/v4l2-mc.h>
  34 #include <linux/i2c.h>
  35 #include "dvb_frontend.h"
  36 #include "au8522.h"
  37 #include "tuner-i2c.h"
  38
  39 #define AU8522_ANALOG_MODE 0
  40 #define AU8522_DIGITAL_MODE 1
  41 #define AU8522_SUSPEND_MODE 2
  42
  43 struct au8522_state {
  44         struct i2c_client *c;
  45         struct i2c_adapter *i2c;
  46
  47         u8 operational_mode;
  48
  49         /* Used for sharing of the state between analog and digital mode */
  50         struct tuner_i2c_props i2c_props;
  51         struct list_head hybrid_tuner_instance_list;
  52
  53         /* configuration settings */
  54         struct au8522_config config;
  55
  56         struct dvb_frontend frontend;
  57
  58         u32 current_frequency;
  59         enum fe_modulation current_modulation;
  60
  61         u32 fe_status;
  62         unsigned int led_state;
  63
  64         /* Analog settings */
  65         struct v4l2_subdev sd;
  66         v4l2_std_id std;
  67         int vid_input;
  68         int aud_input;
  69         u32 id;
  70         u32 rev;
  71         struct v4l2_ctrl_handler hdl;
  72
  73 #ifdef CONFIG_MEDIA_CONTROLLER
  74         struct media_pad pads[DEMOD_NUM_PADS];
  75 #endif
  76 };
  77
  78 /* These are routines shared by both the VSB/QAM demodulator and the analog
  79    decoder */
  80 int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);
  81 u8 au8522_readreg(struct au8522_state *state, u16 reg);
  82 int au8522_init(struct dvb_frontend *fe);
  83 int au8522_sleep(struct dvb_frontend *fe);
  84
  85 int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
  86                      u8 client_address);
  87 void au8522_release_state(struct au8522_state *state);
  88 int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
  89 int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
  90 int au8522_led_ctrl(struct au8522_state *state, int led);
  91
  92 /* REGISTERS */
  93 #define AU8522_INPUT_CONTROL_REG081H                    0x081
  94 #define AU8522_PGA_CONTROL_REG082H                      0x082
  95 #define AU8522_CLAMPING_CONTROL_REG083H                 0x083
  96
  97 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H             0x0A3
  98 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H          0x0A4
  99 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H          0x0A5
 100 #define AU8522_AGC_CONTROL_RANGE_REG0A6H                0x0A6
 101 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H              0x0A7
 102 #define AU8522_TUNER_AGC_RF_STOP_REG0A8H                0x0A8
 103 #define AU8522_TUNER_AGC_RF_START_REG0A9H               0x0A9
 104 #define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH             0x0AA
 105 #define AU8522_TUNER_AGC_IF_STOP_REG0ABH                0x0AB
 106 #define AU8522_TUNER_AGC_IF_START_REG0ACH               0x0AC
 107 #define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH             0x0AD
 108 #define AU8522_TUNER_AGC_STEP_REG0AEH                   0x0AE
 109 #define AU8522_TUNER_GAIN_STEP_REG0AFH                  0x0AF
 110
 111 /* Receiver registers */
 112 #define AU8522_FRMREGTHRD1_REG0B0H                      0x0B0
 113 #define AU8522_FRMREGAGC1H_REG0B1H                      0x0B1
 114 #define AU8522_FRMREGSHIFT1_REG0B2H                     0x0B2
 115 #define AU8522_TOREGAGC1_REG0B3H                        0x0B3
 116 #define AU8522_TOREGASHIFT1_REG0B4H                     0x0B4
 117 #define AU8522_FRMREGBBH_REG0B5H                        0x0B5
 118 #define AU8522_FRMREGBBM_REG0B6H                        0x0B6
 119 #define AU8522_FRMREGBBL_REG0B7H                        0x0B7
 120 /* 0xB8 TO 0xD7 are the filter coefficients */
 121 #define AU8522_FRMREGTHRD2_REG0D8H                      0x0D8
 122 #define AU8522_FRMREGAGC2H_REG0D9H                      0x0D9
 123 #define AU8522_TOREGAGC2_REG0DAH                        0x0DA
 124 #define AU8522_TOREGSHIFT2_REG0DBH                      0x0DB
 125 #define AU8522_FRMREGPILOTH_REG0DCH                     0x0DC
 126 #define AU8522_FRMREGPILOTM_REG0DDH                     0x0DD
 127 #define AU8522_FRMREGPILOTL_REG0DEH                     0x0DE
 128 #define AU8522_TOREGFREQ_REG0DFH                        0x0DF
 129
 130 #define AU8522_RX_PGA_RFOUT_REG0EBH                     0x0EB
 131 #define AU8522_RX_PGA_IFOUT_REG0ECH                     0x0EC
 132 #define AU8522_RX_PGA_PGAOUT_REG0EDH                    0x0ED
 133
 134 #define AU8522_CHIP_MODE_REG0FEH                        0x0FE
 135
 136 /* I2C bus control registers */
 137 #define AU8522_I2C_CONTROL_REG0_REG090H                 0x090
 138 #define AU8522_I2C_CONTROL_REG1_REG091H                 0x091
 139 #define AU8522_I2C_STATUS_REG092H                       0x092
 140 #define AU8522_I2C_WR_DATA0_REG093H                     0x093
 141 #define AU8522_I2C_WR_DATA1_REG094H                     0x094
 142 #define AU8522_I2C_WR_DATA2_REG095H                     0x095
 143 #define AU8522_I2C_WR_DATA3_REG096H                     0x096
 144 #define AU8522_I2C_WR_DATA4_REG097H                     0x097
 145 #define AU8522_I2C_WR_DATA5_REG098H                     0x098
 146 #define AU8522_I2C_WR_DATA6_REG099H                     0x099
 147 #define AU8522_I2C_WR_DATA7_REG09AH                     0x09A
 148 #define AU8522_I2C_RD_DATA0_REG09BH                     0x09B
 149 #define AU8522_I2C_RD_DATA1_REG09CH                     0x09C
 150 #define AU8522_I2C_RD_DATA2_REG09DH                     0x09D
 151 #define AU8522_I2C_RD_DATA3_REG09EH                     0x09E
 152 #define AU8522_I2C_RD_DATA4_REG09FH                     0x09F
 153 #define AU8522_I2C_RD_DATA5_REG0A0H                     0x0A0
 154 #define AU8522_I2C_RD_DATA6_REG0A1H                     0x0A1
 155 #define AU8522_I2C_RD_DATA7_REG0A2H                     0x0A2
 156
 157 #define AU8522_ENA_USB_REG101H                          0x101
 158
 159 #define AU8522_I2S_CTRL_0_REG110H                       0x110
 160 #define AU8522_I2S_CTRL_1_REG111H                       0x111
 161 #define AU8522_I2S_CTRL_2_REG112H                       0x112
 162
 163 #define AU8522_FRMREGFFECONTROL_REG121H                 0x121
 164 #define AU8522_FRMREGDFECONTROL_REG122H                 0x122
 165
 166 #define AU8522_CARRFREQOFFSET0_REG201H                  0x201
 167 #define AU8522_CARRFREQOFFSET1_REG202H                  0x202
 168
 169 #define AU8522_DECIMATION_GAIN_REG21AH                  0x21A
 170 #define AU8522_FRMREGIFSLP_REG21BH                      0x21B
 171 #define AU8522_FRMREGTHRDL2_REG21CH                     0x21C
 172 #define AU8522_FRMREGSTEP3DB_REG21DH                    0x21D
 173 #define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH             0x21E
 174 #define AU8522_FRMREGPLLMODE_REG21FH                    0x21F
 175 #define AU8522_FRMREGCSTHRD_REG220H                     0x220
 176 #define AU8522_FRMREGCRLOCKDMAX_REG221H                 0x221
 177 #define AU8522_FRMREGCRPERIODMASK_REG222H               0x222
 178 #define AU8522_FRMREGCRLOCK0THH_REG223H                 0x223
 179 #define AU8522_FRMREGCRLOCK1THH_REG224H                 0x224
 180 #define AU8522_FRMREGCRLOCK0THL_REG225H                 0x225
 181 #define AU8522_FRMREGCRLOCK1THL_REG226H                 0x226
 182 #define AU_FRMREGPLLACQPHASESCL_REG227H                 0x227
 183 #define AU8522_FRMREGFREQFBCTRL_REG228H                 0x228
 184
 185 /* Analog TV Decoder */
 186 #define AU8522_TVDEC_STATUS_REG000H                     0x000
 187 #define AU8522_TVDEC_INT_STATUS_REG001H                 0x001
 188 #define AU8522_TVDEC_MACROVISION_STATUS_REG002H         0x002
 189 #define AU8522_TVDEC_SHARPNESSREG009H                   0x009
 190 #define AU8522_TVDEC_BRIGHTNESS_REG00AH                 0x00A
 191 #define AU8522_TVDEC_CONTRAST_REG00BH                   0x00B
 192 #define AU8522_TVDEC_SATURATION_CB_REG00CH              0x00C
 193 #define AU8522_TVDEC_SATURATION_CR_REG00DH              0x00D
 194 #define AU8522_TVDEC_HUE_H_REG00EH                      0x00E
 195 #define AU8522_TVDEC_HUE_L_REG00FH                      0x00F
 196 #define AU8522_TVDEC_INT_MASK_REG010H                   0x010
 197 #define AU8522_VIDEO_MODE_REG011H                       0x011
 198 #define AU8522_TVDEC_PGA_REG012H                        0x012
 199 #define AU8522_TVDEC_COMB_MODE_REG015H                  0x015
 200 #define AU8522_REG016H                                  0x016
 201 #define AU8522_TVDED_DBG_MODE_REG060H                   0x060
 202 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H               0x061
 203 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H               0x062
 204 #define AU8522_TVDEC_VCR_DET_LLIM_REG063H               0x063
 205 #define AU8522_TVDEC_VCR_DET_HLIM_REG064H               0x064
 206 #define AU8522_TVDEC_COMB_VDIF_THR1_REG065H             0x065
 207 #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H             0x066
 208 #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H             0x067
 209 #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H             0x068
 210 #define AU8522_TVDEC_COMB_HDIF_THR1_REG069H             0x069
 211 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH             0x06A
 212 #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH             0x06B
 213 #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH            0x06C
 214 #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH            0x06D
 215 #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH            0x06E
 216 #define AU8522_TVDEC_UV_SEP_THR_REG06FH                 0x06F
 217 #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H          0x070
 218 #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H          0x073
 219 #define AU8522_TVDEC_DCAGC_CTRL_REG077H                 0x077
 220 #define AU8522_TVDEC_PIC_START_ADJ_REG078H              0x078
 221 #define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H             0x079
 222 #define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH       0x07A
 223 #define AU8522_TVDEC_INTRP_CTRL_REG07BH                 0x07B
 224 #define AU8522_TVDEC_PLL_STATUS_REG07EH                 0x07E
 225 #define AU8522_TVDEC_FSC_FREQ_REG07FH                   0x07F
 226
 227 #define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H              0x0E4
 228 #define AU8522_TOREGAAGC_REG0E5H                        0x0E5
 229
 230 #define AU8522_TVDEC_CHROMA_AGC_REG401H         0x401
 231 #define AU8522_TVDEC_CHROMA_SFT_REG402H         0x402
 232 #define AU8522_FILTER_COEF_R410                 0x410
 233 #define AU8522_FILTER_COEF_R411                 0x411
 234 #define AU8522_FILTER_COEF_R412                 0x412
 235 #define AU8522_FILTER_COEF_R413                 0x413
 236 #define AU8522_FILTER_COEF_R414                 0x414
 237 #define AU8522_FILTER_COEF_R415                 0x415
 238 #define AU8522_FILTER_COEF_R416                 0x416
 239 #define AU8522_FILTER_COEF_R417                 0x417
 240 #define AU8522_FILTER_COEF_R418                 0x418
 241 #define AU8522_FILTER_COEF_R419                 0x419
 242 #define AU8522_FILTER_COEF_R41A                 0x41A
 243 #define AU8522_FILTER_COEF_R41B                 0x41B
 244 #define AU8522_FILTER_COEF_R41C                 0x41C
 245 #define AU8522_FILTER_COEF_R41D                 0x41D
 246 #define AU8522_FILTER_COEF_R41E                 0x41E
 247 #define AU8522_FILTER_COEF_R41F                 0x41F
 248 #define AU8522_FILTER_COEF_R420                 0x420
 249 #define AU8522_FILTER_COEF_R421                 0x421
 250 #define AU8522_FILTER_COEF_R422                 0x422
 251 #define AU8522_FILTER_COEF_R423                 0x423
 252 #define AU8522_FILTER_COEF_R424                 0x424
 253 #define AU8522_FILTER_COEF_R425                 0x425
 254 #define AU8522_FILTER_COEF_R426                 0x426
 255 #define AU8522_FILTER_COEF_R427                 0x427
 256 #define AU8522_FILTER_COEF_R428                 0x428
 257 #define AU8522_FILTER_COEF_R429                 0x429
 258 #define AU8522_FILTER_COEF_R42A                 0x42A
 259 #define AU8522_FILTER_COEF_R42B                 0x42B
 260 #define AU8522_FILTER_COEF_R42C                 0x42C
 261 #define AU8522_FILTER_COEF_R42D                 0x42D
 262
 263 /* VBI Control Registers */
 264 #define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H        0x004
 265 #define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H        0x005
 266 #define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H           0x006
 267 #define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H            0x007
 268 #define AU8522_TVDEC_VBI_CTRL_H_REG017H                 0x017
 269 #define AU8522_TVDEC_VBI_CTRL_L_REG018H                 0x018
 270 #define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H        0x019
 271 #define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH           0x01A
 272 #define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH           0x01B
 273 #define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH           0x01C
 274 #define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH        0x01E
 275 #define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH        0x01F
 276 #define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H        0x020
 277 #define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H       0x021
 278 #define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H       0x022
 279 #define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H       0x023
 280
 281 #define AU8522_REG071H                                  0x071
 282 #define AU8522_REG072H                                  0x072
 283 #define AU8522_REG074H                                  0x074
 284 #define AU8522_REG075H                                  0x075
 285
 286 /* Digital Demodulator Registers */
 287 #define AU8522_FRAME_COUNT0_REG084H                     0x084
 288 #define AU8522_RS_STATUS_G0_REG085H                     0x085
 289 #define AU8522_RS_STATUS_B0_REG086H                     0x086
 290 #define AU8522_RS_STATUS_E_REG087H                      0x087
 291 #define AU8522_DEMODULATION_STATUS_REG088H              0x088
 292 #define AU8522_TOREGTRESTATUS_REG0E6H                   0x0E6
 293 #define AU8522_TSPORT_CONTROL_REG10BH                   0x10B
 294 #define AU8522_TSTHES_REG10CH                           0x10C
 295 #define AU8522_FRMREGDFEKEEP_REG301H                    0x301
 296 #define AU8522_DFE_AVERAGE_REG302H                      0x302
 297 #define AU8522_FRMREGEQLERRWIN_REG303H                  0x303
 298 #define AU8522_FRMREGFFEKEEP_REG304H                    0x304
 299 #define AU8522_FRMREGDFECONTROL1_REG305H                0x305
 300 #define AU8522_FRMREGEQLERRLOW_REG306H                  0x306
 301
 302 #define AU8522_REG42EH                          0x42E
 303 #define AU8522_REG42FH                          0x42F
 304 #define AU8522_REG430H                          0x430
 305 #define AU8522_REG431H                          0x431
 306 #define AU8522_REG432H                          0x432
 307 #define AU8522_REG433H                          0x433
 308 #define AU8522_REG434H                          0x434
 309 #define AU8522_REG435H                          0x435
 310 #define AU8522_REG436H                          0x436
 311
 312 /* GPIO Registers */
 313 #define AU8522_GPIO_CONTROL_REG0E0H                     0x0E0
 314 #define AU8522_GPIO_STATUS_REG0E1H                      0x0E1
 315 #define AU8522_GPIO_DATA_REG0E2H                        0x0E2
 316
 317 /* Audio Control Registers */
 318 #define AU8522_AUDIOAGC_REG0EEH                         0x0EE
 319 #define AU8522_AUDIO_STATUS_REG0F0H                     0x0F0
 320 #define AU8522_AUDIO_MODE_REG0F1H                       0x0F1
 321 #define AU8522_AUDIO_VOLUME_L_REG0F2H                   0x0F2
 322 #define AU8522_AUDIO_VOLUME_R_REG0F3H                   0x0F3
 323 #define AU8522_AUDIO_VOLUME_REG0F4H                     0x0F4
 324 #define AU8522_FRMREGAUPHASE_REG0F7H                    0x0F7
 325 #define AU8522_REG0F9H                                  0x0F9
 326
 327 #define AU8522_AUDIOAGC2_REG605H                        0x605
 328 #define AU8522_AUDIOFREQ_REG606H                        0x606
 329
 330
 331 /**************************************************************/
 332
 333 /* Format control 1 */
 334
 335 /* VCR Mode 7-6 */
 336 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES          0x80
 337 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO           0x40
 338 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO         0x00
 339 /* Field len 5-4 */
 340 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625         0x20
 341 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525         0x10
 342 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO        0x00
 343 /* Line len (us) 3-2 */
 344 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000       0x0b
 345 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492       0x08
 346 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556       0x04
 347 /* Subcarrier freq 1-0 */
 348 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO  0x03
 349 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443   0x02
 350 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN    0x01
 351 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50    0x00
 352
 353 /* Format control 2 */
 354 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT        0x00
 355 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC              0x01
 356 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M             0x02
 357
 358
 359 #define AU8522_INPUT_CONTROL_REG081H_ATSC                       0xC4
 360 #define AU8522_INPUT_CONTROL_REG081H_ATVRF                      0xC4
 361 #define AU8522_INPUT_CONTROL_REG081H_ATVRF13                    0xC4
 362 #define AU8522_INPUT_CONTROL_REG081H_J83B64                     0xC4
 363 #define AU8522_INPUT_CONTROL_REG081H_J83B256                    0xC4
 364 #define AU8522_INPUT_CONTROL_REG081H_CVBS                       0x20
 365 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1                   0xA2
 366 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2                   0xA0
 367 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3                   0x69
 368 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4                   0x68
 369 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF               0x28
 370 /* CH1 AS Y,CH3 AS C */
 371 #define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13                0x23
 372 /* CH2 AS Y,CH4 AS C */
 373 #define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24                0x20
 374 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC                0x0C
 375 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64              0x09
 376 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256             0x09
 377 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS                0x12
 378 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF               0x1A
 379 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13             0x1A
 380 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO              0x02
 381
 382 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR            0x00
 383 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO           0x9C
 384 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS             0x9D
 385 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC             0xE8
 386 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256          0xCA
 387 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64           0xCA
 388 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF            0xDD
 389 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13          0xDD
 390 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL              0xDD
 391 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM               0xDD
 392
 393 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC             0x80
 394 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256          0x80
 395 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64           0x80
 396 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC      0x40
 397 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256   0x40
 398 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64    0x40
 399 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR     0x00
 400 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF            0x01
 401 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13          0x01
 402 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO           0x04
 403 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS             0x01
 404 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM              0x03
 405 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS              0x09
 406 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL              0x01
 407 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM               0x01
 408
 409 /* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */
 410 #define AU8522_TVDEC_CONTRAST_REG00BH_CVBS                      0x79
 411 #define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS                 0x80
 412 #define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS                 0x80
 413 #define AU8522_TVDEC_HUE_H_REG00EH_CVBS                         0x00
 414 #define AU8522_TVDEC_HUE_L_REG00FH_CVBS                         0x00
 415 #define AU8522_TVDEC_PGA_REG012H_CVBS                           0x0F
 416 #define AU8522_TVDEC_COMB_MODE_REG015H_CVBS                     0x00
 417 #define AU8522_REG016H_CVBS                                     0x00
 418 #define AU8522_TVDED_DBG_MODE_REG060H_CVBS                      0x00
 419 #define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS                  0x19
 420 #define AU8522_REG0F9H_AUDIO                                    0x20
 421 #define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS                  0xA7
 422 #define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS                0x0A
 423 #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS                0x32
 424 #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS                0x19
 425 #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS                0x23
 426 #define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS                0x41
 427 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS                0x0A
 428 #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS                0x32
 429 #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS               0x34
 430 #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO             0x2a
 431 #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS               0x05
 432 #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO             0x15
 433 #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS               0x6E
 434 #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS                    0x0F
 435 #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS             0x80
 436 #define AU8522_REG071H_CVBS                                     0x18
 437 #define AU8522_REG072H_CVBS                                     0x30
 438 #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS             0xF0
 439 #define AU8522_REG074H_CVBS                                     0x80
 440 #define AU8522_REG075H_CVBS                                     0xF0
 441 #define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS                    0xFB
 442 #define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS                 0x04
 443 #define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS                0x00
 444 #define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS          0x00
 445 #define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS                    0xEE
 446 #define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS                 0xFE
 447 #define AU8522_TOREGAAGC_REG0E5H_CVBS                           0x00
 448 #define AU8522_TVDEC_VBI6A_REG035H_CVBS                         0x40
 449
 450 /* Enables Closed captioning */
 451 #define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON                    0x21