drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h

   1 /*
   2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
   3   All rights reserved.
   4
   5   Redistribution and use in source and binary forms, with or without
   6   modification, are permitted provided that the following conditions are met:
   7
   8   * Redistributions of source code must retain the above copyright notice,
   9     this list of conditions and the following disclaimer.
  10   * Redistributions in binary form must reproduce the above copyright notice,
  11     this list of conditions and the following disclaimer in the documentation
  12         and/or other materials provided with the distribution.
  13   * Neither the name of Trident Microsystems nor Hauppauge Computer Works
  14     nor the names of its contributors may be used to endorse or promote
  15         products derived from this software without specific prior written
  16         permission.
  17
  18   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28   POSSIBILITY OF SUCH DAMAGE.
  29 */
  30
  31 /*******************************************************************************
  32 * FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $
  33 *
  34 * DESCRIPTION:
  35 * Part of DRX driver.
  36 * Data access protocol: Fast Access Sequential Interface (fasi)
  37 * Fast access, because of short addressing format (16 instead of 32 bits addr)
  38 * Sequential, because of I2C.
  39 *
  40 * USAGE:
  41 * Include.
  42 *
  43 * NOTES:
  44 *
  45 *
  46 *******************************************************************************/
  47
  48 /*-------- compilation control switches --------------------------------------*/
  49
  50 #ifndef __DRX_DAP_FASI_H__
  51 #define __DRX_DAP_FASI_H__
  52
  53 /*-------- Required includes -------------------------------------------------*/
  54
  55 #include "drx_driver.h"
  56
  57 /*-------- Defines, configuring the API --------------------------------------*/
  58
  59 /********************************************
  60 * Allowed address formats
  61 ********************************************/
  62
  63 /*
  64 * Comments about short/long addressing format:
  65 *
  66 * The DAP FASI offers long address format (4 bytes) and short address format
  67 * (2 bytes). The DAP can operate in 3 modes:
  68 * (1) only short
  69 * (2) only long
  70 * (3) both long and short but short preferred and long only when necesarry
  71 *
  72 * These modes must be selected compile time via compile switches.
  73 * Compile switch settings for the diffrent modes:
  74 * (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
  75 * (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0
  76 * (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
  77 *
  78 * The default setting will be (3) both long and short.
  79 * The default setting will need no compile switches.
  80 * The default setting must be overridden if compile switches are already
  81 * defined.
  82 *
  83 */
  84
  85 /* set default */
  86 #if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED)
  87 #define  DRXDAPFASI_LONG_ADDR_ALLOWED 1
  88 #endif
  89
  90 /* set default */
  91 #if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED)
  92 #define  DRXDAPFASI_SHORT_ADDR_ALLOWED 1
  93 #endif
  94
  95 /* check */
  96 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \
  97       (DRXDAPFASI_SHORT_ADDR_ALLOWED == 0))
  98 #error  At least one of short- or long-addressing format must be allowed.
  99 *;                              /* illegal statement to force compiler error */
 100 #endif
 101
 102 /********************************************
 103 * Single/master multi master setting
 104 ********************************************/
 105 /*
 106 * Comments about SINGLE MASTER/MULTI MASTER  modes:
 107 *
 108 * Consider the two sides:1) the master and 2)the slave.
 109 *
 110 * Master:
 111 * Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch
 112 *  + single master mode means no use of repeated starts
 113 *  + multi master mode means use of repeated starts
 114 *  Default is single master.
 115 *  Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER.
 116 *
 117 * Slave:
 118 * Single/multi master selected via the flags in the FASI protocol.
 119 *  + single master means remember memory address between i2c packets
 120 *  + multimaster means flush memory address between i2c packets
 121 *  Default is single master, DAP FASI changes multi-master setting silently
 122 *  into single master setting. This cannot be overrriden.
 123 *
 124 */
 125 /* set default */
 126 #ifndef DRXDAP_SINGLE_MASTER
 127 #define DRXDAP_SINGLE_MASTER 0
 128 #endif
 129
 130 /********************************************
 131 * Chunk/mode checking
 132 ********************************************/
 133 /*
 134 * Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and
 135 * in combination with short and long addressing format. All text below
 136 * assumes long addressing format. The table also includes information
 137 * for short ADDRessing format.
 138 *
 139 * In single master mode, data can be written by sending the register address
 140 * first, then two or four bytes of data in the next packet.
 141 * Because the device address plus a register address equals five bytes,
 142 * the mimimum chunk size must be five.
 143 * If ten-bit I2C device addresses are used, the minimum chunk size must be six,
 144 * because the I2C device address will then occupy two bytes when writing.
 145 *
 146 * Data in single master mode is transferred as follows:
 147 * <S> <devW>  a0  a1  a2  a3  <P>
 148 * <S> <devW>  d0  d1 [d2  d3] <P>
 149 * ..
 150 * or
 151 * ..
 152 * <S> <devW>  a0  a1  a2  a3  <P>
 153 * <S> <devR> --- <P>
 154 *
 155 * In multi-master mode, the data must immediately follow the address (an I2C
 156 * stop resets the internal address), and hence the minimum chunk size is
 157 * 1 <I2C address> + 4 (register address) + 2 (data to send) = 7 bytes (8 if
 158 * 10-bit I2C device addresses are used).
 159 *
 160 * The 7-bit or 10-bit i2c address parameters is a runtime parameter.
 161 * The other parameters can be limited via compile time switches.
 162 *
 163 *-------------------------------------------------------------------------------
 164 *
 165 *  Minimum chunk size table (in bytes):
 166 *
 167 *       +----------------+----------------+
 168 *       | 7b i2c addr    | 10b i2c addr   |
 169 *       +----------------+----------------+
 170 *       | single | multi | single | multi |
 171 * ------+--------+-------+--------+-------+
 172 * short | 3      | 5     | 4      | 6     |
 173 * long  | 5      | 7     | 6      | 8     |
 174 * ------+--------+-------+--------+-------+
 175 *
 176 */
 177
 178 /* set default */
 179 #if !defined(DRXDAP_MAX_WCHUNKSIZE)
 180 #define  DRXDAP_MAX_WCHUNKSIZE 254
 181 #endif
 182
 183 /* check */
 184 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
 185 #if DRXDAP_SINGLE_MASTER
 186 #define  DRXDAP_MAX_WCHUNKSIZE_MIN 3
 187 #else
 188 #define  DRXDAP_MAX_WCHUNKSIZE_MIN 5
 189 #endif
 190 #else
 191 #if DRXDAP_SINGLE_MASTER
 192 #define  DRXDAP_MAX_WCHUNKSIZE_MIN 5
 193 #else
 194 #define  DRXDAP_MAX_WCHUNKSIZE_MIN 7
 195 #endif
 196 #endif
 197
 198 #if  DRXDAP_MAX_WCHUNKSIZE <  DRXDAP_MAX_WCHUNKSIZE_MIN
 199 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
 200 #if DRXDAP_SINGLE_MASTER
 201 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
 202 *;                              /* illegal statement to force compiler error */
 203 #else
 204 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
 205 *;                              /* illegal statement to force compiler error */
 206 #endif
 207 #else
 208 #if DRXDAP_SINGLE_MASTER
 209 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
 210 *;                              /* illegal statement to force compiler error */
 211 #else
 212 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
 213 *;                              /* illegal statement to force compiler error */
 214 #endif
 215 #endif
 216 #endif
 217
 218 /* set default */
 219 #if !defined(DRXDAP_MAX_RCHUNKSIZE)
 220 #define  DRXDAP_MAX_RCHUNKSIZE 254
 221 #endif
 222
 223 /* check */
 224 #if  DRXDAP_MAX_RCHUNKSIZE < 2
 225 #error  DRXDAP_MAX_RCHUNKSIZE must be at least 2
 226 *;                              /* illegal statement to force compiler error */
 227 #endif
 228
 229 /* check */
 230 #if  DRXDAP_MAX_RCHUNKSIZE & 1
 231 #error  DRXDAP_MAX_RCHUNKSIZE must be even
 232 *;                              /* illegal statement to force compiler error */
 233 #endif
 234
 235 /*-------- Public API functions ----------------------------------------------*/
 236
 237 extern struct drx_access_func drx_dap_fasi_funct_g;
 238
 239 #define DRXDAP_FASI_RMW           0x10000000
 240 #define DRXDAP_FASI_BROADCAST     0x20000000
 241 #define DRXDAP_FASI_CLEARCRC      0x80000000
 242 #define DRXDAP_FASI_SINGLE_MASTER 0xC0000000
 243 #define DRXDAP_FASI_MULTI_MASTER  0x40000000
 244 #define DRXDAP_FASI_SMM_SWITCH    0x40000000    /* single/multi master switch */
 245 #define DRXDAP_FASI_MODEFLAGS     0xC0000000
 246 #define DRXDAP_FASI_FLAGS         0xF0000000
 247
 248 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr)>>22)&0x3F)
 249 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr)>>16)&0x3F)
 250 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF)
 251
 252 #define DRXDAP_FASI_SHORT_FORMAT(addr)     (((addr) & 0xFC30FF80) == 0)
 253 #define DRXDAP_FASI_LONG_FORMAT(addr)      (((addr) & 0xFC30FF80) != 0)
 254 #define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0)
 255
 256 #endif                          /* __DRX_DAP_FASI_H__ */