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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / dvb-frontends / drx39xyj / drxj.c
blobf1c3e3b09b65db6761d3ffa4d48a570e3570fc2a
1 /*
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
16 permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
29
30 DRXJ specific implementation of DRX driver
31 authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
32
33 The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
34 written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
35
36 This program is free software; you can redistribute it and/or modify
37 it under the terms of the GNU General Public License as published by
38 the Free Software Foundation; either version 2 of the License, or
39 (at your option) any later version.
40
41 This program is distributed in the hope that it will be useful,
42 but WITHOUT ANY WARRANTY; without even the implied warranty of
43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44
45 GNU General Public License for more details.
46
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, write to the Free Software
49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
50 */
51
52 /*-----------------------------------------------------------------------------
53 INCLUDE FILES
54 ----------------------------------------------------------------------------*/
55
56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
57
58 #include <linux/module.h>
59 #include <linux/init.h>
60 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <asm/div64.h>
63
64 #include "dvb_frontend.h"
65 #include "drx39xxj.h"
66
67 #include "drxj.h"
68 #include "drxj_map.h"
69
70 /*============================================================================*/
71 /*=== DEFINES ================================================================*/
72 /*============================================================================*/
73
74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
75
76 /**
77 * \brief Maximum u32 value.
78 */
79 #ifndef MAX_U32
80 #define MAX_U32 ((u32) (0xFFFFFFFFL))
81 #endif
82
83 /* Customer configurable hardware settings, etc */
84 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
85 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
86 #endif
87
88 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
89 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
90 #endif
91
92 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
93 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
94 #endif
95
96 #ifndef OOB_CRX_DRIVE_STRENGTH
97 #define OOB_CRX_DRIVE_STRENGTH 0x02
98 #endif
99
100 #ifndef OOB_DRX_DRIVE_STRENGTH
101 #define OOB_DRX_DRIVE_STRENGTH 0x02
102 #endif
103 /**** START DJCOMBO patches to DRXJ registermap constants *********************/
104 /**** registermap 200706071303 from drxj **************************************/
105 #define ATV_TOP_CR_AMP_TH_FM 0x0
106 #define ATV_TOP_CR_AMP_TH_L 0xA
107 #define ATV_TOP_CR_AMP_TH_LP 0xA
108 #define ATV_TOP_CR_AMP_TH_BG 0x8
109 #define ATV_TOP_CR_AMP_TH_DK 0x8
110 #define ATV_TOP_CR_AMP_TH_I 0x8
111 #define ATV_TOP_CR_CONT_CR_D_MN 0x18
112 #define ATV_TOP_CR_CONT_CR_D_FM 0x0
113 #define ATV_TOP_CR_CONT_CR_D_L 0x20
114 #define ATV_TOP_CR_CONT_CR_D_LP 0x20
115 #define ATV_TOP_CR_CONT_CR_D_BG 0x18
116 #define ATV_TOP_CR_CONT_CR_D_DK 0x18
117 #define ATV_TOP_CR_CONT_CR_D_I 0x18
118 #define ATV_TOP_CR_CONT_CR_I_MN 0x80
119 #define ATV_TOP_CR_CONT_CR_I_FM 0x0
120 #define ATV_TOP_CR_CONT_CR_I_L 0x80
121 #define ATV_TOP_CR_CONT_CR_I_LP 0x80
122 #define ATV_TOP_CR_CONT_CR_I_BG 0x80
123 #define ATV_TOP_CR_CONT_CR_I_DK 0x80
124 #define ATV_TOP_CR_CONT_CR_I_I 0x80
125 #define ATV_TOP_CR_CONT_CR_P_MN 0x4
126 #define ATV_TOP_CR_CONT_CR_P_FM 0x0
127 #define ATV_TOP_CR_CONT_CR_P_L 0x4
128 #define ATV_TOP_CR_CONT_CR_P_LP 0x4
129 #define ATV_TOP_CR_CONT_CR_P_BG 0x4
130 #define ATV_TOP_CR_CONT_CR_P_DK 0x4
131 #define ATV_TOP_CR_CONT_CR_P_I 0x4
132 #define ATV_TOP_CR_OVM_TH_MN 0xA0
133 #define ATV_TOP_CR_OVM_TH_FM 0x0
134 #define ATV_TOP_CR_OVM_TH_L 0xA0
135 #define ATV_TOP_CR_OVM_TH_LP 0xA0
136 #define ATV_TOP_CR_OVM_TH_BG 0xA0
137 #define ATV_TOP_CR_OVM_TH_DK 0xA0
138 #define ATV_TOP_CR_OVM_TH_I 0xA0
139 #define ATV_TOP_EQU0_EQU_C0_FM 0x0
140 #define ATV_TOP_EQU0_EQU_C0_L 0x3
141 #define ATV_TOP_EQU0_EQU_C0_LP 0x3
142 #define ATV_TOP_EQU0_EQU_C0_BG 0x7
143 #define ATV_TOP_EQU0_EQU_C0_DK 0x0
144 #define ATV_TOP_EQU0_EQU_C0_I 0x3
145 #define ATV_TOP_EQU1_EQU_C1_FM 0x0
146 #define ATV_TOP_EQU1_EQU_C1_L 0x1F6
147 #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
148 #define ATV_TOP_EQU1_EQU_C1_BG 0x197
149 #define ATV_TOP_EQU1_EQU_C1_DK 0x198
150 #define ATV_TOP_EQU1_EQU_C1_I 0x1F6
151 #define ATV_TOP_EQU2_EQU_C2_FM 0x0
152 #define ATV_TOP_EQU2_EQU_C2_L 0x28
153 #define ATV_TOP_EQU2_EQU_C2_LP 0x28
154 #define ATV_TOP_EQU2_EQU_C2_BG 0xC5
155 #define ATV_TOP_EQU2_EQU_C2_DK 0xB0
156 #define ATV_TOP_EQU2_EQU_C2_I 0x28
157 #define ATV_TOP_EQU3_EQU_C3_FM 0x0
158 #define ATV_TOP_EQU3_EQU_C3_L 0x192
159 #define ATV_TOP_EQU3_EQU_C3_LP 0x192
160 #define ATV_TOP_EQU3_EQU_C3_BG 0x12E
161 #define ATV_TOP_EQU3_EQU_C3_DK 0x18E
162 #define ATV_TOP_EQU3_EQU_C3_I 0x192
163 #define ATV_TOP_STD_MODE_MN 0x0
164 #define ATV_TOP_STD_MODE_FM 0x1
165 #define ATV_TOP_STD_MODE_L 0x0
166 #define ATV_TOP_STD_MODE_LP 0x0
167 #define ATV_TOP_STD_MODE_BG 0x0
168 #define ATV_TOP_STD_MODE_DK 0x0
169 #define ATV_TOP_STD_MODE_I 0x0
170 #define ATV_TOP_STD_VID_POL_MN 0x0
171 #define ATV_TOP_STD_VID_POL_FM 0x0
172 #define ATV_TOP_STD_VID_POL_L 0x2
173 #define ATV_TOP_STD_VID_POL_LP 0x2
174 #define ATV_TOP_STD_VID_POL_BG 0x0
175 #define ATV_TOP_STD_VID_POL_DK 0x0
176 #define ATV_TOP_STD_VID_POL_I 0x0
177 #define ATV_TOP_VID_AMP_MN 0x380
178 #define ATV_TOP_VID_AMP_FM 0x0
179 #define ATV_TOP_VID_AMP_L 0xF50
180 #define ATV_TOP_VID_AMP_LP 0xF50
181 #define ATV_TOP_VID_AMP_BG 0x380
182 #define ATV_TOP_VID_AMP_DK 0x394
183 #define ATV_TOP_VID_AMP_I 0x3D8
184 #define IQM_CF_OUT_ENA_OFDM__M 0x4
185 #define IQM_FS_ADJ_SEL_B_QAM 0x1
186 #define IQM_FS_ADJ_SEL_B_OFF 0x0
187 #define IQM_FS_ADJ_SEL_B_VSB 0x2
188 #define IQM_RC_ADJ_SEL_B_OFF 0x0
189 #define IQM_RC_ADJ_SEL_B_QAM 0x1
190 #define IQM_RC_ADJ_SEL_B_VSB 0x2
191 /**** END DJCOMBO patches to DRXJ registermap *********************************/
192
193 #include "drx_driver_version.h"
194
195 /* #define DRX_DEBUG */
196 #ifdef DRX_DEBUG
197 #include <stdio.h>
198 #endif
199
200 /*-----------------------------------------------------------------------------
201 ENUMS
202 ----------------------------------------------------------------------------*/
203
204 /*-----------------------------------------------------------------------------
205 DEFINES
206 ----------------------------------------------------------------------------*/
207 #ifndef DRXJ_WAKE_UP_KEY
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
209 #endif
210
211 /**
212 * \def DRXJ_DEF_I2C_ADDR
213 * \brief Default I2C address of a demodulator instance.
214 */
215 #define DRXJ_DEF_I2C_ADDR (0x52)
216
217 /**
218 * \def DRXJ_DEF_DEMOD_DEV_ID
219 * \brief Default device identifier of a demodultor instance.
220 */
221 #define DRXJ_DEF_DEMOD_DEV_ID (1)
222
223 /**
224 * \def DRXJ_SCAN_TIMEOUT
225 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
226 */
227 #define DRXJ_SCAN_TIMEOUT 1000
228
229 /**
230 * \def HI_I2C_DELAY
231 * \brief HI timing delay for I2C timing (in nano seconds)
232 *
233 * Used to compute HI_CFG_DIV
234 */
235 #define HI_I2C_DELAY 42
236
237 /**
238 * \def HI_I2C_BRIDGE_DELAY
239 * \brief HI timing delay for I2C timing (in nano seconds)
240 *
241 * Used to compute HI_CFG_BDL
242 */
243 #define HI_I2C_BRIDGE_DELAY 750
244
245 /**
246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
247 */
248 #define VSB_TOP_MEASUREMENT_PERIOD 64
249 #define SYMBOLS_PER_SEGMENT 832
250
251 /**
252 * \brief bit rate and segment rate constants used for SER and BER.
253 */
254 /* values taken from the QAM microcode */
255 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
256 #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
257 #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
258 #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
259 #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
260 #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
261 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
262 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
263 /**
264 * \brief Min supported symbolrates.
265 */
266 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
267 #define DRXJ_QAM_SYMBOLRATE_MIN (520000)
268 #endif
269
270 /**
271 * \brief Max supported symbolrates.
272 */
273 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
274 #define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
275 #endif
276
277 /**
278 * \def DRXJ_QAM_MAX_WAITTIME
279 * \brief Maximal wait time for QAM auto constellation in ms
280 */
281 #ifndef DRXJ_QAM_MAX_WAITTIME
282 #define DRXJ_QAM_MAX_WAITTIME 900
283 #endif
284
285 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
286 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
287 #endif
288
289 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
290 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
291 #endif
292
293 /**
294 * \def SCU status and results
295 * \brief SCU
296 */
297 #define DRX_SCU_READY 0
298 #define DRXJ_MAX_WAITTIME 100 /* ms */
299 #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */
300 #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */
301
302 /**
303 * \def DRX_AUD_MAX_DEVIATION
304 * \brief Needed for calculation of prescale feature in AUD
305 */
306 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
307 #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */
308 #endif
309
310 /**
311 * \brief Needed for calculation of NICAM prescale feature in AUD
312 */
313 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
314 #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */
315 #endif
316
317 /**
318 * \brief Needed for calculation of NICAM prescale feature in AUD
319 */
320 #ifndef DRXJ_AUD_MAX_WAITTIME
321 #define DRXJ_AUD_MAX_WAITTIME 250 /* ms */
322 #endif
323
324 /* ATV config changed flags */
325 #define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
326 #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
327 #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
328 #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
329 #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
330
331 /* UIO define */
332 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
333 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
334
335 /*
336 * MICROCODE RELATED DEFINES
337 */
338
339 /* Magic word for checking correct Endianness of microcode data */
340 #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
341
342 /* CRC flag in ucode header, flags field. */
343 #define DRX_UCODE_CRC_FLAG (0x0001)
344
345 /*
346 * Maximum size of buffer used to verify the microcode.
347 * Must be an even number
348 */
349 #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
350
351 #if DRX_UCODE_MAX_BUF_SIZE & 1
352 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
353 #endif
354
355 /*
356 * Power mode macros
357 */
358
359 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
360 (mode == DRX_POWER_MODE_10) || \
361 (mode == DRX_POWER_MODE_11) || \
362 (mode == DRX_POWER_MODE_12) || \
363 (mode == DRX_POWER_MODE_13) || \
364 (mode == DRX_POWER_MODE_14) || \
365 (mode == DRX_POWER_MODE_15) || \
366 (mode == DRX_POWER_MODE_16) || \
367 (mode == DRX_POWER_DOWN))
368
369 /* Pin safe mode macro */
370 #define DRXJ_PIN_SAFE_MODE 0x0000
371 /*============================================================================*/
372 /*=== GLOBAL VARIABLEs =======================================================*/
373 /*============================================================================*/
374 /**
375 */
376
377 /**
378 * \brief Temporary register definitions.
379 * (register definitions that are not yet available in register master)
380 */
381
382 /******************************************************************************/
383 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
384 /* RAM adresses directly. This must be READ ONLY to avoid problems. */
385 /* Writing to the interface adresses is more than only writing the RAM */
386 /* locations */
387 /******************************************************************************/
388 /**
389 * \brief RAM location of MODUS registers
390 */
391 #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
392 #define AUD_DEM_RAM_MODUS_HI__M 0xF000
393
394 #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
395 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
396
397 /**
398 * \brief RAM location of I2S config registers
399 */
400 #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
401 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
402
403 /**
404 * \brief RAM location of DCO config registers
405 */
406 #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
407 #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
408 #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
409 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
410
411 /**
412 * \brief RAM location of Threshold registers
413 */
414 #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
415 #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
416 #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
417
418 /**
419 * \brief RAM location of Carrier Threshold registers
420 */
421 #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
422 #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
423
424 /**
425 * \brief FM Matrix register fix
426 */
427 #ifdef AUD_DEM_WR_FM_MATRIX__A
428 #undef AUD_DEM_WR_FM_MATRIX__A
429 #endif
430 #define AUD_DEM_WR_FM_MATRIX__A 0x105006F
431
432 /*============================================================================*/
433 /**
434 * \brief Defines required for audio
435 */
436 #define AUD_VOLUME_ZERO_DB 115
437 #define AUD_VOLUME_DB_MIN -60
438 #define AUD_VOLUME_DB_MAX 12
439 #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
440 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
441 #define AUD_MAX_AVC_REF_LEVEL 15
442 #define AUD_I2S_FREQUENCY_MAX 48000UL
443 #define AUD_I2S_FREQUENCY_MIN 12000UL
444 #define AUD_RDS_ARRAY_SIZE 18
445
446 /**
447 * \brief Needed for calculation of prescale feature in AUD
448 */
449 #ifndef DRX_AUD_MAX_FM_DEVIATION
450 #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */
451 #endif
452
453 /**
454 * \brief Needed for calculation of NICAM prescale feature in AUD
455 */
456 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
457 #define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */
458 #endif
459
460 /*============================================================================*/
461 /* Values for I2S Master/Slave pin configurations */
462 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
463 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
464 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
465 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
466
467 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
468 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
469 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
470 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
471
472 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
473 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
474 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
475 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
476
477 /*============================================================================*/
478 /*=== REGISTER ACCESS MACROS =================================================*/
479 /*============================================================================*/
480
481 /**
482 * This macro is used to create byte arrays for block writes.
483 * Block writes speed up I2C traffic between host and demod.
484 * The macro takes care of the required byte order in a 16 bits word.
485 * x -> lowbyte(x), highbyte(x)
486 */
487 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
488 ((u8)((((u16)x)>>8)&0xFF))
489 /**
490 * This macro is used to convert byte array to 16 bit register value for block read.
491 * Block read speed up I2C traffic between host and demod.
492 * The macro takes care of the required byte order in a 16 bits word.
493 */
494 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
495
496 /*============================================================================*/
497 /*=== MISC DEFINES ===========================================================*/
498 /*============================================================================*/
499
500 /*============================================================================*/
501 /*=== HI COMMAND RELATED DEFINES =============================================*/
502 /*============================================================================*/
503
504 /**
505 * \brief General maximum number of retries for ucode command interfaces
506 */
507 #define DRXJ_MAX_RETRIES (100)
508
509 /*============================================================================*/
510 /*=== STANDARD RELATED MACROS ================================================*/
511 /*============================================================================*/
512
513 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
514 (std == DRX_STANDARD_PAL_SECAM_DK) || \
515 (std == DRX_STANDARD_PAL_SECAM_I) || \
516 (std == DRX_STANDARD_PAL_SECAM_L) || \
517 (std == DRX_STANDARD_PAL_SECAM_LP) || \
518 (std == DRX_STANDARD_NTSC) || \
519 (std == DRX_STANDARD_FM))
520
521 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
522 (std == DRX_STANDARD_ITU_B) || \
523 (std == DRX_STANDARD_ITU_C) || \
524 (std == DRX_STANDARD_ITU_D))
525
526 /*-----------------------------------------------------------------------------
527 GLOBAL VARIABLES
528 ----------------------------------------------------------------------------*/
529 /*
530 * DRXJ DAP structures
531 */
532
533 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
534 u32 addr,
535 u16 datasize,
536 u8 *data, u32 flags);
537
538
539 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
540 u32 waddr,
541 u32 raddr,
542 u16 wdata, u16 *rdata);
543
544 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
545 u32 addr,
546 u16 *data, u32 flags);
547
548 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
549 u32 addr,
550 u32 *data, u32 flags);
551
552 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
553 u32 addr,
554 u16 datasize,
555 u8 *data, u32 flags);
556
557 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
558 u32 addr,
559 u16 data, u32 flags);
560
561 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
562 u32 addr,
563 u32 data, u32 flags);
564
565 static struct drxj_data drxj_data_g = {
566 false, /* has_lna : true if LNA (aka PGA) present */
567 false, /* has_oob : true if OOB supported */
568 false, /* has_ntsc: true if NTSC supported */
569 false, /* has_btsc: true if BTSC supported */
570 false, /* has_smatx: true if SMA_TX pin is available */
571 false, /* has_smarx: true if SMA_RX pin is available */
572 false, /* has_gpio : true if GPIO pin is available */
573 false, /* has_irqn : true if IRQN pin is available */
574 0, /* mfx A1/A2/A... */
575
576 /* tuner settings */
577 false, /* tuner mirrors RF signal */
578 /* standard/channel settings */
579 DRX_STANDARD_UNKNOWN, /* current standard */
580 DRX_CONSTELLATION_AUTO, /* constellation */
581 0, /* frequency in KHz */
582 DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */
583 DRX_MIRROR_NO, /* mirror */
584
585 /* signal quality information: */
586 /* default values taken from the QAM Programming guide */
587 /* fec_bits_desired should not be less than 4000000 */
588 4000000, /* fec_bits_desired */
589 5, /* fec_vd_plen */
590 4, /* qam_vd_prescale */
591 0xFFFF, /* qamVDPeriod */
592 204 * 8, /* fec_rs_plen annex A */
593 1, /* fec_rs_prescale */
594 FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */
595 true, /* reset_pkt_err_acc */
596 0, /* pkt_err_acc_start */
597
598 /* HI configuration */
599 0, /* hi_cfg_timing_div */
600 0, /* hi_cfg_bridge_delay */
601 0, /* hi_cfg_wake_up_key */
602 0, /* hi_cfg_ctrl */
603 0, /* HICfgTimeout */
604 /* UIO configuartion */
605 DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */
606 DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */
607 DRX_UIO_MODE_DISABLE, /* uioASELMode */
608 DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */
609 /* FS setting */
610 0UL, /* iqm_fs_rate_ofs */
611 false, /* pos_image */
612 /* RC setting */
613 0UL, /* iqm_rc_rate_ofs */
614 /* AUD information */
615 /* false, * flagSetAUDdone */
616 /* false, * detectedRDS */
617 /* true, * flagASDRequest */
618 /* false, * flagHDevClear */
619 /* false, * flagHDevSet */
620 /* (u16) 0xFFF, * rdsLastCount */
621
622 /* ATV configuartion */
623 0UL, /* flags cfg changes */
624 /* shadow of ATV_TOP_EQU0__A */
625 {-5,
626 ATV_TOP_EQU0_EQU_C0_FM,
627 ATV_TOP_EQU0_EQU_C0_L,
628 ATV_TOP_EQU0_EQU_C0_LP,
629 ATV_TOP_EQU0_EQU_C0_BG,
630 ATV_TOP_EQU0_EQU_C0_DK,
631 ATV_TOP_EQU0_EQU_C0_I},
632 /* shadow of ATV_TOP_EQU1__A */
633 {-50,
634 ATV_TOP_EQU1_EQU_C1_FM,
635 ATV_TOP_EQU1_EQU_C1_L,
636 ATV_TOP_EQU1_EQU_C1_LP,
637 ATV_TOP_EQU1_EQU_C1_BG,
638 ATV_TOP_EQU1_EQU_C1_DK,
639 ATV_TOP_EQU1_EQU_C1_I},
640 /* shadow of ATV_TOP_EQU2__A */
641 {210,
642 ATV_TOP_EQU2_EQU_C2_FM,
643 ATV_TOP_EQU2_EQU_C2_L,
644 ATV_TOP_EQU2_EQU_C2_LP,
645 ATV_TOP_EQU2_EQU_C2_BG,
646 ATV_TOP_EQU2_EQU_C2_DK,
647 ATV_TOP_EQU2_EQU_C2_I},
648 /* shadow of ATV_TOP_EQU3__A */
649 {-160,
650 ATV_TOP_EQU3_EQU_C3_FM,
651 ATV_TOP_EQU3_EQU_C3_L,
652 ATV_TOP_EQU3_EQU_C3_LP,
653 ATV_TOP_EQU3_EQU_C3_BG,
654 ATV_TOP_EQU3_EQU_C3_DK,
655 ATV_TOP_EQU3_EQU_C3_I},
656 false, /* flag: true=bypass */
657 ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
658 ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
659 true, /* flag CVBS ouput enable */
660 false, /* flag SIF ouput enable */
661 DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
662 { /* qam_rf_agc_cfg */
663 DRX_STANDARD_ITU_B, /* standard */
664 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
665 0, /* output_level */
666 0, /* min_output_level */
667 0xFFFF, /* max_output_level */
668 0x0000, /* speed */
669 0x0000, /* top */
670 0x0000 /* c.o.c. */
671 },
672 { /* qam_if_agc_cfg */
673 DRX_STANDARD_ITU_B, /* standard */
674 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
675 0, /* output_level */
676 0, /* min_output_level */
677 0xFFFF, /* max_output_level */
678 0x0000, /* speed */
679 0x0000, /* top (don't care) */
680 0x0000 /* c.o.c. (don't care) */
681 },
682 { /* vsb_rf_agc_cfg */
683 DRX_STANDARD_8VSB, /* standard */
684 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
685 0, /* output_level */
686 0, /* min_output_level */
687 0xFFFF, /* max_output_level */
688 0x0000, /* speed */
689 0x0000, /* top (don't care) */
690 0x0000 /* c.o.c. (don't care) */
691 },
692 { /* vsb_if_agc_cfg */
693 DRX_STANDARD_8VSB, /* standard */
694 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
695 0, /* output_level */
696 0, /* min_output_level */
697 0xFFFF, /* max_output_level */
698 0x0000, /* speed */
699 0x0000, /* top (don't care) */
700 0x0000 /* c.o.c. (don't care) */
701 },
702 0, /* qam_pga_cfg */
703 0, /* vsb_pga_cfg */
704 { /* qam_pre_saw_cfg */
705 DRX_STANDARD_ITU_B, /* standard */
706 0, /* reference */
707 false /* use_pre_saw */
708 },
709 { /* vsb_pre_saw_cfg */
710 DRX_STANDARD_8VSB, /* standard */
711 0, /* reference */
712 false /* use_pre_saw */
713 },
714
715 /* Version information */
716 #ifndef _CH_
717 {
718 "01234567890", /* human readable version microcode */
719 "01234567890" /* human readable version device specific code */
720 },
721 {
722 { /* struct drx_version for microcode */
723 DRX_MODULE_UNKNOWN,
724 (char *)(NULL),
725 0,
726 0,
727 0,
728 (char *)(NULL)
729 },
730 { /* struct drx_version for device specific code */
731 DRX_MODULE_UNKNOWN,
732 (char *)(NULL),
733 0,
734 0,
735 0,
736 (char *)(NULL)
737 }
738 },
739 {
740 { /* struct drx_version_list for microcode */
741 (struct drx_version *) (NULL),
742 (struct drx_version_list *) (NULL)
743 },
744 { /* struct drx_version_list for device specific code */
745 (struct drx_version *) (NULL),
746 (struct drx_version_list *) (NULL)
747 }
748 },
749 #endif
750 false, /* smart_ant_inverted */
751 /* Tracking filter setting for OOB */
752 {
753 12000,
754 9300,
755 6600,
756 5280,
757 3700,
758 3000,
759 2000,
760 0},
761 false, /* oob_power_on */
762 0, /* mpeg_ts_static_bitrate */
763 false, /* disable_te_ihandling */
764 false, /* bit_reverse_mpeg_outout */
765 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */
766 DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */
767
768 /* Pre SAW & Agc configuration for ATV */
769 {
770 DRX_STANDARD_NTSC, /* standard */
771 7, /* reference */
772 true /* use_pre_saw */
773 },
774 { /* ATV RF-AGC */
775 DRX_STANDARD_NTSC, /* standard */
776 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
777 0, /* output_level */
778 0, /* min_output_level (d.c.) */
779 0, /* max_output_level (d.c.) */
780 3, /* speed */
781 9500, /* top */
782 4000 /* cut-off current */
783 },
784 { /* ATV IF-AGC */
785 DRX_STANDARD_NTSC, /* standard */
786 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
787 0, /* output_level */
788 0, /* min_output_level (d.c.) */
789 0, /* max_output_level (d.c.) */
790 3, /* speed */
791 2400, /* top */
792 0 /* c.o.c. (d.c.) */
793 },
794 140, /* ATV PGA config */
795 0, /* curr_symbol_rate */
796
797 false, /* pdr_safe_mode */
798 SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */
799 SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
800 SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */
801 SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */
802
803 4, /* oob_pre_saw */
804 DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */
805 {
806 false /* aud_data, only first member */
807 },
808 };
809
810 /**
811 * \var drxj_default_addr_g
812 * \brief Default I2C address and device identifier.
813 */
814 static struct i2c_device_addr drxj_default_addr_g = {
815 DRXJ_DEF_I2C_ADDR, /* i2c address */
816 DRXJ_DEF_DEMOD_DEV_ID /* device id */
817 };
818
819 /**
820 * \var drxj_default_comm_attr_g
821 * \brief Default common attributes of a drxj demodulator instance.
822 */
823 static struct drx_common_attr drxj_default_comm_attr_g = {
824 NULL, /* ucode file */
825 true, /* ucode verify switch */
826 {0}, /* version record */
827
828 44000, /* IF in kHz in case no tuner instance is used */
829 (151875 - 0), /* system clock frequency in kHz */
830 0, /* oscillator frequency kHz */
831 0, /* oscillator deviation in ppm, signed */
832 false, /* If true mirror frequency spectrum */
833 {
834 /* MPEG output configuration */
835 true, /* If true, enable MPEG ouput */
836 false, /* If true, insert RS byte */
837 false, /* If true, parallel out otherwise serial */
838 false, /* If true, invert DATA signals */
839 false, /* If true, invert ERR signal */
840 false, /* If true, invert STR signals */
841 false, /* If true, invert VAL signals */
842 false, /* If true, invert CLK signals */
843 true, /* If true, static MPEG clockrate will
844 be used, otherwise clockrate will
845 adapt to the bitrate of the TS */
846 19392658UL, /* Maximum bitrate in b/s in case
847 static clockrate is selected */
848 DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
849 },
850 /* Initilisations below can be omitted, they require no user input and
851 are initialy 0, NULL or false. The compiler will initialize them to these
852 values when omitted. */
853 false, /* is_opened */
854
855 /* SCAN */
856 NULL, /* no scan params yet */
857 0, /* current scan index */
858 0, /* next scan frequency */
859 false, /* scan ready flag */
860 0, /* max channels to scan */
861 0, /* nr of channels scanned */
862 NULL, /* default scan function */
863 NULL, /* default context pointer */
864 0, /* millisec to wait for demod lock */
865 DRXJ_DEMOD_LOCK, /* desired lock */
866 false,
867
868 /* Power management */
869 DRX_POWER_UP,
870
871 /* Tuner */
872 1, /* nr of I2C port to wich tuner is */
873 0L, /* minimum RF input frequency, in kHz */
874 0L, /* maximum RF input frequency, in kHz */
875 false, /* Rf Agc Polarity */
876 false, /* If Agc Polarity */
877 false, /* tuner slow mode */
878
879 { /* current channel (all 0) */
880 0UL /* channel.frequency */
881 },
882 DRX_STANDARD_UNKNOWN, /* current standard */
883 DRX_STANDARD_UNKNOWN, /* previous standard */
884 DRX_STANDARD_UNKNOWN, /* di_cache_standard */
885 false, /* use_bootloader */
886 0UL, /* capabilities */
887 0 /* mfx */
888 };
889
890 /**
891 * \var drxj_default_demod_g
892 * \brief Default drxj demodulator instance.
893 */
894 static struct drx_demod_instance drxj_default_demod_g = {
895 &drxj_default_addr_g, /* i2c address & device id */
896 &drxj_default_comm_attr_g, /* demod common attributes */
897 &drxj_data_g /* demod device specific attributes */
898 };
899
900 /**
901 * \brief Default audio data structure for DRK demodulator instance.
902 *
903 * This structure is DRXK specific.
904 *
905 */
906 static struct drx_aud_data drxj_default_aud_data_g = {
907 false, /* audio_is_active */
908 DRX_AUD_STANDARD_AUTO, /* audio_standard */
909
910 /* i2sdata */
911 {
912 false, /* output_enable */
913 48000, /* frequency */
914 DRX_I2S_MODE_MASTER, /* mode */
915 DRX_I2S_WORDLENGTH_32, /* word_length */
916 DRX_I2S_POLARITY_RIGHT, /* polarity */
917 DRX_I2S_FORMAT_WS_WITH_DATA /* format */
918 },
919 /* volume */
920 {
921 true, /* mute; */
922 0, /* volume */
923 DRX_AUD_AVC_OFF, /* avc_mode */
924 0, /* avc_ref_level */
925 DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */
926 DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */
927 0, /* strength_left */
928 0 /* strength_right */
929 },
930 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
931 /* ass_thresholds */
932 {
933 440, /* A2 */
934 12, /* BTSC */
935 700, /* NICAM */
936 },
937 /* carrier */
938 {
939 /* a */
940 {
941 42, /* thres */
942 DRX_NO_CARRIER_NOISE, /* opt */
943 0, /* shift */
944 0 /* dco */
945 },
946 /* b */
947 {
948 42, /* thres */
949 DRX_NO_CARRIER_MUTE, /* opt */
950 0, /* shift */
951 0 /* dco */
952 },
953
954 },
955 /* mixer */
956 {
957 DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */
958 DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */
959 DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
960 },
961 DRX_AUD_DEVIATION_NORMAL, /* deviation */
962 DRX_AUD_AVSYNC_OFF, /* av_sync */
963
964 /* prescale */
965 {
966 DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */
967 DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
968 },
969 DRX_AUD_FM_DEEMPH_75US, /* deemph */
970 DRX_BTSC_STEREO, /* btsc_detect */
971 0, /* rds_data_counter */
972 false /* rds_data_present */
973 };
974
975 /*-----------------------------------------------------------------------------
976 STRUCTURES
977 ----------------------------------------------------------------------------*/
978 struct drxjeq_stat {
979 u16 eq_mse;
980 u8 eq_mode;
981 u8 eq_ctrl;
982 u8 eq_stat;
983 };
984
985 /* HI command */
986 struct drxj_hi_cmd {
987 u16 cmd;
988 u16 param1;
989 u16 param2;
990 u16 param3;
991 u16 param4;
992 u16 param5;
993 u16 param6;
994 };
995
996 /*============================================================================*/
997 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
998 /*============================================================================*/
999
1000 /**
1001 * struct drxu_code_block_hdr - Structure of the microcode block headers
1002 *
1003 * @addr: Destination address of the data in this block
1004 * @size: Size of the block data following this header counted in
1005 * 16 bits words
1006 * @CRC: CRC value of the data block, only valid if CRC flag is
1007 * set.
1008 */
1009 struct drxu_code_block_hdr {
1010 u32 addr;
1011 u16 size;
1012 u16 flags;
1013 u16 CRC;
1014 };
1015
1016 /*-----------------------------------------------------------------------------
1017 FUNCTIONS
1018 ----------------------------------------------------------------------------*/
1019 /* Some prototypes */
1020 static int
1021 hi_command(struct i2c_device_addr *dev_addr,
1022 const struct drxj_hi_cmd *cmd, u16 *result);
1023
1024 static int
1025 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1026
1027 static int
1028 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1029
1030 static int power_down_aud(struct drx_demod_instance *demod);
1031
1032 static int
1033 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1034
1035 static int
1036 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1037
1038 /*============================================================================*/
1039 /*============================================================================*/
1040 /*== HELPER FUNCTIONS ==*/
1041 /*============================================================================*/
1042 /*============================================================================*/
1043
1044
1045 /*============================================================================*/
1046
1047 /*
1048 * \fn u32 frac28(u32 N, u32 D)
1049 * \brief Compute: (1<<28)*N/D
1050 * \param N 32 bits
1051 * \param D 32 bits
1052 * \return (1<<28)*N/D
1053 * This function is used to avoid floating-point calculations as they may
1054 * not be present on the target platform.
1055
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1057 * fraction used for setting the Frequency Shifter registers.
1058 * N and D can hold numbers up to width: 28-bits.
1059 * The 4 bits integer part and the 28 bits fractional part are calculated.
1060
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1062
1063 * N: 0...(1<<28)-1 = 268435454
1064 * D: 0...(1<<28)-1
1065 * Q: 0...(1<<32)-1
1066 */
1067 static u32 frac28(u32 N, u32 D)
1068 {
1069 int i = 0;
1070 u32 Q1 = 0;
1071 u32 R0 = 0;
1072
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
1074 Q1 = N / D; /* integer part, only the 4 least significant bits
1075 will be visible in the result */
1076
1077 /* division using radix 16, 7 nibbles in the result */
1078 for (i = 0; i < 7; i++) {
1079 Q1 = (Q1 << 4) | R0 / D;
1080 R0 = (R0 % D) << 4;
1081 }
1082 /* rounding */
1083 if ((R0 >> 3) >= D)
1084 Q1++;
1085
1086 return Q1;
1087 }
1088
1089 /**
1090 * \fn u32 log1_times100( u32 x)
1091 * \brief Compute: 100*log10(x)
1092 * \param x 32 bits
1093 * \return 100*log10(x)
1094 *
1095 * 100*log10(x)
1096 * = 100*(log2(x)/log2(10)))
1097 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1098 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1099 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1100 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1101 *
1102 * where y = 2^k and 1<= (x/y) < 2
1103 */
1104
1105 static u32 log1_times100(u32 x)
1106 {
1107 static const u8 scale = 15;
1108 static const u8 index_width = 5;
1109 /*
1110 log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1111 0 <= n < ((1<<INDEXWIDTH)+1)
1112 */
1113
1114 static const u32 log2lut[] = {
1115 0, /* 0.000000 */
1116 290941, /* 290941.300628 */
1117 573196, /* 573196.476418 */
1118 847269, /* 847269.179851 */
1119 1113620, /* 1113620.489452 */
1120 1372674, /* 1372673.576986 */
1121 1624818, /* 1624817.752104 */
1122 1870412, /* 1870411.981536 */
1123 2109788, /* 2109787.962654 */
1124 2343253, /* 2343252.817465 */
1125 2571091, /* 2571091.461923 */
1126 2793569, /* 2793568.696416 */
1127 3010931, /* 3010931.055901 */
1128 3223408, /* 3223408.452106 */
1129 3431216, /* 3431215.635215 */
1130 3634553, /* 3634553.498355 */
1131 3833610, /* 3833610.244726 */
1132 4028562, /* 4028562.434393 */
1133 4219576, /* 4219575.925308 */
1134 4406807, /* 4406806.721144 */
1135 4590402, /* 4590401.736809 */
1136 4770499, /* 4770499.491025 */
1137 4947231, /* 4947230.734179 */
1138 5120719, /* 5120719.018555 */
1139 5291081, /* 5291081.217197 */
1140 5458428, /* 5458427.996830 */
1141 5622864, /* 5622864.249668 */
1142 5784489, /* 5784489.488298 */
1143 5943398, /* 5943398.207380 */
1144 6099680, /* 6099680.215452 */
1145 6253421, /* 6253420.939751 */
1146 6404702, /* 6404701.706649 */
1147 6553600, /* 6553600.000000 */
1148 };
1149
1150 u8 i = 0;
1151 u32 y = 0;
1152 u32 d = 0;
1153 u32 k = 0;
1154 u32 r = 0;
1155
1156 if (x == 0)
1157 return 0;
1158
1159 /* Scale x (normalize) */
1160 /* computing y in log(x/y) = log(x) - log(y) */
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162 for (k = scale; k > 0; k--) {
1163 if (x & (((u32) 1) << scale))
1164 break;
1165 x <<= 1;
1166 }
1167 } else {
1168 for (k = scale; k < 31; k++) {
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1170 break;
1171 x >>= 1;
1172 }
1173 }
1174 /*
1175 Now x has binary point between bit[scale] and bit[scale-1]
1176 and 1.0 <= x < 2.0 */
1177
1178 /* correction for division: log(x) = log(x/y)+log(y) */
1179 y = k * ((((u32) 1) << scale) * 200);
1180
1181 /* remove integer part */
1182 x &= ((((u32) 1) << scale) - 1);
1183 /* get index */
1184 i = (u8) (x >> (scale - index_width));
1185 /* compute delta (x-a) */
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187 /* compute log, multiplication ( d* (.. )) must be within range ! */
1188 y += log2lut[i] +
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190 /* Conver to log10() */
1191 y /= 108853; /* (log2(10) << scale) */
1192 r = (y >> 1);
1193 /* rounding */
1194 if (y & ((u32)1))
1195 r++;
1196
1197 return r;
1198
1199 }
1200
1201 /**
1202 * \fn u32 frac_times1e6( u16 N, u32 D)
1203 * \brief Compute: (N/D) * 1000000.
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1206 * \return u32
1207 * \retval ((N/D) * 1000000), 32 bits
1208 *
1209 * No check on D=0!
1210 */
1211 static u32 frac_times1e6(u32 N, u32 D)
1212 {
1213 u32 remainder = 0;
1214 u32 frac = 0;
1215
1216 /*
1217 frac = (N * 1000000) / D
1218 To let it fit in a 32 bits computation:
1219 frac = (N * (1000000 >> 4)) / (D >> 4)
1220 This would result in a problem in case D < 16 (div by 0).
1221 So we do it more elaborate as shown below.
1222 */
1223 frac = (((u32) N) * (1000000 >> 4)) / D;
1224 frac <<= 4;
1225 remainder = (((u32) N) * (1000000 >> 4)) % D;
1226 remainder <<= 4;
1227 frac += remainder / D;
1228 remainder = remainder % D;
1229 if ((remainder * 2) > D)
1230 frac++;
1231
1232 return frac;
1233 }
1234
1235 /*============================================================================*/
1236
1237
1238 /**
1239 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1240 * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1241 *
1242 */
1243 #if 0
1244 /* Currently, unused as we lack support for analog TV */
1245 static const u16 nicam_presc_table_val[43] = {
1246 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1247 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1248 18, 20, 23, 25, 28, 32, 36, 40, 45,
1249 51, 57, 64, 71, 80, 90, 101, 113, 127
1250 };
1251 #endif
1252
1253 /*============================================================================*/
1254 /*== END HELPER FUNCTIONS ==*/
1255 /*============================================================================*/
1256
1257 /*============================================================================*/
1258 /*============================================================================*/
1259 /*== DRXJ DAP FUNCTIONS ==*/
1260 /*============================================================================*/
1261 /*============================================================================*/
1262
1263 /*
1264 This layer takes care of some device specific register access protocols:
1265 -conversion to short address format
1266 -access to audio block
1267 This layer is placed between the drx_dap_fasi and the rest of the drxj
1268 specific implementation. This layer can use address map knowledge whereas
1269 dap_fasi may not use memory map knowledge.
1270
1271 * For audio currently only 16 bits read and write register access is
1272 supported. More is not needed. RMW and 32 or 8 bit access on audio
1273 registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1274 single/multi master) will be ignored.
1275
1276 TODO: check ignoring single/multimaster is ok for AUD access ?
1277 */
1278
1279 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1280 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
1281 /*============================================================================*/
1282
1283 /**
1284 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1285 * \brief Check if this address is handled by the audio token ring interface.
1286 * \param addr
1287 * \return bool
1288 * \retval true Yes, handled by audio token ring interface
1289 * \retval false No, not handled by audio token ring interface
1290 *
1291 */
1292 static
1293 bool is_handled_by_aud_tr_if(u32 addr)
1294 {
1295 bool retval = false;
1296
1297 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1300 retval = true;
1301 }
1302
1303 return retval;
1304 }
1305
1306 /*============================================================================*/
1307
1308 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1309 u16 w_count,
1310 u8 *wData,
1311 struct i2c_device_addr *r_dev_addr,
1312 u16 r_count, u8 *r_data)
1313 {
1314 struct drx39xxj_state *state;
1315 struct i2c_msg msg[2];
1316 unsigned int num_msgs;
1317
1318 if (w_dev_addr == NULL) {
1319 /* Read only */
1320 state = r_dev_addr->user_data;
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 msg[0].flags = I2C_M_RD;
1323 msg[0].buf = r_data;
1324 msg[0].len = r_count;
1325 num_msgs = 1;
1326 } else if (r_dev_addr == NULL) {
1327 /* Write only */
1328 state = w_dev_addr->user_data;
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1330 msg[0].flags = 0;
1331 msg[0].buf = wData;
1332 msg[0].len = w_count;
1333 num_msgs = 1;
1334 } else {
1335 /* Both write and read */
1336 state = w_dev_addr->user_data;
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1338 msg[0].flags = 0;
1339 msg[0].buf = wData;
1340 msg[0].len = w_count;
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 msg[1].flags = I2C_M_RD;
1343 msg[1].buf = r_data;
1344 msg[1].len = r_count;
1345 num_msgs = 2;
1346 }
1347
1348 if (state->i2c == NULL) {
1349 pr_err("i2c was zero, aborting\n");
1350 return 0;
1351 }
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1353 pr_warn("drx3933: I2C write/read failed\n");
1354 return -EREMOTEIO;
1355 }
1356
1357 #ifdef DJH_DEBUG
1358 if (w_dev_addr == NULL || r_dev_addr == NULL)
1359 return 0;
1360
1361 state = w_dev_addr->user_data;
1362
1363 if (state->i2c == NULL)
1364 return 0;
1365
1366 msg[0].addr = w_dev_addr->i2c_addr;
1367 msg[0].flags = 0;
1368 msg[0].buf = wData;
1369 msg[0].len = w_count;
1370 msg[1].addr = r_dev_addr->i2c_addr;
1371 msg[1].flags = I2C_M_RD;
1372 msg[1].buf = r_data;
1373 msg[1].len = r_count;
1374 num_msgs = 2;
1375
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1378
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) {
1380 pr_warn("drx3933: I2C write/read failed\n");
1381 return -EREMOTEIO;
1382 }
1383 #endif
1384 return 0;
1385 }
1386
1387 /*============================================================================*/
1388
1389 /******************************
1390 *
1391 * int drxdap_fasi_read_block (
1392 * struct i2c_device_addr *dev_addr, -- address of I2C device
1393 * u32 addr, -- address of chip register/memory
1394 * u16 datasize, -- number of bytes to read
1395 * u8 *data, -- data to receive
1396 * u32 flags) -- special device flags
1397 *
1398 * Read block data from chip address. Because the chip is word oriented,
1399 * the number of bytes to read must be even.
1400 *
1401 * Make sure that the buffer to receive the data is large enough.
1402 *
1403 * Although this function expects an even number of bytes, it is still byte
1404 * oriented, and the data read back is NOT translated to the endianness of
1405 * the target platform.
1406 *
1407 * Output:
1408 * - 0 if reading was successful
1409 * in that case: data read is in *data.
1410 * - -EIO if anything went wrong
1411 *
1412 ******************************/
1413
1414 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1415 u32 addr,
1416 u16 datasize,
1417 u8 *data, u32 flags)
1418 {
1419 u8 buf[4];
1420 u16 bufx;
1421 int rc;
1422 u16 overhead_size = 0;
1423
1424 /* Check parameters ******************************************************* */
1425 if (dev_addr == NULL)
1426 return -EINVAL;
1427
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1429 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1430
1431 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1432 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1433 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1434 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1435 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1436 return -EINVAL;
1437 }
1438
1439 /* ReadModifyWrite & mode flag bits are not allowed */
1440 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1441 #if DRXDAP_SINGLE_MASTER
1442 flags |= DRXDAP_FASI_SINGLE_MASTER;
1443 #endif
1444
1445 /* Read block from I2C **************************************************** */
1446 do {
1447 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1448 datasize : DRXDAP_MAX_RCHUNKSIZE);
1449
1450 bufx = 0;
1451
1452 addr &= ~DRXDAP_FASI_FLAGS;
1453 addr |= flags;
1454
1455 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1456 /* short format address preferred but long format otherwise */
1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1458 #endif
1459 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1464 #endif
1465 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1466 } else {
1467 #endif
1468 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1470 buf[bufx++] =
1471 (u8) (((addr >> 16) & 0x0F) |
1472 ((addr >> 18) & 0xF0));
1473 #endif
1474 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1475 }
1476 #endif
1477
1478 #if DRXDAP_SINGLE_MASTER
1479 /*
1480 * In single master mode, split the read and write actions.
1481 * No special action is needed for write chunks here.
1482 */
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1484 NULL, 0, NULL);
1485 if (rc == 0)
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1487 #else
1488 /* In multi master mode, do everything in one RW action */
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1490 data);
1491 #endif
1492 data += todo;
1493 addr += (todo >> 1);
1494 datasize -= todo;
1495 } while (datasize && rc == 0);
1496
1497 return rc;
1498 }
1499
1500
1501 /******************************
1502 *
1503 * int drxdap_fasi_read_reg16 (
1504 * struct i2c_device_addr *dev_addr, -- address of I2C device
1505 * u32 addr, -- address of chip register/memory
1506 * u16 *data, -- data to receive
1507 * u32 flags) -- special device flags
1508 *
1509 * Read one 16-bit register or memory location. The data received back is
1510 * converted back to the target platform's endianness.
1511 *
1512 * Output:
1513 * - 0 if reading was successful
1514 * in that case: read data is at *data
1515 * - -EIO if anything went wrong
1516 *
1517 ******************************/
1518
1519 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1520 u32 addr,
1521 u16 *data, u32 flags)
1522 {
1523 u8 buf[sizeof(*data)];
1524 int rc;
1525
1526 if (!data)
1527 return -EINVAL;
1528
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 *data = buf[0] + (((u16) buf[1]) << 8);
1531 return rc;
1532 }
1533
1534 /******************************
1535 *
1536 * int drxdap_fasi_read_reg32 (
1537 * struct i2c_device_addr *dev_addr, -- address of I2C device
1538 * u32 addr, -- address of chip register/memory
1539 * u32 *data, -- data to receive
1540 * u32 flags) -- special device flags
1541 *
1542 * Read one 32-bit register or memory location. The data received back is
1543 * converted back to the target platform's endianness.
1544 *
1545 * Output:
1546 * - 0 if reading was successful
1547 * in that case: read data is at *data
1548 * - -EIO if anything went wrong
1549 *
1550 ******************************/
1551
1552 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1553 u32 addr,
1554 u32 *data, u32 flags)
1555 {
1556 u8 buf[sizeof(*data)];
1557 int rc;
1558
1559 if (!data)
1560 return -EINVAL;
1561
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 *data = (((u32) buf[0]) << 0) +
1564 (((u32) buf[1]) << 8) +
1565 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1566 return rc;
1567 }
1568
1569 /******************************
1570 *
1571 * int drxdap_fasi_write_block (
1572 * struct i2c_device_addr *dev_addr, -- address of I2C device
1573 * u32 addr, -- address of chip register/memory
1574 * u16 datasize, -- number of bytes to read
1575 * u8 *data, -- data to receive
1576 * u32 flags) -- special device flags
1577 *
1578 * Write block data to chip address. Because the chip is word oriented,
1579 * the number of bytes to write must be even.
1580 *
1581 * Although this function expects an even number of bytes, it is still byte
1582 * oriented, and the data being written is NOT translated from the endianness of
1583 * the target platform.
1584 *
1585 * Output:
1586 * - 0 if writing was successful
1587 * - -EIO if anything went wrong
1588 *
1589 ******************************/
1590
1591 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1592 u32 addr,
1593 u16 datasize,
1594 u8 *data, u32 flags)
1595 {
1596 u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1597 int st = -EIO;
1598 int first_err = 0;
1599 u16 overhead_size = 0;
1600 u16 block_size = 0;
1601
1602 /* Check parameters ******************************************************* */
1603 if (dev_addr == NULL)
1604 return -EINVAL;
1605
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1608
1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1610 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1611 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1612 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1614 return -EINVAL;
1615
1616 flags &= DRXDAP_FASI_FLAGS;
1617 flags &= ~DRXDAP_FASI_MODEFLAGS;
1618 #if DRXDAP_SINGLE_MASTER
1619 flags |= DRXDAP_FASI_SINGLE_MASTER;
1620 #endif
1621
1622 /* Write block to I2C ***************************************************** */
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1624 do {
1625 u16 todo = 0;
1626 u16 bufx = 0;
1627
1628 /* Buffer device address */
1629 addr &= ~DRXDAP_FASI_FLAGS;
1630 addr |= flags;
1631 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1632 /* short format address preferred but long format otherwise */
1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1634 #endif
1635 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1640 #endif
1641 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1642 } else {
1643 #endif
1644 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1646 buf[bufx++] =
1647 (u8) (((addr >> 16) & 0x0F) |
1648 ((addr >> 18) & 0xF0));
1649 #endif
1650 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1651 }
1652 #endif
1653
1654 /*
1655 In single master mode block_size can be 0. In such a case this I2C
1656 sequense will be visible: (1) write address {i2c addr,
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1658 (3) write address (4) write data etc...
1659 Address must be rewriten because HI is reset after data transport and
1660 expects an address.
1661 */
1662 todo = (block_size < datasize ? block_size : datasize);
1663 if (todo == 0) {
1664 u16 overhead_size_i2c_addr = 0;
1665 u16 data_block_size = 0;
1666
1667 overhead_size_i2c_addr =
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1669 data_block_size =
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1671
1672 /* write device address */
1673 st = drxbsp_i2c_write_read(dev_addr,
1674 (u16) (bufx),
1675 buf,
1676 (struct i2c_device_addr *)(NULL),
1677 0, (u8 *)(NULL));
1678
1679 if ((st != 0) && (first_err == 0)) {
1680 /* at the end, return the first error encountered */
1681 first_err = st;
1682 }
1683 bufx = 0;
1684 todo =
1685 (data_block_size <
1686 datasize ? data_block_size : datasize);
1687 }
1688 memcpy(&buf[bufx], data, todo);
1689 /* write (address if can do and) data */
1690 st = drxbsp_i2c_write_read(dev_addr,
1691 (u16) (bufx + todo),
1692 buf,
1693 (struct i2c_device_addr *)(NULL),
1694 0, (u8 *)(NULL));
1695
1696 if ((st != 0) && (first_err == 0)) {
1697 /* at the end, return the first error encountered */
1698 first_err = st;
1699 }
1700 datasize -= todo;
1701 data += todo;
1702 addr += (todo >> 1);
1703 } while (datasize);
1704
1705 return first_err;
1706 }
1707
1708 /******************************
1709 *
1710 * int drxdap_fasi_write_reg16 (
1711 * struct i2c_device_addr *dev_addr, -- address of I2C device
1712 * u32 addr, -- address of chip register/memory
1713 * u16 data, -- data to send
1714 * u32 flags) -- special device flags
1715 *
1716 * Write one 16-bit register or memory location. The data being written is
1717 * converted from the target platform's endianness to little endian.
1718 *
1719 * Output:
1720 * - 0 if writing was successful
1721 * - -EIO if anything went wrong
1722 *
1723 ******************************/
1724
1725 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1726 u32 addr,
1727 u16 data, u32 flags)
1728 {
1729 u8 buf[sizeof(data)];
1730
1731 buf[0] = (u8) ((data >> 0) & 0xFF);
1732 buf[1] = (u8) ((data >> 8) & 0xFF);
1733
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1735 }
1736
1737 /******************************
1738 *
1739 * int drxdap_fasi_read_modify_write_reg16 (
1740 * struct i2c_device_addr *dev_addr, -- address of I2C device
1741 * u32 waddr, -- address of chip register/memory
1742 * u32 raddr, -- chip address to read back from
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1745 *
1746 * Write 16-bit data, then read back the original contents of that location.
1747 * Requires long addressing format to be allowed.
1748 *
1749 * Before sending data, the data is converted to little endian. The
1750 * data received back is converted back to the target platform's endianness.
1751 *
1752 * WARNING: This function is only guaranteed to work if there is one
1753 * master on the I2C bus.
1754 *
1755 * Output:
1756 * - 0 if reading was successful
1757 * in that case: read back data is at *rdata
1758 * - -EIO if anything went wrong
1759 *
1760 ******************************/
1761
1762 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1763 u32 waddr,
1764 u32 raddr,
1765 u16 wdata, u16 *rdata)
1766 {
1767 int rc = -EIO;
1768
1769 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1770 if (rdata == NULL)
1771 return -EINVAL;
1772
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1774 if (rc == 0)
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1776 #endif
1777
1778 return rc;
1779 }
1780
1781 /******************************
1782 *
1783 * int drxdap_fasi_write_reg32 (
1784 * struct i2c_device_addr *dev_addr, -- address of I2C device
1785 * u32 addr, -- address of chip register/memory
1786 * u32 data, -- data to send
1787 * u32 flags) -- special device flags
1788 *
1789 * Write one 32-bit register or memory location. The data being written is
1790 * converted from the target platform's endianness to little endian.
1791 *
1792 * Output:
1793 * - 0 if writing was successful
1794 * - -EIO if anything went wrong
1795 *
1796 ******************************/
1797
1798 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1799 u32 addr,
1800 u32 data, u32 flags)
1801 {
1802 u8 buf[sizeof(data)];
1803
1804 buf[0] = (u8) ((data >> 0) & 0xFF);
1805 buf[1] = (u8) ((data >> 8) & 0xFF);
1806 buf[2] = (u8) ((data >> 16) & 0xFF);
1807 buf[3] = (u8) ((data >> 24) & 0xFF);
1808
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1810 }
1811
1812 /*============================================================================*/
1813
1814 /**
1815 * \fn int drxj_dap_rm_write_reg16short
1816 * \brief Read modify write 16 bits audio register using short format only.
1817 * \param dev_addr
1818 * \param waddr Address to write to
1819 * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1820 * \param wdata Data to write
1821 * \param rdata Buffer for data to read
1822 * \return int
1823 * \retval 0 Succes
1824 * \retval -EIO Timeout, I2C error, illegal bank
1825 *
1826 * 16 bits register read modify write access using short addressing format only.
1827 * Requires knowledge of the registermap, thus device dependent.
1828 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1829 *
1830 */
1831
1832 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1833 See comments drxj_dap_read_modify_write_reg16 */
1834 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1835 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1836 u32 waddr,
1837 u32 raddr,
1838 u16 wdata, u16 *rdata)
1839 {
1840 int rc;
1841
1842 if (rdata == NULL)
1843 return -EINVAL;
1844
1845 /* Set RMW flag */
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1847 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1848 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1849 0x0000);
1850 if (rc == 0) {
1851 /* Write new data: triggers RMW */
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1853 0x0000);
1854 }
1855 if (rc == 0) {
1856 /* Read old data */
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1858 0x0000);
1859 }
1860 if (rc == 0) {
1861 /* Reset RMW flag */
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1863 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1864 0, 0x0000);
1865 }
1866
1867 return rc;
1868 }
1869 #endif
1870
1871 /*============================================================================*/
1872
1873 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1874 u32 waddr,
1875 u32 raddr,
1876 u16 wdata, u16 *rdata)
1877 {
1878 /* TODO: correct short/long addressing format decision,
1879 now long format has higher prio then short because short also
1880 needs virt bnks (not impl yet) for certain audio registers */
1881 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1882 return drxdap_fasi_read_modify_write_reg16(dev_addr,
1883 waddr,
1884 raddr, wdata, rdata);
1885 #else
1886 return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1887 #endif
1888 }
1889
1890
1891 /*============================================================================*/
1892
1893 /**
1894 * \fn int drxj_dap_read_aud_reg16
1895 * \brief Read 16 bits audio register
1896 * \param dev_addr
1897 * \param addr
1898 * \param data
1899 * \return int
1900 * \retval 0 Succes
1901 * \retval -EIO Timeout, I2C error, illegal bank
1902 *
1903 * 16 bits register read access via audio token ring interface.
1904 *
1905 */
1906 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1907 u32 addr, u16 *data)
1908 {
1909 u32 start_timer = 0;
1910 u32 current_timer = 0;
1911 u32 delta_timer = 0;
1912 u16 tr_status = 0;
1913 int stat = -EIO;
1914
1915 /* No read possible for bank 3, return with error */
1916 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1917 stat = -EINVAL;
1918 } else {
1919 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1920
1921 /* Force reset write bit */
1922 addr &= (~write_bit);
1923
1924 /* Set up read */
1925 start_timer = jiffies_to_msecs(jiffies);
1926 do {
1927 /* RMW to aud TR IF until request is granted or timeout */
1928 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1929 addr,
1930 SIO_HI_RA_RAM_S0_RMWBUF__A,
1931 0x0000, &tr_status);
1932
1933 if (stat != 0)
1934 break;
1935
1936 current_timer = jiffies_to_msecs(jiffies);
1937 delta_timer = current_timer - start_timer;
1938 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1939 stat = -EIO;
1940 break;
1941 }
1942
1943 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1944 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1945 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1946 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1947 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1948
1949 /* Wait for read ready status or timeout */
1950 if (stat == 0) {
1951 start_timer = jiffies_to_msecs(jiffies);
1952
1953 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1954 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1955 stat = drxj_dap_read_reg16(dev_addr,
1956 AUD_TOP_TR_CTR__A,
1957 &tr_status, 0x0000);
1958 if (stat != 0)
1959 break;
1960
1961 current_timer = jiffies_to_msecs(jiffies);
1962 delta_timer = current_timer - start_timer;
1963 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1964 stat = -EIO;
1965 break;
1966 }
1967 } /* while ( ... ) */
1968 }
1969
1970 /* Read value */
1971 if (stat == 0)
1972 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1973 AUD_TOP_TR_RD_REG__A,
1974 SIO_HI_RA_RAM_S0_RMWBUF__A,
1975 0x0000, data);
1976 return stat;
1977 }
1978
1979 /*============================================================================*/
1980
1981 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1982 u32 addr,
1983 u16 *data, u32 flags)
1984 {
1985 int stat = -EIO;
1986
1987 /* Check param */
1988 if ((dev_addr == NULL) || (data == NULL))
1989 return -EINVAL;
1990
1991 if (is_handled_by_aud_tr_if(addr))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1993 else
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1995
1996 return stat;
1997 }
1998 /*============================================================================*/
1999
2000 /**
2001 * \fn int drxj_dap_write_aud_reg16
2002 * \brief Write 16 bits audio register
2003 * \param dev_addr
2004 * \param addr
2005 * \param data
2006 * \return int
2007 * \retval 0 Succes
2008 * \retval -EIO Timeout, I2C error, illegal bank
2009 *
2010 * 16 bits register write access via audio token ring interface.
2011 *
2012 */
2013 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2014 u32 addr, u16 data)
2015 {
2016 int stat = -EIO;
2017
2018 /* No write possible for bank 2, return with error */
2019 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2020 stat = -EINVAL;
2021 } else {
2022 u32 start_timer = 0;
2023 u32 current_timer = 0;
2024 u32 delta_timer = 0;
2025 u16 tr_status = 0;
2026 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2027
2028 /* Force write bit */
2029 addr |= write_bit;
2030 start_timer = jiffies_to_msecs(jiffies);
2031 do {
2032 /* RMW to aud TR IF until request is granted or timeout */
2033 stat = drxj_dap_read_modify_write_reg16(dev_addr,
2034 addr,
2035 SIO_HI_RA_RAM_S0_RMWBUF__A,
2036 data, &tr_status);
2037 if (stat != 0)
2038 break;
2039
2040 current_timer = jiffies_to_msecs(jiffies);
2041 delta_timer = current_timer - start_timer;
2042 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2043 stat = -EIO;
2044 break;
2045 }
2046
2047 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2048 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2049 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2050 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2051
2052 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2053
2054 return stat;
2055 }
2056
2057 /*============================================================================*/
2058
2059 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2060 u32 addr,
2061 u16 data, u32 flags)
2062 {
2063 int stat = -EIO;
2064
2065 /* Check param */
2066 if (dev_addr == NULL)
2067 return -EINVAL;
2068
2069 if (is_handled_by_aud_tr_if(addr))
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2071 else
2072 stat = drxdap_fasi_write_reg16(dev_addr,
2073 addr, data, flags);
2074
2075 return stat;
2076 }
2077
2078 /*============================================================================*/
2079
2080 /* Free data ram in SIO HI */
2081 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2082 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2083
2084 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2085 #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2086 #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2087 #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2088
2089 /**
2090 * \fn int drxj_dap_atomic_read_write_block()
2091 * \brief Basic access routine for atomic read or write access
2092 * \param dev_addr pointer to i2c dev address
2093 * \param addr destination/source address
2094 * \param datasize size of data buffer in bytes
2095 * \param data pointer to data buffer
2096 * \return int
2097 * \retval 0 Succes
2098 * \retval -EIO Timeout, I2C error, illegal bank
2099 *
2100 */
2101 static
2102 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2103 u32 addr,
2104 u16 datasize,
2105 u8 *data, bool read_flag)
2106 {
2107 struct drxj_hi_cmd hi_cmd;
2108 int rc;
2109 u16 word;
2110 u16 dummy = 0;
2111 u16 i = 0;
2112
2113 /* Parameter check */
2114 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2115 return -EINVAL;
2116
2117 /* Set up HI parameters to read or write n bytes */
2118 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2119 hi_cmd.param1 =
2120 (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2121 DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2122 hi_cmd.param2 =
2123 (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2125 if (!read_flag)
2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2127 else
2128 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 DRXDAP_FASI_ADDR2BANK(addr));
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2132
2133 if (!read_flag) {
2134 /* write data to buffer */
2135 for (i = 0; i < (datasize / 2); i++) {
2136
2137 word = ((u16) data[2 * i]);
2138 word += (((u16) data[(2 * i) + 1]) << 8);
2139 drxj_dap_write_reg16(dev_addr,
2140 (DRXJ_HI_ATOMIC_BUF_START + i),
2141 word, 0);
2142 }
2143 }
2144
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2146 if (rc != 0) {
2147 pr_err("error %d\n", rc);
2148 goto rw_error;
2149 }
2150
2151 if (read_flag) {
2152 /* read data from buffer */
2153 for (i = 0; i < (datasize / 2); i++) {
2154 drxj_dap_read_reg16(dev_addr,
2155 (DRXJ_HI_ATOMIC_BUF_START + i),
2156 &word, 0);
2157 data[2 * i] = (u8) (word & 0xFF);
2158 data[(2 * i) + 1] = (u8) (word >> 8);
2159 }
2160 }
2161
2162 return 0;
2163
2164 rw_error:
2165 return rc;
2166
2167 }
2168
2169 /*============================================================================*/
2170
2171 /**
2172 * \fn int drxj_dap_atomic_read_reg32()
2173 * \brief Atomic read of 32 bits words
2174 */
2175 static
2176 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2177 u32 addr,
2178 u32 *data, u32 flags)
2179 {
2180 u8 buf[sizeof(*data)] = { 0 };
2181 int rc = -EIO;
2182 u32 word = 0;
2183
2184 if (!data)
2185 return -EINVAL;
2186
2187 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2188 sizeof(*data), buf, true);
2189
2190 if (rc < 0)
2191 return 0;
2192
2193 word = (u32) buf[3];
2194 word <<= 8;
2195 word |= (u32) buf[2];
2196 word <<= 8;
2197 word |= (u32) buf[1];
2198 word <<= 8;
2199 word |= (u32) buf[0];
2200
2201 *data = word;
2202
2203 return rc;
2204 }
2205
2206 /*============================================================================*/
2207
2208 /*============================================================================*/
2209 /*== END DRXJ DAP FUNCTIONS ==*/
2210 /*============================================================================*/
2211
2212 /*============================================================================*/
2213 /*============================================================================*/
2214 /*== HOST INTERFACE FUNCTIONS ==*/
2215 /*============================================================================*/
2216 /*============================================================================*/
2217
2218 /**
2219 * \fn int hi_cfg_command()
2220 * \brief Configure HI with settings stored in the demod structure.
2221 * \param demod Demodulator.
2222 * \return int.
2223 *
2224 * This routine was created because to much orthogonal settings have
2225 * been put into one HI API function (configure). Especially the I2C bridge
2226 * enable/disable should not need re-configuration of the HI.
2227 *
2228 */
2229 static int hi_cfg_command(const struct drx_demod_instance *demod)
2230 {
2231 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2232 struct drxj_hi_cmd hi_cmd;
2233 u16 result = 0;
2234 int rc;
2235
2236 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2237
2238 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2239 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2240 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2241 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2242 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2243 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2244 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2245
2246 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2247 if (rc != 0) {
2248 pr_err("error %d\n", rc);
2249 goto rw_error;
2250 }
2251
2252 /* Reset power down flag (set one call only) */
2253 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2254
2255 return 0;
2256
2257 rw_error:
2258 return rc;
2259 }
2260
2261 /**
2262 * \fn int hi_command()
2263 * \brief Configure HI with settings stored in the demod structure.
2264 * \param dev_addr I2C address.
2265 * \param cmd HI command.
2266 * \param result HI command result.
2267 * \return int.
2268 *
2269 * Sends command to HI
2270 *
2271 */
2272 static int
2273 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2274 {
2275 u16 wait_cmd = 0;
2276 u16 nr_retries = 0;
2277 bool powerdown_cmd = false;
2278 int rc;
2279
2280 /* Write parameters */
2281 switch (cmd->cmd) {
2282
2283 case SIO_HI_RA_RAM_CMD_CONFIG:
2284 case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2286 if (rc != 0) {
2287 pr_err("error %d\n", rc);
2288 goto rw_error;
2289 }
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2291 if (rc != 0) {
2292 pr_err("error %d\n", rc);
2293 goto rw_error;
2294 }
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2296 if (rc != 0) {
2297 pr_err("error %d\n", rc);
2298 goto rw_error;
2299 }
2300 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2301 if (rc != 0) {
2302 pr_err("error %d\n", rc);
2303 goto rw_error;
2304 }
2305 /* fallthrough */
2306 case SIO_HI_RA_RAM_CMD_BRDCTRL:
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2308 if (rc != 0) {
2309 pr_err("error %d\n", rc);
2310 goto rw_error;
2311 }
2312 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2313 if (rc != 0) {
2314 pr_err("error %d\n", rc);
2315 goto rw_error;
2316 }
2317 /* fallthrough */
2318 case SIO_HI_RA_RAM_CMD_NULL:
2319 /* No parameters */
2320 break;
2321
2322 default:
2323 return -EINVAL;
2324 break;
2325 }
2326
2327 /* Write command */
2328 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2329 if (rc != 0) {
2330 pr_err("error %d\n", rc);
2331 goto rw_error;
2332 }
2333
2334 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2335 msleep(1);
2336
2337 /* Detect power down to ommit reading result */
2338 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2339 (((cmd->
2340 param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2341 == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2342 if (!powerdown_cmd) {
2343 /* Wait until command rdy */
2344 do {
2345 nr_retries++;
2346 if (nr_retries > DRXJ_MAX_RETRIES) {
2347 pr_err("timeout\n");
2348 goto rw_error;
2349 }
2350
2351 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2352 if (rc != 0) {
2353 pr_err("error %d\n", rc);
2354 goto rw_error;
2355 }
2356 } while (wait_cmd != 0);
2357
2358 /* Read result */
2359 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2360 if (rc != 0) {
2361 pr_err("error %d\n", rc);
2362 goto rw_error;
2363 }
2364
2365 }
2366 /* if ( powerdown_cmd == true ) */
2367 return 0;
2368 rw_error:
2369 return rc;
2370 }
2371
2372 /**
2373 * \fn int init_hi( const struct drx_demod_instance *demod )
2374 * \brief Initialise and configurate HI.
2375 * \param demod pointer to demod data.
2376 * \return int Return status.
2377 * \retval 0 Success.
2378 * \retval -EIO Failure.
2379 *
2380 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2381 * Need to store configuration in driver because of the way I2C
2382 * bridging is controlled.
2383 *
2384 */
2385 static int init_hi(const struct drx_demod_instance *demod)
2386 {
2387 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2388 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2389 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2390 int rc;
2391
2392 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2393 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2394 dev_addr = demod->my_i2c_dev_addr;
2395
2396 /* PATCH for bug 5003, HI ucode v3.1.0 */
2397 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2398 if (rc != 0) {
2399 pr_err("error %d\n", rc);
2400 goto rw_error;
2401 }
2402
2403 /* Timing div, 250ns/Psys */
2404 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2405 ext_attr->hi_cfg_timing_div =
2406 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2407 /* Clipping */
2408 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2409 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2410 /* Bridge delay, uses oscilator clock */
2411 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2412 /* SDA brdige delay */
2413 ext_attr->hi_cfg_bridge_delay =
2414 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2415 1000;
2416 /* Clipping */
2417 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2418 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2419 /* SCL bridge delay, same as SDA for now */
2420 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2421 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2422 /* Wakeup key, setting the read flag (as suggest in the documentation) does
2423 not always result into a working solution (barebones worked VI2C failed).
2424 Not setting the bit works in all cases . */
2425 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2426 /* port/bridge/power down ctrl */
2427 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2428 /* transit mode time out delay and watch dog divider */
2429 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2430
2431 rc = hi_cfg_command(demod);
2432 if (rc != 0) {
2433 pr_err("error %d\n", rc);
2434 goto rw_error;
2435 }
2436
2437 return 0;
2438
2439 rw_error:
2440 return rc;
2441 }
2442
2443 /*============================================================================*/
2444 /*== END HOST INTERFACE FUNCTIONS ==*/
2445 /*============================================================================*/
2446
2447 /*============================================================================*/
2448 /*============================================================================*/
2449 /*== AUXILIARY FUNCTIONS ==*/
2450 /*============================================================================*/
2451 /*============================================================================*/
2452
2453 /**
2454 * \fn int get_device_capabilities()
2455 * \brief Get and store device capabilities.
2456 * \param demod Pointer to demodulator instance.
2457 * \return int.
2458 * \return 0 Success
2459 * \retval -EIO Failure
2460 *
2461 * Depending on pulldowns on MDx pins the following internals are set:
2462 * * common_attr->osc_clock_freq
2463 * * ext_attr->has_lna
2464 * * ext_attr->has_ntsc
2465 * * ext_attr->has_btsc
2466 * * ext_attr->has_oob
2467 *
2468 */
2469 static int get_device_capabilities(struct drx_demod_instance *demod)
2470 {
2471 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2472 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2473 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2474 u16 sio_pdr_ohw_cfg = 0;
2475 u32 sio_top_jtagid_lo = 0;
2476 u16 bid = 0;
2477 int rc;
2478
2479 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2480 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2481 dev_addr = demod->my_i2c_dev_addr;
2482
2483 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2484 if (rc != 0) {
2485 pr_err("error %d\n", rc);
2486 goto rw_error;
2487 }
2488 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2489 if (rc != 0) {
2490 pr_err("error %d\n", rc);
2491 goto rw_error;
2492 }
2493 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2494 if (rc != 0) {
2495 pr_err("error %d\n", rc);
2496 goto rw_error;
2497 }
2498
2499 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2500 case 0:
2501 /* ignore (bypass ?) */
2502 break;
2503 case 1:
2504 /* 27 MHz */
2505 common_attr->osc_clock_freq = 27000;
2506 break;
2507 case 2:
2508 /* 20.25 MHz */
2509 common_attr->osc_clock_freq = 20250;
2510 break;
2511 case 3:
2512 /* 4 MHz */
2513 common_attr->osc_clock_freq = 4000;
2514 break;
2515 default:
2516 return -EIO;
2517 }
2518
2519 /*
2520 Determine device capabilities
2521 Based on pinning v47
2522 */
2523 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2524 if (rc != 0) {
2525 pr_err("error %d\n", rc);
2526 goto rw_error;
2527 }
2528 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2529
2530 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2531 case 0x31:
2532 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2533 if (rc != 0) {
2534 pr_err("error %d\n", rc);
2535 goto rw_error;
2536 }
2537 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2538 if (rc != 0) {
2539 pr_err("error %d\n", rc);
2540 goto rw_error;
2541 }
2542 bid = (bid >> 10) & 0xf;
2543 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2544 if (rc != 0) {
2545 pr_err("error %d\n", rc);
2546 goto rw_error;
2547 }
2548
2549 ext_attr->has_lna = true;
2550 ext_attr->has_ntsc = false;
2551 ext_attr->has_btsc = false;
2552 ext_attr->has_oob = false;
2553 ext_attr->has_smatx = true;
2554 ext_attr->has_smarx = false;
2555 ext_attr->has_gpio = false;
2556 ext_attr->has_irqn = false;
2557 break;
2558 case 0x33:
2559 ext_attr->has_lna = false;
2560 ext_attr->has_ntsc = false;
2561 ext_attr->has_btsc = false;
2562 ext_attr->has_oob = false;
2563 ext_attr->has_smatx = true;
2564 ext_attr->has_smarx = false;
2565 ext_attr->has_gpio = false;
2566 ext_attr->has_irqn = false;
2567 break;
2568 case 0x45:
2569 ext_attr->has_lna = true;
2570 ext_attr->has_ntsc = true;
2571 ext_attr->has_btsc = false;
2572 ext_attr->has_oob = false;
2573 ext_attr->has_smatx = true;
2574 ext_attr->has_smarx = true;
2575 ext_attr->has_gpio = true;
2576 ext_attr->has_irqn = false;
2577 break;
2578 case 0x46:
2579 ext_attr->has_lna = false;
2580 ext_attr->has_ntsc = true;
2581 ext_attr->has_btsc = false;
2582 ext_attr->has_oob = false;
2583 ext_attr->has_smatx = true;
2584 ext_attr->has_smarx = true;
2585 ext_attr->has_gpio = true;
2586 ext_attr->has_irqn = false;
2587 break;
2588 case 0x41:
2589 ext_attr->has_lna = true;
2590 ext_attr->has_ntsc = true;
2591 ext_attr->has_btsc = true;
2592 ext_attr->has_oob = false;
2593 ext_attr->has_smatx = true;
2594 ext_attr->has_smarx = true;
2595 ext_attr->has_gpio = true;
2596 ext_attr->has_irqn = false;
2597 break;
2598 case 0x43:
2599 ext_attr->has_lna = false;
2600 ext_attr->has_ntsc = true;
2601 ext_attr->has_btsc = true;
2602 ext_attr->has_oob = false;
2603 ext_attr->has_smatx = true;
2604 ext_attr->has_smarx = true;
2605 ext_attr->has_gpio = true;
2606 ext_attr->has_irqn = false;
2607 break;
2608 case 0x32:
2609 ext_attr->has_lna = true;
2610 ext_attr->has_ntsc = false;
2611 ext_attr->has_btsc = false;
2612 ext_attr->has_oob = true;
2613 ext_attr->has_smatx = true;
2614 ext_attr->has_smarx = true;
2615 ext_attr->has_gpio = true;
2616 ext_attr->has_irqn = true;
2617 break;
2618 case 0x34:
2619 ext_attr->has_lna = false;
2620 ext_attr->has_ntsc = true;
2621 ext_attr->has_btsc = true;
2622 ext_attr->has_oob = true;
2623 ext_attr->has_smatx = true;
2624 ext_attr->has_smarx = true;
2625 ext_attr->has_gpio = true;
2626 ext_attr->has_irqn = true;
2627 break;
2628 case 0x42:
2629 ext_attr->has_lna = true;
2630 ext_attr->has_ntsc = true;
2631 ext_attr->has_btsc = true;
2632 ext_attr->has_oob = true;
2633 ext_attr->has_smatx = true;
2634 ext_attr->has_smarx = true;
2635 ext_attr->has_gpio = true;
2636 ext_attr->has_irqn = true;
2637 break;
2638 case 0x44:
2639 ext_attr->has_lna = false;
2640 ext_attr->has_ntsc = true;
2641 ext_attr->has_btsc = true;
2642 ext_attr->has_oob = true;
2643 ext_attr->has_smatx = true;
2644 ext_attr->has_smarx = true;
2645 ext_attr->has_gpio = true;
2646 ext_attr->has_irqn = true;
2647 break;
2648 default:
2649 /* Unknown device variant */
2650 return -EIO;
2651 break;
2652 }
2653
2654 return 0;
2655 rw_error:
2656 return rc;
2657 }
2658
2659 /**
2660 * \fn int power_up_device()
2661 * \brief Power up device.
2662 * \param demod Pointer to demodulator instance.
2663 * \return int.
2664 * \return 0 Success
2665 * \retval -EIO Failure, I2C or max retries reached
2666 *
2667 */
2668
2669 #ifndef DRXJ_MAX_RETRIES_POWERUP
2670 #define DRXJ_MAX_RETRIES_POWERUP 10
2671 #endif
2672
2673 static int power_up_device(struct drx_demod_instance *demod)
2674 {
2675 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2676 u8 data = 0;
2677 u16 retry_count = 0;
2678 struct i2c_device_addr wake_up_addr;
2679
2680 dev_addr = demod->my_i2c_dev_addr;
2681 wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2682 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2683 wake_up_addr.user_data = dev_addr->user_data;
2684 /*
2685 * I2C access may fail in this case: no ack
2686 * dummy write must be used to wake uop device, dummy read must be used to
2687 * reset HI state machine (avoiding actual writes)
2688 */
2689 do {
2690 data = 0;
2691 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2692 (struct i2c_device_addr *)(NULL), 0,
2693 (u8 *)(NULL));
2694 msleep(10);
2695 retry_count++;
2696 } while ((drxbsp_i2c_write_read
2697 ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2698 &data)
2699 != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2700
2701 /* Need some recovery time .... */
2702 msleep(10);
2703
2704 if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2705 return -EIO;
2706
2707 return 0;
2708 }
2709
2710 /*----------------------------------------------------------------------------*/
2711 /* MPEG Output Configuration Functions - begin */
2712 /*----------------------------------------------------------------------------*/
2713 /**
2714 * \fn int ctrl_set_cfg_mpeg_output()
2715 * \brief Set MPEG output configuration of the device.
2716 * \param devmod Pointer to demodulator instance.
2717 * \param cfg_data Pointer to mpeg output configuaration.
2718 * \return int.
2719 *
2720 * Configure MPEG output parameters.
2721 *
2722 */
2723 static int
2724 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2725 {
2726 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2727 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2728 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2729 int rc;
2730 u16 fec_oc_reg_mode = 0;
2731 u16 fec_oc_reg_ipr_mode = 0;
2732 u16 fec_oc_reg_ipr_invert = 0;
2733 u32 max_bit_rate = 0;
2734 u32 rcn_rate = 0;
2735 u32 nr_bits = 0;
2736 u16 sio_pdr_md_cfg = 0;
2737 /* data mask for the output data byte */
2738 u16 invert_data_mask =
2739 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2740 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2741 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2742 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2743
2744 /* check arguments */
2745 if ((demod == NULL) || (cfg_data == NULL))
2746 return -EINVAL;
2747
2748 dev_addr = demod->my_i2c_dev_addr;
2749 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2750 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2751
2752 if (cfg_data->enable_mpeg_output == true) {
2753 /* quick and dirty patch to set MPEG incase current std is not
2754 producing MPEG */
2755 switch (ext_attr->standard) {
2756 case DRX_STANDARD_8VSB:
2757 case DRX_STANDARD_ITU_A:
2758 case DRX_STANDARD_ITU_B:
2759 case DRX_STANDARD_ITU_C:
2760 break;
2761 default:
2762 return 0;
2763 }
2764
2765 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2766 if (rc != 0) {
2767 pr_err("error %d\n", rc);
2768 goto rw_error;
2769 }
2770 switch (ext_attr->standard) {
2771 case DRX_STANDARD_8VSB:
2772 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2773 if (rc != 0) {
2774 pr_err("error %d\n", rc);
2775 goto rw_error;
2776 } /* 2048 bytes fifo ram */
2777 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2778 if (rc != 0) {
2779 pr_err("error %d\n", rc);
2780 goto rw_error;
2781 }
2782 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2783 if (rc != 0) {
2784 pr_err("error %d\n", rc);
2785 goto rw_error;
2786 }
2787 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2788 if (rc != 0) {
2789 pr_err("error %d\n", rc);
2790 goto rw_error;
2791 }
2792 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2793 if (rc != 0) {
2794 pr_err("error %d\n", rc);
2795 goto rw_error;
2796 }
2797 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2798 if (rc != 0) {
2799 pr_err("error %d\n", rc);
2800 goto rw_error;
2801 }
2802 /* Low Water Mark for synchronization */
2803 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2804 if (rc != 0) {
2805 pr_err("error %d\n", rc);
2806 goto rw_error;
2807 }
2808 /* High Water Mark for synchronization */
2809 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2810 if (rc != 0) {
2811 pr_err("error %d\n", rc);
2812 goto rw_error;
2813 }
2814 break;
2815 case DRX_STANDARD_ITU_A:
2816 case DRX_STANDARD_ITU_C:
2817 switch (ext_attr->constellation) {
2818 case DRX_CONSTELLATION_QAM256:
2819 nr_bits = 8;
2820 break;
2821 case DRX_CONSTELLATION_QAM128:
2822 nr_bits = 7;
2823 break;
2824 case DRX_CONSTELLATION_QAM64:
2825 nr_bits = 6;
2826 break;
2827 case DRX_CONSTELLATION_QAM32:
2828 nr_bits = 5;
2829 break;
2830 case DRX_CONSTELLATION_QAM16:
2831 nr_bits = 4;
2832 break;
2833 default:
2834 return -EIO;
2835 } /* ext_attr->constellation */
2836 /* max_bit_rate = symbol_rate * nr_bits * coef */
2837 /* coef = 188/204 */
2838 max_bit_rate =
2839 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2840 /* pass through b/c Annex A/c need following settings */
2841 case DRX_STANDARD_ITU_B:
2842 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2843 if (rc != 0) {
2844 pr_err("error %d\n", rc);
2845 goto rw_error;
2846 }
2847 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2848 if (rc != 0) {
2849 pr_err("error %d\n", rc);
2850 goto rw_error;
2851 }
2852 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2853 if (rc != 0) {
2854 pr_err("error %d\n", rc);
2855 goto rw_error;
2856 }
2857 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2858 if (rc != 0) {
2859 pr_err("error %d\n", rc);
2860 goto rw_error;
2861 }
2862 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2863 if (rc != 0) {
2864 pr_err("error %d\n", rc);
2865 goto rw_error;
2866 }
2867 if (cfg_data->static_clk == true) {
2868 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2869 if (rc != 0) {
2870 pr_err("error %d\n", rc);
2871 goto rw_error;
2872 }
2873 } else {
2874 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2875 if (rc != 0) {
2876 pr_err("error %d\n", rc);
2877 goto rw_error;
2878 }
2879 }
2880 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2881 if (rc != 0) {
2882 pr_err("error %d\n", rc);
2883 goto rw_error;
2884 }
2885 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2886 if (rc != 0) {
2887 pr_err("error %d\n", rc);
2888 goto rw_error;
2889 }
2890 break;
2891 default:
2892 break;
2893 } /* swtich (standard) */
2894
2895 /* Check insertion of the Reed-Solomon parity bytes */
2896 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2897 if (rc != 0) {
2898 pr_err("error %d\n", rc);
2899 goto rw_error;
2900 }
2901 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2902 if (rc != 0) {
2903 pr_err("error %d\n", rc);
2904 goto rw_error;
2905 }
2906 if (cfg_data->insert_rs_byte == true) {
2907 /* enable parity symbol forward */
2908 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2909 /* MVAL disable during parity bytes */
2910 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2911 switch (ext_attr->standard) {
2912 case DRX_STANDARD_8VSB:
2913 rcn_rate = 0x004854D3;
2914 break;
2915 case DRX_STANDARD_ITU_B:
2916 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2917 switch (ext_attr->constellation) {
2918 case DRX_CONSTELLATION_QAM256:
2919 rcn_rate = 0x008945E7;
2920 break;
2921 case DRX_CONSTELLATION_QAM64:
2922 rcn_rate = 0x005F64D4;
2923 break;
2924 default:
2925 return -EIO;
2926 }
2927 break;
2928 case DRX_STANDARD_ITU_A:
2929 case DRX_STANDARD_ITU_C:
2930 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2931 rcn_rate =
2932 (frac28
2933 (max_bit_rate,
2934 (u32) (common_attr->sys_clock_freq / 8))) /
2935 188;
2936 break;
2937 default:
2938 return -EIO;
2939 } /* ext_attr->standard */
2940 } else { /* insert_rs_byte == false */
2941
2942 /* disable parity symbol forward */
2943 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2944 /* MVAL enable during parity bytes */
2945 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2946 switch (ext_attr->standard) {
2947 case DRX_STANDARD_8VSB:
2948 rcn_rate = 0x0041605C;
2949 break;
2950 case DRX_STANDARD_ITU_B:
2951 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2952 switch (ext_attr->constellation) {
2953 case DRX_CONSTELLATION_QAM256:
2954 rcn_rate = 0x0082D6A0;
2955 break;
2956 case DRX_CONSTELLATION_QAM64:
2957 rcn_rate = 0x005AEC1A;
2958 break;
2959 default:
2960 return -EIO;
2961 }
2962 break;
2963 case DRX_STANDARD_ITU_A:
2964 case DRX_STANDARD_ITU_C:
2965 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2966 rcn_rate =
2967 (frac28
2968 (max_bit_rate,
2969 (u32) (common_attr->sys_clock_freq / 8))) /
2970 204;
2971 break;
2972 default:
2973 return -EIO;
2974 } /* ext_attr->standard */
2975 }
2976
2977 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
2978 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2979 } else { /* MPEG data output is serial -> set ipr_mode[0] */
2980 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2981 }
2982
2983 /* Control slective inversion of output bits */
2984 if (cfg_data->invert_data == true)
2985 fec_oc_reg_ipr_invert |= invert_data_mask;
2986 else
2987 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2988
2989 if (cfg_data->invert_err == true)
2990 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2991 else
2992 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2993
2994 if (cfg_data->invert_str == true)
2995 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2996 else
2997 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2998
2999 if (cfg_data->invert_val == true)
3000 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
3001 else
3002 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3003
3004 if (cfg_data->invert_clk == true)
3005 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3006 else
3007 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3008
3009
3010 if (cfg_data->static_clk == true) { /* Static mode */
3011 u32 dto_rate = 0;
3012 u32 bit_rate = 0;
3013 u16 fec_oc_dto_burst_len = 0;
3014 u16 fec_oc_dto_period = 0;
3015
3016 fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3017
3018 switch (ext_attr->standard) {
3019 case DRX_STANDARD_8VSB:
3020 fec_oc_dto_period = 4;
3021 if (cfg_data->insert_rs_byte == true)
3022 fec_oc_dto_burst_len = 208;
3023 break;
3024 case DRX_STANDARD_ITU_A:
3025 {
3026 u32 symbol_rate_th = 6400000;
3027 if (cfg_data->insert_rs_byte == true) {
3028 fec_oc_dto_burst_len = 204;
3029 symbol_rate_th = 5900000;
3030 }
3031 if (ext_attr->curr_symbol_rate >=
3032 symbol_rate_th) {
3033 fec_oc_dto_period = 0;
3034 } else {
3035 fec_oc_dto_period = 1;
3036 }
3037 }
3038 break;
3039 case DRX_STANDARD_ITU_B:
3040 fec_oc_dto_period = 1;
3041 if (cfg_data->insert_rs_byte == true)
3042 fec_oc_dto_burst_len = 128;
3043 break;
3044 case DRX_STANDARD_ITU_C:
3045 fec_oc_dto_period = 1;
3046 if (cfg_data->insert_rs_byte == true)
3047 fec_oc_dto_burst_len = 204;
3048 break;
3049 default:
3050 return -EIO;
3051 }
3052 bit_rate =
3053 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3054 2);
3055 dto_rate =
3056 frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3057 dto_rate >>= 3;
3058 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3059 if (rc != 0) {
3060 pr_err("error %d\n", rc);
3061 goto rw_error;
3062 }
3063 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3064 if (rc != 0) {
3065 pr_err("error %d\n", rc);
3066 goto rw_error;
3067 }
3068 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3069 if (rc != 0) {
3070 pr_err("error %d\n", rc);
3071 goto rw_error;
3072 }
3073 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3074 if (rc != 0) {
3075 pr_err("error %d\n", rc);
3076 goto rw_error;
3077 }
3078 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3079 if (rc != 0) {
3080 pr_err("error %d\n", rc);
3081 goto rw_error;
3082 }
3083 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3084 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3085 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3086 if (rc != 0) {
3087 pr_err("error %d\n", rc);
3088 goto rw_error;
3089 }
3090 } else { /* Dynamic mode */
3091
3092 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3093 if (rc != 0) {
3094 pr_err("error %d\n", rc);
3095 goto rw_error;
3096 }
3097 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3098 if (rc != 0) {
3099 pr_err("error %d\n", rc);
3100 goto rw_error;
3101 }
3102 }
3103
3104 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3105 if (rc != 0) {
3106 pr_err("error %d\n", rc);
3107 goto rw_error;
3108 }
3109
3110 /* Write appropriate registers with requested configuration */
3111 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3112 if (rc != 0) {
3113 pr_err("error %d\n", rc);
3114 goto rw_error;
3115 }
3116 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3117 if (rc != 0) {
3118 pr_err("error %d\n", rc);
3119 goto rw_error;
3120 }
3121 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3122 if (rc != 0) {
3123 pr_err("error %d\n", rc);
3124 goto rw_error;
3125 }
3126
3127 /* enabling for both parallel and serial now */
3128 /* Write magic word to enable pdr reg write */
3129 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3130 if (rc != 0) {
3131 pr_err("error %d\n", rc);
3132 goto rw_error;
3133 }
3134 /* Set MPEG TS pads to outputmode */
3135 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3136 if (rc != 0) {
3137 pr_err("error %d\n", rc);
3138 goto rw_error;
3139 }
3140 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3141 if (rc != 0) {
3142 pr_err("error %d\n", rc);
3143 goto rw_error;
3144 }
3145 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3146 if (rc != 0) {
3147 pr_err("error %d\n", rc);
3148 goto rw_error;
3149 }
3150 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3151 if (rc != 0) {
3152 pr_err("error %d\n", rc);
3153 goto rw_error;
3154 }
3155 sio_pdr_md_cfg =
3156 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3157 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3158 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3159 if (rc != 0) {
3160 pr_err("error %d\n", rc);
3161 goto rw_error;
3162 }
3163 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3164 sio_pdr_md_cfg =
3165 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3166 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3167 SIO_PDR_MD0_CFG_MODE__B;
3168 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3169 if (rc != 0) {
3170 pr_err("error %d\n", rc);
3171 goto rw_error;
3172 }
3173 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3174 if (rc != 0) {
3175 pr_err("error %d\n", rc);
3176 goto rw_error;
3177 }
3178 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3179 if (rc != 0) {
3180 pr_err("error %d\n", rc);
3181 goto rw_error;
3182 }
3183 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3184 if (rc != 0) {
3185 pr_err("error %d\n", rc);
3186 goto rw_error;
3187 }
3188 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3189 if (rc != 0) {
3190 pr_err("error %d\n", rc);
3191 goto rw_error;
3192 }
3193 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3194 if (rc != 0) {
3195 pr_err("error %d\n", rc);
3196 goto rw_error;
3197 }
3198 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3199 if (rc != 0) {
3200 pr_err("error %d\n", rc);
3201 goto rw_error;
3202 }
3203 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3204 if (rc != 0) {
3205 pr_err("error %d\n", rc);
3206 goto rw_error;
3207 }
3208 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3209 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3210 if (rc != 0) {
3211 pr_err("error %d\n", rc);
3212 goto rw_error;
3213 }
3214 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3215 if (rc != 0) {
3216 pr_err("error %d\n", rc);
3217 goto rw_error;
3218 }
3219 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3220 if (rc != 0) {
3221 pr_err("error %d\n", rc);
3222 goto rw_error;
3223 }
3224 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3225 if (rc != 0) {
3226 pr_err("error %d\n", rc);
3227 goto rw_error;
3228 }
3229 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3230 if (rc != 0) {
3231 pr_err("error %d\n", rc);
3232 goto rw_error;
3233 }
3234 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3235 if (rc != 0) {
3236 pr_err("error %d\n", rc);
3237 goto rw_error;
3238 }
3239 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3240 if (rc != 0) {
3241 pr_err("error %d\n", rc);
3242 goto rw_error;
3243 }
3244 }
3245 /* Enable Monitor Bus output over MPEG pads and ctl input */
3246 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3247 if (rc != 0) {
3248 pr_err("error %d\n", rc);
3249 goto rw_error;
3250 }
3251 /* Write nomagic word to enable pdr reg write */
3252 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3253 if (rc != 0) {
3254 pr_err("error %d\n", rc);
3255 goto rw_error;
3256 }
3257 } else {
3258 /* Write magic word to enable pdr reg write */
3259 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3260 if (rc != 0) {
3261 pr_err("error %d\n", rc);
3262 goto rw_error;
3263 }
3264 /* Set MPEG TS pads to inputmode */
3265 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3266 if (rc != 0) {
3267 pr_err("error %d\n", rc);
3268 goto rw_error;
3269 }
3270 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3271 if (rc != 0) {
3272 pr_err("error %d\n", rc);
3273 goto rw_error;
3274 }
3275 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3276 if (rc != 0) {
3277 pr_err("error %d\n", rc);
3278 goto rw_error;
3279 }
3280 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3281 if (rc != 0) {
3282 pr_err("error %d\n", rc);
3283 goto rw_error;
3284 }
3285 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3286 if (rc != 0) {
3287 pr_err("error %d\n", rc);
3288 goto rw_error;
3289 }
3290 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3291 if (rc != 0) {
3292 pr_err("error %d\n", rc);
3293 goto rw_error;
3294 }
3295 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3296 if (rc != 0) {
3297 pr_err("error %d\n", rc);
3298 goto rw_error;
3299 }
3300 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3301 if (rc != 0) {
3302 pr_err("error %d\n", rc);
3303 goto rw_error;
3304 }
3305 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3306 if (rc != 0) {
3307 pr_err("error %d\n", rc);
3308 goto rw_error;
3309 }
3310 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3311 if (rc != 0) {
3312 pr_err("error %d\n", rc);
3313 goto rw_error;
3314 }
3315 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3316 if (rc != 0) {
3317 pr_err("error %d\n", rc);
3318 goto rw_error;
3319 }
3320 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3321 if (rc != 0) {
3322 pr_err("error %d\n", rc);
3323 goto rw_error;
3324 }
3325 /* Enable Monitor Bus output over MPEG pads and ctl input */
3326 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3327 if (rc != 0) {
3328 pr_err("error %d\n", rc);
3329 goto rw_error;
3330 }
3331 /* Write nomagic word to enable pdr reg write */
3332 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3333 if (rc != 0) {
3334 pr_err("error %d\n", rc);
3335 goto rw_error;
3336 }
3337 }
3338
3339 /* save values for restore after re-acquire */
3340 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3341
3342 return 0;
3343 rw_error:
3344 return rc;
3345 }
3346
3347 /*----------------------------------------------------------------------------*/
3348
3349
3350 /*----------------------------------------------------------------------------*/
3351 /* MPEG Output Configuration Functions - end */
3352 /*----------------------------------------------------------------------------*/
3353
3354 /*----------------------------------------------------------------------------*/
3355 /* miscellaneous configuartions - begin */
3356 /*----------------------------------------------------------------------------*/
3357
3358 /**
3359 * \fn int set_mpegtei_handling()
3360 * \brief Activate MPEG TEI handling settings.
3361 * \param devmod Pointer to demodulator instance.
3362 * \return int.
3363 *
3364 * This routine should be called during a set channel of QAM/VSB
3365 *
3366 */
3367 static int set_mpegtei_handling(struct drx_demod_instance *demod)
3368 {
3369 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3370 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3371 int rc;
3372 u16 fec_oc_dpr_mode = 0;
3373 u16 fec_oc_snc_mode = 0;
3374 u16 fec_oc_ems_mode = 0;
3375
3376 dev_addr = demod->my_i2c_dev_addr;
3377 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3378
3379 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3380 if (rc != 0) {
3381 pr_err("error %d\n", rc);
3382 goto rw_error;
3383 }
3384 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3385 if (rc != 0) {
3386 pr_err("error %d\n", rc);
3387 goto rw_error;
3388 }
3389 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3390 if (rc != 0) {
3391 pr_err("error %d\n", rc);
3392 goto rw_error;
3393 }
3394
3395 /* reset to default, allow TEI bit to be changed */
3396 fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3397 fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3398 FEC_OC_SNC_MODE_CORR_DISABLE__M));
3399 fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3400
3401 if (ext_attr->disable_te_ihandling) {
3402 /* do not change TEI bit */
3403 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3404 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3405 ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3406 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3407 }
3408
3409 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3410 if (rc != 0) {
3411 pr_err("error %d\n", rc);
3412 goto rw_error;
3413 }
3414 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3415 if (rc != 0) {
3416 pr_err("error %d\n", rc);
3417 goto rw_error;
3418 }
3419 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3420 if (rc != 0) {
3421 pr_err("error %d\n", rc);
3422 goto rw_error;
3423 }
3424
3425 return 0;
3426 rw_error:
3427 return rc;
3428 }
3429
3430 /*----------------------------------------------------------------------------*/
3431 /**
3432 * \fn int bit_reverse_mpeg_output()
3433 * \brief Set MPEG output bit-endian settings.
3434 * \param devmod Pointer to demodulator instance.
3435 * \return int.
3436 *
3437 * This routine should be called during a set channel of QAM/VSB
3438 *
3439 */
3440 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3441 {
3442 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3443 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3444 int rc;
3445 u16 fec_oc_ipr_mode = 0;
3446
3447 dev_addr = demod->my_i2c_dev_addr;
3448 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3449
3450 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3451 if (rc != 0) {
3452 pr_err("error %d\n", rc);
3453 goto rw_error;
3454 }
3455
3456 /* reset to default (normal bit order) */
3457 fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3458
3459 if (ext_attr->bit_reverse_mpeg_outout)
3460 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3461
3462 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3463 if (rc != 0) {
3464 pr_err("error %d\n", rc);
3465 goto rw_error;
3466 }
3467
3468 return 0;
3469 rw_error:
3470 return rc;
3471 }
3472
3473 /*----------------------------------------------------------------------------*/
3474 /**
3475 * \fn int set_mpeg_start_width()
3476 * \brief Set MPEG start width.
3477 * \param devmod Pointer to demodulator instance.
3478 * \return int.
3479 *
3480 * This routine should be called during a set channel of QAM/VSB
3481 *
3482 */
3483 static int set_mpeg_start_width(struct drx_demod_instance *demod)
3484 {
3485 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3486 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3487 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3488 int rc;
3489 u16 fec_oc_comm_mb = 0;
3490
3491 dev_addr = demod->my_i2c_dev_addr;
3492 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3493 common_attr = demod->my_common_attr;
3494
3495 if ((common_attr->mpeg_cfg.static_clk == true)
3496 && (common_attr->mpeg_cfg.enable_parallel == false)) {
3497 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3498 if (rc != 0) {
3499 pr_err("error %d\n", rc);
3500 goto rw_error;
3501 }
3502 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3503 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3504 fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3505 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3506 if (rc != 0) {
3507 pr_err("error %d\n", rc);
3508 goto rw_error;
3509 }
3510 }
3511
3512 return 0;
3513 rw_error:
3514 return rc;
3515 }
3516
3517 /*----------------------------------------------------------------------------*/
3518 /* miscellaneous configuartions - end */
3519 /*----------------------------------------------------------------------------*/
3520
3521 /*----------------------------------------------------------------------------*/
3522 /* UIO Configuration Functions - begin */
3523 /*----------------------------------------------------------------------------*/
3524 /**
3525 * \fn int ctrl_set_uio_cfg()
3526 * \brief Configure modus oprandi UIO.
3527 * \param demod Pointer to demodulator instance.
3528 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3529 * \return int.
3530 */
3531 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3532 {
3533 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3534 int rc;
3535
3536 if ((uio_cfg == NULL) || (demod == NULL))
3537 return -EINVAL;
3538
3539 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3540
3541 /* Write magic word to enable pdr reg write */
3542 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3543 if (rc != 0) {
3544 pr_err("error %d\n", rc);
3545 goto rw_error;
3546 }
3547 switch (uio_cfg->uio) {
3548 /*====================================================================*/
3549 case DRX_UIO1:
3550 /* DRX_UIO1: SMA_TX UIO-1 */
3551 if (!ext_attr->has_smatx)
3552 return -EIO;
3553 switch (uio_cfg->mode) {
3554 case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
3555 case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */
3556 case DRX_UIO_MODE_READWRITE:
3557 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3558 break;
3559 case DRX_UIO_MODE_DISABLE:
3560 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3561 /* pad configuration register is set 0 - input mode */
3562 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3563 if (rc != 0) {
3564 pr_err("error %d\n", rc);
3565 goto rw_error;
3566 }
3567 break;
3568 default:
3569 return -EINVAL;
3570 } /* switch ( uio_cfg->mode ) */
3571 break;
3572 /*====================================================================*/
3573 case DRX_UIO2:
3574 /* DRX_UIO2: SMA_RX UIO-2 */
3575 if (!ext_attr->has_smarx)
3576 return -EIO;
3577 switch (uio_cfg->mode) {
3578 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3579 case DRX_UIO_MODE_READWRITE:
3580 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3581 break;
3582 case DRX_UIO_MODE_DISABLE:
3583 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3584 /* pad configuration register is set 0 - input mode */
3585 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3586 if (rc != 0) {
3587 pr_err("error %d\n", rc);
3588 goto rw_error;
3589 }
3590 break;
3591 default:
3592 return -EINVAL;
3593 break;
3594 } /* switch ( uio_cfg->mode ) */
3595 break;
3596 /*====================================================================*/
3597 case DRX_UIO3:
3598 /* DRX_UIO3: GPIO UIO-3 */
3599 if (!ext_attr->has_gpio)
3600 return -EIO;
3601 switch (uio_cfg->mode) {
3602 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3603 case DRX_UIO_MODE_READWRITE:
3604 ext_attr->uio_gpio_mode = uio_cfg->mode;
3605 break;
3606 case DRX_UIO_MODE_DISABLE:
3607 ext_attr->uio_gpio_mode = uio_cfg->mode;
3608 /* pad configuration register is set 0 - input mode */
3609 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3610 if (rc != 0) {
3611 pr_err("error %d\n", rc);
3612 goto rw_error;
3613 }
3614 break;
3615 default:
3616 return -EINVAL;
3617 break;
3618 } /* switch ( uio_cfg->mode ) */
3619 break;
3620 /*====================================================================*/
3621 case DRX_UIO4:
3622 /* DRX_UIO4: IRQN UIO-4 */
3623 if (!ext_attr->has_irqn)
3624 return -EIO;
3625 switch (uio_cfg->mode) {
3626 case DRX_UIO_MODE_READWRITE:
3627 ext_attr->uio_irqn_mode = uio_cfg->mode;
3628 break;
3629 case DRX_UIO_MODE_DISABLE:
3630 /* pad configuration register is set 0 - input mode */
3631 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3632 if (rc != 0) {
3633 pr_err("error %d\n", rc);
3634 goto rw_error;
3635 }
3636 ext_attr->uio_irqn_mode = uio_cfg->mode;
3637 break;
3638 case DRX_UIO_MODE_FIRMWARE0: /* falltrough */
3639 default:
3640 return -EINVAL;
3641 break;
3642 } /* switch ( uio_cfg->mode ) */
3643 break;
3644 /*====================================================================*/
3645 default:
3646 return -EINVAL;
3647 } /* switch ( uio_cfg->uio ) */
3648
3649 /* Write magic word to disable pdr reg write */
3650 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3651 if (rc != 0) {
3652 pr_err("error %d\n", rc);
3653 goto rw_error;
3654 }
3655
3656 return 0;
3657 rw_error:
3658 return rc;
3659 }
3660
3661 /**
3662 * \fn int ctrl_uio_write()
3663 * \brief Write to a UIO.
3664 * \param demod Pointer to demodulator instance.
3665 * \param uio_data Pointer to data container for a certain UIO.
3666 * \return int.
3667 */
3668 static int
3669 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3670 {
3671 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3672 int rc;
3673 u16 pin_cfg_value = 0;
3674 u16 value = 0;
3675
3676 if ((uio_data == NULL) || (demod == NULL))
3677 return -EINVAL;
3678
3679 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3680
3681 /* Write magic word to enable pdr reg write */
3682 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3683 if (rc != 0) {
3684 pr_err("error %d\n", rc);
3685 goto rw_error;
3686 }
3687 switch (uio_data->uio) {
3688 /*====================================================================*/
3689 case DRX_UIO1:
3690 /* DRX_UIO1: SMA_TX UIO-1 */
3691 if (!ext_attr->has_smatx)
3692 return -EIO;
3693 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3694 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3695 return -EIO;
3696 }
3697 pin_cfg_value = 0;
3698 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3699 pin_cfg_value |= 0x0113;
3700 /* io_pad_cfg_mode output mode is drive always */
3701 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3702
3703 /* write to io pad configuration register - output mode */
3704 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3705 if (rc != 0) {
3706 pr_err("error %d\n", rc);
3707 goto rw_error;
3708 }
3709
3710 /* use corresponding bit in io data output registar */
3711 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3712 if (rc != 0) {
3713 pr_err("error %d\n", rc);
3714 goto rw_error;
3715 }
3716 if (!uio_data->value)
3717 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
3718 else
3719 value |= 0x8000; /* write one to 15th bit - 1st UIO */
3720
3721 /* write back to io data output register */
3722 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3723 if (rc != 0) {
3724 pr_err("error %d\n", rc);
3725 goto rw_error;
3726 }
3727 break;
3728 /*======================================================================*/
3729 case DRX_UIO2:
3730 /* DRX_UIO2: SMA_RX UIO-2 */
3731 if (!ext_attr->has_smarx)
3732 return -EIO;
3733 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3734 return -EIO;
3735
3736 pin_cfg_value = 0;
3737 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3738 pin_cfg_value |= 0x0113;
3739 /* io_pad_cfg_mode output mode is drive always */
3740 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3741
3742 /* write to io pad configuration register - output mode */
3743 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3744 if (rc != 0) {
3745 pr_err("error %d\n", rc);
3746 goto rw_error;
3747 }
3748
3749 /* use corresponding bit in io data output registar */
3750 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3751 if (rc != 0) {
3752 pr_err("error %d\n", rc);
3753 goto rw_error;
3754 }
3755 if (!uio_data->value)
3756 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
3757 else
3758 value |= 0x4000; /* write one to 14th bit - 2nd UIO */
3759
3760 /* write back to io data output register */
3761 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3762 if (rc != 0) {
3763 pr_err("error %d\n", rc);
3764 goto rw_error;
3765 }
3766 break;
3767 /*====================================================================*/
3768 case DRX_UIO3:
3769 /* DRX_UIO3: ASEL UIO-3 */
3770 if (!ext_attr->has_gpio)
3771 return -EIO;
3772 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3773 return -EIO;
3774
3775 pin_cfg_value = 0;
3776 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3777 pin_cfg_value |= 0x0113;
3778 /* io_pad_cfg_mode output mode is drive always */
3779 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3780
3781 /* write to io pad configuration register - output mode */
3782 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3783 if (rc != 0) {
3784 pr_err("error %d\n", rc);
3785 goto rw_error;
3786 }
3787
3788 /* use corresponding bit in io data output registar */
3789 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3790 if (rc != 0) {
3791 pr_err("error %d\n", rc);
3792 goto rw_error;
3793 }
3794 if (!uio_data->value)
3795 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
3796 else
3797 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
3798
3799 /* write back to io data output register */
3800 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3801 if (rc != 0) {
3802 pr_err("error %d\n", rc);
3803 goto rw_error;
3804 }
3805 break;
3806 /*=====================================================================*/
3807 case DRX_UIO4:
3808 /* DRX_UIO4: IRQN UIO-4 */
3809 if (!ext_attr->has_irqn)
3810 return -EIO;
3811
3812 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3813 return -EIO;
3814
3815 pin_cfg_value = 0;
3816 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3817 pin_cfg_value |= 0x0113;
3818 /* io_pad_cfg_mode output mode is drive always */
3819 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3820
3821 /* write to io pad configuration register - output mode */
3822 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3823 if (rc != 0) {
3824 pr_err("error %d\n", rc);
3825 goto rw_error;
3826 }
3827
3828 /* use corresponding bit in io data output registar */
3829 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3830 if (rc != 0) {
3831 pr_err("error %d\n", rc);
3832 goto rw_error;
3833 }
3834 if (uio_data->value == false)
3835 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
3836 else
3837 value |= 0x1000; /* write one to 12th bit - 4th UIO */
3838
3839 /* write back to io data output register */
3840 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3841 if (rc != 0) {
3842 pr_err("error %d\n", rc);
3843 goto rw_error;
3844 }
3845 break;
3846 /*=====================================================================*/
3847 default:
3848 return -EINVAL;
3849 } /* switch ( uio_data->uio ) */
3850
3851 /* Write magic word to disable pdr reg write */
3852 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3853 if (rc != 0) {
3854 pr_err("error %d\n", rc);
3855 goto rw_error;
3856 }
3857
3858 return 0;
3859 rw_error:
3860 return rc;
3861 }
3862
3863 /*---------------------------------------------------------------------------*/
3864 /* UIO Configuration Functions - end */
3865 /*---------------------------------------------------------------------------*/
3866
3867 /*----------------------------------------------------------------------------*/
3868 /* I2C Bridge Functions - begin */
3869 /*----------------------------------------------------------------------------*/
3870 /**
3871 * \fn int ctrl_i2c_bridge()
3872 * \brief Open or close the I2C switch to tuner.
3873 * \param demod Pointer to demodulator instance.
3874 * \param bridge_closed Pointer to bool indication if bridge is closed not.
3875 * \return int.
3876
3877 */
3878 static int
3879 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3880 {
3881 struct drxj_hi_cmd hi_cmd;
3882 u16 result = 0;
3883
3884 /* check arguments */
3885 if (bridge_closed == NULL)
3886 return -EINVAL;
3887
3888 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3889 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3890 if (*bridge_closed)
3891 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3892 else
3893 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3894
3895 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3896 }
3897
3898 /*----------------------------------------------------------------------------*/
3899 /* I2C Bridge Functions - end */
3900 /*----------------------------------------------------------------------------*/
3901
3902 /*----------------------------------------------------------------------------*/
3903 /* Smart antenna Functions - begin */
3904 /*----------------------------------------------------------------------------*/
3905 /**
3906 * \fn int smart_ant_init()
3907 * \brief Initialize Smart Antenna.
3908 * \param pointer to struct drx_demod_instance.
3909 * \return int.
3910 *
3911 */
3912 static int smart_ant_init(struct drx_demod_instance *demod)
3913 {
3914 struct drxj_data *ext_attr = NULL;
3915 struct i2c_device_addr *dev_addr = NULL;
3916 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3917 int rc;
3918 u16 data = 0;
3919
3920 dev_addr = demod->my_i2c_dev_addr;
3921 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3922
3923 /* Write magic word to enable pdr reg write */
3924 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3925 if (rc != 0) {
3926 pr_err("error %d\n", rc);
3927 goto rw_error;
3928 }
3929 /* init smart antenna */
3930 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3931 if (rc != 0) {
3932 pr_err("error %d\n", rc);
3933 goto rw_error;
3934 }
3935 if (ext_attr->smart_ant_inverted) {
3936 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3937 if (rc != 0) {
3938 pr_err("error %d\n", rc);
3939 goto rw_error;
3940 }
3941 } else {
3942 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3943 if (rc != 0) {
3944 pr_err("error %d\n", rc);
3945 goto rw_error;
3946 }
3947 }
3948
3949 /* config SMA_TX pin to smart antenna mode */
3950 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3951 if (rc != 0) {
3952 pr_err("error %d\n", rc);
3953 goto rw_error;
3954 }
3955 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3956 if (rc != 0) {
3957 pr_err("error %d\n", rc);
3958 goto rw_error;
3959 }
3960 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3961 if (rc != 0) {
3962 pr_err("error %d\n", rc);
3963 goto rw_error;
3964 }
3965
3966 /* Write magic word to disable pdr reg write */
3967 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3968 if (rc != 0) {
3969 pr_err("error %d\n", rc);
3970 goto rw_error;
3971 }
3972
3973 return 0;
3974 rw_error:
3975 return rc;
3976 }
3977
3978 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3979 {
3980 int rc;
3981 u16 cur_cmd = 0;
3982 unsigned long timeout;
3983
3984 /* Check param */
3985 if (cmd == NULL)
3986 return -EINVAL;
3987
3988 /* Wait until SCU command interface is ready to receive command */
3989 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3990 if (rc != 0) {
3991 pr_err("error %d\n", rc);
3992 goto rw_error;
3993 }
3994 if (cur_cmd != DRX_SCU_READY)
3995 return -EIO;
3996
3997 switch (cmd->parameter_len) {
3998 case 5:
3999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4000 if (rc != 0) {
4001 pr_err("error %d\n", rc);
4002 goto rw_error;
4003 } /* fallthrough */
4004 case 4:
4005 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4006 if (rc != 0) {
4007 pr_err("error %d\n", rc);
4008 goto rw_error;
4009 } /* fallthrough */
4010 case 3:
4011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4012 if (rc != 0) {
4013 pr_err("error %d\n", rc);
4014 goto rw_error;
4015 } /* fallthrough */
4016 case 2:
4017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4018 if (rc != 0) {
4019 pr_err("error %d\n", rc);
4020 goto rw_error;
4021 } /* fallthrough */
4022 case 1:
4023 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4024 if (rc != 0) {
4025 pr_err("error %d\n", rc);
4026 goto rw_error;
4027 } /* fallthrough */
4028 case 0:
4029 /* do nothing */
4030 break;
4031 default:
4032 /* this number of parameters is not supported */
4033 return -EIO;
4034 }
4035 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4036 if (rc != 0) {
4037 pr_err("error %d\n", rc);
4038 goto rw_error;
4039 }
4040
4041 /* Wait until SCU has processed command */
4042 timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4043 while (time_is_after_jiffies(timeout)) {
4044 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4045 if (rc != 0) {
4046 pr_err("error %d\n", rc);
4047 goto rw_error;
4048 }
4049 if (cur_cmd == DRX_SCU_READY)
4050 break;
4051 usleep_range(1000, 2000);
4052 }
4053
4054 if (cur_cmd != DRX_SCU_READY)
4055 return -EIO;
4056
4057 /* read results */
4058 if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4059 s16 err;
4060
4061 switch (cmd->result_len) {
4062 case 4:
4063 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4064 if (rc != 0) {
4065 pr_err("error %d\n", rc);
4066 goto rw_error;
4067 } /* fallthrough */
4068 case 3:
4069 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4070 if (rc != 0) {
4071 pr_err("error %d\n", rc);
4072 goto rw_error;
4073 } /* fallthrough */
4074 case 2:
4075 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4076 if (rc != 0) {
4077 pr_err("error %d\n", rc);
4078 goto rw_error;
4079 } /* fallthrough */
4080 case 1:
4081 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4082 if (rc != 0) {
4083 pr_err("error %d\n", rc);
4084 goto rw_error;
4085 } /* fallthrough */
4086 case 0:
4087 /* do nothing */
4088 break;
4089 default:
4090 /* this number of parameters is not supported */
4091 return -EIO;
4092 }
4093
4094 /* Check if an error was reported by SCU */
4095 err = cmd->result[0];
4096
4097 /* check a few fixed error codes */
4098 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4099 || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4100 || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4101 || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4102 ) {
4103 return -EINVAL;
4104 }
4105 /* here it is assumed that negative means error, and positive no error */
4106 else if (err < 0)
4107 return -EIO;
4108 else
4109 return 0;
4110 }
4111
4112 return 0;
4113
4114 rw_error:
4115 return rc;
4116 }
4117
4118 /**
4119 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4120 * \brief Basic access routine for SCU atomic read or write access
4121 * \param dev_addr pointer to i2c dev address
4122 * \param addr destination/source address
4123 * \param datasize size of data buffer in bytes
4124 * \param data pointer to data buffer
4125 * \return int
4126 * \retval 0 Succes
4127 * \retval -EIO Timeout, I2C error, illegal bank
4128 *
4129 */
4130 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4131 static
4132 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
4133 u8 *data, bool read_flag)
4134 {
4135 struct drxjscu_cmd scu_cmd;
4136 int rc;
4137 u16 set_param_parameters[18];
4138 u16 cmd_result[15];
4139
4140 /* Parameter check */
4141 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4142 return -EINVAL;
4143
4144 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4145 if (read_flag) { /* read */
4146 set_param_parameters[0] = ((~(0x0080)) & datasize);
4147 scu_cmd.parameter_len = 2;
4148 scu_cmd.result_len = datasize / 2 + 2;
4149 } else {
4150 int i = 0;
4151
4152 set_param_parameters[0] = 0x0080 | datasize;
4153 for (i = 0; i < (datasize / 2); i++) {
4154 set_param_parameters[i + 2] =
4155 (data[2 * i] | (data[(2 * i) + 1] << 8));
4156 }
4157 scu_cmd.parameter_len = datasize / 2 + 2;
4158 scu_cmd.result_len = 1;
4159 }
4160
4161 scu_cmd.command =
4162 SCU_RAM_COMMAND_STANDARD_TOP |
4163 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4164 scu_cmd.result = cmd_result;
4165 scu_cmd.parameter = set_param_parameters;
4166 rc = scu_command(dev_addr, &scu_cmd);
4167 if (rc != 0) {
4168 pr_err("error %d\n", rc);
4169 goto rw_error;
4170 }
4171
4172 if (read_flag) {
4173 int i = 0;
4174 /* read data from buffer */
4175 for (i = 0; i < (datasize / 2); i++) {
4176 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4177 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4178 }
4179 }
4180
4181 return 0;
4182
4183 rw_error:
4184 return rc;
4185
4186 }
4187
4188 /*============================================================================*/
4189
4190 /**
4191 * \fn int DRXJ_DAP_AtomicReadReg16()
4192 * \brief Atomic read of 16 bits words
4193 */
4194 static
4195 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4196 u32 addr,
4197 u16 *data, u32 flags)
4198 {
4199 u8 buf[2] = { 0 };
4200 int rc = -EIO;
4201 u16 word = 0;
4202
4203 if (!data)
4204 return -EINVAL;
4205
4206 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4207 if (rc < 0)
4208 return rc;
4209
4210 word = (u16) (buf[0] + (buf[1] << 8));
4211
4212 *data = word;
4213
4214 return rc;
4215 }
4216
4217 /*============================================================================*/
4218 /**
4219 * \fn int drxj_dap_scu_atomic_write_reg16()
4220 * \brief Atomic read of 16 bits words
4221 */
4222 static
4223 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4224 u32 addr,
4225 u16 data, u32 flags)
4226 {
4227 u8 buf[2];
4228 int rc = -EIO;
4229
4230 buf[0] = (u8) (data & 0xff);
4231 buf[1] = (u8) ((data >> 8) & 0xff);
4232
4233 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4234
4235 return rc;
4236 }
4237
4238 /* -------------------------------------------------------------------------- */
4239 /**
4240 * \brief Measure result of ADC synchronisation
4241 * \param demod demod instance
4242 * \param count (returned) count
4243 * \return int.
4244 * \retval 0 Success
4245 * \retval -EIO Failure: I2C error
4246 *
4247 */
4248 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4249 {
4250 struct i2c_device_addr *dev_addr = NULL;
4251 int rc;
4252 u16 data = 0;
4253
4254 dev_addr = demod->my_i2c_dev_addr;
4255
4256 /* Start measurement */
4257 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4258 if (rc != 0) {
4259 pr_err("error %d\n", rc);
4260 goto rw_error;
4261 }
4262 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4263 if (rc != 0) {
4264 pr_err("error %d\n", rc);
4265 goto rw_error;
4266 }
4267
4268 /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4269 msleep(1);
4270
4271 *count = 0;
4272 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4273 if (rc != 0) {
4274 pr_err("error %d\n", rc);
4275 goto rw_error;
4276 }
4277 if (data == 127)
4278 *count = *count + 1;
4279 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4280 if (rc != 0) {
4281 pr_err("error %d\n", rc);
4282 goto rw_error;
4283 }
4284 if (data == 127)
4285 *count = *count + 1;
4286 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4287 if (rc != 0) {
4288 pr_err("error %d\n", rc);
4289 goto rw_error;
4290 }
4291 if (data == 127)
4292 *count = *count + 1;
4293
4294 return 0;
4295 rw_error:
4296 return rc;
4297 }
4298
4299 /**
4300 * \brief Synchronize analog and digital clock domains
4301 * \param demod demod instance
4302 * \return int.
4303 * \retval 0 Success
4304 * \retval -EIO Failure: I2C error or failure to synchronize
4305 *
4306 * An IQM reset will also reset the results of this synchronization.
4307 * After an IQM reset this routine needs to be called again.
4308 *
4309 */
4310
4311 static int adc_synchronization(struct drx_demod_instance *demod)
4312 {
4313 struct i2c_device_addr *dev_addr = NULL;
4314 int rc;
4315 u16 count = 0;
4316
4317 dev_addr = demod->my_i2c_dev_addr;
4318
4319 rc = adc_sync_measurement(demod, &count);
4320 if (rc != 0) {
4321 pr_err("error %d\n", rc);
4322 goto rw_error;
4323 }
4324
4325 if (count == 1) {
4326 /* Try sampling on a different edge */
4327 u16 clk_neg = 0;
4328
4329 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4330 if (rc != 0) {
4331 pr_err("error %d\n", rc);
4332 goto rw_error;
4333 }
4334
4335 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4336 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4337 if (rc != 0) {
4338 pr_err("error %d\n", rc);
4339 goto rw_error;
4340 }
4341
4342 rc = adc_sync_measurement(demod, &count);
4343 if (rc != 0) {
4344 pr_err("error %d\n", rc);
4345 goto rw_error;
4346 }
4347 }
4348
4349 /* TODO: implement fallback scenarios */
4350 if (count < 2)
4351 return -EIO;
4352
4353 return 0;
4354 rw_error:
4355 return rc;
4356 }
4357
4358 /*============================================================================*/
4359 /*== END AUXILIARY FUNCTIONS ==*/
4360 /*============================================================================*/
4361
4362 /*============================================================================*/
4363 /*============================================================================*/
4364 /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
4365 /*============================================================================*/
4366 /*============================================================================*/
4367 /**
4368 * \fn int init_agc ()
4369 * \brief Initialize AGC for all standards.
4370 * \param demod instance of demodulator.
4371 * \param channel pointer to channel data.
4372 * \return int.
4373 */
4374 static int init_agc(struct drx_demod_instance *demod)
4375 {
4376 struct i2c_device_addr *dev_addr = NULL;
4377 struct drx_common_attr *common_attr = NULL;
4378 struct drxj_data *ext_attr = NULL;
4379 struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4380 struct drxj_cfg_agc *p_agc_if_settings = NULL;
4381 int rc;
4382 u16 ingain_tgt_max = 0;
4383 u16 clp_dir_to = 0;
4384 u16 sns_sum_max = 0;
4385 u16 clp_sum_max = 0;
4386 u16 sns_dir_to = 0;
4387 u16 ki_innergain_min = 0;
4388 u16 agc_ki = 0;
4389 u16 ki_max = 0;
4390 u16 if_iaccu_hi_tgt_min = 0;
4391 u16 data = 0;
4392 u16 agc_ki_dgain = 0;
4393 u16 ki_min = 0;
4394 u16 clp_ctrl_mode = 0;
4395 u16 agc_rf = 0;
4396 u16 agc_if = 0;
4397
4398 dev_addr = demod->my_i2c_dev_addr;
4399 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4400 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4401
4402 switch (ext_attr->standard) {
4403 case DRX_STANDARD_8VSB:
4404 clp_sum_max = 1023;
4405 clp_dir_to = (u16) (-9);
4406 sns_sum_max = 1023;
4407 sns_dir_to = (u16) (-9);
4408 ki_innergain_min = (u16) (-32768);
4409 ki_max = 0x032C;
4410 agc_ki_dgain = 0xC;
4411 if_iaccu_hi_tgt_min = 2047;
4412 ki_min = 0x0117;
4413 ingain_tgt_max = 16383;
4414 clp_ctrl_mode = 0;
4415 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4416 if (rc != 0) {
4417 pr_err("error %d\n", rc);
4418 goto rw_error;
4419 }
4420 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4421 if (rc != 0) {
4422 pr_err("error %d\n", rc);
4423 goto rw_error;
4424 }
4425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4426 if (rc != 0) {
4427 pr_err("error %d\n", rc);
4428 goto rw_error;
4429 }
4430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4431 if (rc != 0) {
4432 pr_err("error %d\n", rc);
4433 goto rw_error;
4434 }
4435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4436 if (rc != 0) {
4437 pr_err("error %d\n", rc);
4438 goto rw_error;
4439 }
4440 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4441 if (rc != 0) {
4442 pr_err("error %d\n", rc);
4443 goto rw_error;
4444 }
4445 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4446 if (rc != 0) {
4447 pr_err("error %d\n", rc);
4448 goto rw_error;
4449 }
4450 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4451 if (rc != 0) {
4452 pr_err("error %d\n", rc);
4453 goto rw_error;
4454 }
4455 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4456 if (rc != 0) {
4457 pr_err("error %d\n", rc);
4458 goto rw_error;
4459 }
4460 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4461 if (rc != 0) {
4462 pr_err("error %d\n", rc);
4463 goto rw_error;
4464 }
4465 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4466 if (rc != 0) {
4467 pr_err("error %d\n", rc);
4468 goto rw_error;
4469 }
4470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4471 if (rc != 0) {
4472 pr_err("error %d\n", rc);
4473 goto rw_error;
4474 }
4475 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4476 if (rc != 0) {
4477 pr_err("error %d\n", rc);
4478 goto rw_error;
4479 }
4480 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4481 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4482 break;
4483 #ifndef DRXJ_VSB_ONLY
4484 case DRX_STANDARD_ITU_A:
4485 case DRX_STANDARD_ITU_C:
4486 case DRX_STANDARD_ITU_B:
4487 ingain_tgt_max = 5119;
4488 clp_sum_max = 1023;
4489 clp_dir_to = (u16) (-5);
4490 sns_sum_max = 127;
4491 sns_dir_to = (u16) (-3);
4492 ki_innergain_min = 0;
4493 ki_max = 0x0657;
4494 if_iaccu_hi_tgt_min = 2047;
4495 agc_ki_dgain = 0x7;
4496 ki_min = 0x0117;
4497 clp_ctrl_mode = 0;
4498 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4499 if (rc != 0) {
4500 pr_err("error %d\n", rc);
4501 goto rw_error;
4502 }
4503 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4504 if (rc != 0) {
4505 pr_err("error %d\n", rc);
4506 goto rw_error;
4507 }
4508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4509 if (rc != 0) {
4510 pr_err("error %d\n", rc);
4511 goto rw_error;
4512 }
4513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4514 if (rc != 0) {
4515 pr_err("error %d\n", rc);
4516 goto rw_error;
4517 }
4518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4519 if (rc != 0) {
4520 pr_err("error %d\n", rc);
4521 goto rw_error;
4522 }
4523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4524 if (rc != 0) {
4525 pr_err("error %d\n", rc);
4526 goto rw_error;
4527 }
4528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4529 if (rc != 0) {
4530 pr_err("error %d\n", rc);
4531 goto rw_error;
4532 }
4533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4534 if (rc != 0) {
4535 pr_err("error %d\n", rc);
4536 goto rw_error;
4537 }
4538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4539 if (rc != 0) {
4540 pr_err("error %d\n", rc);
4541 goto rw_error;
4542 }
4543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4544 if (rc != 0) {
4545 pr_err("error %d\n", rc);
4546 goto rw_error;
4547 }
4548 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4549 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4550 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4551 if (rc != 0) {
4552 pr_err("error %d\n", rc);
4553 goto rw_error;
4554 }
4555
4556 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4557 if (rc != 0) {
4558 pr_err("error %d\n", rc);
4559 goto rw_error;
4560 }
4561 agc_ki &= 0xf000;
4562 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4563 if (rc != 0) {
4564 pr_err("error %d\n", rc);
4565 goto rw_error;
4566 }
4567 break;
4568 #endif
4569 default:
4570 return -EINVAL;
4571 }
4572
4573 /* for new AGC interface */
4574 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4575 if (rc != 0) {
4576 pr_err("error %d\n", rc);
4577 goto rw_error;
4578 }
4579 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4580 if (rc != 0) {
4581 pr_err("error %d\n", rc);
4582 goto rw_error;
4583 } /* Gain fed from inner to outer AGC */
4584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4585 if (rc != 0) {
4586 pr_err("error %d\n", rc);
4587 goto rw_error;
4588 }
4589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4590 if (rc != 0) {
4591 pr_err("error %d\n", rc);
4592 goto rw_error;
4593 }
4594 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4595 if (rc != 0) {
4596 pr_err("error %d\n", rc);
4597 goto rw_error;
4598 } /* set to p_agc_settings->top before */
4599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4600 if (rc != 0) {
4601 pr_err("error %d\n", rc);
4602 goto rw_error;
4603 }
4604 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4605 if (rc != 0) {
4606 pr_err("error %d\n", rc);
4607 goto rw_error;
4608 }
4609 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4610 if (rc != 0) {
4611 pr_err("error %d\n", rc);
4612 goto rw_error;
4613 }
4614 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4615 if (rc != 0) {
4616 pr_err("error %d\n", rc);
4617 goto rw_error;
4618 }
4619 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4620 if (rc != 0) {
4621 pr_err("error %d\n", rc);
4622 goto rw_error;
4623 }
4624 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4625 if (rc != 0) {
4626 pr_err("error %d\n", rc);
4627 goto rw_error;
4628 }
4629 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4630 if (rc != 0) {
4631 pr_err("error %d\n", rc);
4632 goto rw_error;
4633 }
4634 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4635 if (rc != 0) {
4636 pr_err("error %d\n", rc);
4637 goto rw_error;
4638 }
4639 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4640 if (rc != 0) {
4641 pr_err("error %d\n", rc);
4642 goto rw_error;
4643 }
4644 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4645 if (rc != 0) {
4646 pr_err("error %d\n", rc);
4647 goto rw_error;
4648 }
4649 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4650 if (rc != 0) {
4651 pr_err("error %d\n", rc);
4652 goto rw_error;
4653 }
4654 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4655 if (rc != 0) {
4656 pr_err("error %d\n", rc);
4657 goto rw_error;
4658 }
4659 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4660 if (rc != 0) {
4661 pr_err("error %d\n", rc);
4662 goto rw_error;
4663 }
4664 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4665 if (rc != 0) {
4666 pr_err("error %d\n", rc);
4667 goto rw_error;
4668 }
4669 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4670 if (rc != 0) {
4671 pr_err("error %d\n", rc);
4672 goto rw_error;
4673 }
4674 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4675 if (rc != 0) {
4676 pr_err("error %d\n", rc);
4677 goto rw_error;
4678 }
4679 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4680 if (rc != 0) {
4681 pr_err("error %d\n", rc);
4682 goto rw_error;
4683 }
4684 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4685 if (rc != 0) {
4686 pr_err("error %d\n", rc);
4687 goto rw_error;
4688 }
4689 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4690 if (rc != 0) {
4691 pr_err("error %d\n", rc);
4692 goto rw_error;
4693 }
4694 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4695 if (rc != 0) {
4696 pr_err("error %d\n", rc);
4697 goto rw_error;
4698 }
4699 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4700 if (rc != 0) {
4701 pr_err("error %d\n", rc);
4702 goto rw_error;
4703 }
4704
4705 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4706 if (common_attr->tuner_rf_agc_pol == true)
4707 agc_rf = 0x87ff - agc_rf;
4708
4709 agc_if = 0x800;
4710 if (common_attr->tuner_if_agc_pol == true)
4711 agc_rf = 0x87ff - agc_rf;
4712
4713 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4714 if (rc != 0) {
4715 pr_err("error %d\n", rc);
4716 goto rw_error;
4717 }
4718 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4719 if (rc != 0) {
4720 pr_err("error %d\n", rc);
4721 goto rw_error;
4722 }
4723
4724 /* Set/restore Ki DGAIN factor */
4725 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4726 if (rc != 0) {
4727 pr_err("error %d\n", rc);
4728 goto rw_error;
4729 }
4730 data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4731 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4732 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4733 if (rc != 0) {
4734 pr_err("error %d\n", rc);
4735 goto rw_error;
4736 }
4737
4738 return 0;
4739 rw_error:
4740 return rc;
4741 }
4742
4743 /**
4744 * \fn int set_frequency ()
4745 * \brief Set frequency shift.
4746 * \param demod instance of demodulator.
4747 * \param channel pointer to channel data.
4748 * \param tuner_freq_offset residual frequency from tuner.
4749 * \return int.
4750 */
4751 static int
4752 set_frequency(struct drx_demod_instance *demod,
4753 struct drx_channel *channel, s32 tuner_freq_offset)
4754 {
4755 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4756 struct drxj_data *ext_attr = demod->my_ext_attr;
4757 int rc;
4758 s32 sampling_frequency = 0;
4759 s32 frequency_shift = 0;
4760 s32 if_freq_actual = 0;
4761 s32 rf_freq_residual = -1 * tuner_freq_offset;
4762 s32 adc_freq = 0;
4763 s32 intermediate_freq = 0;
4764 u32 iqm_fs_rate_ofs = 0;
4765 bool adc_flip = true;
4766 bool select_pos_image = false;
4767 bool rf_mirror;
4768 bool tuner_mirror;
4769 bool image_to_select = true;
4770 s32 fm_frequency_shift = 0;
4771
4772 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4773 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4774 /*
4775 Program frequency shifter
4776 No need to account for mirroring on RF
4777 */
4778 switch (ext_attr->standard) {
4779 case DRX_STANDARD_ITU_A: /* fallthrough */
4780 case DRX_STANDARD_ITU_C: /* fallthrough */
4781 case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
4782 case DRX_STANDARD_8VSB:
4783 select_pos_image = true;
4784 break;
4785 case DRX_STANDARD_FM:
4786 /* After IQM FS sound carrier must appear at 4 Mhz in spect.
4787 Sound carrier is already 3Mhz above centre frequency due
4788 to tuner setting so now add an extra shift of 1MHz... */
4789 fm_frequency_shift = 1000;
4790 case DRX_STANDARD_ITU_B: /* fallthrough */
4791 case DRX_STANDARD_NTSC: /* fallthrough */
4792 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
4793 case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
4794 case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
4795 case DRX_STANDARD_PAL_SECAM_L:
4796 select_pos_image = false;
4797 break;
4798 default:
4799 return -EINVAL;
4800 }
4801 intermediate_freq = demod->my_common_attr->intermediate_freq;
4802 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4803 if (tuner_mirror)
4804 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4805 else
4806 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4807 if (if_freq_actual > sampling_frequency / 2) {
4808 /* adc mirrors */
4809 adc_freq = sampling_frequency - if_freq_actual;
4810 adc_flip = true;
4811 } else {
4812 /* adc doesn't mirror */
4813 adc_freq = if_freq_actual;
4814 adc_flip = false;
4815 }
4816
4817 frequency_shift = adc_freq;
4818 image_to_select =
4819 (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4820 iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4821
4822 if (image_to_select)
4823 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4824
4825 /* Program frequency shifter with tuner offset compensation */
4826 /* frequency_shift += tuner_freq_offset; TODO */
4827 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4828 if (rc != 0) {
4829 pr_err("error %d\n", rc);
4830 goto rw_error;
4831 }
4832 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4833 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4834
4835 return 0;
4836 rw_error:
4837 return rc;
4838 }
4839
4840 /**
4841 * \fn int get_acc_pkt_err()
4842 * \brief Retrieve signal strength for VSB and QAM.
4843 * \param demod Pointer to demod instance
4844 * \param packet_err Pointer to packet error
4845 * \return int.
4846 * \retval 0 sig_strength contains valid data.
4847 * \retval -EINVAL sig_strength is NULL.
4848 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4849 */
4850 #ifdef DRXJ_SIGNAL_ACCUM_ERR
4851 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4852 {
4853 int rc;
4854 static u16 pkt_err;
4855 static u16 last_pkt_err;
4856 u16 data = 0;
4857 struct drxj_data *ext_attr = NULL;
4858 struct i2c_device_addr *dev_addr = NULL;
4859
4860 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4861 dev_addr = demod->my_i2c_dev_addr;
4862
4863 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4864 if (rc != 0) {
4865 pr_err("error %d\n", rc);
4866 goto rw_error;
4867 }
4868 if (ext_attr->reset_pkt_err_acc) {
4869 last_pkt_err = data;
4870 pkt_err = 0;
4871 ext_attr->reset_pkt_err_acc = false;
4872 }
4873
4874 if (data < last_pkt_err) {
4875 pkt_err += 0xffff - last_pkt_err;
4876 pkt_err += data;
4877 } else {
4878 pkt_err += (data - last_pkt_err);
4879 }
4880 *packet_err = pkt_err;
4881 last_pkt_err = data;
4882
4883 return 0;
4884 rw_error:
4885 return rc;
4886 }
4887 #endif
4888
4889
4890 /*============================================================================*/
4891
4892 /**
4893 * \fn int set_agc_rf ()
4894 * \brief Configure RF AGC
4895 * \param demod instance of demodulator.
4896 * \param agc_settings AGC configuration structure
4897 * \return int.
4898 */
4899 static int
4900 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4901 {
4902 struct i2c_device_addr *dev_addr = NULL;
4903 struct drxj_data *ext_attr = NULL;
4904 struct drxj_cfg_agc *p_agc_settings = NULL;
4905 struct drx_common_attr *common_attr = NULL;
4906 int rc;
4907 drx_write_reg16func_t scu_wr16 = NULL;
4908 drx_read_reg16func_t scu_rr16 = NULL;
4909
4910 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4911 dev_addr = demod->my_i2c_dev_addr;
4912 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4913
4914 if (atomic) {
4915 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4916 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4917 } else {
4918 scu_rr16 = drxj_dap_read_reg16;
4919 scu_wr16 = drxj_dap_write_reg16;
4920 }
4921
4922 /* Configure AGC only if standard is currently active */
4923 if ((ext_attr->standard == agc_settings->standard) ||
4924 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4925 DRXJ_ISQAMSTD(agc_settings->standard)) ||
4926 (DRXJ_ISATVSTD(ext_attr->standard) &&
4927 DRXJ_ISATVSTD(agc_settings->standard))) {
4928 u16 data = 0;
4929
4930 switch (agc_settings->ctrl_mode) {
4931 case DRX_AGC_CTRL_AUTO:
4932
4933 /* Enable RF AGC DAC */
4934 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4935 if (rc != 0) {
4936 pr_err("error %d\n", rc);
4937 goto rw_error;
4938 }
4939 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4940 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4941 if (rc != 0) {
4942 pr_err("error %d\n", rc);
4943 goto rw_error;
4944 }
4945
4946 /* Enable SCU RF AGC loop */
4947 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4948 if (rc != 0) {
4949 pr_err("error %d\n", rc);
4950 goto rw_error;
4951 }
4952 data &= ~SCU_RAM_AGC_KI_RF__M;
4953 if (ext_attr->standard == DRX_STANDARD_8VSB)
4954 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4955 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4956 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4957 else
4958 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4959
4960 if (common_attr->tuner_rf_agc_pol)
4961 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4962 else
4963 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4964 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4965 if (rc != 0) {
4966 pr_err("error %d\n", rc);
4967 goto rw_error;
4968 }
4969
4970 /* Set speed ( using complementary reduction value ) */
4971 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4972 if (rc != 0) {
4973 pr_err("error %d\n", rc);
4974 goto rw_error;
4975 }
4976 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4977 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4978 if (rc != 0) {
4979 pr_err("error %d\n", rc);
4980 goto rw_error;
4981 }
4982
4983 if (agc_settings->standard == DRX_STANDARD_8VSB)
4984 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4985 else if (DRXJ_ISQAMSTD(agc_settings->standard))
4986 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4987 else if (DRXJ_ISATVSTD(agc_settings->standard))
4988 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4989 else
4990 return -EINVAL;
4991
4992 /* Set TOP, only if IF-AGC is in AUTO mode */
4993 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
4994 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
4995 if (rc != 0) {
4996 pr_err("error %d\n", rc);
4997 goto rw_error;
4998 }
4999 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5000 if (rc != 0) {
5001 pr_err("error %d\n", rc);
5002 goto rw_error;
5003 }
5004 }
5005
5006 /* Cut-Off current */
5007 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5008 if (rc != 0) {
5009 pr_err("error %d\n", rc);
5010 goto rw_error;
5011 }
5012 break;
5013 case DRX_AGC_CTRL_USER:
5014
5015 /* Enable RF AGC DAC */
5016 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5017 if (rc != 0) {
5018 pr_err("error %d\n", rc);
5019 goto rw_error;
5020 }
5021 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5022 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5023 if (rc != 0) {
5024 pr_err("error %d\n", rc);
5025 goto rw_error;
5026 }
5027
5028 /* Disable SCU RF AGC loop */
5029 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5030 if (rc != 0) {
5031 pr_err("error %d\n", rc);
5032 goto rw_error;
5033 }
5034 data &= ~SCU_RAM_AGC_KI_RF__M;
5035 if (common_attr->tuner_rf_agc_pol)
5036 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5037 else
5038 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5039 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5040 if (rc != 0) {
5041 pr_err("error %d\n", rc);
5042 goto rw_error;
5043 }
5044
5045 /* Write value to output pin */
5046 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5047 if (rc != 0) {
5048 pr_err("error %d\n", rc);
5049 goto rw_error;
5050 }
5051 break;
5052 case DRX_AGC_CTRL_OFF:
5053
5054 /* Disable RF AGC DAC */
5055 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5056 if (rc != 0) {
5057 pr_err("error %d\n", rc);
5058 goto rw_error;
5059 }
5060 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5061 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5062 if (rc != 0) {
5063 pr_err("error %d\n", rc);
5064 goto rw_error;
5065 }
5066
5067 /* Disable SCU RF AGC loop */
5068 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5069 if (rc != 0) {
5070 pr_err("error %d\n", rc);
5071 goto rw_error;
5072 }
5073 data &= ~SCU_RAM_AGC_KI_RF__M;
5074 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5075 if (rc != 0) {
5076 pr_err("error %d\n", rc);
5077 goto rw_error;
5078 }
5079 break;
5080 default:
5081 return -EINVAL;
5082 } /* switch ( agcsettings->ctrl_mode ) */
5083 }
5084
5085 /* Store rf agc settings */
5086 switch (agc_settings->standard) {
5087 case DRX_STANDARD_8VSB:
5088 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5089 break;
5090 #ifndef DRXJ_VSB_ONLY
5091 case DRX_STANDARD_ITU_A:
5092 case DRX_STANDARD_ITU_B:
5093 case DRX_STANDARD_ITU_C:
5094 ext_attr->qam_rf_agc_cfg = *agc_settings;
5095 break;
5096 #endif
5097 default:
5098 return -EIO;
5099 }
5100
5101 return 0;
5102 rw_error:
5103 return rc;
5104 }
5105
5106 /**
5107 * \fn int set_agc_if ()
5108 * \brief Configure If AGC
5109 * \param demod instance of demodulator.
5110 * \param agc_settings AGC configuration structure
5111 * \return int.
5112 */
5113 static int
5114 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5115 {
5116 struct i2c_device_addr *dev_addr = NULL;
5117 struct drxj_data *ext_attr = NULL;
5118 struct drxj_cfg_agc *p_agc_settings = NULL;
5119 struct drx_common_attr *common_attr = NULL;
5120 drx_write_reg16func_t scu_wr16 = NULL;
5121 drx_read_reg16func_t scu_rr16 = NULL;
5122 int rc;
5123
5124 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5125 dev_addr = demod->my_i2c_dev_addr;
5126 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5127
5128 if (atomic) {
5129 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5130 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5131 } else {
5132 scu_rr16 = drxj_dap_read_reg16;
5133 scu_wr16 = drxj_dap_write_reg16;
5134 }
5135
5136 /* Configure AGC only if standard is currently active */
5137 if ((ext_attr->standard == agc_settings->standard) ||
5138 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5139 DRXJ_ISQAMSTD(agc_settings->standard)) ||
5140 (DRXJ_ISATVSTD(ext_attr->standard) &&
5141 DRXJ_ISATVSTD(agc_settings->standard))) {
5142 u16 data = 0;
5143
5144 switch (agc_settings->ctrl_mode) {
5145 case DRX_AGC_CTRL_AUTO:
5146 /* Enable IF AGC DAC */
5147 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5148 if (rc != 0) {
5149 pr_err("error %d\n", rc);
5150 goto rw_error;
5151 }
5152 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5153 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5154 if (rc != 0) {
5155 pr_err("error %d\n", rc);
5156 goto rw_error;
5157 }
5158
5159 /* Enable SCU IF AGC loop */
5160 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5161 if (rc != 0) {
5162 pr_err("error %d\n", rc);
5163 goto rw_error;
5164 }
5165 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5166 data &= ~SCU_RAM_AGC_KI_IF__M;
5167 if (ext_attr->standard == DRX_STANDARD_8VSB)
5168 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5169 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5170 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5171 else
5172 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5173
5174 if (common_attr->tuner_if_agc_pol)
5175 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5176 else
5177 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5178 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5179 if (rc != 0) {
5180 pr_err("error %d\n", rc);
5181 goto rw_error;
5182 }
5183
5184 /* Set speed (using complementary reduction value) */
5185 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5186 if (rc != 0) {
5187 pr_err("error %d\n", rc);
5188 goto rw_error;
5189 }
5190 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5191 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5192 if (rc != 0) {
5193 pr_err("error %d\n", rc);
5194 goto rw_error;
5195 }
5196
5197 if (agc_settings->standard == DRX_STANDARD_8VSB)
5198 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5199 else if (DRXJ_ISQAMSTD(agc_settings->standard))
5200 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5201 else if (DRXJ_ISATVSTD(agc_settings->standard))
5202 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5203 else
5204 return -EINVAL;
5205
5206 /* Restore TOP */
5207 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5208 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5209 if (rc != 0) {
5210 pr_err("error %d\n", rc);
5211 goto rw_error;
5212 }
5213 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5214 if (rc != 0) {
5215 pr_err("error %d\n", rc);
5216 goto rw_error;
5217 }
5218 } else {
5219 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5220 if (rc != 0) {
5221 pr_err("error %d\n", rc);
5222 goto rw_error;
5223 }
5224 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5225 if (rc != 0) {
5226 pr_err("error %d\n", rc);
5227 goto rw_error;
5228 }
5229 }
5230 break;
5231
5232 case DRX_AGC_CTRL_USER:
5233
5234 /* Enable IF AGC DAC */
5235 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5236 if (rc != 0) {
5237 pr_err("error %d\n", rc);
5238 goto rw_error;
5239 }
5240 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5241 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5242 if (rc != 0) {
5243 pr_err("error %d\n", rc);
5244 goto rw_error;
5245 }
5246
5247 /* Disable SCU IF AGC loop */
5248 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5249 if (rc != 0) {
5250 pr_err("error %d\n", rc);
5251 goto rw_error;
5252 }
5253 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5254 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5255 if (common_attr->tuner_if_agc_pol)
5256 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5257 else
5258 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5259 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5260 if (rc != 0) {
5261 pr_err("error %d\n", rc);
5262 goto rw_error;
5263 }
5264
5265 /* Write value to output pin */
5266 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5267 if (rc != 0) {
5268 pr_err("error %d\n", rc);
5269 goto rw_error;
5270 }
5271 break;
5272
5273 case DRX_AGC_CTRL_OFF:
5274
5275 /* Disable If AGC DAC */
5276 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5277 if (rc != 0) {
5278 pr_err("error %d\n", rc);
5279 goto rw_error;
5280 }
5281 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5282 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5283 if (rc != 0) {
5284 pr_err("error %d\n", rc);
5285 goto rw_error;
5286 }
5287
5288 /* Disable SCU IF AGC loop */
5289 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5290 if (rc != 0) {
5291 pr_err("error %d\n", rc);
5292 goto rw_error;
5293 }
5294 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5295 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5296 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5297 if (rc != 0) {
5298 pr_err("error %d\n", rc);
5299 goto rw_error;
5300 }
5301 break;
5302 default:
5303 return -EINVAL;
5304 } /* switch ( agcsettings->ctrl_mode ) */
5305
5306 /* always set the top to support configurations without if-loop */
5307 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5308 if (rc != 0) {
5309 pr_err("error %d\n", rc);
5310 goto rw_error;
5311 }
5312 }
5313
5314 /* Store if agc settings */
5315 switch (agc_settings->standard) {
5316 case DRX_STANDARD_8VSB:
5317 ext_attr->vsb_if_agc_cfg = *agc_settings;
5318 break;
5319 #ifndef DRXJ_VSB_ONLY
5320 case DRX_STANDARD_ITU_A:
5321 case DRX_STANDARD_ITU_B:
5322 case DRX_STANDARD_ITU_C:
5323 ext_attr->qam_if_agc_cfg = *agc_settings;
5324 break;
5325 #endif
5326 default:
5327 return -EIO;
5328 }
5329
5330 return 0;
5331 rw_error:
5332 return rc;
5333 }
5334
5335 /**
5336 * \fn int set_iqm_af ()
5337 * \brief Configure IQM AF registers
5338 * \param demod instance of demodulator.
5339 * \param active
5340 * \return int.
5341 */
5342 static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5343 {
5344 u16 data = 0;
5345 struct i2c_device_addr *dev_addr = NULL;
5346 int rc;
5347
5348 dev_addr = demod->my_i2c_dev_addr;
5349
5350 /* Configure IQM */
5351 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5352 if (rc != 0) {
5353 pr_err("error %d\n", rc);
5354 goto rw_error;
5355 }
5356 if (!active)
5357 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5358 else
5359 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5360 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5361 if (rc != 0) {
5362 pr_err("error %d\n", rc);
5363 goto rw_error;
5364 }
5365
5366 return 0;
5367 rw_error:
5368 return rc;
5369 }
5370
5371 /*============================================================================*/
5372 /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
5373 /*============================================================================*/
5374
5375 /*============================================================================*/
5376 /*============================================================================*/
5377 /*== 8VSB DATAPATH FUNCTIONS ==*/
5378 /*============================================================================*/
5379 /*============================================================================*/
5380
5381 /**
5382 * \fn int power_down_vsb ()
5383 * \brief Powr down QAM related blocks.
5384 * \param demod instance of demodulator.
5385 * \param channel pointer to channel data.
5386 * \return int.
5387 */
5388 static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5389 {
5390 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5391 struct drxjscu_cmd cmd_scu = { /* command */ 0,
5392 /* parameter_len */ 0,
5393 /* result_len */ 0,
5394 /* *parameter */ NULL,
5395 /* *result */ NULL
5396 };
5397 struct drx_cfg_mpeg_output cfg_mpeg_output;
5398 int rc;
5399 u16 cmd_result = 0;
5400
5401 /*
5402 STOP demodulator
5403 reset of FEC and VSB HW
5404 */
5405 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5406 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5407 cmd_scu.parameter_len = 0;
5408 cmd_scu.result_len = 1;
5409 cmd_scu.parameter = NULL;
5410 cmd_scu.result = &cmd_result;
5411 rc = scu_command(dev_addr, &cmd_scu);
5412 if (rc != 0) {
5413 pr_err("error %d\n", rc);
5414 goto rw_error;
5415 }
5416
5417 /* stop all comm_exec */
5418 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5419 if (rc != 0) {
5420 pr_err("error %d\n", rc);
5421 goto rw_error;
5422 }
5423 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5424 if (rc != 0) {
5425 pr_err("error %d\n", rc);
5426 goto rw_error;
5427 }
5428 if (primary) {
5429 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5430 if (rc != 0) {
5431 pr_err("error %d\n", rc);
5432 goto rw_error;
5433 }
5434 rc = set_iqm_af(demod, false);
5435 if (rc != 0) {
5436 pr_err("error %d\n", rc);
5437 goto rw_error;
5438 }
5439 } else {
5440 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5441 if (rc != 0) {
5442 pr_err("error %d\n", rc);
5443 goto rw_error;
5444 }
5445 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5446 if (rc != 0) {
5447 pr_err("error %d\n", rc);
5448 goto rw_error;
5449 }
5450 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5451 if (rc != 0) {
5452 pr_err("error %d\n", rc);
5453 goto rw_error;
5454 }
5455 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5456 if (rc != 0) {
5457 pr_err("error %d\n", rc);
5458 goto rw_error;
5459 }
5460 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5461 if (rc != 0) {
5462 pr_err("error %d\n", rc);
5463 goto rw_error;
5464 }
5465 }
5466
5467 cfg_mpeg_output.enable_mpeg_output = false;
5468 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5469 if (rc != 0) {
5470 pr_err("error %d\n", rc);
5471 goto rw_error;
5472 }
5473
5474 return 0;
5475 rw_error:
5476 return rc;
5477 }
5478
5479 /**
5480 * \fn int set_vsb_leak_n_gain ()
5481 * \brief Set ATSC demod.
5482 * \param demod instance of demodulator.
5483 * \return int.
5484 */
5485 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5486 {
5487 struct i2c_device_addr *dev_addr = NULL;
5488 int rc;
5489
5490 const u8 vsb_ffe_leak_gain_ram0[] = {
5491 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */
5492 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */
5493 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */
5494 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */
5495 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */
5496 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */
5497 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */
5498 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */
5499 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */
5500 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */
5501 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */
5502 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */
5503 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */
5504 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */
5505 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */
5506 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */
5507 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */
5508 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */
5509 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */
5510 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */
5511 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */
5512 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */
5513 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */
5514 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */
5515 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */
5516 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */
5517 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */
5518 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */
5519 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */
5520 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */
5521 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */
5522 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */
5523 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */
5524 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */
5525 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */
5526 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */
5527 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */
5528 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */
5529 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */
5530 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */
5531 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */
5532 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */
5533 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */
5534 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */
5535 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */
5536 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */
5537 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */
5538 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */
5539 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */
5540 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */
5541 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */
5542 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */
5543 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */
5544 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */
5545 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */
5546 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */
5547 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */
5548 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */
5549 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */
5550 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */
5551 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */
5552 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */
5553 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */
5554 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */
5555 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */
5556 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */
5557 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */
5558 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */
5559 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */
5560 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */
5561 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */
5562 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */
5563 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */
5564 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */
5565 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */
5566 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */
5567 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */
5568 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */
5569 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */
5570 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */
5571 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */
5572 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */
5573 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */
5574 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */
5575 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */
5576 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */
5577 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */
5578 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */
5579 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */
5580 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */
5581 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */
5582 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */
5583 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */
5584 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */
5585 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */
5586 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */
5587 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */
5588 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */
5589 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */
5590 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */
5591 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */
5592 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */
5593 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */
5594 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */
5595 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */
5596 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */
5597 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */
5598 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */
5599 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */
5600 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */
5601 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */
5602 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */
5603 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */
5604 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */
5605 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */
5606 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */
5607 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */
5608 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */
5609 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */
5610 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */
5611 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */
5612 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */
5613 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */
5614 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */
5615 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */
5616 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */
5617 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */
5618 DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */
5619 };
5620
5621 const u8 vsb_ffe_leak_gain_ram1[] = {
5622 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */
5623 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */
5624 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */
5625 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */
5626 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */
5627 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */
5628 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */
5629 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */
5630 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */
5631 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */
5632 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */
5633 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */
5634 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */
5635 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */
5636 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */
5637 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */
5638 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */
5639 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */
5640 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */
5641 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */
5642 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */
5643 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */
5644 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */
5645 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */
5646 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */
5647 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */
5648 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */
5649 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */
5650 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */
5651 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */
5652 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */
5653 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */
5654 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */
5655 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */
5656 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */
5657 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */
5658 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */
5659 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */
5660 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */
5661 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */
5662 DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */
5663 DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */
5664 DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */
5665 DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */
5666 DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */
5667 DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */
5668 DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */
5669 DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */
5670 DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */
5671 DRXJ_16TO8(0x0000), /* DFETRAINGAIN */
5672 DRXJ_16TO8(0x2020), /* DFERCA1GAIN */
5673 DRXJ_16TO8(0x1010), /* DFERCA2GAIN */
5674 DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */
5675 DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */
5676 };
5677
5678 dev_addr = demod->my_i2c_dev_addr;
5679 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5680 if (rc != 0) {
5681 pr_err("error %d\n", rc);
5682 goto rw_error;
5683 }
5684 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5685 if (rc != 0) {
5686 pr_err("error %d\n", rc);
5687 goto rw_error;
5688 }
5689
5690 return 0;
5691 rw_error:
5692 return rc;
5693 }
5694
5695 /**
5696 * \fn int set_vsb()
5697 * \brief Set 8VSB demod.
5698 * \param demod instance of demodulator.
5699 * \return int.
5700 *
5701 */
5702 static int set_vsb(struct drx_demod_instance *demod)
5703 {
5704 struct i2c_device_addr *dev_addr = NULL;
5705 int rc;
5706 struct drx_common_attr *common_attr = NULL;
5707 struct drxjscu_cmd cmd_scu;
5708 struct drxj_data *ext_attr = NULL;
5709 u16 cmd_result = 0;
5710 u16 cmd_param = 0;
5711 const u8 vsb_taps_re[] = {
5712 DRXJ_16TO8(-2), /* re0 */
5713 DRXJ_16TO8(4), /* re1 */
5714 DRXJ_16TO8(1), /* re2 */
5715 DRXJ_16TO8(-4), /* re3 */
5716 DRXJ_16TO8(1), /* re4 */
5717 DRXJ_16TO8(4), /* re5 */
5718 DRXJ_16TO8(-3), /* re6 */
5719 DRXJ_16TO8(-3), /* re7 */
5720 DRXJ_16TO8(6), /* re8 */
5721 DRXJ_16TO8(1), /* re9 */
5722 DRXJ_16TO8(-9), /* re10 */
5723 DRXJ_16TO8(3), /* re11 */
5724 DRXJ_16TO8(12), /* re12 */
5725 DRXJ_16TO8(-9), /* re13 */
5726 DRXJ_16TO8(-15), /* re14 */
5727 DRXJ_16TO8(17), /* re15 */
5728 DRXJ_16TO8(19), /* re16 */
5729 DRXJ_16TO8(-29), /* re17 */
5730 DRXJ_16TO8(-22), /* re18 */
5731 DRXJ_16TO8(45), /* re19 */
5732 DRXJ_16TO8(25), /* re20 */
5733 DRXJ_16TO8(-70), /* re21 */
5734 DRXJ_16TO8(-28), /* re22 */
5735 DRXJ_16TO8(111), /* re23 */
5736 DRXJ_16TO8(30), /* re24 */
5737 DRXJ_16TO8(-201), /* re25 */
5738 DRXJ_16TO8(-31), /* re26 */
5739 DRXJ_16TO8(629) /* re27 */
5740 };
5741
5742 dev_addr = demod->my_i2c_dev_addr;
5743 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5744 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5745
5746 /* stop all comm_exec */
5747 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5748 if (rc != 0) {
5749 pr_err("error %d\n", rc);
5750 goto rw_error;
5751 }
5752 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5753 if (rc != 0) {
5754 pr_err("error %d\n", rc);
5755 goto rw_error;
5756 }
5757 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5758 if (rc != 0) {
5759 pr_err("error %d\n", rc);
5760 goto rw_error;
5761 }
5762 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5763 if (rc != 0) {
5764 pr_err("error %d\n", rc);
5765 goto rw_error;
5766 }
5767 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5768 if (rc != 0) {
5769 pr_err("error %d\n", rc);
5770 goto rw_error;
5771 }
5772 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5773 if (rc != 0) {
5774 pr_err("error %d\n", rc);
5775 goto rw_error;
5776 }
5777 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5778 if (rc != 0) {
5779 pr_err("error %d\n", rc);
5780 goto rw_error;
5781 }
5782
5783 /* reset demodulator */
5784 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5785 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5786 cmd_scu.parameter_len = 0;
5787 cmd_scu.result_len = 1;
5788 cmd_scu.parameter = NULL;
5789 cmd_scu.result = &cmd_result;
5790 rc = scu_command(dev_addr, &cmd_scu);
5791 if (rc != 0) {
5792 pr_err("error %d\n", rc);
5793 goto rw_error;
5794 }
5795
5796 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5797 if (rc != 0) {
5798 pr_err("error %d\n", rc);
5799 goto rw_error;
5800 }
5801 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5802 if (rc != 0) {
5803 pr_err("error %d\n", rc);
5804 goto rw_error;
5805 }
5806 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5807 if (rc != 0) {
5808 pr_err("error %d\n", rc);
5809 goto rw_error;
5810 }
5811 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5812 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5813 if (rc != 0) {
5814 pr_err("error %d\n", rc);
5815 goto rw_error;
5816 }
5817 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5818 if (rc != 0) {
5819 pr_err("error %d\n", rc);
5820 goto rw_error;
5821 }
5822 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5823 if (rc != 0) {
5824 pr_err("error %d\n", rc);
5825 goto rw_error;
5826 }
5827
5828 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5829 if (rc != 0) {
5830 pr_err("error %d\n", rc);
5831 goto rw_error;
5832 }
5833 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5834 if (rc != 0) {
5835 pr_err("error %d\n", rc);
5836 goto rw_error;
5837 }
5838 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5839 if (rc != 0) {
5840 pr_err("error %d\n", rc);
5841 goto rw_error;
5842 }
5843 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5844 if (rc != 0) {
5845 pr_err("error %d\n", rc);
5846 goto rw_error;
5847 }
5848 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5849 if (rc != 0) {
5850 pr_err("error %d\n", rc);
5851 goto rw_error;
5852 }
5853 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5854 if (rc != 0) {
5855 pr_err("error %d\n", rc);
5856 goto rw_error;
5857 }
5858 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5859 if (rc != 0) {
5860 pr_err("error %d\n", rc);
5861 goto rw_error;
5862 }
5863 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5864 if (rc != 0) {
5865 pr_err("error %d\n", rc);
5866 goto rw_error;
5867 }
5868 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5869 if (rc != 0) {
5870 pr_err("error %d\n", rc);
5871 goto rw_error;
5872 }
5873
5874 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5875 if (rc != 0) {
5876 pr_err("error %d\n", rc);
5877 goto rw_error;
5878 }
5879 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5880 if (rc != 0) {
5881 pr_err("error %d\n", rc);
5882 goto rw_error;
5883 }
5884
5885 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5886 if (rc != 0) {
5887 pr_err("error %d\n", rc);
5888 goto rw_error;
5889 } /* set higher threshold */
5890 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5891 if (rc != 0) {
5892 pr_err("error %d\n", rc);
5893 goto rw_error;
5894 } /* burst detection on */
5895 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5896 if (rc != 0) {
5897 pr_err("error %d\n", rc);
5898 goto rw_error;
5899 } /* drop thresholds by 1 dB */
5900 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5901 if (rc != 0) {
5902 pr_err("error %d\n", rc);
5903 goto rw_error;
5904 } /* drop thresholds by 2 dB */
5905 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5906 if (rc != 0) {
5907 pr_err("error %d\n", rc);
5908 goto rw_error;
5909 } /* cma on */
5910 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5911 if (rc != 0) {
5912 pr_err("error %d\n", rc);
5913 goto rw_error;
5914 } /* GPIO */
5915
5916 /* Initialize the FEC Subsystem */
5917 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5918 if (rc != 0) {
5919 pr_err("error %d\n", rc);
5920 goto rw_error;
5921 }
5922 {
5923 u16 fec_oc_snc_mode = 0;
5924 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5925 if (rc != 0) {
5926 pr_err("error %d\n", rc);
5927 goto rw_error;
5928 }
5929 /* output data even when not locked */
5930 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5931 if (rc != 0) {
5932 pr_err("error %d\n", rc);
5933 goto rw_error;
5934 }
5935 }
5936
5937 /* set clip */
5938 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5939 if (rc != 0) {
5940 pr_err("error %d\n", rc);
5941 goto rw_error;
5942 }
5943 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5944 if (rc != 0) {
5945 pr_err("error %d\n", rc);
5946 goto rw_error;
5947 }
5948 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5949 if (rc != 0) {
5950 pr_err("error %d\n", rc);
5951 goto rw_error;
5952 }
5953 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5954 if (rc != 0) {
5955 pr_err("error %d\n", rc);
5956 goto rw_error;
5957 }
5958 /* no transparent, no A&C framing; parity is set in mpegoutput */
5959 {
5960 u16 fec_oc_reg_mode = 0;
5961 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5962 if (rc != 0) {
5963 pr_err("error %d\n", rc);
5964 goto rw_error;
5965 }
5966 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5967 if (rc != 0) {
5968 pr_err("error %d\n", rc);
5969 goto rw_error;
5970 }
5971 }
5972
5973 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5974 if (rc != 0) {
5975 pr_err("error %d\n", rc);
5976 goto rw_error;
5977 } /* timeout counter for restarting */
5978 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5979 if (rc != 0) {
5980 pr_err("error %d\n", rc);
5981 goto rw_error;
5982 }
5983 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5984 if (rc != 0) {
5985 pr_err("error %d\n", rc);
5986 goto rw_error;
5987 } /* bypass disabled */
5988 /* initialize RS packet error measurement parameters */
5989 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
5990 if (rc != 0) {
5991 pr_err("error %d\n", rc);
5992 goto rw_error;
5993 }
5994 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
5995 if (rc != 0) {
5996 pr_err("error %d\n", rc);
5997 goto rw_error;
5998 }
5999
6000 /* init measurement period of MER/SER */
6001 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6002 if (rc != 0) {
6003 pr_err("error %d\n", rc);
6004 goto rw_error;
6005 }
6006 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6007 if (rc != 0) {
6008 pr_err("error %d\n", rc);
6009 goto rw_error;
6010 }
6011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6012 if (rc != 0) {
6013 pr_err("error %d\n", rc);
6014 goto rw_error;
6015 }
6016 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6017 if (rc != 0) {
6018 pr_err("error %d\n", rc);
6019 goto rw_error;
6020 }
6021
6022 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6023 if (rc != 0) {
6024 pr_err("error %d\n", rc);
6025 goto rw_error;
6026 }
6027 /* B-Input to ADC, PGA+filter in standby */
6028 if (!ext_attr->has_lna) {
6029 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6030 if (rc != 0) {
6031 pr_err("error %d\n", rc);
6032 goto rw_error;
6033 }
6034 }
6035
6036 /* turn on IQMAF. It has to be in front of setAgc**() */
6037 rc = set_iqm_af(demod, true);
6038 if (rc != 0) {
6039 pr_err("error %d\n", rc);
6040 goto rw_error;
6041 }
6042 rc = adc_synchronization(demod);
6043 if (rc != 0) {
6044 pr_err("error %d\n", rc);
6045 goto rw_error;
6046 }
6047
6048 rc = init_agc(demod);
6049 if (rc != 0) {
6050 pr_err("error %d\n", rc);
6051 goto rw_error;
6052 }
6053 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6054 if (rc != 0) {
6055 pr_err("error %d\n", rc);
6056 goto rw_error;
6057 }
6058 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6059 if (rc != 0) {
6060 pr_err("error %d\n", rc);
6061 goto rw_error;
6062 }
6063 {
6064 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
6065 of only the gain */
6066 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6067
6068 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6069 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6070 if (rc != 0) {
6071 pr_err("error %d\n", rc);
6072 goto rw_error;
6073 }
6074 }
6075 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6076 if (rc != 0) {
6077 pr_err("error %d\n", rc);
6078 goto rw_error;
6079 }
6080
6081 /* Mpeg output has to be in front of FEC active */
6082 rc = set_mpegtei_handling(demod);
6083 if (rc != 0) {
6084 pr_err("error %d\n", rc);
6085 goto rw_error;
6086 }
6087 rc = bit_reverse_mpeg_output(demod);
6088 if (rc != 0) {
6089 pr_err("error %d\n", rc);
6090 goto rw_error;
6091 }
6092 rc = set_mpeg_start_width(demod);
6093 if (rc != 0) {
6094 pr_err("error %d\n", rc);
6095 goto rw_error;
6096 }
6097 {
6098 /* TODO: move to set_standard after hardware reset value problem is solved */
6099 /* Configure initial MPEG output */
6100 struct drx_cfg_mpeg_output cfg_mpeg_output;
6101
6102 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6103 cfg_mpeg_output.enable_mpeg_output = true;
6104
6105 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6106 if (rc != 0) {
6107 pr_err("error %d\n", rc);
6108 goto rw_error;
6109 }
6110 }
6111
6112 /* TBD: what parameters should be set */
6113 cmd_param = 0x00; /* Default mode AGC on, etc */
6114 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6115 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6116 cmd_scu.parameter_len = 1;
6117 cmd_scu.result_len = 1;
6118 cmd_scu.parameter = &cmd_param;
6119 cmd_scu.result = &cmd_result;
6120 rc = scu_command(dev_addr, &cmd_scu);
6121 if (rc != 0) {
6122 pr_err("error %d\n", rc);
6123 goto rw_error;
6124 }
6125
6126 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6127 if (rc != 0) {
6128 pr_err("error %d\n", rc);
6129 goto rw_error;
6130 }
6131 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6132 if (rc != 0) {
6133 pr_err("error %d\n", rc);
6134 goto rw_error;
6135 }
6136 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6137 if (rc != 0) {
6138 pr_err("error %d\n", rc);
6139 goto rw_error;
6140 }
6141 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6142 if (rc != 0) {
6143 pr_err("error %d\n", rc);
6144 goto rw_error;
6145 }
6146 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6147 if (rc != 0) {
6148 pr_err("error %d\n", rc);
6149 goto rw_error;
6150 }
6151 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6152 if (rc != 0) {
6153 pr_err("error %d\n", rc);
6154 goto rw_error;
6155 }
6156 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6157 if (rc != 0) {
6158 pr_err("error %d\n", rc);
6159 goto rw_error;
6160 }
6161 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6162 if (rc != 0) {
6163 pr_err("error %d\n", rc);
6164 goto rw_error;
6165 }
6166
6167 /* start demodulator */
6168 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6169 | SCU_RAM_COMMAND_CMD_DEMOD_START;
6170 cmd_scu.parameter_len = 0;
6171 cmd_scu.result_len = 1;
6172 cmd_scu.parameter = NULL;
6173 cmd_scu.result = &cmd_result;
6174 rc = scu_command(dev_addr, &cmd_scu);
6175 if (rc != 0) {
6176 pr_err("error %d\n", rc);
6177 goto rw_error;
6178 }
6179
6180 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6181 if (rc != 0) {
6182 pr_err("error %d\n", rc);
6183 goto rw_error;
6184 }
6185 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6186 if (rc != 0) {
6187 pr_err("error %d\n", rc);
6188 goto rw_error;
6189 }
6190 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6191 if (rc != 0) {
6192 pr_err("error %d\n", rc);
6193 goto rw_error;
6194 }
6195
6196 return 0;
6197 rw_error:
6198 return rc;
6199 }
6200
6201 /**
6202 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
6203 * \brief Get the values of packet error in 8VSB mode
6204 * \return Error code
6205 */
6206 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6207 u32 *pck_errs, u32 *pck_count)
6208 {
6209 int rc;
6210 u16 data = 0;
6211 u16 period = 0;
6212 u16 prescale = 0;
6213 u16 packet_errors_mant = 0;
6214 u16 packet_errors_exp = 0;
6215
6216 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6217 if (rc != 0) {
6218 pr_err("error %d\n", rc);
6219 goto rw_error;
6220 }
6221 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6222 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6223 >> FEC_RS_NR_FAILURES_EXP__B;
6224 period = FEC_RS_MEASUREMENT_PERIOD;
6225 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6226 /* packet error rate = (error packet number) per second */
6227 /* 77.3 us is time for per packet */
6228 if (period * prescale == 0) {
6229 pr_err("error: period and/or prescale is zero!\n");
6230 return -EIO;
6231 }
6232 *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6233 *pck_count = period * prescale * 77;
6234
6235 return 0;
6236 rw_error:
6237 return rc;
6238 }
6239
6240 /**
6241 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
6242 * \brief Get the values of ber in VSB mode
6243 * \return Error code
6244 */
6245 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6246 u32 *ber, u32 *cnt)
6247 {
6248 int rc;
6249 u16 data = 0;
6250 u16 period = 0;
6251 u16 prescale = 0;
6252 u16 bit_errors_mant = 0;
6253 u16 bit_errors_exp = 0;
6254
6255 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6256 if (rc != 0) {
6257 pr_err("error %d\n", rc);
6258 goto rw_error;
6259 }
6260 period = FEC_RS_MEASUREMENT_PERIOD;
6261 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6262
6263 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6264 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6265 >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6266
6267 *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6268
6269 if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6270 *ber = (*cnt) * 26570;
6271 else {
6272 if (period * prescale == 0) {
6273 pr_err("error: period and/or prescale is zero!\n");
6274 return -EIO;
6275 }
6276 *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6277 (bit_errors_exp - 3) : bit_errors_exp);
6278 }
6279
6280 return 0;
6281 rw_error:
6282 return rc;
6283 }
6284
6285 /**
6286 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
6287 * \brief Get the values of ber in VSB mode
6288 * \return Error code
6289 */
6290 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6291 u32 *ber, u32 *cnt)
6292 {
6293 u16 data = 0;
6294 int rc;
6295
6296 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6297 if (rc != 0) {
6298 pr_err("error %d\n", rc);
6299 return -EIO;
6300 }
6301 *ber = data;
6302 *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6303
6304 return 0;
6305 }
6306
6307 /**
6308 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6309 * \brief Get the values of MER
6310 * \return Error code
6311 */
6312 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6313 {
6314 int rc;
6315 u16 data_hi = 0;
6316
6317 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6318 if (rc != 0) {
6319 pr_err("error %d\n", rc);
6320 goto rw_error;
6321 }
6322 *mer =
6323 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6324
6325 return 0;
6326 rw_error:
6327 return rc;
6328 }
6329
6330
6331 /*============================================================================*/
6332 /*== END 8VSB DATAPATH FUNCTIONS ==*/
6333 /*============================================================================*/
6334
6335 /*============================================================================*/
6336 /*============================================================================*/
6337 /*== QAM DATAPATH FUNCTIONS ==*/
6338 /*============================================================================*/
6339 /*============================================================================*/
6340
6341 /**
6342 * \fn int power_down_qam ()
6343 * \brief Powr down QAM related blocks.
6344 * \param demod instance of demodulator.
6345 * \param channel pointer to channel data.
6346 * \return int.
6347 */
6348 static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6349 {
6350 struct drxjscu_cmd cmd_scu = { /* command */ 0,
6351 /* parameter_len */ 0,
6352 /* result_len */ 0,
6353 /* *parameter */ NULL,
6354 /* *result */ NULL
6355 };
6356 int rc;
6357 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6358 struct drx_cfg_mpeg_output cfg_mpeg_output;
6359 struct drx_common_attr *common_attr = demod->my_common_attr;
6360 u16 cmd_result = 0;
6361
6362 /*
6363 STOP demodulator
6364 resets IQM, QAM and FEC HW blocks
6365 */
6366 /* stop all comm_exec */
6367 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6368 if (rc != 0) {
6369 pr_err("error %d\n", rc);
6370 goto rw_error;
6371 }
6372 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6373 if (rc != 0) {
6374 pr_err("error %d\n", rc);
6375 goto rw_error;
6376 }
6377
6378 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6379 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6380 cmd_scu.parameter_len = 0;
6381 cmd_scu.result_len = 1;
6382 cmd_scu.parameter = NULL;
6383 cmd_scu.result = &cmd_result;
6384 rc = scu_command(dev_addr, &cmd_scu);
6385 if (rc != 0) {
6386 pr_err("error %d\n", rc);
6387 goto rw_error;
6388 }
6389
6390 if (primary) {
6391 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6392 if (rc != 0) {
6393 pr_err("error %d\n", rc);
6394 goto rw_error;
6395 }
6396 rc = set_iqm_af(demod, false);
6397 if (rc != 0) {
6398 pr_err("error %d\n", rc);
6399 goto rw_error;
6400 }
6401 } else {
6402 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6403 if (rc != 0) {
6404 pr_err("error %d\n", rc);
6405 goto rw_error;
6406 }
6407 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6408 if (rc != 0) {
6409 pr_err("error %d\n", rc);
6410 goto rw_error;
6411 }
6412 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6413 if (rc != 0) {
6414 pr_err("error %d\n", rc);
6415 goto rw_error;
6416 }
6417 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6418 if (rc != 0) {
6419 pr_err("error %d\n", rc);
6420 goto rw_error;
6421 }
6422 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6423 if (rc != 0) {
6424 pr_err("error %d\n", rc);
6425 goto rw_error;
6426 }
6427 }
6428
6429 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6430 cfg_mpeg_output.enable_mpeg_output = false;
6431
6432 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6433 if (rc != 0) {
6434 pr_err("error %d\n", rc);
6435 goto rw_error;
6436 }
6437
6438 return 0;
6439 rw_error:
6440 return rc;
6441 }
6442
6443 /*============================================================================*/
6444
6445 /**
6446 * \fn int set_qam_measurement ()
6447 * \brief Setup of the QAM Measuremnt intervals for signal quality
6448 * \param demod instance of demod.
6449 * \param constellation current constellation.
6450 * \return int.
6451 *
6452 * NOTE:
6453 * Take into account that for certain settings the errorcounters can overflow.
6454 * The implementation does not check this.
6455 *
6456 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6457 * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
6458 * field ?
6459 *
6460 */
6461 #ifndef DRXJ_VSB_ONLY
6462 static int
6463 set_qam_measurement(struct drx_demod_instance *demod,
6464 enum drx_modulation constellation, u32 symbol_rate)
6465 {
6466 struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */
6467 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
6468 int rc;
6469 u32 fec_bits_desired = 0; /* BER accounting period */
6470 u16 fec_rs_plen = 0; /* defines RS BER measurement period */
6471 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
6472 u32 fec_rs_period = 0; /* Value for corresponding I2C register */
6473 u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
6474 u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
6475 u32 qam_vd_period = 0; /* Value for corresponding I2C register */
6476 u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
6477 u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */
6478 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
6479
6480 dev_addr = demod->my_i2c_dev_addr;
6481 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6482
6483 fec_bits_desired = ext_attr->fec_bits_desired;
6484 fec_rs_prescale = ext_attr->fec_rs_prescale;
6485
6486 switch (constellation) {
6487 case DRX_CONSTELLATION_QAM16:
6488 fec_bits_desired = 4 * symbol_rate;
6489 break;
6490 case DRX_CONSTELLATION_QAM32:
6491 fec_bits_desired = 5 * symbol_rate;
6492 break;
6493 case DRX_CONSTELLATION_QAM64:
6494 fec_bits_desired = 6 * symbol_rate;
6495 break;
6496 case DRX_CONSTELLATION_QAM128:
6497 fec_bits_desired = 7 * symbol_rate;
6498 break;
6499 case DRX_CONSTELLATION_QAM256:
6500 fec_bits_desired = 8 * symbol_rate;
6501 break;
6502 default:
6503 return -EINVAL;
6504 }
6505
6506 /* Parameters for Reed-Solomon Decoder */
6507 /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
6508 /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
6509 /* result is within 32 bit arithmetic -> */
6510 /* no need for mult or frac functions */
6511
6512 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6513 switch (ext_attr->standard) {
6514 case DRX_STANDARD_ITU_A:
6515 case DRX_STANDARD_ITU_C:
6516 fec_rs_plen = 204 * 8;
6517 break;
6518 case DRX_STANDARD_ITU_B:
6519 fec_rs_plen = 128 * 7;
6520 break;
6521 default:
6522 return -EINVAL;
6523 }
6524
6525 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
6526 fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */
6527 if (fec_rs_bit_cnt == 0) {
6528 pr_err("error: fec_rs_bit_cnt is zero!\n");
6529 return -EIO;
6530 }
6531 fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */
6532 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6533 fec_oc_snc_fail_period = fec_rs_period;
6534
6535 /* limit to max 16 bit value (I2C register width) if needed */
6536 if (fec_rs_period > 0xFFFF)
6537 fec_rs_period = 0xFFFF;
6538
6539 /* write corresponding registers */
6540 switch (ext_attr->standard) {
6541 case DRX_STANDARD_ITU_A:
6542 case DRX_STANDARD_ITU_C:
6543 break;
6544 case DRX_STANDARD_ITU_B:
6545 switch (constellation) {
6546 case DRX_CONSTELLATION_QAM64:
6547 fec_rs_period = 31581;
6548 fec_oc_snc_fail_period = 17932;
6549 break;
6550 case DRX_CONSTELLATION_QAM256:
6551 fec_rs_period = 45446;
6552 fec_oc_snc_fail_period = 25805;
6553 break;
6554 default:
6555 return -EINVAL;
6556 }
6557 break;
6558 default:
6559 return -EINVAL;
6560 }
6561
6562 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6563 if (rc != 0) {
6564 pr_err("error %d\n", rc);
6565 goto rw_error;
6566 }
6567 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6568 if (rc != 0) {
6569 pr_err("error %d\n", rc);
6570 goto rw_error;
6571 }
6572 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6573 if (rc != 0) {
6574 pr_err("error %d\n", rc);
6575 goto rw_error;
6576 }
6577 ext_attr->fec_rs_period = (u16) fec_rs_period;
6578 ext_attr->fec_rs_prescale = fec_rs_prescale;
6579 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6580 if (rc != 0) {
6581 pr_err("error %d\n", rc);
6582 goto rw_error;
6583 }
6584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6585 if (rc != 0) {
6586 pr_err("error %d\n", rc);
6587 goto rw_error;
6588 }
6589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6590 if (rc != 0) {
6591 pr_err("error %d\n", rc);
6592 goto rw_error;
6593 }
6594
6595 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6596 /* Parameters for Viterbi Decoder */
6597 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
6598 /* (qamvd_prescale*plen*(qam_constellation+1))) */
6599 /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
6600 /* result is within 32 bit arithmetic -> */
6601 /* no need for mult or frac functions */
6602
6603 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
6604 fec_vd_plen = ext_attr->fec_vd_plen;
6605 qam_vd_prescale = ext_attr->qam_vd_prescale;
6606 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
6607
6608 switch (constellation) {
6609 case DRX_CONSTELLATION_QAM64:
6610 /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
6611 qam_vd_period =
6612 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6613 * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6614 break;
6615 case DRX_CONSTELLATION_QAM256:
6616 /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
6617 qam_vd_period =
6618 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6619 * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6620 break;
6621 default:
6622 return -EINVAL;
6623 }
6624 if (qam_vd_period == 0) {
6625 pr_err("error: qam_vd_period is zero!\n");
6626 return -EIO;
6627 }
6628 qam_vd_period = fec_bits_desired / qam_vd_period;
6629 /* limit to max 16 bit value (I2C register width) if needed */
6630 if (qam_vd_period > 0xFFFF)
6631 qam_vd_period = 0xFFFF;
6632
6633 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
6634 qam_vd_bit_cnt *= qam_vd_period;
6635
6636 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6637 if (rc != 0) {
6638 pr_err("error %d\n", rc);
6639 goto rw_error;
6640 }
6641 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6642 if (rc != 0) {
6643 pr_err("error %d\n", rc);
6644 goto rw_error;
6645 }
6646 ext_attr->qam_vd_period = (u16) qam_vd_period;
6647 ext_attr->qam_vd_prescale = qam_vd_prescale;
6648 }
6649
6650 return 0;
6651 rw_error:
6652 return rc;
6653 }
6654
6655 /*============================================================================*/
6656
6657 /**
6658 * \fn int set_qam16 ()
6659 * \brief QAM16 specific setup
6660 * \param demod instance of demod.
6661 * \return int.
6662 */
6663 static int set_qam16(struct drx_demod_instance *demod)
6664 {
6665 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6666 int rc;
6667 const u8 qam_dq_qual_fun[] = {
6668 DRXJ_16TO8(2), /* fun0 */
6669 DRXJ_16TO8(2), /* fun1 */
6670 DRXJ_16TO8(2), /* fun2 */
6671 DRXJ_16TO8(2), /* fun3 */
6672 DRXJ_16TO8(3), /* fun4 */
6673 DRXJ_16TO8(3), /* fun5 */
6674 };
6675 const u8 qam_eq_cma_rad[] = {
6676 DRXJ_16TO8(13517), /* RAD0 */
6677 DRXJ_16TO8(13517), /* RAD1 */
6678 DRXJ_16TO8(13517), /* RAD2 */
6679 DRXJ_16TO8(13517), /* RAD3 */
6680 DRXJ_16TO8(13517), /* RAD4 */
6681 DRXJ_16TO8(13517), /* RAD5 */
6682 };
6683
6684 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6685 if (rc != 0) {
6686 pr_err("error %d\n", rc);
6687 goto rw_error;
6688 }
6689 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6690 if (rc != 0) {
6691 pr_err("error %d\n", rc);
6692 goto rw_error;
6693 }
6694
6695 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6696 if (rc != 0) {
6697 pr_err("error %d\n", rc);
6698 goto rw_error;
6699 }
6700 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6701 if (rc != 0) {
6702 pr_err("error %d\n", rc);
6703 goto rw_error;
6704 }
6705 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6706 if (rc != 0) {
6707 pr_err("error %d\n", rc);
6708 goto rw_error;
6709 }
6710 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6711 if (rc != 0) {
6712 pr_err("error %d\n", rc);
6713 goto rw_error;
6714 }
6715 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6716 if (rc != 0) {
6717 pr_err("error %d\n", rc);
6718 goto rw_error;
6719 }
6720 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6721 if (rc != 0) {
6722 pr_err("error %d\n", rc);
6723 goto rw_error;
6724 }
6725
6726 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6727 if (rc != 0) {
6728 pr_err("error %d\n", rc);
6729 goto rw_error;
6730 }
6731 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6732 if (rc != 0) {
6733 pr_err("error %d\n", rc);
6734 goto rw_error;
6735 }
6736 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6737 if (rc != 0) {
6738 pr_err("error %d\n", rc);
6739 goto rw_error;
6740 }
6741
6742 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6743 if (rc != 0) {
6744 pr_err("error %d\n", rc);
6745 goto rw_error;
6746 }
6747 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6748 if (rc != 0) {
6749 pr_err("error %d\n", rc);
6750 goto rw_error;
6751 }
6752 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6753 if (rc != 0) {
6754 pr_err("error %d\n", rc);
6755 goto rw_error;
6756 }
6757 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6758 if (rc != 0) {
6759 pr_err("error %d\n", rc);
6760 goto rw_error;
6761 }
6762 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6763 if (rc != 0) {
6764 pr_err("error %d\n", rc);
6765 goto rw_error;
6766 }
6767 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6768 if (rc != 0) {
6769 pr_err("error %d\n", rc);
6770 goto rw_error;
6771 }
6772 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6773 if (rc != 0) {
6774 pr_err("error %d\n", rc);
6775 goto rw_error;
6776 }
6777
6778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6779 if (rc != 0) {
6780 pr_err("error %d\n", rc);
6781 goto rw_error;
6782 }
6783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6784 if (rc != 0) {
6785 pr_err("error %d\n", rc);
6786 goto rw_error;
6787 }
6788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6789 if (rc != 0) {
6790 pr_err("error %d\n", rc);
6791 goto rw_error;
6792 }
6793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6794 if (rc != 0) {
6795 pr_err("error %d\n", rc);
6796 goto rw_error;
6797 }
6798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6799 if (rc != 0) {
6800 pr_err("error %d\n", rc);
6801 goto rw_error;
6802 }
6803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6804 if (rc != 0) {
6805 pr_err("error %d\n", rc);
6806 goto rw_error;
6807 }
6808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6809 if (rc != 0) {
6810 pr_err("error %d\n", rc);
6811 goto rw_error;
6812 }
6813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6814 if (rc != 0) {
6815 pr_err("error %d\n", rc);
6816 goto rw_error;
6817 }
6818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6819 if (rc != 0) {
6820 pr_err("error %d\n", rc);
6821 goto rw_error;
6822 }
6823 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6824 if (rc != 0) {
6825 pr_err("error %d\n", rc);
6826 goto rw_error;
6827 }
6828 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6829 if (rc != 0) {
6830 pr_err("error %d\n", rc);
6831 goto rw_error;
6832 }
6833 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6834 if (rc != 0) {
6835 pr_err("error %d\n", rc);
6836 goto rw_error;
6837 }
6838 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6839 if (rc != 0) {
6840 pr_err("error %d\n", rc);
6841 goto rw_error;
6842 }
6843 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6844 if (rc != 0) {
6845 pr_err("error %d\n", rc);
6846 goto rw_error;
6847 }
6848 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6849 if (rc != 0) {
6850 pr_err("error %d\n", rc);
6851 goto rw_error;
6852 }
6853 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6854 if (rc != 0) {
6855 pr_err("error %d\n", rc);
6856 goto rw_error;
6857 }
6858 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6859 if (rc != 0) {
6860 pr_err("error %d\n", rc);
6861 goto rw_error;
6862 }
6863 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6864 if (rc != 0) {
6865 pr_err("error %d\n", rc);
6866 goto rw_error;
6867 }
6868 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6869 if (rc != 0) {
6870 pr_err("error %d\n", rc);
6871 goto rw_error;
6872 }
6873 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6874 if (rc != 0) {
6875 pr_err("error %d\n", rc);
6876 goto rw_error;
6877 }
6878
6879 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6880 if (rc != 0) {
6881 pr_err("error %d\n", rc);
6882 goto rw_error;
6883 }
6884
6885 return 0;
6886 rw_error:
6887 return rc;
6888 }
6889
6890 /*============================================================================*/
6891
6892 /**
6893 * \fn int set_qam32 ()
6894 * \brief QAM32 specific setup
6895 * \param demod instance of demod.
6896 * \return int.
6897 */
6898 static int set_qam32(struct drx_demod_instance *demod)
6899 {
6900 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6901 int rc;
6902 const u8 qam_dq_qual_fun[] = {
6903 DRXJ_16TO8(3), /* fun0 */
6904 DRXJ_16TO8(3), /* fun1 */
6905 DRXJ_16TO8(3), /* fun2 */
6906 DRXJ_16TO8(3), /* fun3 */
6907 DRXJ_16TO8(4), /* fun4 */
6908 DRXJ_16TO8(4), /* fun5 */
6909 };
6910 const u8 qam_eq_cma_rad[] = {
6911 DRXJ_16TO8(6707), /* RAD0 */
6912 DRXJ_16TO8(6707), /* RAD1 */
6913 DRXJ_16TO8(6707), /* RAD2 */
6914 DRXJ_16TO8(6707), /* RAD3 */
6915 DRXJ_16TO8(6707), /* RAD4 */
6916 DRXJ_16TO8(6707), /* RAD5 */
6917 };
6918
6919 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6920 if (rc != 0) {
6921 pr_err("error %d\n", rc);
6922 goto rw_error;
6923 }
6924 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6925 if (rc != 0) {
6926 pr_err("error %d\n", rc);
6927 goto rw_error;
6928 }
6929
6930 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6931 if (rc != 0) {
6932 pr_err("error %d\n", rc);
6933 goto rw_error;
6934 }
6935 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6936 if (rc != 0) {
6937 pr_err("error %d\n", rc);
6938 goto rw_error;
6939 }
6940 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6941 if (rc != 0) {
6942 pr_err("error %d\n", rc);
6943 goto rw_error;
6944 }
6945 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6946 if (rc != 0) {
6947 pr_err("error %d\n", rc);
6948 goto rw_error;
6949 }
6950 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6951 if (rc != 0) {
6952 pr_err("error %d\n", rc);
6953 goto rw_error;
6954 }
6955 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6956 if (rc != 0) {
6957 pr_err("error %d\n", rc);
6958 goto rw_error;
6959 }
6960
6961 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6962 if (rc != 0) {
6963 pr_err("error %d\n", rc);
6964 goto rw_error;
6965 }
6966 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6967 if (rc != 0) {
6968 pr_err("error %d\n", rc);
6969 goto rw_error;
6970 }
6971 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6972 if (rc != 0) {
6973 pr_err("error %d\n", rc);
6974 goto rw_error;
6975 }
6976
6977 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6978 if (rc != 0) {
6979 pr_err("error %d\n", rc);
6980 goto rw_error;
6981 }
6982 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6983 if (rc != 0) {
6984 pr_err("error %d\n", rc);
6985 goto rw_error;
6986 }
6987 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6988 if (rc != 0) {
6989 pr_err("error %d\n", rc);
6990 goto rw_error;
6991 }
6992 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6993 if (rc != 0) {
6994 pr_err("error %d\n", rc);
6995 goto rw_error;
6996 }
6997 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
6998 if (rc != 0) {
6999 pr_err("error %d\n", rc);
7000 goto rw_error;
7001 }
7002 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7003 if (rc != 0) {
7004 pr_err("error %d\n", rc);
7005 goto rw_error;
7006 }
7007 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7008 if (rc != 0) {
7009 pr_err("error %d\n", rc);
7010 goto rw_error;
7011 }
7012
7013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7014 if (rc != 0) {
7015 pr_err("error %d\n", rc);
7016 goto rw_error;
7017 }
7018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7019 if (rc != 0) {
7020 pr_err("error %d\n", rc);
7021 goto rw_error;
7022 }
7023 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7024 if (rc != 0) {
7025 pr_err("error %d\n", rc);
7026 goto rw_error;
7027 }
7028 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7029 if (rc != 0) {
7030 pr_err("error %d\n", rc);
7031 goto rw_error;
7032 }
7033 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7034 if (rc != 0) {
7035 pr_err("error %d\n", rc);
7036 goto rw_error;
7037 }
7038 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7039 if (rc != 0) {
7040 pr_err("error %d\n", rc);
7041 goto rw_error;
7042 }
7043 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7044 if (rc != 0) {
7045 pr_err("error %d\n", rc);
7046 goto rw_error;
7047 }
7048 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7049 if (rc != 0) {
7050 pr_err("error %d\n", rc);
7051 goto rw_error;
7052 }
7053 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7054 if (rc != 0) {
7055 pr_err("error %d\n", rc);
7056 goto rw_error;
7057 }
7058 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7059 if (rc != 0) {
7060 pr_err("error %d\n", rc);
7061 goto rw_error;
7062 }
7063 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7064 if (rc != 0) {
7065 pr_err("error %d\n", rc);
7066 goto rw_error;
7067 }
7068 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7069 if (rc != 0) {
7070 pr_err("error %d\n", rc);
7071 goto rw_error;
7072 }
7073 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7074 if (rc != 0) {
7075 pr_err("error %d\n", rc);
7076 goto rw_error;
7077 }
7078 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7079 if (rc != 0) {
7080 pr_err("error %d\n", rc);
7081 goto rw_error;
7082 }
7083 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7084 if (rc != 0) {
7085 pr_err("error %d\n", rc);
7086 goto rw_error;
7087 }
7088 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7089 if (rc != 0) {
7090 pr_err("error %d\n", rc);
7091 goto rw_error;
7092 }
7093 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7094 if (rc != 0) {
7095 pr_err("error %d\n", rc);
7096 goto rw_error;
7097 }
7098 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7099 if (rc != 0) {
7100 pr_err("error %d\n", rc);
7101 goto rw_error;
7102 }
7103 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7104 if (rc != 0) {
7105 pr_err("error %d\n", rc);
7106 goto rw_error;
7107 }
7108 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7109 if (rc != 0) {
7110 pr_err("error %d\n", rc);
7111 goto rw_error;
7112 }
7113
7114 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7115 if (rc != 0) {
7116 pr_err("error %d\n", rc);
7117 goto rw_error;
7118 }
7119
7120 return 0;
7121 rw_error:
7122 return rc;
7123 }
7124
7125 /*============================================================================*/
7126
7127 /**
7128 * \fn int set_qam64 ()
7129 * \brief QAM64 specific setup
7130 * \param demod instance of demod.
7131 * \return int.
7132 */
7133 static int set_qam64(struct drx_demod_instance *demod)
7134 {
7135 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7136 int rc;
7137 const u8 qam_dq_qual_fun[] = { /* this is hw reset value. no necessary to re-write */
7138 DRXJ_16TO8(4), /* fun0 */
7139 DRXJ_16TO8(4), /* fun1 */
7140 DRXJ_16TO8(4), /* fun2 */
7141 DRXJ_16TO8(4), /* fun3 */
7142 DRXJ_16TO8(6), /* fun4 */
7143 DRXJ_16TO8(6), /* fun5 */
7144 };
7145 const u8 qam_eq_cma_rad[] = {
7146 DRXJ_16TO8(13336), /* RAD0 */
7147 DRXJ_16TO8(12618), /* RAD1 */
7148 DRXJ_16TO8(11988), /* RAD2 */
7149 DRXJ_16TO8(13809), /* RAD3 */
7150 DRXJ_16TO8(13809), /* RAD4 */
7151 DRXJ_16TO8(15609), /* RAD5 */
7152 };
7153
7154 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7155 if (rc != 0) {
7156 pr_err("error %d\n", rc);
7157 goto rw_error;
7158 }
7159 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7160 if (rc != 0) {
7161 pr_err("error %d\n", rc);
7162 goto rw_error;
7163 }
7164
7165 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7166 if (rc != 0) {
7167 pr_err("error %d\n", rc);
7168 goto rw_error;
7169 }
7170 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7171 if (rc != 0) {
7172 pr_err("error %d\n", rc);
7173 goto rw_error;
7174 }
7175 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7176 if (rc != 0) {
7177 pr_err("error %d\n", rc);
7178 goto rw_error;
7179 }
7180 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7181 if (rc != 0) {
7182 pr_err("error %d\n", rc);
7183 goto rw_error;
7184 }
7185 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7186 if (rc != 0) {
7187 pr_err("error %d\n", rc);
7188 goto rw_error;
7189 }
7190 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7191 if (rc != 0) {
7192 pr_err("error %d\n", rc);
7193 goto rw_error;
7194 }
7195
7196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7197 if (rc != 0) {
7198 pr_err("error %d\n", rc);
7199 goto rw_error;
7200 }
7201 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7202 if (rc != 0) {
7203 pr_err("error %d\n", rc);
7204 goto rw_error;
7205 }
7206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7207 if (rc != 0) {
7208 pr_err("error %d\n", rc);
7209 goto rw_error;
7210 }
7211
7212 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7213 if (rc != 0) {
7214 pr_err("error %d\n", rc);
7215 goto rw_error;
7216 }
7217 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7218 if (rc != 0) {
7219 pr_err("error %d\n", rc);
7220 goto rw_error;
7221 }
7222 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7223 if (rc != 0) {
7224 pr_err("error %d\n", rc);
7225 goto rw_error;
7226 }
7227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7228 if (rc != 0) {
7229 pr_err("error %d\n", rc);
7230 goto rw_error;
7231 }
7232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7233 if (rc != 0) {
7234 pr_err("error %d\n", rc);
7235 goto rw_error;
7236 }
7237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7238 if (rc != 0) {
7239 pr_err("error %d\n", rc);
7240 goto rw_error;
7241 }
7242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7243 if (rc != 0) {
7244 pr_err("error %d\n", rc);
7245 goto rw_error;
7246 }
7247
7248 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7249 if (rc != 0) {
7250 pr_err("error %d\n", rc);
7251 goto rw_error;
7252 }
7253 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7254 if (rc != 0) {
7255 pr_err("error %d\n", rc);
7256 goto rw_error;
7257 }
7258 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7259 if (rc != 0) {
7260 pr_err("error %d\n", rc);
7261 goto rw_error;
7262 }
7263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7264 if (rc != 0) {
7265 pr_err("error %d\n", rc);
7266 goto rw_error;
7267 }
7268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7269 if (rc != 0) {
7270 pr_err("error %d\n", rc);
7271 goto rw_error;
7272 }
7273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7274 if (rc != 0) {
7275 pr_err("error %d\n", rc);
7276 goto rw_error;
7277 }
7278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7279 if (rc != 0) {
7280 pr_err("error %d\n", rc);
7281 goto rw_error;
7282 }
7283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7284 if (rc != 0) {
7285 pr_err("error %d\n", rc);
7286 goto rw_error;
7287 }
7288 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7289 if (rc != 0) {
7290 pr_err("error %d\n", rc);
7291 goto rw_error;
7292 }
7293 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7294 if (rc != 0) {
7295 pr_err("error %d\n", rc);
7296 goto rw_error;
7297 }
7298 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7299 if (rc != 0) {
7300 pr_err("error %d\n", rc);
7301 goto rw_error;
7302 }
7303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7304 if (rc != 0) {
7305 pr_err("error %d\n", rc);
7306 goto rw_error;
7307 }
7308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7309 if (rc != 0) {
7310 pr_err("error %d\n", rc);
7311 goto rw_error;
7312 }
7313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7314 if (rc != 0) {
7315 pr_err("error %d\n", rc);
7316 goto rw_error;
7317 }
7318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7319 if (rc != 0) {
7320 pr_err("error %d\n", rc);
7321 goto rw_error;
7322 }
7323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7324 if (rc != 0) {
7325 pr_err("error %d\n", rc);
7326 goto rw_error;
7327 }
7328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7329 if (rc != 0) {
7330 pr_err("error %d\n", rc);
7331 goto rw_error;
7332 }
7333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7334 if (rc != 0) {
7335 pr_err("error %d\n", rc);
7336 goto rw_error;
7337 }
7338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7339 if (rc != 0) {
7340 pr_err("error %d\n", rc);
7341 goto rw_error;
7342 }
7343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7344 if (rc != 0) {
7345 pr_err("error %d\n", rc);
7346 goto rw_error;
7347 }
7348
7349 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7350 if (rc != 0) {
7351 pr_err("error %d\n", rc);
7352 goto rw_error;
7353 }
7354
7355 return 0;
7356 rw_error:
7357 return rc;
7358 }
7359
7360 /*============================================================================*/
7361
7362 /**
7363 * \fn int set_qam128 ()
7364 * \brief QAM128 specific setup
7365 * \param demod: instance of demod.
7366 * \return int.
7367 */
7368 static int set_qam128(struct drx_demod_instance *demod)
7369 {
7370 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7371 int rc;
7372 const u8 qam_dq_qual_fun[] = {
7373 DRXJ_16TO8(6), /* fun0 */
7374 DRXJ_16TO8(6), /* fun1 */
7375 DRXJ_16TO8(6), /* fun2 */
7376 DRXJ_16TO8(6), /* fun3 */
7377 DRXJ_16TO8(9), /* fun4 */
7378 DRXJ_16TO8(9), /* fun5 */
7379 };
7380 const u8 qam_eq_cma_rad[] = {
7381 DRXJ_16TO8(6164), /* RAD0 */
7382 DRXJ_16TO8(6598), /* RAD1 */
7383 DRXJ_16TO8(6394), /* RAD2 */
7384 DRXJ_16TO8(6409), /* RAD3 */
7385 DRXJ_16TO8(6656), /* RAD4 */
7386 DRXJ_16TO8(7238), /* RAD5 */
7387 };
7388
7389 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7390 if (rc != 0) {
7391 pr_err("error %d\n", rc);
7392 goto rw_error;
7393 }
7394 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7395 if (rc != 0) {
7396 pr_err("error %d\n", rc);
7397 goto rw_error;
7398 }
7399
7400 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7401 if (rc != 0) {
7402 pr_err("error %d\n", rc);
7403 goto rw_error;
7404 }
7405 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7406 if (rc != 0) {
7407 pr_err("error %d\n", rc);
7408 goto rw_error;
7409 }
7410 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7411 if (rc != 0) {
7412 pr_err("error %d\n", rc);
7413 goto rw_error;
7414 }
7415 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7416 if (rc != 0) {
7417 pr_err("error %d\n", rc);
7418 goto rw_error;
7419 }
7420 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7421 if (rc != 0) {
7422 pr_err("error %d\n", rc);
7423 goto rw_error;
7424 }
7425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7426 if (rc != 0) {
7427 pr_err("error %d\n", rc);
7428 goto rw_error;
7429 }
7430
7431 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7432 if (rc != 0) {
7433 pr_err("error %d\n", rc);
7434 goto rw_error;
7435 }
7436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7437 if (rc != 0) {
7438 pr_err("error %d\n", rc);
7439 goto rw_error;
7440 }
7441 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7442 if (rc != 0) {
7443 pr_err("error %d\n", rc);
7444 goto rw_error;
7445 }
7446
7447 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7448 if (rc != 0) {
7449 pr_err("error %d\n", rc);
7450 goto rw_error;
7451 }
7452 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7453 if (rc != 0) {
7454 pr_err("error %d\n", rc);
7455 goto rw_error;
7456 }
7457 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7458 if (rc != 0) {
7459 pr_err("error %d\n", rc);
7460 goto rw_error;
7461 }
7462 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7463 if (rc != 0) {
7464 pr_err("error %d\n", rc);
7465 goto rw_error;
7466 }
7467 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7468 if (rc != 0) {
7469 pr_err("error %d\n", rc);
7470 goto rw_error;
7471 }
7472 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7473 if (rc != 0) {
7474 pr_err("error %d\n", rc);
7475 goto rw_error;
7476 }
7477 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7478 if (rc != 0) {
7479 pr_err("error %d\n", rc);
7480 goto rw_error;
7481 }
7482
7483 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7484 if (rc != 0) {
7485 pr_err("error %d\n", rc);
7486 goto rw_error;
7487 }
7488 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7489 if (rc != 0) {
7490 pr_err("error %d\n", rc);
7491 goto rw_error;
7492 }
7493 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7494 if (rc != 0) {
7495 pr_err("error %d\n", rc);
7496 goto rw_error;
7497 }
7498 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7499 if (rc != 0) {
7500 pr_err("error %d\n", rc);
7501 goto rw_error;
7502 }
7503 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7504 if (rc != 0) {
7505 pr_err("error %d\n", rc);
7506 goto rw_error;
7507 }
7508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7509 if (rc != 0) {
7510 pr_err("error %d\n", rc);
7511 goto rw_error;
7512 }
7513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7514 if (rc != 0) {
7515 pr_err("error %d\n", rc);
7516 goto rw_error;
7517 }
7518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7519 if (rc != 0) {
7520 pr_err("error %d\n", rc);
7521 goto rw_error;
7522 }
7523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7524 if (rc != 0) {
7525 pr_err("error %d\n", rc);
7526 goto rw_error;
7527 }
7528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7529 if (rc != 0) {
7530 pr_err("error %d\n", rc);
7531 goto rw_error;
7532 }
7533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7534 if (rc != 0) {
7535 pr_err("error %d\n", rc);
7536 goto rw_error;
7537 }
7538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7539 if (rc != 0) {
7540 pr_err("error %d\n", rc);
7541 goto rw_error;
7542 }
7543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7544 if (rc != 0) {
7545 pr_err("error %d\n", rc);
7546 goto rw_error;
7547 }
7548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7549 if (rc != 0) {
7550 pr_err("error %d\n", rc);
7551 goto rw_error;
7552 }
7553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7554 if (rc != 0) {
7555 pr_err("error %d\n", rc);
7556 goto rw_error;
7557 }
7558 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7559 if (rc != 0) {
7560 pr_err("error %d\n", rc);
7561 goto rw_error;
7562 }
7563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7564 if (rc != 0) {
7565 pr_err("error %d\n", rc);
7566 goto rw_error;
7567 }
7568 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7569 if (rc != 0) {
7570 pr_err("error %d\n", rc);
7571 goto rw_error;
7572 }
7573 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7574 if (rc != 0) {
7575 pr_err("error %d\n", rc);
7576 goto rw_error;
7577 }
7578 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7579 if (rc != 0) {
7580 pr_err("error %d\n", rc);
7581 goto rw_error;
7582 }
7583
7584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7585 if (rc != 0) {
7586 pr_err("error %d\n", rc);
7587 goto rw_error;
7588 }
7589
7590 return 0;
7591 rw_error:
7592 return rc;
7593 }
7594
7595 /*============================================================================*/
7596
7597 /**
7598 * \fn int set_qam256 ()
7599 * \brief QAM256 specific setup
7600 * \param demod: instance of demod.
7601 * \return int.
7602 */
7603 static int set_qam256(struct drx_demod_instance *demod)
7604 {
7605 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7606 int rc;
7607 const u8 qam_dq_qual_fun[] = {
7608 DRXJ_16TO8(8), /* fun0 */
7609 DRXJ_16TO8(8), /* fun1 */
7610 DRXJ_16TO8(8), /* fun2 */
7611 DRXJ_16TO8(8), /* fun3 */
7612 DRXJ_16TO8(12), /* fun4 */
7613 DRXJ_16TO8(12), /* fun5 */
7614 };
7615 const u8 qam_eq_cma_rad[] = {
7616 DRXJ_16TO8(12345), /* RAD0 */
7617 DRXJ_16TO8(12345), /* RAD1 */
7618 DRXJ_16TO8(13626), /* RAD2 */
7619 DRXJ_16TO8(12931), /* RAD3 */
7620 DRXJ_16TO8(14719), /* RAD4 */
7621 DRXJ_16TO8(15356), /* RAD5 */
7622 };
7623
7624 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7625 if (rc != 0) {
7626 pr_err("error %d\n", rc);
7627 goto rw_error;
7628 }
7629 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7630 if (rc != 0) {
7631 pr_err("error %d\n", rc);
7632 goto rw_error;
7633 }
7634
7635 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7636 if (rc != 0) {
7637 pr_err("error %d\n", rc);
7638 goto rw_error;
7639 }
7640 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7641 if (rc != 0) {
7642 pr_err("error %d\n", rc);
7643 goto rw_error;
7644 }
7645 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7646 if (rc != 0) {
7647 pr_err("error %d\n", rc);
7648 goto rw_error;
7649 }
7650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7651 if (rc != 0) {
7652 pr_err("error %d\n", rc);
7653 goto rw_error;
7654 }
7655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7656 if (rc != 0) {
7657 pr_err("error %d\n", rc);
7658 goto rw_error;
7659 }
7660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7661 if (rc != 0) {
7662 pr_err("error %d\n", rc);
7663 goto rw_error;
7664 }
7665
7666 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7667 if (rc != 0) {
7668 pr_err("error %d\n", rc);
7669 goto rw_error;
7670 }
7671 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7672 if (rc != 0) {
7673 pr_err("error %d\n", rc);
7674 goto rw_error;
7675 }
7676 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7677 if (rc != 0) {
7678 pr_err("error %d\n", rc);
7679 goto rw_error;
7680 }
7681
7682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7683 if (rc != 0) {
7684 pr_err("error %d\n", rc);
7685 goto rw_error;
7686 }
7687 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7688 if (rc != 0) {
7689 pr_err("error %d\n", rc);
7690 goto rw_error;
7691 }
7692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7693 if (rc != 0) {
7694 pr_err("error %d\n", rc);
7695 goto rw_error;
7696 }
7697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7698 if (rc != 0) {
7699 pr_err("error %d\n", rc);
7700 goto rw_error;
7701 }
7702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7703 if (rc != 0) {
7704 pr_err("error %d\n", rc);
7705 goto rw_error;
7706 }
7707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7708 if (rc != 0) {
7709 pr_err("error %d\n", rc);
7710 goto rw_error;
7711 }
7712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7713 if (rc != 0) {
7714 pr_err("error %d\n", rc);
7715 goto rw_error;
7716 }
7717
7718 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7719 if (rc != 0) {
7720 pr_err("error %d\n", rc);
7721 goto rw_error;
7722 }
7723 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7724 if (rc != 0) {
7725 pr_err("error %d\n", rc);
7726 goto rw_error;
7727 }
7728 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7729 if (rc != 0) {
7730 pr_err("error %d\n", rc);
7731 goto rw_error;
7732 }
7733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7734 if (rc != 0) {
7735 pr_err("error %d\n", rc);
7736 goto rw_error;
7737 }
7738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7739 if (rc != 0) {
7740 pr_err("error %d\n", rc);
7741 goto rw_error;
7742 }
7743 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7744 if (rc != 0) {
7745 pr_err("error %d\n", rc);
7746 goto rw_error;
7747 }
7748 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7749 if (rc != 0) {
7750 pr_err("error %d\n", rc);
7751 goto rw_error;
7752 }
7753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7754 if (rc != 0) {
7755 pr_err("error %d\n", rc);
7756 goto rw_error;
7757 }
7758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7759 if (rc != 0) {
7760 pr_err("error %d\n", rc);
7761 goto rw_error;
7762 }
7763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7764 if (rc != 0) {
7765 pr_err("error %d\n", rc);
7766 goto rw_error;
7767 }
7768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7769 if (rc != 0) {
7770 pr_err("error %d\n", rc);
7771 goto rw_error;
7772 }
7773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7774 if (rc != 0) {
7775 pr_err("error %d\n", rc);
7776 goto rw_error;
7777 }
7778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7779 if (rc != 0) {
7780 pr_err("error %d\n", rc);
7781 goto rw_error;
7782 }
7783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7784 if (rc != 0) {
7785 pr_err("error %d\n", rc);
7786 goto rw_error;
7787 }
7788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7789 if (rc != 0) {
7790 pr_err("error %d\n", rc);
7791 goto rw_error;
7792 }
7793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7794 if (rc != 0) {
7795 pr_err("error %d\n", rc);
7796 goto rw_error;
7797 }
7798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7799 if (rc != 0) {
7800 pr_err("error %d\n", rc);
7801 goto rw_error;
7802 }
7803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7804 if (rc != 0) {
7805 pr_err("error %d\n", rc);
7806 goto rw_error;
7807 }
7808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7809 if (rc != 0) {
7810 pr_err("error %d\n", rc);
7811 goto rw_error;
7812 }
7813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7814 if (rc != 0) {
7815 pr_err("error %d\n", rc);
7816 goto rw_error;
7817 }
7818
7819 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7820 if (rc != 0) {
7821 pr_err("error %d\n", rc);
7822 goto rw_error;
7823 }
7824
7825 return 0;
7826 rw_error:
7827 return rc;
7828 }
7829
7830 /*============================================================================*/
7831 #define QAM_SET_OP_ALL 0x1
7832 #define QAM_SET_OP_CONSTELLATION 0x2
7833 #define QAM_SET_OP_SPECTRUM 0X4
7834
7835 /**
7836 * \fn int set_qam ()
7837 * \brief Set QAM demod.
7838 * \param demod: instance of demod.
7839 * \param channel: pointer to channel data.
7840 * \return int.
7841 */
7842 static int
7843 set_qam(struct drx_demod_instance *demod,
7844 struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7845 {
7846 struct i2c_device_addr *dev_addr = NULL;
7847 struct drxj_data *ext_attr = NULL;
7848 struct drx_common_attr *common_attr = NULL;
7849 int rc;
7850 u32 adc_frequency = 0;
7851 u32 iqm_rc_rate = 0;
7852 u16 cmd_result = 0;
7853 u16 lc_symbol_freq = 0;
7854 u16 iqm_rc_stretch = 0;
7855 u16 set_env_parameters = 0;
7856 u16 set_param_parameters[2] = { 0 };
7857 struct drxjscu_cmd cmd_scu = { /* command */ 0,
7858 /* parameter_len */ 0,
7859 /* result_len */ 0,
7860 /* parameter */ NULL,
7861 /* result */ NULL
7862 };
7863 const u8 qam_a_taps[] = {
7864 DRXJ_16TO8(-1), /* re0 */
7865 DRXJ_16TO8(1), /* re1 */
7866 DRXJ_16TO8(1), /* re2 */
7867 DRXJ_16TO8(-1), /* re3 */
7868 DRXJ_16TO8(-1), /* re4 */
7869 DRXJ_16TO8(2), /* re5 */
7870 DRXJ_16TO8(1), /* re6 */
7871 DRXJ_16TO8(-2), /* re7 */
7872 DRXJ_16TO8(0), /* re8 */
7873 DRXJ_16TO8(3), /* re9 */
7874 DRXJ_16TO8(-1), /* re10 */
7875 DRXJ_16TO8(-3), /* re11 */
7876 DRXJ_16TO8(4), /* re12 */
7877 DRXJ_16TO8(1), /* re13 */
7878 DRXJ_16TO8(-8), /* re14 */
7879 DRXJ_16TO8(4), /* re15 */
7880 DRXJ_16TO8(13), /* re16 */
7881 DRXJ_16TO8(-13), /* re17 */
7882 DRXJ_16TO8(-19), /* re18 */
7883 DRXJ_16TO8(28), /* re19 */
7884 DRXJ_16TO8(25), /* re20 */
7885 DRXJ_16TO8(-53), /* re21 */
7886 DRXJ_16TO8(-31), /* re22 */
7887 DRXJ_16TO8(96), /* re23 */
7888 DRXJ_16TO8(37), /* re24 */
7889 DRXJ_16TO8(-190), /* re25 */
7890 DRXJ_16TO8(-40), /* re26 */
7891 DRXJ_16TO8(619) /* re27 */
7892 };
7893 const u8 qam_b64_taps[] = {
7894 DRXJ_16TO8(0), /* re0 */
7895 DRXJ_16TO8(-2), /* re1 */
7896 DRXJ_16TO8(1), /* re2 */
7897 DRXJ_16TO8(2), /* re3 */
7898 DRXJ_16TO8(-2), /* re4 */
7899 DRXJ_16TO8(0), /* re5 */
7900 DRXJ_16TO8(4), /* re6 */
7901 DRXJ_16TO8(-2), /* re7 */
7902 DRXJ_16TO8(-4), /* re8 */
7903 DRXJ_16TO8(4), /* re9 */
7904 DRXJ_16TO8(3), /* re10 */
7905 DRXJ_16TO8(-6), /* re11 */
7906 DRXJ_16TO8(0), /* re12 */
7907 DRXJ_16TO8(6), /* re13 */
7908 DRXJ_16TO8(-5), /* re14 */
7909 DRXJ_16TO8(-3), /* re15 */
7910 DRXJ_16TO8(11), /* re16 */
7911 DRXJ_16TO8(-4), /* re17 */
7912 DRXJ_16TO8(-19), /* re18 */
7913 DRXJ_16TO8(19), /* re19 */
7914 DRXJ_16TO8(28), /* re20 */
7915 DRXJ_16TO8(-45), /* re21 */
7916 DRXJ_16TO8(-36), /* re22 */
7917 DRXJ_16TO8(90), /* re23 */
7918 DRXJ_16TO8(42), /* re24 */
7919 DRXJ_16TO8(-185), /* re25 */
7920 DRXJ_16TO8(-46), /* re26 */
7921 DRXJ_16TO8(614) /* re27 */
7922 };
7923 const u8 qam_b256_taps[] = {
7924 DRXJ_16TO8(-2), /* re0 */
7925 DRXJ_16TO8(4), /* re1 */
7926 DRXJ_16TO8(1), /* re2 */
7927 DRXJ_16TO8(-4), /* re3 */
7928 DRXJ_16TO8(0), /* re4 */
7929 DRXJ_16TO8(4), /* re5 */
7930 DRXJ_16TO8(-2), /* re6 */
7931 DRXJ_16TO8(-4), /* re7 */
7932 DRXJ_16TO8(5), /* re8 */
7933 DRXJ_16TO8(2), /* re9 */
7934 DRXJ_16TO8(-8), /* re10 */
7935 DRXJ_16TO8(2), /* re11 */
7936 DRXJ_16TO8(11), /* re12 */
7937 DRXJ_16TO8(-8), /* re13 */
7938 DRXJ_16TO8(-15), /* re14 */
7939 DRXJ_16TO8(16), /* re15 */
7940 DRXJ_16TO8(19), /* re16 */
7941 DRXJ_16TO8(-27), /* re17 */
7942 DRXJ_16TO8(-22), /* re18 */
7943 DRXJ_16TO8(44), /* re19 */
7944 DRXJ_16TO8(26), /* re20 */
7945 DRXJ_16TO8(-69), /* re21 */
7946 DRXJ_16TO8(-28), /* re22 */
7947 DRXJ_16TO8(110), /* re23 */
7948 DRXJ_16TO8(31), /* re24 */
7949 DRXJ_16TO8(-201), /* re25 */
7950 DRXJ_16TO8(-32), /* re26 */
7951 DRXJ_16TO8(628) /* re27 */
7952 };
7953 const u8 qam_c_taps[] = {
7954 DRXJ_16TO8(-3), /* re0 */
7955 DRXJ_16TO8(3), /* re1 */
7956 DRXJ_16TO8(2), /* re2 */
7957 DRXJ_16TO8(-4), /* re3 */
7958 DRXJ_16TO8(0), /* re4 */
7959 DRXJ_16TO8(4), /* re5 */
7960 DRXJ_16TO8(-1), /* re6 */
7961 DRXJ_16TO8(-4), /* re7 */
7962 DRXJ_16TO8(3), /* re8 */
7963 DRXJ_16TO8(3), /* re9 */
7964 DRXJ_16TO8(-5), /* re10 */
7965 DRXJ_16TO8(0), /* re11 */
7966 DRXJ_16TO8(9), /* re12 */
7967 DRXJ_16TO8(-4), /* re13 */
7968 DRXJ_16TO8(-12), /* re14 */
7969 DRXJ_16TO8(10), /* re15 */
7970 DRXJ_16TO8(16), /* re16 */
7971 DRXJ_16TO8(-21), /* re17 */
7972 DRXJ_16TO8(-20), /* re18 */
7973 DRXJ_16TO8(37), /* re19 */
7974 DRXJ_16TO8(25), /* re20 */
7975 DRXJ_16TO8(-62), /* re21 */
7976 DRXJ_16TO8(-28), /* re22 */
7977 DRXJ_16TO8(105), /* re23 */
7978 DRXJ_16TO8(31), /* re24 */
7979 DRXJ_16TO8(-197), /* re25 */
7980 DRXJ_16TO8(-33), /* re26 */
7981 DRXJ_16TO8(626) /* re27 */
7982 };
7983
7984 dev_addr = demod->my_i2c_dev_addr;
7985 ext_attr = (struct drxj_data *) demod->my_ext_attr;
7986 common_attr = (struct drx_common_attr *) demod->my_common_attr;
7987
7988 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
7989 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7990 switch (channel->constellation) {
7991 case DRX_CONSTELLATION_QAM256:
7992 iqm_rc_rate = 0x00AE3562;
7993 lc_symbol_freq =
7994 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
7995 channel->symbolrate = 5360537;
7996 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
7997 break;
7998 case DRX_CONSTELLATION_QAM64:
7999 iqm_rc_rate = 0x00C05A0E;
8000 lc_symbol_freq = 409;
8001 channel->symbolrate = 5056941;
8002 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8003 break;
8004 default:
8005 return -EINVAL;
8006 }
8007 } else {
8008 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8009 if (channel->symbolrate == 0) {
8010 pr_err("error: channel symbolrate is zero!\n");
8011 return -EIO;
8012 }
8013 iqm_rc_rate =
8014 (adc_frequency / channel->symbolrate) * (1 << 21) +
8015 (frac28
8016 ((adc_frequency % channel->symbolrate),
8017 channel->symbolrate) >> 7) - (1 << 23);
8018 lc_symbol_freq =
8019 (u16) (frac28
8020 (channel->symbolrate +
8021 (adc_frequency >> 13),
8022 adc_frequency) >> 16);
8023 if (lc_symbol_freq > 511)
8024 lc_symbol_freq = 511;
8025
8026 iqm_rc_stretch = 21;
8027 }
8028
8029 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8030 set_env_parameters = QAM_TOP_ANNEX_A; /* annex */
8031 set_param_parameters[0] = channel->constellation; /* constellation */
8032 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8033 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8034 set_env_parameters = QAM_TOP_ANNEX_B; /* annex */
8035 set_param_parameters[0] = channel->constellation; /* constellation */
8036 set_param_parameters[1] = channel->interleavemode; /* interleave mode */
8037 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8038 set_env_parameters = QAM_TOP_ANNEX_C; /* annex */
8039 set_param_parameters[0] = channel->constellation; /* constellation */
8040 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8041 } else {
8042 return -EINVAL;
8043 }
8044 }
8045
8046 if (op & QAM_SET_OP_ALL) {
8047 /*
8048 STEP 1: reset demodulator
8049 resets IQM, QAM and FEC HW blocks
8050 resets SCU variables
8051 */
8052 /* stop all comm_exec */
8053 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8054 if (rc != 0) {
8055 pr_err("error %d\n", rc);
8056 goto rw_error;
8057 }
8058 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8059 if (rc != 0) {
8060 pr_err("error %d\n", rc);
8061 goto rw_error;
8062 }
8063 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8064 if (rc != 0) {
8065 pr_err("error %d\n", rc);
8066 goto rw_error;
8067 }
8068 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8069 if (rc != 0) {
8070 pr_err("error %d\n", rc);
8071 goto rw_error;
8072 }
8073 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8074 if (rc != 0) {
8075 pr_err("error %d\n", rc);
8076 goto rw_error;
8077 }
8078 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8079 if (rc != 0) {
8080 pr_err("error %d\n", rc);
8081 goto rw_error;
8082 }
8083 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8084 if (rc != 0) {
8085 pr_err("error %d\n", rc);
8086 goto rw_error;
8087 }
8088
8089 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8090 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8091 cmd_scu.parameter_len = 0;
8092 cmd_scu.result_len = 1;
8093 cmd_scu.parameter = NULL;
8094 cmd_scu.result = &cmd_result;
8095 rc = scu_command(dev_addr, &cmd_scu);
8096 if (rc != 0) {
8097 pr_err("error %d\n", rc);
8098 goto rw_error;
8099 }
8100 }
8101
8102 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8103 /*
8104 STEP 2: configure demodulator
8105 -set env
8106 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8107 */
8108 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8109 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8110 cmd_scu.parameter_len = 1;
8111 cmd_scu.result_len = 1;
8112 cmd_scu.parameter = &set_env_parameters;
8113 cmd_scu.result = &cmd_result;
8114 rc = scu_command(dev_addr, &cmd_scu);
8115 if (rc != 0) {
8116 pr_err("error %d\n", rc);
8117 goto rw_error;
8118 }
8119
8120 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8121 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8122 cmd_scu.parameter_len = 2;
8123 cmd_scu.result_len = 1;
8124 cmd_scu.parameter = set_param_parameters;
8125 cmd_scu.result = &cmd_result;
8126 rc = scu_command(dev_addr, &cmd_scu);
8127 if (rc != 0) {
8128 pr_err("error %d\n", rc);
8129 goto rw_error;
8130 }
8131 /* set symbol rate */
8132 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8133 if (rc != 0) {
8134 pr_err("error %d\n", rc);
8135 goto rw_error;
8136 }
8137 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8138 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8139 if (rc != 0) {
8140 pr_err("error %d\n", rc);
8141 goto rw_error;
8142 }
8143 }
8144 /* STEP 3: enable the system in a mode where the ADC provides valid signal
8145 setup constellation independent registers */
8146 /* from qam_cmd.py script (qam_driver_b) */
8147 /* TODO: remove re-writes of HW reset values */
8148 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8149 rc = set_frequency(demod, channel, tuner_freq_offset);
8150 if (rc != 0) {
8151 pr_err("error %d\n", rc);
8152 goto rw_error;
8153 }
8154 }
8155
8156 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8157
8158 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8159 if (rc != 0) {
8160 pr_err("error %d\n", rc);
8161 goto rw_error;
8162 }
8163 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8164 if (rc != 0) {
8165 pr_err("error %d\n", rc);
8166 goto rw_error;
8167 }
8168 }
8169
8170 if (op & QAM_SET_OP_ALL) {
8171 if (!ext_attr->has_lna) {
8172 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8173 if (rc != 0) {
8174 pr_err("error %d\n", rc);
8175 goto rw_error;
8176 }
8177 }
8178 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8179 if (rc != 0) {
8180 pr_err("error %d\n", rc);
8181 goto rw_error;
8182 }
8183 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8184 if (rc != 0) {
8185 pr_err("error %d\n", rc);
8186 goto rw_error;
8187 }
8188 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8189 if (rc != 0) {
8190 pr_err("error %d\n", rc);
8191 goto rw_error;
8192 }
8193
8194 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8195 if (rc != 0) {
8196 pr_err("error %d\n", rc);
8197 goto rw_error;
8198 } /* scu temporary shut down agc */
8199
8200 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8201 if (rc != 0) {
8202 pr_err("error %d\n", rc);
8203 goto rw_error;
8204 }
8205 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8206 if (rc != 0) {
8207 pr_err("error %d\n", rc);
8208 goto rw_error;
8209 }
8210 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8211 if (rc != 0) {
8212 pr_err("error %d\n", rc);
8213 goto rw_error;
8214 }
8215 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8216 if (rc != 0) {
8217 pr_err("error %d\n", rc);
8218 goto rw_error;
8219 }
8220 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8221 if (rc != 0) {
8222 pr_err("error %d\n", rc);
8223 goto rw_error;
8224 }
8225 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8226 if (rc != 0) {
8227 pr_err("error %d\n", rc);
8228 goto rw_error;
8229 }
8230 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8231 if (rc != 0) {
8232 pr_err("error %d\n", rc);
8233 goto rw_error;
8234 }
8235
8236 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8237 if (rc != 0) {
8238 pr_err("error %d\n", rc);
8239 goto rw_error;
8240 }
8241 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8242 if (rc != 0) {
8243 pr_err("error %d\n", rc);
8244 goto rw_error;
8245 } /*! reset default val ! */
8246
8247 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8248 if (rc != 0) {
8249 pr_err("error %d\n", rc);
8250 goto rw_error;
8251 } /*! reset default val ! */
8252 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8253 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8254 if (rc != 0) {
8255 pr_err("error %d\n", rc);
8256 goto rw_error;
8257 } /*! reset default val ! */
8258 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8259 if (rc != 0) {
8260 pr_err("error %d\n", rc);
8261 goto rw_error;
8262 } /*! reset default val ! */
8263 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8264 if (rc != 0) {
8265 pr_err("error %d\n", rc);
8266 goto rw_error;
8267 } /*! reset default val ! */
8268 } else {
8269 switch (channel->constellation) {
8270 case DRX_CONSTELLATION_QAM16:
8271 case DRX_CONSTELLATION_QAM64:
8272 case DRX_CONSTELLATION_QAM256:
8273 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8274 if (rc != 0) {
8275 pr_err("error %d\n", rc);
8276 goto rw_error;
8277 }
8278 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8279 if (rc != 0) {
8280 pr_err("error %d\n", rc);
8281 goto rw_error;
8282 }
8283 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8284 if (rc != 0) {
8285 pr_err("error %d\n", rc);
8286 goto rw_error;
8287 } /*! reset default val ! */
8288 break;
8289 case DRX_CONSTELLATION_QAM32:
8290 case DRX_CONSTELLATION_QAM128:
8291 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8292 if (rc != 0) {
8293 pr_err("error %d\n", rc);
8294 goto rw_error;
8295 }
8296 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8297 if (rc != 0) {
8298 pr_err("error %d\n", rc);
8299 goto rw_error;
8300 }
8301 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8302 if (rc != 0) {
8303 pr_err("error %d\n", rc);
8304 goto rw_error;
8305 }
8306 break;
8307 default:
8308 return -EIO;
8309 } /* switch */
8310 }
8311
8312 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8313 if (rc != 0) {
8314 pr_err("error %d\n", rc);
8315 goto rw_error;
8316 } /*! reset default val ! */
8317 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8318 if (rc != 0) {
8319 pr_err("error %d\n", rc);
8320 goto rw_error;
8321 }
8322 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8323 if (rc != 0) {
8324 pr_err("error %d\n", rc);
8325 goto rw_error;
8326 }
8327 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8328 if (rc != 0) {
8329 pr_err("error %d\n", rc);
8330 goto rw_error;
8331 }
8332 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8333 if (rc != 0) {
8334 pr_err("error %d\n", rc);
8335 goto rw_error;
8336 }
8337 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8338 if (rc != 0) {
8339 pr_err("error %d\n", rc);
8340 goto rw_error;
8341 }
8342 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8343 if (rc != 0) {
8344 pr_err("error %d\n", rc);
8345 goto rw_error;
8346 }
8347 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8348 if (rc != 0) {
8349 pr_err("error %d\n", rc);
8350 goto rw_error;
8351 }
8352 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8353 if (rc != 0) {
8354 pr_err("error %d\n", rc);
8355 goto rw_error;
8356 }
8357 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8358 if (rc != 0) {
8359 pr_err("error %d\n", rc);
8360 goto rw_error;
8361 }
8362 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8363 if (rc != 0) {
8364 pr_err("error %d\n", rc);
8365 goto rw_error;
8366 }
8367 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8368 if (rc != 0) {
8369 pr_err("error %d\n", rc);
8370 goto rw_error;
8371 }
8372 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8373 if (rc != 0) {
8374 pr_err("error %d\n", rc);
8375 goto rw_error;
8376 }
8377 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8378 if (rc != 0) {
8379 pr_err("error %d\n", rc);
8380 goto rw_error;
8381 }
8382 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8383 if (rc != 0) {
8384 pr_err("error %d\n", rc);
8385 goto rw_error;
8386 }
8387 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8388 if (rc != 0) {
8389 pr_err("error %d\n", rc);
8390 goto rw_error;
8391 }
8392 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8393 if (rc != 0) {
8394 pr_err("error %d\n", rc);
8395 goto rw_error;
8396 }
8397 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8398 if (rc != 0) {
8399 pr_err("error %d\n", rc);
8400 goto rw_error;
8401 }
8402 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8403 if (rc != 0) {
8404 pr_err("error %d\n", rc);
8405 goto rw_error;
8406 }
8407 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8408 if (rc != 0) {
8409 pr_err("error %d\n", rc);
8410 goto rw_error;
8411 }
8412
8413 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8414 if (rc != 0) {
8415 pr_err("error %d\n", rc);
8416 goto rw_error;
8417 }
8418 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8419 if (rc != 0) {
8420 pr_err("error %d\n", rc);
8421 goto rw_error;
8422 }
8423 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8424 if (rc != 0) {
8425 pr_err("error %d\n", rc);
8426 goto rw_error;
8427 }
8428 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8429 if (rc != 0) {
8430 pr_err("error %d\n", rc);
8431 goto rw_error;
8432 }
8433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8434 if (rc != 0) {
8435 pr_err("error %d\n", rc);
8436 goto rw_error;
8437 }
8438
8439 /* No more resets of the IQM, current standard correctly set =>
8440 now AGCs can be configured. */
8441 /* turn on IQMAF. It has to be in front of setAgc**() */
8442 rc = set_iqm_af(demod, true);
8443 if (rc != 0) {
8444 pr_err("error %d\n", rc);
8445 goto rw_error;
8446 }
8447 rc = adc_synchronization(demod);
8448 if (rc != 0) {
8449 pr_err("error %d\n", rc);
8450 goto rw_error;
8451 }
8452
8453 rc = init_agc(demod);
8454 if (rc != 0) {
8455 pr_err("error %d\n", rc);
8456 goto rw_error;
8457 }
8458 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8459 if (rc != 0) {
8460 pr_err("error %d\n", rc);
8461 goto rw_error;
8462 }
8463 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8464 if (rc != 0) {
8465 pr_err("error %d\n", rc);
8466 goto rw_error;
8467 }
8468 {
8469 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
8470 of only the gain */
8471 struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8472
8473 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8474 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8475 if (rc != 0) {
8476 pr_err("error %d\n", rc);
8477 goto rw_error;
8478 }
8479 }
8480 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8481 if (rc != 0) {
8482 pr_err("error %d\n", rc);
8483 goto rw_error;
8484 }
8485 }
8486
8487 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8488 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8489 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8490 if (rc != 0) {
8491 pr_err("error %d\n", rc);
8492 goto rw_error;
8493 }
8494 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8495 if (rc != 0) {
8496 pr_err("error %d\n", rc);
8497 goto rw_error;
8498 }
8499 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8500 switch (channel->constellation) {
8501 case DRX_CONSTELLATION_QAM64:
8502 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8503 if (rc != 0) {
8504 pr_err("error %d\n", rc);
8505 goto rw_error;
8506 }
8507 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8508 if (rc != 0) {
8509 pr_err("error %d\n", rc);
8510 goto rw_error;
8511 }
8512 break;
8513 case DRX_CONSTELLATION_QAM256:
8514 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8515 if (rc != 0) {
8516 pr_err("error %d\n", rc);
8517 goto rw_error;
8518 }
8519 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8520 if (rc != 0) {
8521 pr_err("error %d\n", rc);
8522 goto rw_error;
8523 }
8524 break;
8525 default:
8526 return -EIO;
8527 }
8528 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8529 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8530 if (rc != 0) {
8531 pr_err("error %d\n", rc);
8532 goto rw_error;
8533 }
8534 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8535 if (rc != 0) {
8536 pr_err("error %d\n", rc);
8537 goto rw_error;
8538 }
8539 }
8540
8541 /* SETP 4: constellation specific setup */
8542 switch (channel->constellation) {
8543 case DRX_CONSTELLATION_QAM16:
8544 rc = set_qam16(demod);
8545 if (rc != 0) {
8546 pr_err("error %d\n", rc);
8547 goto rw_error;
8548 }
8549 break;
8550 case DRX_CONSTELLATION_QAM32:
8551 rc = set_qam32(demod);
8552 if (rc != 0) {
8553 pr_err("error %d\n", rc);
8554 goto rw_error;
8555 }
8556 break;
8557 case DRX_CONSTELLATION_QAM64:
8558 rc = set_qam64(demod);
8559 if (rc != 0) {
8560 pr_err("error %d\n", rc);
8561 goto rw_error;
8562 }
8563 break;
8564 case DRX_CONSTELLATION_QAM128:
8565 rc = set_qam128(demod);
8566 if (rc != 0) {
8567 pr_err("error %d\n", rc);
8568 goto rw_error;
8569 }
8570 break;
8571 case DRX_CONSTELLATION_QAM256:
8572 rc = set_qam256(demod);
8573 if (rc != 0) {
8574 pr_err("error %d\n", rc);
8575 goto rw_error;
8576 }
8577 break;
8578 default:
8579 return -EIO;
8580 } /* switch */
8581 }
8582
8583 if ((op & QAM_SET_OP_ALL)) {
8584 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8585 if (rc != 0) {
8586 pr_err("error %d\n", rc);
8587 goto rw_error;
8588 }
8589
8590 /* Mpeg output has to be in front of FEC active */
8591 rc = set_mpegtei_handling(demod);
8592 if (rc != 0) {
8593 pr_err("error %d\n", rc);
8594 goto rw_error;
8595 }
8596 rc = bit_reverse_mpeg_output(demod);
8597 if (rc != 0) {
8598 pr_err("error %d\n", rc);
8599 goto rw_error;
8600 }
8601 rc = set_mpeg_start_width(demod);
8602 if (rc != 0) {
8603 pr_err("error %d\n", rc);
8604 goto rw_error;
8605 }
8606 {
8607 /* TODO: move to set_standard after hardware reset value problem is solved */
8608 /* Configure initial MPEG output */
8609 struct drx_cfg_mpeg_output cfg_mpeg_output;
8610
8611 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8612 cfg_mpeg_output.enable_mpeg_output = true;
8613
8614 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8615 if (rc != 0) {
8616 pr_err("error %d\n", rc);
8617 goto rw_error;
8618 }
8619 }
8620 }
8621
8622 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8623
8624 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
8625 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8626 SCU_RAM_COMMAND_CMD_DEMOD_START;
8627 cmd_scu.parameter_len = 0;
8628 cmd_scu.result_len = 1;
8629 cmd_scu.parameter = NULL;
8630 cmd_scu.result = &cmd_result;
8631 rc = scu_command(dev_addr, &cmd_scu);
8632 if (rc != 0) {
8633 pr_err("error %d\n", rc);
8634 goto rw_error;
8635 }
8636 }
8637
8638 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8639 if (rc != 0) {
8640 pr_err("error %d\n", rc);
8641 goto rw_error;
8642 }
8643 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8644 if (rc != 0) {
8645 pr_err("error %d\n", rc);
8646 goto rw_error;
8647 }
8648 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8649 if (rc != 0) {
8650 pr_err("error %d\n", rc);
8651 goto rw_error;
8652 }
8653
8654 return 0;
8655 rw_error:
8656 return rc;
8657 }
8658
8659 /*============================================================================*/
8660 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8661
8662 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8663 {
8664 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8665 struct drxj_data *ext_attr = demod->my_ext_attr;
8666 int rc;
8667 u32 iqm_fs_rate_ofs = 0;
8668 u32 iqm_fs_rate_lo = 0;
8669 u16 qam_ctl_ena = 0;
8670 u16 data = 0;
8671 u16 equ_mode = 0;
8672 u16 fsm_state = 0;
8673 int i = 0;
8674 int ofsofs = 0;
8675
8676 /* Silence the controlling of lc, equ, and the acquisition state machine */
8677 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8678 if (rc != 0) {
8679 pr_err("error %d\n", rc);
8680 goto rw_error;
8681 }
8682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8683 if (rc != 0) {
8684 pr_err("error %d\n", rc);
8685 goto rw_error;
8686 }
8687
8688 /* freeze the frequency control loop */
8689 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8690 if (rc != 0) {
8691 pr_err("error %d\n", rc);
8692 goto rw_error;
8693 }
8694 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8695 if (rc != 0) {
8696 pr_err("error %d\n", rc);
8697 goto rw_error;
8698 }
8699
8700 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8701 if (rc != 0) {
8702 pr_err("error %d\n", rc);
8703 goto rw_error;
8704 }
8705 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8706 if (rc != 0) {
8707 pr_err("error %d\n", rc);
8708 goto rw_error;
8709 }
8710 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8711 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8712 iqm_fs_rate_ofs -= 2 * ofsofs;
8713
8714 /* freeze dq/fq updating */
8715 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8716 if (rc != 0) {
8717 pr_err("error %d\n", rc);
8718 goto rw_error;
8719 }
8720 data = (data & 0xfff9);
8721 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8722 if (rc != 0) {
8723 pr_err("error %d\n", rc);
8724 goto rw_error;
8725 }
8726 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8727 if (rc != 0) {
8728 pr_err("error %d\n", rc);
8729 goto rw_error;
8730 }
8731
8732 /* lc_cp / _ci / _ca */
8733 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8734 if (rc != 0) {
8735 pr_err("error %d\n", rc);
8736 goto rw_error;
8737 }
8738 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8739 if (rc != 0) {
8740 pr_err("error %d\n", rc);
8741 goto rw_error;
8742 }
8743 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8744 if (rc != 0) {
8745 pr_err("error %d\n", rc);
8746 goto rw_error;
8747 }
8748
8749 /* flip the spec */
8750 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8751 if (rc != 0) {
8752 pr_err("error %d\n", rc);
8753 goto rw_error;
8754 }
8755 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8756 ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8757
8758 /* freeze dq/fq updating */
8759 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8760 if (rc != 0) {
8761 pr_err("error %d\n", rc);
8762 goto rw_error;
8763 }
8764 equ_mode = data;
8765 data = (data & 0xfff9);
8766 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8767 if (rc != 0) {
8768 pr_err("error %d\n", rc);
8769 goto rw_error;
8770 }
8771 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8772 if (rc != 0) {
8773 pr_err("error %d\n", rc);
8774 goto rw_error;
8775 }
8776
8777 for (i = 0; i < 28; i++) {
8778 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8779 if (rc != 0) {
8780 pr_err("error %d\n", rc);
8781 goto rw_error;
8782 }
8783 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8784 if (rc != 0) {
8785 pr_err("error %d\n", rc);
8786 goto rw_error;
8787 }
8788 }
8789
8790 for (i = 0; i < 24; i++) {
8791 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8792 if (rc != 0) {
8793 pr_err("error %d\n", rc);
8794 goto rw_error;
8795 }
8796 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8797 if (rc != 0) {
8798 pr_err("error %d\n", rc);
8799 goto rw_error;
8800 }
8801 }
8802
8803 data = equ_mode;
8804 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8805 if (rc != 0) {
8806 pr_err("error %d\n", rc);
8807 goto rw_error;
8808 }
8809 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8810 if (rc != 0) {
8811 pr_err("error %d\n", rc);
8812 goto rw_error;
8813 }
8814
8815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8816 if (rc != 0) {
8817 pr_err("error %d\n", rc);
8818 goto rw_error;
8819 }
8820
8821 i = 0;
8822 while ((fsm_state != 4) && (i++ < 100)) {
8823 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8824 if (rc != 0) {
8825 pr_err("error %d\n", rc);
8826 goto rw_error;
8827 }
8828 }
8829 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8830 if (rc != 0) {
8831 pr_err("error %d\n", rc);
8832 goto rw_error;
8833 }
8834
8835 return 0;
8836 rw_error:
8837 return rc;
8838
8839 }
8840
8841 #define NO_LOCK 0x0
8842 #define DEMOD_LOCKED 0x1
8843 #define SYNC_FLIPPED 0x2
8844 #define SPEC_MIRRORED 0x4
8845 /**
8846 * \fn int qam64auto ()
8847 * \brief auto do sync pattern switching and mirroring.
8848 * \param demod: instance of demod.
8849 * \param channel: pointer to channel data.
8850 * \param tuner_freq_offset: tuner frequency offset.
8851 * \param lock_status: pointer to lock status.
8852 * \return int.
8853 */
8854 static int
8855 qam64auto(struct drx_demod_instance *demod,
8856 struct drx_channel *channel,
8857 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8858 {
8859 struct drxj_data *ext_attr = demod->my_ext_attr;
8860 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8861 struct drx39xxj_state *state = dev_addr->user_data;
8862 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8863 int rc;
8864 u32 lck_state = NO_LOCK;
8865 u32 start_time = 0;
8866 u32 d_locked_time = 0;
8867 u32 timeout_ofs = 0;
8868 u16 data = 0;
8869
8870 /* external attributes for storing acquired channel constellation */
8871 *lock_status = DRX_NOT_LOCKED;
8872 start_time = jiffies_to_msecs(jiffies);
8873 lck_state = NO_LOCK;
8874 do {
8875 rc = ctrl_lock_status(demod, lock_status);
8876 if (rc != 0) {
8877 pr_err("error %d\n", rc);
8878 goto rw_error;
8879 }
8880
8881 switch (lck_state) {
8882 case NO_LOCK:
8883 if (*lock_status == DRXJ_DEMOD_LOCK) {
8884 rc = ctrl_get_qam_sig_quality(demod);
8885 if (rc != 0) {
8886 pr_err("error %d\n", rc);
8887 goto rw_error;
8888 }
8889 if (p->cnr.stat[0].svalue > 20800) {
8890 lck_state = DEMOD_LOCKED;
8891 /* some delay to see if fec_lock possible TODO find the right value */
8892 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */
8893 d_locked_time = jiffies_to_msecs(jiffies);
8894 }
8895 }
8896 break;
8897 case DEMOD_LOCKED:
8898 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8899 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8900 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8901 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8902 if (rc != 0) {
8903 pr_err("error %d\n", rc);
8904 goto rw_error;
8905 }
8906 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8907 if (rc != 0) {
8908 pr_err("error %d\n", rc);
8909 goto rw_error;
8910 }
8911 lck_state = SYNC_FLIPPED;
8912 msleep(10);
8913 }
8914 break;
8915 case SYNC_FLIPPED:
8916 if (*lock_status == DRXJ_DEMOD_LOCK) {
8917 if (channel->mirror == DRX_MIRROR_AUTO) {
8918 /* flip sync pattern back */
8919 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8920 if (rc != 0) {
8921 pr_err("error %d\n", rc);
8922 goto rw_error;
8923 }
8924 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8925 if (rc != 0) {
8926 pr_err("error %d\n", rc);
8927 goto rw_error;
8928 }
8929 /* flip spectrum */
8930 ext_attr->mirror = DRX_MIRROR_YES;
8931 rc = qam_flip_spec(demod, channel);
8932 if (rc != 0) {
8933 pr_err("error %d\n", rc);
8934 goto rw_error;
8935 }
8936 lck_state = SPEC_MIRRORED;
8937 /* reset timer TODO: still need 500ms? */
8938 start_time = d_locked_time =
8939 jiffies_to_msecs(jiffies);
8940 timeout_ofs = 0;
8941 } else { /* no need to wait lock */
8942
8943 start_time =
8944 jiffies_to_msecs(jiffies) -
8945 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8946 }
8947 }
8948 break;
8949 case SPEC_MIRRORED:
8950 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8951 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8952 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8953 rc = ctrl_get_qam_sig_quality(demod);
8954 if (rc != 0) {
8955 pr_err("error %d\n", rc);
8956 goto rw_error;
8957 }
8958 if (p->cnr.stat[0].svalue > 20800) {
8959 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8960 if (rc != 0) {
8961 pr_err("error %d\n", rc);
8962 goto rw_error;
8963 }
8964 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8965 if (rc != 0) {
8966 pr_err("error %d\n", rc);
8967 goto rw_error;
8968 }
8969 /* no need to wait lock */
8970 start_time =
8971 jiffies_to_msecs(jiffies) -
8972 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8973 }
8974 }
8975 break;
8976 default:
8977 break;
8978 }
8979 msleep(10);
8980 } while
8981 ((*lock_status != DRX_LOCKED) &&
8982 (*lock_status != DRX_NEVER_LOCK) &&
8983 ((jiffies_to_msecs(jiffies) - start_time) <
8984 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8985 );
8986 /* Returning control to apllication ... */
8987
8988 return 0;
8989 rw_error:
8990 return rc;
8991 }
8992
8993 /**
8994 * \fn int qam256auto ()
8995 * \brief auto do sync pattern switching and mirroring.
8996 * \param demod: instance of demod.
8997 * \param channel: pointer to channel data.
8998 * \param tuner_freq_offset: tuner frequency offset.
8999 * \param lock_status: pointer to lock status.
9000 * \return int.
9001 */
9002 static int
9003 qam256auto(struct drx_demod_instance *demod,
9004 struct drx_channel *channel,
9005 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9006 {
9007 struct drxj_data *ext_attr = demod->my_ext_attr;
9008 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9009 struct drx39xxj_state *state = dev_addr->user_data;
9010 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9011 int rc;
9012 u32 lck_state = NO_LOCK;
9013 u32 start_time = 0;
9014 u32 d_locked_time = 0;
9015 u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9016
9017 /* external attributes for storing acquired channel constellation */
9018 *lock_status = DRX_NOT_LOCKED;
9019 start_time = jiffies_to_msecs(jiffies);
9020 lck_state = NO_LOCK;
9021 do {
9022 rc = ctrl_lock_status(demod, lock_status);
9023 if (rc != 0) {
9024 pr_err("error %d\n", rc);
9025 goto rw_error;
9026 }
9027 switch (lck_state) {
9028 case NO_LOCK:
9029 if (*lock_status == DRXJ_DEMOD_LOCK) {
9030 rc = ctrl_get_qam_sig_quality(demod);
9031 if (rc != 0) {
9032 pr_err("error %d\n", rc);
9033 goto rw_error;
9034 }
9035 if (p->cnr.stat[0].svalue > 26800) {
9036 lck_state = DEMOD_LOCKED;
9037 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */
9038 d_locked_time = jiffies_to_msecs(jiffies);
9039 }
9040 }
9041 break;
9042 case DEMOD_LOCKED:
9043 if (*lock_status == DRXJ_DEMOD_LOCK) {
9044 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9045 ((jiffies_to_msecs(jiffies) - d_locked_time) >
9046 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9047 ext_attr->mirror = DRX_MIRROR_YES;
9048 rc = qam_flip_spec(demod, channel);
9049 if (rc != 0) {
9050 pr_err("error %d\n", rc);
9051 goto rw_error;
9052 }
9053 lck_state = SPEC_MIRRORED;
9054 /* reset timer TODO: still need 300ms? */
9055 start_time = jiffies_to_msecs(jiffies);
9056 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9057 }
9058 }
9059 break;
9060 case SPEC_MIRRORED:
9061 break;
9062 default:
9063 break;
9064 }
9065 msleep(10);
9066 } while
9067 ((*lock_status < DRX_LOCKED) &&
9068 (*lock_status != DRX_NEVER_LOCK) &&
9069 ((jiffies_to_msecs(jiffies) - start_time) <
9070 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9071
9072 return 0;
9073 rw_error:
9074 return rc;
9075 }
9076
9077 /**
9078 * \fn int set_qam_channel ()
9079 * \brief Set QAM channel according to the requested constellation.
9080 * \param demod: instance of demod.
9081 * \param channel: pointer to channel data.
9082 * \return int.
9083 */
9084 static int
9085 set_qam_channel(struct drx_demod_instance *demod,
9086 struct drx_channel *channel, s32 tuner_freq_offset)
9087 {
9088 struct drxj_data *ext_attr = NULL;
9089 int rc;
9090 enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9091 bool auto_flag = false;
9092
9093 /* external attributes for storing acquired channel constellation */
9094 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9095
9096 /* set QAM channel constellation */
9097 switch (channel->constellation) {
9098 case DRX_CONSTELLATION_QAM16:
9099 case DRX_CONSTELLATION_QAM32:
9100 case DRX_CONSTELLATION_QAM128:
9101 return -EINVAL;
9102 case DRX_CONSTELLATION_QAM64:
9103 case DRX_CONSTELLATION_QAM256:
9104 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9105 return -EINVAL;
9106
9107 ext_attr->constellation = channel->constellation;
9108 if (channel->mirror == DRX_MIRROR_AUTO)
9109 ext_attr->mirror = DRX_MIRROR_NO;
9110 else
9111 ext_attr->mirror = channel->mirror;
9112
9113 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9114 if (rc != 0) {
9115 pr_err("error %d\n", rc);
9116 goto rw_error;
9117 }
9118
9119 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9120 rc = qam64auto(demod, channel, tuner_freq_offset,
9121 &lock_status);
9122 else
9123 rc = qam256auto(demod, channel, tuner_freq_offset,
9124 &lock_status);
9125 if (rc != 0) {
9126 pr_err("error %d\n", rc);
9127 goto rw_error;
9128 }
9129 break;
9130 case DRX_CONSTELLATION_AUTO: /* for channel scan */
9131 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9132 u16 qam_ctl_ena = 0;
9133
9134 auto_flag = true;
9135
9136 /* try to lock default QAM constellation: QAM256 */
9137 channel->constellation = DRX_CONSTELLATION_QAM256;
9138 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9139 if (channel->mirror == DRX_MIRROR_AUTO)
9140 ext_attr->mirror = DRX_MIRROR_NO;
9141 else
9142 ext_attr->mirror = channel->mirror;
9143 rc = set_qam(demod, channel, tuner_freq_offset,
9144 QAM_SET_OP_ALL);
9145 if (rc != 0) {
9146 pr_err("error %d\n", rc);
9147 goto rw_error;
9148 }
9149 rc = qam256auto(demod, channel, tuner_freq_offset,
9150 &lock_status);
9151 if (rc != 0) {
9152 pr_err("error %d\n", rc);
9153 goto rw_error;
9154 }
9155
9156 if (lock_status >= DRX_LOCKED) {
9157 channel->constellation = DRX_CONSTELLATION_AUTO;
9158 break;
9159 }
9160
9161 /* QAM254 not locked. Try QAM64 constellation */
9162 channel->constellation = DRX_CONSTELLATION_QAM64;
9163 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9164 if (channel->mirror == DRX_MIRROR_AUTO)
9165 ext_attr->mirror = DRX_MIRROR_NO;
9166 else
9167 ext_attr->mirror = channel->mirror;
9168
9169 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9170 SCU_RAM_QAM_CTL_ENA__A,
9171 &qam_ctl_ena, 0);
9172 if (rc != 0) {
9173 pr_err("error %d\n", rc);
9174 goto rw_error;
9175 }
9176 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9177 SCU_RAM_QAM_CTL_ENA__A,
9178 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9179 if (rc != 0) {
9180 pr_err("error %d\n", rc);
9181 goto rw_error;
9182 }
9183 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9184 SCU_RAM_QAM_FSM_STATE_TGT__A,
9185 0x2, 0);
9186 if (rc != 0) {
9187 pr_err("error %d\n", rc);
9188 goto rw_error;
9189 } /* force to rate hunting */
9190
9191 rc = set_qam(demod, channel, tuner_freq_offset,
9192 QAM_SET_OP_CONSTELLATION);
9193 if (rc != 0) {
9194 pr_err("error %d\n", rc);
9195 goto rw_error;
9196 }
9197 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9198 SCU_RAM_QAM_CTL_ENA__A,
9199 qam_ctl_ena, 0);
9200 if (rc != 0) {
9201 pr_err("error %d\n", rc);
9202 goto rw_error;
9203 }
9204
9205 rc = qam64auto(demod, channel, tuner_freq_offset,
9206 &lock_status);
9207 if (rc != 0) {
9208 pr_err("error %d\n", rc);
9209 goto rw_error;
9210 }
9211
9212 channel->constellation = DRX_CONSTELLATION_AUTO;
9213 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9214 u16 qam_ctl_ena = 0;
9215
9216 channel->constellation = DRX_CONSTELLATION_QAM64;
9217 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9218 auto_flag = true;
9219
9220 if (channel->mirror == DRX_MIRROR_AUTO)
9221 ext_attr->mirror = DRX_MIRROR_NO;
9222 else
9223 ext_attr->mirror = channel->mirror;
9224 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9225 SCU_RAM_QAM_CTL_ENA__A,
9226 &qam_ctl_ena, 0);
9227 if (rc != 0) {
9228 pr_err("error %d\n", rc);
9229 goto rw_error;
9230 }
9231 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9232 SCU_RAM_QAM_CTL_ENA__A,
9233 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9234 if (rc != 0) {
9235 pr_err("error %d\n", rc);
9236 goto rw_error;
9237 }
9238 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9239 SCU_RAM_QAM_FSM_STATE_TGT__A,
9240 0x2, 0);
9241 if (rc != 0) {
9242 pr_err("error %d\n", rc);
9243 goto rw_error;
9244 } /* force to rate hunting */
9245
9246 rc = set_qam(demod, channel, tuner_freq_offset,
9247 QAM_SET_OP_CONSTELLATION);
9248 if (rc != 0) {
9249 pr_err("error %d\n", rc);
9250 goto rw_error;
9251 }
9252 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9253 SCU_RAM_QAM_CTL_ENA__A,
9254 qam_ctl_ena, 0);
9255 if (rc != 0) {
9256 pr_err("error %d\n", rc);
9257 goto rw_error;
9258 }
9259 rc = qam64auto(demod, channel, tuner_freq_offset,
9260 &lock_status);
9261 if (rc != 0) {
9262 pr_err("error %d\n", rc);
9263 goto rw_error;
9264 }
9265 channel->constellation = DRX_CONSTELLATION_AUTO;
9266 } else {
9267 return -EINVAL;
9268 }
9269 break;
9270 default:
9271 return -EINVAL;
9272 }
9273
9274 return 0;
9275 rw_error:
9276 /* restore starting value */
9277 if (auto_flag)
9278 channel->constellation = DRX_CONSTELLATION_AUTO;
9279 return rc;
9280 }
9281
9282 /*============================================================================*/
9283
9284 /**
9285 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
9286 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
9287 * \return Error code
9288 *
9289 * precondition: measurement period & measurement prescale must be set
9290 *
9291 */
9292 static int
9293 get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9294 struct drxjrs_errors *rs_errors)
9295 {
9296 int rc;
9297 u16 nr_bit_errors = 0,
9298 nr_symbol_errors = 0,
9299 nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9300
9301 /* check arguments */
9302 if (dev_addr == NULL)
9303 return -EINVAL;
9304
9305 /* all reported errors are received in the */
9306 /* most recently finished measurment period */
9307 /* no of pre RS bit errors */
9308 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9309 if (rc != 0) {
9310 pr_err("error %d\n", rc);
9311 goto rw_error;
9312 }
9313 /* no of symbol errors */
9314 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9315 if (rc != 0) {
9316 pr_err("error %d\n", rc);
9317 goto rw_error;
9318 }
9319 /* no of packet errors */
9320 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9321 if (rc != 0) {
9322 pr_err("error %d\n", rc);
9323 goto rw_error;
9324 }
9325 /* no of failures to decode */
9326 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9327 if (rc != 0) {
9328 pr_err("error %d\n", rc);
9329 goto rw_error;
9330 }
9331 /* no of post RS bit erros */
9332 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9333 if (rc != 0) {
9334 pr_err("error %d\n", rc);
9335 goto rw_error;
9336 }
9337 /* TODO: NOTE */
9338 /* These register values are fetched in non-atomic fashion */
9339 /* It is possible that the read values contain unrelated information */
9340
9341 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9342 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9343 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9344 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9345 rs_errors->nr_snc_par_fail_count =
9346 nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9347
9348 return 0;
9349 rw_error:
9350 return rc;
9351 }
9352
9353 /*============================================================================*/
9354
9355 /**
9356 * \fn int get_sig_strength()
9357 * \brief Retrieve signal strength for VSB and QAM.
9358 * \param demod Pointer to demod instance
9359 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9360 * \return int.
9361 * \retval 0 sig_strength contains valid data.
9362 * \retval -EINVAL sig_strength is NULL.
9363 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9364 */
9365 #define DRXJ_AGC_TOP 0x2800
9366 #define DRXJ_AGC_SNS 0x1600
9367 #define DRXJ_RFAGC_MAX 0x3fff
9368 #define DRXJ_RFAGC_MIN 0x800
9369
9370 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9371 {
9372 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9373 int rc;
9374 u16 rf_gain = 0;
9375 u16 if_gain = 0;
9376 u16 if_agc_sns = 0;
9377 u16 if_agc_top = 0;
9378 u16 rf_agc_max = 0;
9379 u16 rf_agc_min = 0;
9380
9381 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9382 if (rc != 0) {
9383 pr_err("error %d\n", rc);
9384 goto rw_error;
9385 }
9386 if_gain &= IQM_AF_AGC_IF__M;
9387 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9388 if (rc != 0) {
9389 pr_err("error %d\n", rc);
9390 goto rw_error;
9391 }
9392 rf_gain &= IQM_AF_AGC_RF__M;
9393
9394 if_agc_sns = DRXJ_AGC_SNS;
9395 if_agc_top = DRXJ_AGC_TOP;
9396 rf_agc_max = DRXJ_RFAGC_MAX;
9397 rf_agc_min = DRXJ_RFAGC_MIN;
9398
9399 if (if_gain > if_agc_top) {
9400 if (rf_gain > rf_agc_max)
9401 *sig_strength = 100;
9402 else if (rf_gain > rf_agc_min) {
9403 if (rf_agc_max == rf_agc_min) {
9404 pr_err("error: rf_agc_max == rf_agc_min\n");
9405 return -EIO;
9406 }
9407 *sig_strength =
9408 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9409 rf_agc_min);
9410 } else
9411 *sig_strength = 75;
9412 } else if (if_gain > if_agc_sns) {
9413 if (if_agc_top == if_agc_sns) {
9414 pr_err("error: if_agc_top == if_agc_sns\n");
9415 return -EIO;
9416 }
9417 *sig_strength =
9418 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9419 } else {
9420 if (!if_agc_sns) {
9421 pr_err("error: if_agc_sns is zero!\n");
9422 return -EIO;
9423 }
9424 *sig_strength = (20 * if_gain / if_agc_sns);
9425 }
9426
9427 if (*sig_strength <= 7)
9428 *sig_strength = 0;
9429
9430 return 0;
9431 rw_error:
9432 return rc;
9433 }
9434
9435 /**
9436 * \fn int ctrl_get_qam_sig_quality()
9437 * \brief Retrieve QAM signal quality from device.
9438 * \param devmod Pointer to demodulator instance.
9439 * \param sig_quality Pointer to signal quality data.
9440 * \return int.
9441 * \retval 0 sig_quality contains valid data.
9442 * \retval -EINVAL sig_quality is NULL.
9443 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9444
9445 * Pre-condition: Device must be started and in lock.
9446 */
9447 static int
9448 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9449 {
9450 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9451 struct drxj_data *ext_attr = demod->my_ext_attr;
9452 struct drx39xxj_state *state = dev_addr->user_data;
9453 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9454 struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9455 enum drx_modulation constellation = ext_attr->constellation;
9456 int rc;
9457
9458 u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
9459 u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */
9460 u32 pkt_errs = 0; /* no of packet errors in RS */
9461 u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */
9462 u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */
9463 u16 fec_oc_period = 0; /* SNC sync failure measurement period */
9464 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
9465 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
9466 /* calculation constants */
9467 u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */
9468 u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */
9469 /* intermediate results */
9470 u32 e = 0; /* exponent value used for QAM BER/SER */
9471 u32 m = 0; /* mantisa value used for QAM BER/SER */
9472 u32 ber_cnt = 0; /* BER count */
9473 /* signal quality info */
9474 u32 qam_sl_mer = 0; /* QAM MER */
9475 u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
9476 u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */
9477 u32 qam_vd_ser = 0; /* ViterbiDecoder SER */
9478 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
9479 u16 qam_vd_period = 0; /* Viterbi Measurement period */
9480 u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */
9481
9482 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9483
9484 /* read the physical registers */
9485 /* Get the RS error data */
9486 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9487 if (rc != 0) {
9488 pr_err("error %d\n", rc);
9489 goto rw_error;
9490 }
9491 /* get the register value needed for MER */
9492 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9493 if (rc != 0) {
9494 pr_err("error %d\n", rc);
9495 goto rw_error;
9496 }
9497 /* get the register value needed for post RS BER */
9498 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9499 if (rc != 0) {
9500 pr_err("error %d\n", rc);
9501 goto rw_error;
9502 }
9503
9504 /* get constants needed for signal quality calculation */
9505 fec_rs_period = ext_attr->fec_rs_period;
9506 fec_rs_prescale = ext_attr->fec_rs_prescale;
9507 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9508 qam_vd_period = ext_attr->qam_vd_period;
9509 qam_vd_prescale = ext_attr->qam_vd_prescale;
9510 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9511
9512 /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
9513 switch (constellation) {
9514 case DRX_CONSTELLATION_QAM16:
9515 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9516 break;
9517 case DRX_CONSTELLATION_QAM32:
9518 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9519 break;
9520 case DRX_CONSTELLATION_QAM64:
9521 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9522 break;
9523 case DRX_CONSTELLATION_QAM128:
9524 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9525 break;
9526 case DRX_CONSTELLATION_QAM256:
9527 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9528 break;
9529 default:
9530 return -EIO;
9531 }
9532
9533 /* ------------------------------ */
9534 /* MER Calculation */
9535 /* ------------------------------ */
9536 /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
9537
9538 /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
9539 if (qam_sl_err_power == 0)
9540 qam_sl_mer = 0;
9541 else
9542 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9543
9544 /* ----------------------------------------- */
9545 /* Pre Viterbi Symbol Error Rate Calculation */
9546 /* ----------------------------------------- */
9547 /* pre viterbi SER is good if it is below 0.025 */
9548
9549 /* get the register value */
9550 /* no of quadrature symbol errors */
9551 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9552 if (rc != 0) {
9553 pr_err("error %d\n", rc);
9554 goto rw_error;
9555 }
9556 /* Extract the Exponent and the Mantisa */
9557 /* of number of quadrature symbol errors */
9558 e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9559 QAM_VD_NR_QSYM_ERRORS_EXP__B;
9560 m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9561 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9562
9563 if ((m << e) >> 3 > 549752)
9564 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9565 else
9566 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9567
9568 /* --------------------------------------- */
9569 /* pre and post RedSolomon BER Calculation */
9570 /* --------------------------------------- */
9571 /* pre RS BER is good if it is below 3.5e-4 */
9572
9573 /* get the register values */
9574 pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9575 pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9576
9577 /* Extract the Exponent and the Mantisa of the */
9578 /* pre Reed-Solomon bit error count */
9579 e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9580 FEC_RS_NR_BIT_ERRORS_EXP__B;
9581 m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9582 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9583
9584 ber_cnt = m << e;
9585
9586 /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
9587 if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9588 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9589 else
9590 qam_pre_rs_ber = ber_cnt;
9591
9592 /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
9593 /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
9594 /*
9595 => c = (1000000*100*11.17)/1504 =
9596 post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
9597 (100 * FEC_OC_SNC_FAIL_PERIOD__A)
9598 *100 and /100 is for more precision.
9599 => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
9600
9601 Precision errors still possible.
9602 */
9603 if (!fec_oc_period) {
9604 qam_post_rs_ber = 0xFFFFFFFF;
9605 } else {
9606 e = post_bit_err_rs * 742686;
9607 m = fec_oc_period * 100;
9608 qam_post_rs_ber = e / m;
9609 }
9610
9611 /* fill signal quality data structure */
9612 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9613 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9614 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9615 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9616 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9617 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9618
9619 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9620 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9621 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9622 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9623 } else {
9624 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9625 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9626 }
9627
9628 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9629 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9630
9631 p->block_error.stat[0].uvalue += pkt_errs;
9632
9633 #ifdef DRXJ_SIGNAL_ACCUM_ERR
9634 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9635 if (rc != 0) {
9636 pr_err("error %d\n", rc);
9637 goto rw_error;
9638 }
9639 #endif
9640
9641 return 0;
9642 rw_error:
9643 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9644 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9645 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9646 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9647 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9648 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9649
9650 return rc;
9651 }
9652
9653 #endif /* #ifndef DRXJ_VSB_ONLY */
9654
9655 /*============================================================================*/
9656 /*== END QAM DATAPATH FUNCTIONS ==*/
9657 /*============================================================================*/
9658
9659 /*============================================================================*/
9660 /*============================================================================*/
9661 /*== ATV DATAPATH FUNCTIONS ==*/
9662 /*============================================================================*/
9663 /*============================================================================*/
9664
9665 /*
9666 Implementation notes.
9667
9668 NTSC/FM AGCs
9669
9670 Four AGCs are used for NTSC:
9671 (1) RF (used to attenuate the input signal in case of to much power)
9672 (2) IF (used to attenuate the input signal in case of to much power)
9673 (3) Video AGC (used to amplify the output signal in case input to low)
9674 (4) SIF AGC (used to amplify the output signal in case input to low)
9675
9676 Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
9677 that the coupling between Video AGC and the RF and IF AGCs also works in
9678 favor of the SIF AGC.
9679
9680 Three AGCs are used for FM:
9681 (1) RF (used to attenuate the input signal in case of to much power)
9682 (2) IF (used to attenuate the input signal in case of to much power)
9683 (3) SIF AGC (used to amplify the output signal in case input to low)
9684
9685 The SIF AGC is now coupled to the RF/IF AGCs.
9686 The SIF AGC is needed for both SIF ouput and the internal SIF signal to
9687 the AUD block.
9688
9689 RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
9690 the ATV block. The AGC control algorithms are all implemented in
9691 microcode.
9692
9693 ATV SETTINGS
9694
9695 (Shadow settings will not be used for now, they will be implemented
9696 later on because of the schedule)
9697
9698 Several HW/SCU "settings" can be used for ATV. The standard selection
9699 will reset most of these settings. To avoid that the end user apllication
9700 has to perform these settings each time the ATV or FM standards is
9701 selected the driver will shadow these settings. This enables the end user
9702 to perform the settings only once after a drx_open(). The driver must
9703 write the shadow settings to HW/SCU incase:
9704 ( setstandard FM/ATV) ||
9705 ( settings have changed && FM/ATV standard is active)
9706 The shadow settings will be stored in the device specific data container.
9707 A set of flags will be defined to flag changes in shadow settings.
9708 A routine will be implemented to write all changed shadow settings to
9709 HW/SCU.
9710
9711 The "settings" will consist of: AGC settings, filter settings etc.
9712
9713 Disadvantage of use of shadow settings:
9714 Direct changes in HW/SCU registers will not be reflected in the
9715 shadow settings and these changes will be overwritten during a next
9716 update. This can happen during evaluation. This will not be a problem
9717 for normal customer usage.
9718 */
9719 /* -------------------------------------------------------------------------- */
9720
9721 /**
9722 * \fn int power_down_atv ()
9723 * \brief Power down ATV.
9724 * \param demod instance of demodulator
9725 * \param standard either NTSC or FM (sub strandard for ATV )
9726 * \return int.
9727 *
9728 * Stops and thus resets ATV and IQM block
9729 * SIF and CVBS ADC are powered down
9730 * Calls audio power down
9731 */
9732 static int
9733 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9734 {
9735 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9736 struct drxjscu_cmd cmd_scu = { /* command */ 0,
9737 /* parameter_len */ 0,
9738 /* result_len */ 0,
9739 /* *parameter */ NULL,
9740 /* *result */ NULL
9741 };
9742 int rc;
9743 u16 cmd_result = 0;
9744
9745 /* ATV NTSC */
9746
9747 /* Stop ATV SCU (will reset ATV and IQM hardware */
9748 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9749 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9750 cmd_scu.parameter_len = 0;
9751 cmd_scu.result_len = 1;
9752 cmd_scu.parameter = NULL;
9753 cmd_scu.result = &cmd_result;
9754 rc = scu_command(dev_addr, &cmd_scu);
9755 if (rc != 0) {
9756 pr_err("error %d\n", rc);
9757 goto rw_error;
9758 }
9759 /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
9760 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9761 if (rc != 0) {
9762 pr_err("error %d\n", rc);
9763 goto rw_error;
9764 }
9765
9766 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9767 if (rc != 0) {
9768 pr_err("error %d\n", rc);
9769 goto rw_error;
9770 }
9771 if (primary) {
9772 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9773 if (rc != 0) {
9774 pr_err("error %d\n", rc);
9775 goto rw_error;
9776 }
9777 rc = set_iqm_af(demod, false);
9778 if (rc != 0) {
9779 pr_err("error %d\n", rc);
9780 goto rw_error;
9781 }
9782 } else {
9783 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9784 if (rc != 0) {
9785 pr_err("error %d\n", rc);
9786 goto rw_error;
9787 }
9788 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9789 if (rc != 0) {
9790 pr_err("error %d\n", rc);
9791 goto rw_error;
9792 }
9793 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9794 if (rc != 0) {
9795 pr_err("error %d\n", rc);
9796 goto rw_error;
9797 }
9798 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9799 if (rc != 0) {
9800 pr_err("error %d\n", rc);
9801 goto rw_error;
9802 }
9803 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9804 if (rc != 0) {
9805 pr_err("error %d\n", rc);
9806 goto rw_error;
9807 }
9808 }
9809 rc = power_down_aud(demod);
9810 if (rc != 0) {
9811 pr_err("error %d\n", rc);
9812 goto rw_error;
9813 }
9814
9815 return 0;
9816 rw_error:
9817 return rc;
9818 }
9819
9820 /*============================================================================*/
9821
9822 /**
9823 * \brief Power up AUD.
9824 * \param demod instance of demodulator
9825 * \return int.
9826 *
9827 */
9828 static int power_down_aud(struct drx_demod_instance *demod)
9829 {
9830 struct i2c_device_addr *dev_addr = NULL;
9831 struct drxj_data *ext_attr = NULL;
9832 int rc;
9833
9834 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9835 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9836
9837 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9838 if (rc != 0) {
9839 pr_err("error %d\n", rc);
9840 goto rw_error;
9841 }
9842
9843 ext_attr->aud_data.audio_is_active = false;
9844
9845 return 0;
9846 rw_error:
9847 return rc;
9848 }
9849
9850 /**
9851 * \fn int set_orx_nsu_aox()
9852 * \brief Configure OrxNsuAox for OOB
9853 * \param demod instance of demodulator.
9854 * \param active
9855 * \return int.
9856 */
9857 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9858 {
9859 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9860 int rc;
9861 u16 data = 0;
9862
9863 /* Configure NSU_AOX */
9864 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9865 if (rc != 0) {
9866 pr_err("error %d\n", rc);
9867 goto rw_error;
9868 }
9869 if (!active)
9870 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9871 else
9872 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9873 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9874 if (rc != 0) {
9875 pr_err("error %d\n", rc);
9876 goto rw_error;
9877 }
9878
9879 return 0;
9880 rw_error:
9881 return rc;
9882 }
9883
9884 /**
9885 * \fn int ctrl_set_oob()
9886 * \brief Set OOB channel to be used.
9887 * \param demod instance of demodulator
9888 * \param oob_param OOB parameters for channel setting.
9889 * \frequency should be in KHz
9890 * \return int.
9891 *
9892 * Accepts only. Returns error otherwise.
9893 * Demapper value is written after scu_command START
9894 * because START command causes COMM_EXEC transition
9895 * from 0 to 1 which causes all registers to be
9896 * overwritten with initial value
9897 *
9898 */
9899
9900 /* Nyquist filter impulse response */
9901 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
9902 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
9903 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
9904
9905 /* Coefficients for the nyquist fitler (total: 27 taps) */
9906 #define NYQFILTERLEN 27
9907
9908 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9909 {
9910 int rc;
9911 s32 freq = 0; /* KHz */
9912 struct i2c_device_addr *dev_addr = NULL;
9913 struct drxj_data *ext_attr = NULL;
9914 u16 i = 0;
9915 bool mirror_freq_spect_oob = false;
9916 u16 trk_filter_value = 0;
9917 struct drxjscu_cmd scu_cmd;
9918 u16 set_param_parameters[3];
9919 u16 cmd_result[2] = { 0, 0 };
9920 s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9921 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */
9922 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */
9923 IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */
9924 IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
9925 };
9926 u8 mode_val[4] = { 2, 2, 0, 1 };
9927 u8 pfi_coeffs[4][6] = {
9928 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9929 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9930 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9931 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9932 };
9933 u16 mode_index;
9934
9935 dev_addr = demod->my_i2c_dev_addr;
9936 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9937 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9938
9939 /* Check parameters */
9940 if (oob_param == NULL) {
9941 /* power off oob module */
9942 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9943 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9944 scu_cmd.parameter_len = 0;
9945 scu_cmd.result_len = 1;
9946 scu_cmd.result = cmd_result;
9947 rc = scu_command(dev_addr, &scu_cmd);
9948 if (rc != 0) {
9949 pr_err("error %d\n", rc);
9950 goto rw_error;
9951 }
9952 rc = set_orx_nsu_aox(demod, false);
9953 if (rc != 0) {
9954 pr_err("error %d\n", rc);
9955 goto rw_error;
9956 }
9957 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9958 if (rc != 0) {
9959 pr_err("error %d\n", rc);
9960 goto rw_error;
9961 }
9962
9963 ext_attr->oob_power_on = false;
9964 return 0;
9965 }
9966
9967 freq = oob_param->frequency;
9968 if ((freq < 70000) || (freq > 130000))
9969 return -EIO;
9970 freq = (freq - 50000) / 50;
9971
9972 {
9973 u16 index = 0;
9974 u16 remainder = 0;
9975 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9976
9977 index = (u16) ((freq - 400) / 200);
9978 remainder = (u16) ((freq - 400) % 200);
9979 trk_filter_value =
9980 trk_filtercfg[index] - (trk_filtercfg[index] -
9981 trk_filtercfg[index +
9982 1]) / 10 * remainder /
9983 20;
9984 }
9985
9986 /*********/
9987 /* Stop */
9988 /*********/
9989 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9990 if (rc != 0) {
9991 pr_err("error %d\n", rc);
9992 goto rw_error;
9993 }
9994 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9995 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9996 scu_cmd.parameter_len = 0;
9997 scu_cmd.result_len = 1;
9998 scu_cmd.result = cmd_result;
9999 rc = scu_command(dev_addr, &scu_cmd);
10000 if (rc != 0) {
10001 pr_err("error %d\n", rc);
10002 goto rw_error;
10003 }
10004 /*********/
10005 /* Reset */
10006 /*********/
10007 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10008 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10009 scu_cmd.parameter_len = 0;
10010 scu_cmd.result_len = 1;
10011 scu_cmd.result = cmd_result;
10012 rc = scu_command(dev_addr, &scu_cmd);
10013 if (rc != 0) {
10014 pr_err("error %d\n", rc);
10015 goto rw_error;
10016 }
10017 /***********/
10018 /* SET_ENV */
10019 /***********/
10020 /* set frequency, spectrum inversion and data rate */
10021 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10022 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10023 scu_cmd.parameter_len = 3;
10024 /* 1-data rate;2-frequency */
10025 switch (oob_param->standard) {
10026 case DRX_OOB_MODE_A:
10027 if (
10028 /* signal is transmitted inverted */
10029 ((oob_param->spectrum_inverted == true) &&
10030 /* and tuner is not mirroring the signal */
10031 (!mirror_freq_spect_oob)) |
10032 /* or */
10033 /* signal is transmitted noninverted */
10034 ((oob_param->spectrum_inverted == false) &&
10035 /* and tuner is mirroring the signal */
10036 (mirror_freq_spect_oob))
10037 )
10038 set_param_parameters[0] =
10039 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10040 else
10041 set_param_parameters[0] =
10042 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10043 break;
10044 case DRX_OOB_MODE_B_GRADE_A:
10045 if (
10046 /* signal is transmitted inverted */
10047 ((oob_param->spectrum_inverted == true) &&
10048 /* and tuner is not mirroring the signal */
10049 (!mirror_freq_spect_oob)) |
10050 /* or */
10051 /* signal is transmitted noninverted */
10052 ((oob_param->spectrum_inverted == false) &&
10053 /* and tuner is mirroring the signal */
10054 (mirror_freq_spect_oob))
10055 )
10056 set_param_parameters[0] =
10057 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10058 else
10059 set_param_parameters[0] =
10060 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10061 break;
10062 case DRX_OOB_MODE_B_GRADE_B:
10063 default:
10064 if (
10065 /* signal is transmitted inverted */
10066 ((oob_param->spectrum_inverted == true) &&
10067 /* and tuner is not mirroring the signal */
10068 (!mirror_freq_spect_oob)) |
10069 /* or */
10070 /* signal is transmitted noninverted */
10071 ((oob_param->spectrum_inverted == false) &&
10072 /* and tuner is mirroring the signal */
10073 (mirror_freq_spect_oob))
10074 )
10075 set_param_parameters[0] =
10076 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10077 else
10078 set_param_parameters[0] =
10079 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10080 break;
10081 }
10082 set_param_parameters[1] = (u16) (freq & 0xFFFF);
10083 set_param_parameters[2] = trk_filter_value;
10084 scu_cmd.parameter = set_param_parameters;
10085 scu_cmd.result_len = 1;
10086 scu_cmd.result = cmd_result;
10087 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10088 rc = scu_command(dev_addr, &scu_cmd);
10089 if (rc != 0) {
10090 pr_err("error %d\n", rc);
10091 goto rw_error;
10092 }
10093
10094 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10095 if (rc != 0) {
10096 pr_err("error %d\n", rc);
10097 goto rw_error;
10098 } /* Write magic word to enable pdr reg write */
10099 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10100 if (rc != 0) {
10101 pr_err("error %d\n", rc);
10102 goto rw_error;
10103 }
10104 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10105 if (rc != 0) {
10106 pr_err("error %d\n", rc);
10107 goto rw_error;
10108 }
10109 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10110 if (rc != 0) {
10111 pr_err("error %d\n", rc);
10112 goto rw_error;
10113 } /* Write magic word to disable pdr reg write */
10114
10115 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10116 if (rc != 0) {
10117 pr_err("error %d\n", rc);
10118 goto rw_error;
10119 }
10120 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10121 if (rc != 0) {
10122 pr_err("error %d\n", rc);
10123 goto rw_error;
10124 }
10125 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10126 if (rc != 0) {
10127 pr_err("error %d\n", rc);
10128 goto rw_error;
10129 }
10130
10131 /* ddc */
10132 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10133 if (rc != 0) {
10134 pr_err("error %d\n", rc);
10135 goto rw_error;
10136 }
10137
10138 /* nsu */
10139 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10140 if (rc != 0) {
10141 pr_err("error %d\n", rc);
10142 goto rw_error;
10143 }
10144
10145 /* initialization for target mode */
10146 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10147 if (rc != 0) {
10148 pr_err("error %d\n", rc);
10149 goto rw_error;
10150 }
10151 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10152 if (rc != 0) {
10153 pr_err("error %d\n", rc);
10154 goto rw_error;
10155 }
10156
10157 /* Reset bits for timing and freq. recovery */
10158 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10159 if (rc != 0) {
10160 pr_err("error %d\n", rc);
10161 goto rw_error;
10162 }
10163 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10164 if (rc != 0) {
10165 pr_err("error %d\n", rc);
10166 goto rw_error;
10167 }
10168 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10169 if (rc != 0) {
10170 pr_err("error %d\n", rc);
10171 goto rw_error;
10172 }
10173 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10174 if (rc != 0) {
10175 pr_err("error %d\n", rc);
10176 goto rw_error;
10177 }
10178
10179 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10180 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10181 if (rc != 0) {
10182 pr_err("error %d\n", rc);
10183 goto rw_error;
10184 }
10185 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10186 if (rc != 0) {
10187 pr_err("error %d\n", rc);
10188 goto rw_error;
10189 }
10190 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10191 if (rc != 0) {
10192 pr_err("error %d\n", rc);
10193 goto rw_error;
10194 }
10195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10196 if (rc != 0) {
10197 pr_err("error %d\n", rc);
10198 goto rw_error;
10199 }
10200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10201 if (rc != 0) {
10202 pr_err("error %d\n", rc);
10203 goto rw_error;
10204 }
10205
10206 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10207 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10208 if (rc != 0) {
10209 pr_err("error %d\n", rc);
10210 goto rw_error;
10211 }
10212 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10213 if (rc != 0) {
10214 pr_err("error %d\n", rc);
10215 goto rw_error;
10216 }
10217 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10218 if (rc != 0) {
10219 pr_err("error %d\n", rc);
10220 goto rw_error;
10221 }
10222 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10223 if (rc != 0) {
10224 pr_err("error %d\n", rc);
10225 goto rw_error;
10226 }
10227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10228 if (rc != 0) {
10229 pr_err("error %d\n", rc);
10230 goto rw_error;
10231 }
10232
10233 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10234 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10235 if (rc != 0) {
10236 pr_err("error %d\n", rc);
10237 goto rw_error;
10238 }
10239 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10240 if (rc != 0) {
10241 pr_err("error %d\n", rc);
10242 goto rw_error;
10243 }
10244 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10245 if (rc != 0) {
10246 pr_err("error %d\n", rc);
10247 goto rw_error;
10248 }
10249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10250 if (rc != 0) {
10251 pr_err("error %d\n", rc);
10252 goto rw_error;
10253 }
10254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10255 if (rc != 0) {
10256 pr_err("error %d\n", rc);
10257 goto rw_error;
10258 }
10259
10260 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10261 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10262 if (rc != 0) {
10263 pr_err("error %d\n", rc);
10264 goto rw_error;
10265 }
10266 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10267 if (rc != 0) {
10268 pr_err("error %d\n", rc);
10269 goto rw_error;
10270 }
10271 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10272 if (rc != 0) {
10273 pr_err("error %d\n", rc);
10274 goto rw_error;
10275 }
10276 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10277 if (rc != 0) {
10278 pr_err("error %d\n", rc);
10279 goto rw_error;
10280 }
10281 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10282 if (rc != 0) {
10283 pr_err("error %d\n", rc);
10284 goto rw_error;
10285 }
10286
10287 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
10288 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10289 if (rc != 0) {
10290 pr_err("error %d\n", rc);
10291 goto rw_error;
10292 }
10293 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10294 if (rc != 0) {
10295 pr_err("error %d\n", rc);
10296 goto rw_error;
10297 }
10298 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10299 if (rc != 0) {
10300 pr_err("error %d\n", rc);
10301 goto rw_error;
10302 }
10303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10304 if (rc != 0) {
10305 pr_err("error %d\n", rc);
10306 goto rw_error;
10307 }
10308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10309 if (rc != 0) {
10310 pr_err("error %d\n", rc);
10311 goto rw_error;
10312 }
10313
10314 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
10315 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10316 if (rc != 0) {
10317 pr_err("error %d\n", rc);
10318 goto rw_error;
10319 }
10320 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10321 if (rc != 0) {
10322 pr_err("error %d\n", rc);
10323 goto rw_error;
10324 }
10325 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10326 if (rc != 0) {
10327 pr_err("error %d\n", rc);
10328 goto rw_error;
10329 }
10330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10331 if (rc != 0) {
10332 pr_err("error %d\n", rc);
10333 goto rw_error;
10334 }
10335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10336 if (rc != 0) {
10337 pr_err("error %d\n", rc);
10338 goto rw_error;
10339 }
10340
10341 /* PRE-Filter coefficients (PFI) */
10342 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10343 if (rc != 0) {
10344 pr_err("error %d\n", rc);
10345 goto rw_error;
10346 }
10347 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10348 if (rc != 0) {
10349 pr_err("error %d\n", rc);
10350 goto rw_error;
10351 }
10352
10353 /* NYQUIST-Filter coefficients (NYQ) */
10354 for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10355 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10356 if (rc != 0) {
10357 pr_err("error %d\n", rc);
10358 goto rw_error;
10359 }
10360 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10361 if (rc != 0) {
10362 pr_err("error %d\n", rc);
10363 goto rw_error;
10364 }
10365 }
10366 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10367 if (rc != 0) {
10368 pr_err("error %d\n", rc);
10369 goto rw_error;
10370 }
10371 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10372 if (rc != 0) {
10373 pr_err("error %d\n", rc);
10374 goto rw_error;
10375 }
10376 /*********/
10377 /* Start */
10378 /*********/
10379 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10380 | SCU_RAM_COMMAND_CMD_DEMOD_START;
10381 scu_cmd.parameter_len = 0;
10382 scu_cmd.result_len = 1;
10383 scu_cmd.result = cmd_result;
10384 rc = scu_command(dev_addr, &scu_cmd);
10385 if (rc != 0) {
10386 pr_err("error %d\n", rc);
10387 goto rw_error;
10388 }
10389
10390 rc = set_orx_nsu_aox(demod, true);
10391 if (rc != 0) {
10392 pr_err("error %d\n", rc);
10393 goto rw_error;
10394 }
10395 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10396 if (rc != 0) {
10397 pr_err("error %d\n", rc);
10398 goto rw_error;
10399 }
10400
10401 ext_attr->oob_power_on = true;
10402
10403 return 0;
10404 rw_error:
10405 return rc;
10406 }
10407
10408 /*============================================================================*/
10409 /*== END OOB DATAPATH FUNCTIONS ==*/
10410 /*============================================================================*/
10411
10412 /*=============================================================================
10413 ===== MC command related functions ==========================================
10414 ===========================================================================*/
10415
10416 /*=============================================================================
10417 ===== ctrl_set_channel() ==========================================================
10418 ===========================================================================*/
10419 /**
10420 * \fn int ctrl_set_channel()
10421 * \brief Select a new transmission channel.
10422 * \param demod instance of demod.
10423 * \param channel Pointer to channel data.
10424 * \return int.
10425 *
10426 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
10427 * must tune the tuner to the centre frequency of the NTSC/FM channel.
10428 *
10429 */
10430 static int
10431 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10432 {
10433 int rc;
10434 s32 tuner_freq_offset = 0;
10435 struct drxj_data *ext_attr = NULL;
10436 struct i2c_device_addr *dev_addr = NULL;
10437 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10438 #ifndef DRXJ_VSB_ONLY
10439 u32 min_symbol_rate = 0;
10440 u32 max_symbol_rate = 0;
10441 int bandwidth_temp = 0;
10442 int bandwidth = 0;
10443 #endif
10444 /*== check arguments ======================================================*/
10445 if ((demod == NULL) || (channel == NULL))
10446 return -EINVAL;
10447
10448 dev_addr = demod->my_i2c_dev_addr;
10449 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10450 standard = ext_attr->standard;
10451
10452 /* check valid standards */
10453 switch (standard) {
10454 case DRX_STANDARD_8VSB:
10455 #ifndef DRXJ_VSB_ONLY
10456 case DRX_STANDARD_ITU_A:
10457 case DRX_STANDARD_ITU_B:
10458 case DRX_STANDARD_ITU_C:
10459 #endif /* DRXJ_VSB_ONLY */
10460 break;
10461 case DRX_STANDARD_UNKNOWN:
10462 default:
10463 return -EINVAL;
10464 }
10465
10466 /* check bandwidth QAM annex B, NTSC and 8VSB */
10467 if ((standard == DRX_STANDARD_ITU_B) ||
10468 (standard == DRX_STANDARD_8VSB) ||
10469 (standard == DRX_STANDARD_NTSC)) {
10470 switch (channel->bandwidth) {
10471 case DRX_BANDWIDTH_6MHZ:
10472 case DRX_BANDWIDTH_UNKNOWN: /* fall through */
10473 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10474 break;
10475 case DRX_BANDWIDTH_8MHZ: /* fall through */
10476 case DRX_BANDWIDTH_7MHZ: /* fall through */
10477 default:
10478 return -EINVAL;
10479 }
10480 }
10481
10482 /* For QAM annex A and annex C:
10483 -check symbolrate and constellation
10484 -derive bandwidth from symbolrate (input bandwidth is ignored)
10485 */
10486 #ifndef DRXJ_VSB_ONLY
10487 if ((standard == DRX_STANDARD_ITU_A) ||
10488 (standard == DRX_STANDARD_ITU_C)) {
10489 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10490 int bw_rolloff_factor = 0;
10491
10492 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10493 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10494 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10495 /* config SMA_TX pin to SAW switch mode */
10496 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10497 if (rc != 0) {
10498 pr_err("error %d\n", rc);
10499 goto rw_error;
10500 }
10501
10502 if (channel->symbolrate < min_symbol_rate ||
10503 channel->symbolrate > max_symbol_rate) {
10504 return -EINVAL;
10505 }
10506
10507 switch (channel->constellation) {
10508 case DRX_CONSTELLATION_QAM16: /* fall through */
10509 case DRX_CONSTELLATION_QAM32: /* fall through */
10510 case DRX_CONSTELLATION_QAM64: /* fall through */
10511 case DRX_CONSTELLATION_QAM128: /* fall through */
10512 case DRX_CONSTELLATION_QAM256:
10513 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10514 bandwidth = bandwidth_temp / 100;
10515
10516 if ((bandwidth_temp % 100) >= 50)
10517 bandwidth++;
10518
10519 if (bandwidth <= 6100000) {
10520 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10521 } else if ((bandwidth > 6100000)
10522 && (bandwidth <= 7100000)) {
10523 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10524 } else if (bandwidth > 7100000) {
10525 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10526 }
10527 break;
10528 default:
10529 return -EINVAL;
10530 }
10531 }
10532
10533 /* For QAM annex B:
10534 -check constellation
10535 */
10536 if (standard == DRX_STANDARD_ITU_B) {
10537 switch (channel->constellation) {
10538 case DRX_CONSTELLATION_AUTO:
10539 case DRX_CONSTELLATION_QAM256:
10540 case DRX_CONSTELLATION_QAM64:
10541 break;
10542 default:
10543 return -EINVAL;
10544 }
10545
10546 switch (channel->interleavemode) {
10547 case DRX_INTERLEAVEMODE_I128_J1:
10548 case DRX_INTERLEAVEMODE_I128_J1_V2:
10549 case DRX_INTERLEAVEMODE_I128_J2:
10550 case DRX_INTERLEAVEMODE_I64_J2:
10551 case DRX_INTERLEAVEMODE_I128_J3:
10552 case DRX_INTERLEAVEMODE_I32_J4:
10553 case DRX_INTERLEAVEMODE_I128_J4:
10554 case DRX_INTERLEAVEMODE_I16_J8:
10555 case DRX_INTERLEAVEMODE_I128_J5:
10556 case DRX_INTERLEAVEMODE_I8_J16:
10557 case DRX_INTERLEAVEMODE_I128_J6:
10558 case DRX_INTERLEAVEMODE_I128_J7:
10559 case DRX_INTERLEAVEMODE_I128_J8:
10560 case DRX_INTERLEAVEMODE_I12_J17:
10561 case DRX_INTERLEAVEMODE_I5_J4:
10562 case DRX_INTERLEAVEMODE_B52_M240:
10563 case DRX_INTERLEAVEMODE_B52_M720:
10564 case DRX_INTERLEAVEMODE_UNKNOWN:
10565 case DRX_INTERLEAVEMODE_AUTO:
10566 break;
10567 default:
10568 return -EINVAL;
10569 }
10570 }
10571
10572 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10573 /* SAW SW, user UIO is used for switchable SAW */
10574 struct drxuio_data uio1 = { DRX_UIO1, false };
10575
10576 switch (channel->bandwidth) {
10577 case DRX_BANDWIDTH_8MHZ:
10578 uio1.value = true;
10579 break;
10580 case DRX_BANDWIDTH_7MHZ:
10581 uio1.value = false;
10582 break;
10583 case DRX_BANDWIDTH_6MHZ:
10584 uio1.value = false;
10585 break;
10586 case DRX_BANDWIDTH_UNKNOWN:
10587 default:
10588 return -EINVAL;
10589 }
10590
10591 rc = ctrl_uio_write(demod, &uio1);
10592 if (rc != 0) {
10593 pr_err("error %d\n", rc);
10594 goto rw_error;
10595 }
10596 }
10597 #endif /* DRXJ_VSB_ONLY */
10598 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10599 if (rc != 0) {
10600 pr_err("error %d\n", rc);
10601 goto rw_error;
10602 }
10603
10604 tuner_freq_offset = 0;
10605
10606 /*== Setup demod for specific standard ====================================*/
10607 switch (standard) {
10608 case DRX_STANDARD_8VSB:
10609 if (channel->mirror == DRX_MIRROR_AUTO)
10610 ext_attr->mirror = DRX_MIRROR_NO;
10611 else
10612 ext_attr->mirror = channel->mirror;
10613 rc = set_vsb(demod);
10614 if (rc != 0) {
10615 pr_err("error %d\n", rc);
10616 goto rw_error;
10617 }
10618 rc = set_frequency(demod, channel, tuner_freq_offset);
10619 if (rc != 0) {
10620 pr_err("error %d\n", rc);
10621 goto rw_error;
10622 }
10623 break;
10624 #ifndef DRXJ_VSB_ONLY
10625 case DRX_STANDARD_ITU_A: /* fallthrough */
10626 case DRX_STANDARD_ITU_B: /* fallthrough */
10627 case DRX_STANDARD_ITU_C:
10628 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10629 if (rc != 0) {
10630 pr_err("error %d\n", rc);
10631 goto rw_error;
10632 }
10633 break;
10634 #endif
10635 case DRX_STANDARD_UNKNOWN:
10636 default:
10637 return -EIO;
10638 }
10639
10640 /* flag the packet error counter reset */
10641 ext_attr->reset_pkt_err_acc = true;
10642
10643 return 0;
10644 rw_error:
10645 return rc;
10646 }
10647
10648 /*=============================================================================
10649 ===== SigQuality() ==========================================================
10650 ===========================================================================*/
10651
10652 /**
10653 * \fn int ctrl_sig_quality()
10654 * \brief Retrieve signal quality form device.
10655 * \param devmod Pointer to demodulator instance.
10656 * \param sig_quality Pointer to signal quality data.
10657 * \return int.
10658 * \retval 0 sig_quality contains valid data.
10659 * \retval -EINVAL sig_quality is NULL.
10660 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10661
10662 */
10663 static int
10664 ctrl_sig_quality(struct drx_demod_instance *demod,
10665 enum drx_lock_status lock_status)
10666 {
10667 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10668 struct drxj_data *ext_attr = demod->my_ext_attr;
10669 struct drx39xxj_state *state = dev_addr->user_data;
10670 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10671 enum drx_standard standard = ext_attr->standard;
10672 int rc;
10673 u32 ber, cnt, err, pkt;
10674 u16 mer, strength = 0;
10675
10676 rc = get_sig_strength(demod, &strength);
10677 if (rc < 0) {
10678 pr_err("error getting signal strength %d\n", rc);
10679 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10680 } else {
10681 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10682 p->strength.stat[0].uvalue = 65535UL * strength/ 100;
10683 }
10684
10685 switch (standard) {
10686 case DRX_STANDARD_8VSB:
10687 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10688 rc = get_acc_pkt_err(demod, &pkt);
10689 if (rc != 0) {
10690 pr_err("error %d\n", rc);
10691 goto rw_error;
10692 }
10693 #endif
10694 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10695 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10696 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10697 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10698 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10699 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10700 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10701 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10702 } else {
10703 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10704 if (rc != 0) {
10705 pr_err("error %d getting UCB\n", rc);
10706 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10707 } else {
10708 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10709 p->block_error.stat[0].uvalue += err;
10710 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10711 p->block_count.stat[0].uvalue += pkt;
10712 }
10713
10714 /* PostViterbi is compute in steps of 10^(-6) */
10715 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10716 if (rc != 0) {
10717 pr_err("error %d getting pre-ber\n", rc);
10718 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10719 } else {
10720 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10721 p->pre_bit_error.stat[0].uvalue += ber;
10722 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10723 p->pre_bit_count.stat[0].uvalue += cnt;
10724 }
10725
10726 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10727 if (rc != 0) {
10728 pr_err("error %d getting post-ber\n", rc);
10729 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10730 } else {
10731 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10732 p->post_bit_error.stat[0].uvalue += ber;
10733 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10734 p->post_bit_count.stat[0].uvalue += cnt;
10735 }
10736 rc = get_vsbmer(dev_addr, &mer);
10737 if (rc != 0) {
10738 pr_err("error %d getting MER\n", rc);
10739 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10740 } else {
10741 p->cnr.stat[0].svalue = mer * 100;
10742 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10743 }
10744 }
10745 break;
10746 #ifndef DRXJ_VSB_ONLY
10747 case DRX_STANDARD_ITU_A:
10748 case DRX_STANDARD_ITU_B:
10749 case DRX_STANDARD_ITU_C:
10750 rc = ctrl_get_qam_sig_quality(demod);
10751 if (rc != 0) {
10752 pr_err("error %d\n", rc);
10753 goto rw_error;
10754 }
10755 break;
10756 #endif
10757 default:
10758 return -EIO;
10759 }
10760
10761 return 0;
10762 rw_error:
10763 return rc;
10764 }
10765
10766 /*============================================================================*/
10767
10768 /**
10769 * \fn int ctrl_lock_status()
10770 * \brief Retrieve lock status .
10771 * \param dev_addr Pointer to demodulator device address.
10772 * \param lock_stat Pointer to lock status structure.
10773 * \return int.
10774 *
10775 */
10776 static int
10777 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10778 {
10779 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10780 struct drxj_data *ext_attr = NULL;
10781 struct i2c_device_addr *dev_addr = NULL;
10782 struct drxjscu_cmd cmd_scu = { /* command */ 0,
10783 /* parameter_len */ 0,
10784 /* result_len */ 0,
10785 /* *parameter */ NULL,
10786 /* *result */ NULL
10787 };
10788 int rc;
10789 u16 cmd_result[2] = { 0, 0 };
10790 u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10791
10792 /* check arguments */
10793 if ((demod == NULL) || (lock_stat == NULL))
10794 return -EINVAL;
10795
10796 dev_addr = demod->my_i2c_dev_addr;
10797 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10798 standard = ext_attr->standard;
10799
10800 *lock_stat = DRX_NOT_LOCKED;
10801
10802 /* define the SCU command code */
10803 switch (standard) {
10804 case DRX_STANDARD_8VSB:
10805 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10806 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10807 demod_lock |= 0x6;
10808 break;
10809 #ifndef DRXJ_VSB_ONLY
10810 case DRX_STANDARD_ITU_A:
10811 case DRX_STANDARD_ITU_B:
10812 case DRX_STANDARD_ITU_C:
10813 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10814 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10815 break;
10816 #endif
10817 case DRX_STANDARD_UNKNOWN: /* fallthrough */
10818 default:
10819 return -EIO;
10820 }
10821
10822 /* define the SCU command parameters and execute the command */
10823 cmd_scu.parameter_len = 0;
10824 cmd_scu.result_len = 2;
10825 cmd_scu.parameter = NULL;
10826 cmd_scu.result = cmd_result;
10827 rc = scu_command(dev_addr, &cmd_scu);
10828 if (rc != 0) {
10829 pr_err("error %d\n", rc);
10830 goto rw_error;
10831 }
10832
10833 /* set the lock status */
10834 if (cmd_scu.result[1] < demod_lock) {
10835 /* 0x0000 NOT LOCKED */
10836 *lock_stat = DRX_NOT_LOCKED;
10837 } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10838 *lock_stat = DRXJ_DEMOD_LOCK;
10839 } else if (cmd_scu.result[1] <
10840 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10841 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
10842 *lock_stat = DRX_LOCKED;
10843 } else {
10844 /* 0xC000 NEVER LOCKED */
10845 /* (system will never be able to lock to the signal) */
10846 *lock_stat = DRX_NEVER_LOCK;
10847 }
10848
10849 return 0;
10850 rw_error:
10851 return rc;
10852 }
10853
10854 /*============================================================================*/
10855
10856 /**
10857 * \fn int ctrl_set_standard()
10858 * \brief Set modulation standard to be used.
10859 * \param standard Modulation standard.
10860 * \return int.
10861 *
10862 * Setup stuff for the desired demodulation standard.
10863 * Disable and power down the previous selected demodulation standard
10864 *
10865 */
10866 static int
10867 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10868 {
10869 struct drxj_data *ext_attr = NULL;
10870 int rc;
10871 enum drx_standard prev_standard;
10872
10873 /* check arguments */
10874 if ((standard == NULL) || (demod == NULL))
10875 return -EINVAL;
10876
10877 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10878 prev_standard = ext_attr->standard;
10879
10880 /*
10881 Stop and power down previous standard
10882 */
10883 switch (prev_standard) {
10884 #ifndef DRXJ_VSB_ONLY
10885 case DRX_STANDARD_ITU_A: /* fallthrough */
10886 case DRX_STANDARD_ITU_B: /* fallthrough */
10887 case DRX_STANDARD_ITU_C:
10888 rc = power_down_qam(demod, false);
10889 if (rc != 0) {
10890 pr_err("error %d\n", rc);
10891 goto rw_error;
10892 }
10893 break;
10894 #endif
10895 case DRX_STANDARD_8VSB:
10896 rc = power_down_vsb(demod, false);
10897 if (rc != 0) {
10898 pr_err("error %d\n", rc);
10899 goto rw_error;
10900 }
10901 break;
10902 case DRX_STANDARD_UNKNOWN:
10903 /* Do nothing */
10904 break;
10905 case DRX_STANDARD_AUTO: /* fallthrough */
10906 default:
10907 return -EINVAL;
10908 }
10909
10910 /*
10911 Initialize channel independent registers
10912 Power up new standard
10913 */
10914 ext_attr->standard = *standard;
10915
10916 switch (*standard) {
10917 #ifndef DRXJ_VSB_ONLY
10918 case DRX_STANDARD_ITU_A: /* fallthrough */
10919 case DRX_STANDARD_ITU_B: /* fallthrough */
10920 case DRX_STANDARD_ITU_C:
10921 do {
10922 u16 dummy;
10923 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10924 if (rc != 0) {
10925 pr_err("error %d\n", rc);
10926 goto rw_error;
10927 }
10928 } while (0);
10929 break;
10930 #endif
10931 case DRX_STANDARD_8VSB:
10932 rc = set_vsb_leak_n_gain(demod);
10933 if (rc != 0) {
10934 pr_err("error %d\n", rc);
10935 goto rw_error;
10936 }
10937 break;
10938 default:
10939 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10940 return -EINVAL;
10941 break;
10942 }
10943
10944 return 0;
10945 rw_error:
10946 /* Don't know what the standard is now ... try again */
10947 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10948 return rc;
10949 }
10950
10951 /*============================================================================*/
10952
10953 static void drxj_reset_mode(struct drxj_data *ext_attr)
10954 {
10955 /* Initialize default AFE configuartion for QAM */
10956 if (ext_attr->has_lna) {
10957 /* IF AGC off, PGA active */
10958 #ifndef DRXJ_VSB_ONLY
10959 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10960 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10961 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10962 #endif
10963 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10964 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10965 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10966 } else {
10967 /* IF AGC on, PGA not active */
10968 #ifndef DRXJ_VSB_ONLY
10969 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10970 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10971 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10972 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10973 ext_attr->qam_if_agc_cfg.speed = 3;
10974 ext_attr->qam_if_agc_cfg.top = 1297;
10975 ext_attr->qam_pga_cfg = 140;
10976 #endif
10977 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10978 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10979 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10980 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10981 ext_attr->vsb_if_agc_cfg.speed = 3;
10982 ext_attr->vsb_if_agc_cfg.top = 1024;
10983 ext_attr->vsb_pga_cfg = 140;
10984 }
10985 /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
10986 /* mc has not used them */
10987 #ifndef DRXJ_VSB_ONLY
10988 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10989 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10990 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10991 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10992 ext_attr->qam_rf_agc_cfg.speed = 3;
10993 ext_attr->qam_rf_agc_cfg.top = 9500;
10994 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
10995 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
10996 ext_attr->qam_pre_saw_cfg.reference = 0x07;
10997 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
10998 #endif
10999 /* Initialize default AFE configuartion for VSB */
11000 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11001 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11002 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11003 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11004 ext_attr->vsb_rf_agc_cfg.speed = 3;
11005 ext_attr->vsb_rf_agc_cfg.top = 9500;
11006 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11007 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11008 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11009 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11010 }
11011
11012 /**
11013 * \fn int ctrl_power_mode()
11014 * \brief Set the power mode of the device to the specified power mode
11015 * \param demod Pointer to demodulator instance.
11016 * \param mode Pointer to new power mode.
11017 * \return int.
11018 * \retval 0 Success
11019 * \retval -EIO I2C error or other failure
11020 * \retval -EINVAL Invalid mode argument.
11021 *
11022 *
11023 */
11024 static int
11025 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11026 {
11027 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11028 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11029 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11030 int rc;
11031 u16 sio_cc_pwd_mode = 0;
11032
11033 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11034 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11035 dev_addr = demod->my_i2c_dev_addr;
11036
11037 /* Check arguments */
11038 if (mode == NULL)
11039 return -EINVAL;
11040
11041 /* If already in requested power mode, do nothing */
11042 if (common_attr->current_power_mode == *mode)
11043 return 0;
11044
11045 switch (*mode) {
11046 case DRX_POWER_UP:
11047 case DRXJ_POWER_DOWN_MAIN_PATH:
11048 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11049 break;
11050 case DRXJ_POWER_DOWN_CORE:
11051 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11052 break;
11053 case DRXJ_POWER_DOWN_PLL:
11054 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11055 break;
11056 case DRX_POWER_DOWN:
11057 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11058 break;
11059 default:
11060 /* Unknow sleep mode */
11061 return -EINVAL;
11062 break;
11063 }
11064
11065 /* Check if device needs to be powered up */
11066 if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11067 rc = power_up_device(demod);
11068 if (rc != 0) {
11069 pr_err("error %d\n", rc);
11070 goto rw_error;
11071 }
11072 }
11073
11074 if ((*mode == DRX_POWER_UP)) {
11075 /* Restore analog & pin configuartion */
11076
11077 /* Initialize default AFE configuartion for VSB */
11078 drxj_reset_mode(ext_attr);
11079 } else {
11080 /* Power down to requested mode */
11081 /* Backup some register settings */
11082 /* Set pins with possible pull-ups connected to them in input mode */
11083 /* Analog power down */
11084 /* ADC power down */
11085 /* Power down device */
11086 /* stop all comm_exec */
11087 /*
11088 Stop and power down previous standard
11089 */
11090
11091 switch (ext_attr->standard) {
11092 case DRX_STANDARD_ITU_A:
11093 case DRX_STANDARD_ITU_B:
11094 case DRX_STANDARD_ITU_C:
11095 rc = power_down_qam(demod, true);
11096 if (rc != 0) {
11097 pr_err("error %d\n", rc);
11098 goto rw_error;
11099 }
11100 break;
11101 case DRX_STANDARD_8VSB:
11102 rc = power_down_vsb(demod, true);
11103 if (rc != 0) {
11104 pr_err("error %d\n", rc);
11105 goto rw_error;
11106 }
11107 break;
11108 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
11109 case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
11110 case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */
11111 case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */
11112 case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
11113 case DRX_STANDARD_NTSC: /* fallthrough */
11114 case DRX_STANDARD_FM:
11115 rc = power_down_atv(demod, ext_attr->standard, true);
11116 if (rc != 0) {
11117 pr_err("error %d\n", rc);
11118 goto rw_error;
11119 }
11120 break;
11121 case DRX_STANDARD_UNKNOWN:
11122 /* Do nothing */
11123 break;
11124 case DRX_STANDARD_AUTO: /* fallthrough */
11125 default:
11126 return -EIO;
11127 }
11128 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11129 }
11130
11131 if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11132 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11133 if (rc != 0) {
11134 pr_err("error %d\n", rc);
11135 goto rw_error;
11136 }
11137 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11138 if (rc != 0) {
11139 pr_err("error %d\n", rc);
11140 goto rw_error;
11141 }
11142
11143 if ((*mode != DRX_POWER_UP)) {
11144 /* Initialize HI, wakeup key especially before put IC to sleep */
11145 rc = init_hi(demod);
11146 if (rc != 0) {
11147 pr_err("error %d\n", rc);
11148 goto rw_error;
11149 }
11150
11151 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11152 rc = hi_cfg_command(demod);
11153 if (rc != 0) {
11154 pr_err("error %d\n", rc);
11155 goto rw_error;
11156 }
11157 }
11158 }
11159
11160 common_attr->current_power_mode = *mode;
11161
11162 return 0;
11163 rw_error:
11164 return rc;
11165 }
11166
11167 /*============================================================================*/
11168 /*== CTRL Set/Get Config related functions ===================================*/
11169 /*============================================================================*/
11170
11171 /**
11172 * \fn int ctrl_set_cfg_pre_saw()
11173 * \brief Set Pre-saw reference.
11174 * \param demod demod instance
11175 * \param u16 *
11176 * \return int.
11177 *
11178 * Check arguments
11179 * Dispatch handling to standard specific function.
11180 *
11181 */
11182 static int
11183 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11184 {
11185 struct i2c_device_addr *dev_addr = NULL;
11186 struct drxj_data *ext_attr = NULL;
11187 int rc;
11188
11189 dev_addr = demod->my_i2c_dev_addr;
11190 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11191
11192 /* check arguments */
11193 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11194 ) {
11195 return -EINVAL;
11196 }
11197
11198 /* Only if standard is currently active */
11199 if ((ext_attr->standard == pre_saw->standard) ||
11200 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11201 DRXJ_ISQAMSTD(pre_saw->standard)) ||
11202 (DRXJ_ISATVSTD(ext_attr->standard) &&
11203 DRXJ_ISATVSTD(pre_saw->standard))) {
11204 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11205 if (rc != 0) {
11206 pr_err("error %d\n", rc);
11207 goto rw_error;
11208 }
11209 }
11210
11211 /* Store pre-saw settings */
11212 switch (pre_saw->standard) {
11213 case DRX_STANDARD_8VSB:
11214 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11215 break;
11216 #ifndef DRXJ_VSB_ONLY
11217 case DRX_STANDARD_ITU_A: /* fallthrough */
11218 case DRX_STANDARD_ITU_B: /* fallthrough */
11219 case DRX_STANDARD_ITU_C:
11220 ext_attr->qam_pre_saw_cfg = *pre_saw;
11221 break;
11222 #endif
11223 default:
11224 return -EINVAL;
11225 }
11226
11227 return 0;
11228 rw_error:
11229 return rc;
11230 }
11231
11232 /*============================================================================*/
11233
11234 /**
11235 * \fn int ctrl_set_cfg_afe_gain()
11236 * \brief Set AFE Gain.
11237 * \param demod demod instance
11238 * \param u16 *
11239 * \return int.
11240 *
11241 * Check arguments
11242 * Dispatch handling to standard specific function.
11243 *
11244 */
11245 static int
11246 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11247 {
11248 struct i2c_device_addr *dev_addr = NULL;
11249 struct drxj_data *ext_attr = NULL;
11250 int rc;
11251 u8 gain = 0;
11252
11253 /* check arguments */
11254 if (afe_gain == NULL)
11255 return -EINVAL;
11256
11257 dev_addr = demod->my_i2c_dev_addr;
11258 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11259
11260 switch (afe_gain->standard) {
11261 case DRX_STANDARD_8VSB: /* fallthrough */
11262 #ifndef DRXJ_VSB_ONLY
11263 case DRX_STANDARD_ITU_A: /* fallthrough */
11264 case DRX_STANDARD_ITU_B: /* fallthrough */
11265 case DRX_STANDARD_ITU_C:
11266 #endif
11267 /* Do nothing */
11268 break;
11269 default:
11270 return -EINVAL;
11271 }
11272
11273 /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
11274 So I (PJ) think interface requires choice between auto, user mode */
11275
11276 if (afe_gain->gain >= 329)
11277 gain = 15;
11278 else if (afe_gain->gain <= 147)
11279 gain = 0;
11280 else
11281 gain = (afe_gain->gain - 140 + 6) / 13;
11282
11283 /* Only if standard is currently active */
11284 if (ext_attr->standard == afe_gain->standard) {
11285 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11286 if (rc != 0) {
11287 pr_err("error %d\n", rc);
11288 goto rw_error;
11289 }
11290 }
11291
11292 /* Store AFE Gain settings */
11293 switch (afe_gain->standard) {
11294 case DRX_STANDARD_8VSB:
11295 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11296 break;
11297 #ifndef DRXJ_VSB_ONLY
11298 case DRX_STANDARD_ITU_A: /* fallthrough */
11299 case DRX_STANDARD_ITU_B: /* fallthrough */
11300 case DRX_STANDARD_ITU_C:
11301 ext_attr->qam_pga_cfg = gain * 13 + 140;
11302 break;
11303 #endif
11304 default:
11305 return -EIO;
11306 }
11307
11308 return 0;
11309 rw_error:
11310 return rc;
11311 }
11312
11313 /*============================================================================*/
11314
11315
11316 /*=============================================================================
11317 ===== EXPORTED FUNCTIONS ====================================================*/
11318
11319 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11320 struct drxu_code_info *mc_info,
11321 enum drxu_code_action action);
11322 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11323
11324 /**
11325 * \fn drxj_open()
11326 * \brief Open the demod instance, configure device, configure drxdriver
11327 * \return Status_t Return status.
11328 *
11329 * drxj_open() can be called with a NULL ucode image => no ucode upload.
11330 * This means that drxj_open() must NOT contain SCU commands or, in general,
11331 * rely on SCU or AUD ucode to be present.
11332 *
11333 */
11334
11335 static int drxj_open(struct drx_demod_instance *demod)
11336 {
11337 struct i2c_device_addr *dev_addr = NULL;
11338 struct drxj_data *ext_attr = NULL;
11339 struct drx_common_attr *common_attr = NULL;
11340 u32 driver_version = 0;
11341 struct drxu_code_info ucode_info;
11342 struct drx_cfg_mpeg_output cfg_mpeg_output;
11343 int rc;
11344 enum drx_power_mode power_mode = DRX_POWER_UP;
11345
11346 if ((demod == NULL) ||
11347 (demod->my_common_attr == NULL) ||
11348 (demod->my_ext_attr == NULL) ||
11349 (demod->my_i2c_dev_addr == NULL) ||
11350 (demod->my_common_attr->is_opened)) {
11351 return -EINVAL;
11352 }
11353
11354 /* Check arguments */
11355 if (demod->my_ext_attr == NULL)
11356 return -EINVAL;
11357
11358 dev_addr = demod->my_i2c_dev_addr;
11359 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11360 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11361
11362 rc = ctrl_power_mode(demod, &power_mode);
11363 if (rc != 0) {
11364 pr_err("error %d\n", rc);
11365 goto rw_error;
11366 }
11367 if (power_mode != DRX_POWER_UP) {
11368 rc = -EINVAL;
11369 pr_err("failed to powerup device\n");
11370 goto rw_error;
11371 }
11372
11373 /* has to be in front of setIqmAf and setOrxNsuAox */
11374 rc = get_device_capabilities(demod);
11375 if (rc != 0) {
11376 pr_err("error %d\n", rc);
11377 goto rw_error;
11378 }
11379
11380 /*
11381 * Soft reset of sys- and osc-clockdomain
11382 *
11383 * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
11384 * As we didn't load the firmware here yet, we should do the same.
11385 * Btw, this is coherent with DRX-K, where we send reset codes
11386 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11387 */
11388 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11389 if (rc != 0) {
11390 pr_err("error %d\n", rc);
11391 goto rw_error;
11392 }
11393 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11394 if (rc != 0) {
11395 pr_err("error %d\n", rc);
11396 goto rw_error;
11397 }
11398 msleep(1);
11399
11400 /* TODO first make sure that everything keeps working before enabling this */
11401 /* PowerDownAnalogBlocks() */
11402 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11403 if (rc != 0) {
11404 pr_err("error %d\n", rc);
11405 goto rw_error;
11406 }
11407
11408 rc = set_iqm_af(demod, false);
11409 if (rc != 0) {
11410 pr_err("error %d\n", rc);
11411 goto rw_error;
11412 }
11413 rc = set_orx_nsu_aox(demod, false);
11414 if (rc != 0) {
11415 pr_err("error %d\n", rc);
11416 goto rw_error;
11417 }
11418
11419 rc = init_hi(demod);
11420 if (rc != 0) {
11421 pr_err("error %d\n", rc);
11422 goto rw_error;
11423 }
11424
11425 /* disable mpegoutput pins */
11426 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11427 cfg_mpeg_output.enable_mpeg_output = false;
11428
11429 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11430 if (rc != 0) {
11431 pr_err("error %d\n", rc);
11432 goto rw_error;
11433 }
11434 /* Stop AUD Inform SetAudio it will need to do all setting */
11435 rc = power_down_aud(demod);
11436 if (rc != 0) {
11437 pr_err("error %d\n", rc);
11438 goto rw_error;
11439 }
11440 /* Stop SCU */
11441 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11442 if (rc != 0) {
11443 pr_err("error %d\n", rc);
11444 goto rw_error;
11445 }
11446
11447 /* Upload microcode */
11448 if (common_attr->microcode_file != NULL) {
11449 /* Dirty trick to use common ucode upload & verify,
11450 pretend device is already open */
11451 common_attr->is_opened = true;
11452 ucode_info.mc_file = common_attr->microcode_file;
11453
11454 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11455 pr_err("Should powerup before loading the firmware.");
11456 return -EINVAL;
11457 }
11458
11459 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11460 if (rc != 0) {
11461 pr_err("error %d while uploading the firmware\n", rc);
11462 goto rw_error;
11463 }
11464 if (common_attr->verify_microcode == true) {
11465 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11466 if (rc != 0) {
11467 pr_err("error %d while verifying the firmware\n",
11468 rc);
11469 goto rw_error;
11470 }
11471 }
11472 common_attr->is_opened = false;
11473 }
11474
11475 /* Run SCU for a little while to initialize microcode version numbers */
11476 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11477 if (rc != 0) {
11478 pr_err("error %d\n", rc);
11479 goto rw_error;
11480 }
11481
11482 /* Initialize scan timeout */
11483 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11484 common_attr->scan_desired_lock = DRX_LOCKED;
11485
11486 drxj_reset_mode(ext_attr);
11487 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11488
11489 rc = smart_ant_init(demod);
11490 if (rc != 0) {
11491 pr_err("error %d\n", rc);
11492 goto rw_error;
11493 }
11494
11495 /* Stamp driver version number in SCU data RAM in BCD code
11496 Done to enable field application engineers to retrieve drxdriver version
11497 via I2C from SCU RAM
11498 */
11499 driver_version = (VERSION_MAJOR / 100) % 10;
11500 driver_version <<= 4;
11501 driver_version += (VERSION_MAJOR / 10) % 10;
11502 driver_version <<= 4;
11503 driver_version += (VERSION_MAJOR % 10);
11504 driver_version <<= 4;
11505 driver_version += (VERSION_MINOR % 10);
11506 driver_version <<= 4;
11507 driver_version += (VERSION_PATCH / 1000) % 10;
11508 driver_version <<= 4;
11509 driver_version += (VERSION_PATCH / 100) % 10;
11510 driver_version <<= 4;
11511 driver_version += (VERSION_PATCH / 10) % 10;
11512 driver_version <<= 4;
11513 driver_version += (VERSION_PATCH % 10);
11514 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11515 if (rc != 0) {
11516 pr_err("error %d\n", rc);
11517 goto rw_error;
11518 }
11519 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11520 if (rc != 0) {
11521 pr_err("error %d\n", rc);
11522 goto rw_error;
11523 }
11524
11525 rc = ctrl_set_oob(demod, NULL);
11526 if (rc != 0) {
11527 pr_err("error %d\n", rc);
11528 goto rw_error;
11529 }
11530
11531 /* refresh the audio data structure with default */
11532 ext_attr->aud_data = drxj_default_aud_data_g;
11533
11534 demod->my_common_attr->is_opened = true;
11535 drxj_set_lna_state(demod, false);
11536 return 0;
11537 rw_error:
11538 common_attr->is_opened = false;
11539 return rc;
11540 }
11541
11542 /*============================================================================*/
11543 /**
11544 * \fn drxj_close()
11545 * \brief Close the demod instance, power down the device
11546 * \return Status_t Return status.
11547 *
11548 */
11549 static int drxj_close(struct drx_demod_instance *demod)
11550 {
11551 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11552 int rc;
11553 enum drx_power_mode power_mode = DRX_POWER_UP;
11554
11555 if ((demod->my_common_attr == NULL) ||
11556 (demod->my_ext_attr == NULL) ||
11557 (demod->my_i2c_dev_addr == NULL) ||
11558 (!demod->my_common_attr->is_opened)) {
11559 return -EINVAL;
11560 }
11561
11562 /* power up */
11563 rc = ctrl_power_mode(demod, &power_mode);
11564 if (rc != 0) {
11565 pr_err("error %d\n", rc);
11566 goto rw_error;
11567 }
11568
11569 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11570 if (rc != 0) {
11571 pr_err("error %d\n", rc);
11572 goto rw_error;
11573 }
11574 power_mode = DRX_POWER_DOWN;
11575 rc = ctrl_power_mode(demod, &power_mode);
11576 if (rc != 0) {
11577 pr_err("error %d\n", rc);
11578 goto rw_error;
11579 }
11580
11581 DRX_ATTR_ISOPENED(demod) = false;
11582
11583 return 0;
11584 rw_error:
11585 DRX_ATTR_ISOPENED(demod) = false;
11586
11587 return rc;
11588 }
11589
11590 /*
11591 * Microcode related functions
11592 */
11593
11594 /**
11595 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11596 * @block_data: Pointer to microcode data.
11597 * @nr_words: Size of microcode block (number of 16 bits words).
11598 *
11599 * returns The computed CRC residue.
11600 */
11601 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11602 {
11603 u16 i = 0;
11604 u16 j = 0;
11605 u32 crc_word = 0;
11606 u32 carry = 0;
11607
11608 while (i < nr_words) {
11609 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11610 for (j = 0; j < 16; j++) {
11611 crc_word <<= 1;
11612 if (carry != 0)
11613 crc_word ^= 0x80050000UL;
11614 carry = crc_word & 0x80000000UL;
11615 }
11616 i++;
11617 block_data += (sizeof(u16));
11618 }
11619 return (u16)(crc_word >> 16);
11620 }
11621
11622 /**
11623 * drx_check_firmware - checks if the loaded firmware is valid
11624 *
11625 * @demod: demod structure
11626 * @mc_data: pointer to the start of the firmware
11627 * @size: firmware size
11628 */
11629 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11630 unsigned size)
11631 {
11632 struct drxu_code_block_hdr block_hdr;
11633 int i;
11634 unsigned count = 2 * sizeof(u16);
11635 u32 mc_dev_type, mc_version, mc_base_version;
11636 u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11637
11638 /*
11639 * Scan microcode blocks first for version info
11640 * and firmware check
11641 */
11642
11643 /* Clear version block */
11644 DRX_ATTR_MCRECORD(demod).aux_type = 0;
11645 DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11646 DRX_ATTR_MCRECORD(demod).mc_version = 0;
11647 DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11648
11649 for (i = 0; i < mc_nr_of_blks; i++) {
11650 if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11651 goto eof;
11652
11653 /* Process block header */
11654 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11655 count += sizeof(u32);
11656 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11657 count += sizeof(u16);
11658 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11659 count += sizeof(u16);
11660 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11661 count += sizeof(u16);
11662
11663 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11664 count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11665 block_hdr.CRC);
11666
11667 if (block_hdr.flags & 0x8) {
11668 u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11669 u16 auxtype;
11670
11671 if (block_hdr.addr + sizeof(u16) > size)
11672 goto eof;
11673
11674 auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11675
11676 /* Aux block. Check type */
11677 if (DRX_ISMCVERTYPE(auxtype)) {
11678 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11679 goto eof;
11680
11681 auxblk += sizeof(u16);
11682 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11683 auxblk += sizeof(u32);
11684 mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11685 auxblk += sizeof(u32);
11686 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11687
11688 DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11689 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11690 DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11691 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11692
11693 pr_info("Firmware dev %x, ver %x, base ver %x\n",
11694 mc_dev_type, mc_version, mc_base_version);
11695
11696 }
11697 } else if (count + block_hdr.size * sizeof(u16) > size)
11698 goto eof;
11699
11700 count += block_hdr.size * sizeof(u16);
11701 }
11702 return 0;
11703 eof:
11704 pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11705 return -EINVAL;
11706 }
11707
11708 /**
11709 * drx_ctrl_u_code - Handle microcode upload or verify.
11710 * @dev_addr: Address of device.
11711 * @mc_info: Pointer to information about microcode data.
11712 * @action: Either UCODE_UPLOAD or UCODE_VERIFY
11713 *
11714 * This function returns:
11715 * 0:
11716 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11717 * - In case of UCODE_VERIFY: image on device is equal to
11718 * image provided to this control function.
11719 * -EIO:
11720 * - In case of UCODE_UPLOAD: I2C error.
11721 * - In case of UCODE_VERIFY: I2C error or image on device
11722 * is not equal to image provided to this control function.
11723 * -EINVAL:
11724 * - Invalid arguments.
11725 * - Provided image is corrupt
11726 */
11727 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11728 struct drxu_code_info *mc_info,
11729 enum drxu_code_action action)
11730 {
11731 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11732 int rc;
11733 u16 i = 0;
11734 u16 mc_nr_of_blks = 0;
11735 u16 mc_magic_word = 0;
11736 const u8 *mc_data_init = NULL;
11737 u8 *mc_data = NULL;
11738 unsigned size;
11739 char *mc_file;
11740
11741 /* Check arguments */
11742 if (!mc_info || !mc_info->mc_file)
11743 return -EINVAL;
11744
11745 mc_file = mc_info->mc_file;
11746
11747 if (!demod->firmware) {
11748 const struct firmware *fw = NULL;
11749
11750 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11751 if (rc < 0) {
11752 pr_err("Couldn't read firmware %s\n", mc_file);
11753 return rc;
11754 }
11755 demod->firmware = fw;
11756
11757 if (demod->firmware->size < 2 * sizeof(u16)) {
11758 rc = -EINVAL;
11759 pr_err("Firmware is too short!\n");
11760 goto release;
11761 }
11762
11763 pr_info("Firmware %s, size %zu\n",
11764 mc_file, demod->firmware->size);
11765 }
11766
11767 mc_data_init = demod->firmware->data;
11768 size = demod->firmware->size;
11769
11770 mc_data = (void *)mc_data_init;
11771 /* Check data */
11772 mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11773 mc_data += sizeof(u16);
11774 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11775 mc_data += sizeof(u16);
11776
11777 if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11778 rc = -EINVAL;
11779 pr_err("Firmware magic word doesn't match\n");
11780 goto release;
11781 }
11782
11783 if (action == UCODE_UPLOAD) {
11784 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11785 if (rc)
11786 goto release;
11787 pr_info("Uploading firmware %s\n", mc_file);
11788 } else {
11789 pr_info("Verifying if firmware upload was ok.\n");
11790 }
11791
11792 /* Process microcode blocks */
11793 for (i = 0; i < mc_nr_of_blks; i++) {
11794 struct drxu_code_block_hdr block_hdr;
11795 u16 mc_block_nr_bytes = 0;
11796
11797 /* Process block header */
11798 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11799 mc_data += sizeof(u32);
11800 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11801 mc_data += sizeof(u16);
11802 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11803 mc_data += sizeof(u16);
11804 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11805 mc_data += sizeof(u16);
11806
11807 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11808 (unsigned)(mc_data - mc_data_init), block_hdr.addr,
11809 block_hdr.size, block_hdr.flags, block_hdr.CRC);
11810
11811 /* Check block header on:
11812 - data larger than 64Kb
11813 - if CRC enabled check CRC
11814 */
11815 if ((block_hdr.size > 0x7FFF) ||
11816 (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11817 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11818 ) {
11819 /* Wrong data ! */
11820 rc = -EINVAL;
11821 pr_err("firmware CRC is wrong\n");
11822 goto release;
11823 }
11824
11825 if (!block_hdr.size)
11826 continue;
11827
11828 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11829
11830 /* Perform the desired action */
11831 switch (action) {
11832 case UCODE_UPLOAD: /* Upload microcode */
11833 if (drxdap_fasi_write_block(dev_addr,
11834 block_hdr.addr,
11835 mc_block_nr_bytes,
11836 mc_data, 0x0000)) {
11837 rc = -EIO;
11838 pr_err("error writing firmware at pos %u\n",
11839 (unsigned)(mc_data - mc_data_init));
11840 goto release;
11841 }
11842 break;
11843 case UCODE_VERIFY: { /* Verify uploaded microcode */
11844 int result = 0;
11845 u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11846 u32 bytes_to_comp = 0;
11847 u32 bytes_left = mc_block_nr_bytes;
11848 u32 curr_addr = block_hdr.addr;
11849 u8 *curr_ptr = mc_data;
11850
11851 while (bytes_left != 0) {
11852 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11853 bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11854 else
11855 bytes_to_comp = bytes_left;
11856
11857 if (drxdap_fasi_read_block(dev_addr,
11858 curr_addr,
11859 (u16)bytes_to_comp,
11860 (u8 *)mc_data_buffer,
11861 0x0000)) {
11862 pr_err("error reading firmware at pos %u\n",
11863 (unsigned)(mc_data - mc_data_init));
11864 return -EIO;
11865 }
11866
11867 result = memcmp(curr_ptr, mc_data_buffer,
11868 bytes_to_comp);
11869
11870 if (result) {
11871 pr_err("error verifying firmware at pos %u\n",
11872 (unsigned)(mc_data - mc_data_init));
11873 return -EIO;
11874 }
11875
11876 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11877 curr_ptr =&(curr_ptr[bytes_to_comp]);
11878 bytes_left -=((u32) bytes_to_comp);
11879 }
11880 break;
11881 }
11882 default:
11883 return -EINVAL;
11884 break;
11885
11886 }
11887 mc_data += mc_block_nr_bytes;
11888 }
11889
11890 return 0;
11891
11892 release:
11893 release_firmware(demod->firmware);
11894 demod->firmware = NULL;
11895
11896 return rc;
11897 }
11898
11899 /* caller is expected to check if lna is supported before enabling */
11900 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11901 {
11902 struct drxuio_cfg uio_cfg;
11903 struct drxuio_data uio_data;
11904 int result;
11905
11906 uio_cfg.uio = DRX_UIO1;
11907 uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11908 /* Configure user-I/O #3: enable read/write */
11909 result = ctrl_set_uio_cfg(demod, &uio_cfg);
11910 if (result) {
11911 pr_err("Failed to setup LNA GPIO!\n");
11912 return result;
11913 }
11914
11915 uio_data.uio = DRX_UIO1;
11916 uio_data.value = state;
11917 result = ctrl_uio_write(demod, &uio_data);
11918 if (result != 0) {
11919 pr_err("Failed to %sable LNA!\n",
11920 state ? "en" : "dis");
11921 return result;
11922 }
11923 return 0;
11924 }
11925
11926 /*
11927 * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
11928 *
11929 * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
11930 */
11931
11932 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11933 {
11934 struct drx39xxj_state *state = fe->demodulator_priv;
11935 struct drx_demod_instance *demod = state->demod;
11936 int result;
11937 enum drx_power_mode power_mode;
11938
11939 if (enable)
11940 power_mode = DRX_POWER_UP;
11941 else
11942 power_mode = DRX_POWER_DOWN;
11943
11944 result = ctrl_power_mode(demod, &power_mode);
11945 if (result != 0) {
11946 pr_err("Power state change failed\n");
11947 return 0;
11948 }
11949
11950 return 0;
11951 }
11952
11953 static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
11954 {
11955 struct drx39xxj_state *state = fe->demodulator_priv;
11956 struct drx_demod_instance *demod = state->demod;
11957 int result;
11958 enum drx_lock_status lock_status;
11959
11960 *status = 0;
11961
11962 result = ctrl_lock_status(demod, &lock_status);
11963 if (result != 0) {
11964 pr_err("drx39xxj: could not get lock status!\n");
11965 *status = 0;
11966 }
11967
11968 switch (lock_status) {
11969 case DRX_NEVER_LOCK:
11970 *status = 0;
11971 pr_err("drx says NEVER_LOCK\n");
11972 break;
11973 case DRX_NOT_LOCKED:
11974 *status = 0;
11975 break;
11976 case DRX_LOCK_STATE_1:
11977 case DRX_LOCK_STATE_2:
11978 case DRX_LOCK_STATE_3:
11979 case DRX_LOCK_STATE_4:
11980 case DRX_LOCK_STATE_5:
11981 case DRX_LOCK_STATE_6:
11982 case DRX_LOCK_STATE_7:
11983 case DRX_LOCK_STATE_8:
11984 case DRX_LOCK_STATE_9:
11985 *status = FE_HAS_SIGNAL
11986 | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11987 break;
11988 case DRX_LOCKED:
11989 *status = FE_HAS_SIGNAL
11990 | FE_HAS_CARRIER
11991 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
11992 break;
11993 default:
11994 pr_err("Lock state unknown %d\n", lock_status);
11995 }
11996 ctrl_sig_quality(demod, lock_status);
11997
11998 return 0;
11999 }
12000
12001 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
12002 {
12003 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12004
12005 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12006 *ber = 0;
12007 return 0;
12008 }
12009
12010 if (!p->pre_bit_count.stat[0].uvalue) {
12011 if (!p->pre_bit_error.stat[0].uvalue)
12012 *ber = 0;
12013 else
12014 *ber = 1000000;
12015 } else {
12016 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12017 p->pre_bit_count.stat[0].uvalue);
12018 }
12019 return 0;
12020 }
12021
12022 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12023 u16 *strength)
12024 {
12025 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12026
12027 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12028 *strength = 0;
12029 return 0;
12030 }
12031
12032 *strength = p->strength.stat[0].uvalue;
12033 return 0;
12034 }
12035
12036 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12037 {
12038 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12039 u64 tmp64;
12040
12041 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12042 *snr = 0;
12043 return 0;
12044 }
12045
12046 tmp64 = p->cnr.stat[0].svalue;
12047 do_div(tmp64, 10);
12048 *snr = tmp64;
12049 return 0;
12050 }
12051
12052 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12053 {
12054 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12055
12056 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12057 *ucb = 0;
12058 return 0;
12059 }
12060
12061 *ucb = p->block_error.stat[0].uvalue;
12062 return 0;
12063 }
12064
12065 static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12066 {
12067 #ifdef DJH_DEBUG
12068 int i;
12069 #endif
12070 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12071 struct drx39xxj_state *state = fe->demodulator_priv;
12072 struct drx_demod_instance *demod = state->demod;
12073 enum drx_standard standard = DRX_STANDARD_8VSB;
12074 struct drx_channel channel;
12075 int result;
12076 static const struct drx_channel def_channel = {
12077 /* frequency */ 0,
12078 /* bandwidth */ DRX_BANDWIDTH_6MHZ,
12079 /* mirror */ DRX_MIRROR_NO,
12080 /* constellation */ DRX_CONSTELLATION_AUTO,
12081 /* hierarchy */ DRX_HIERARCHY_UNKNOWN,
12082 /* priority */ DRX_PRIORITY_UNKNOWN,
12083 /* coderate */ DRX_CODERATE_UNKNOWN,
12084 /* guard */ DRX_GUARD_UNKNOWN,
12085 /* fftmode */ DRX_FFTMODE_UNKNOWN,
12086 /* classification */ DRX_CLASSIFICATION_AUTO,
12087 /* symbolrate */ 5057000,
12088 /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
12089 /* ldpc */ DRX_LDPC_UNKNOWN,
12090 /* carrier */ DRX_CARRIER_UNKNOWN,
12091 /* frame mode */ DRX_FRAMEMODE_UNKNOWN
12092 };
12093 u32 constellation = DRX_CONSTELLATION_AUTO;
12094
12095 /* Bring the demod out of sleep */
12096 drx39xxj_set_powerstate(fe, 1);
12097
12098 if (fe->ops.tuner_ops.set_params) {
12099 u32 int_freq;
12100
12101 if (fe->ops.i2c_gate_ctrl)
12102 fe->ops.i2c_gate_ctrl(fe, 1);
12103
12104 /* Set tuner to desired frequency and standard */
12105 fe->ops.tuner_ops.set_params(fe);
12106
12107 /* Use the tuner's IF */
12108 if (fe->ops.tuner_ops.get_if_frequency) {
12109 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12110 demod->my_common_attr->intermediate_freq = int_freq / 1000;
12111 }
12112
12113 if (fe->ops.i2c_gate_ctrl)
12114 fe->ops.i2c_gate_ctrl(fe, 0);
12115 }
12116
12117 switch (p->delivery_system) {
12118 case SYS_ATSC:
12119 standard = DRX_STANDARD_8VSB;
12120 break;
12121 case SYS_DVBC_ANNEX_B:
12122 standard = DRX_STANDARD_ITU_B;
12123
12124 switch (p->modulation) {
12125 case QAM_64:
12126 constellation = DRX_CONSTELLATION_QAM64;
12127 break;
12128 case QAM_256:
12129 constellation = DRX_CONSTELLATION_QAM256;
12130 break;
12131 default:
12132 constellation = DRX_CONSTELLATION_AUTO;
12133 break;
12134 }
12135 break;
12136 default:
12137 return -EINVAL;
12138 }
12139 /* Set the standard (will be powered up if necessary */
12140 result = ctrl_set_standard(demod, &standard);
12141 if (result != 0) {
12142 pr_err("Failed to set standard! result=%02x\n",
12143 result);
12144 return -EINVAL;
12145 }
12146
12147 /* set channel parameters */
12148 channel = def_channel;
12149 channel.frequency = p->frequency / 1000;
12150 channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12151 channel.constellation = constellation;
12152
12153 /* program channel */
12154 result = ctrl_set_channel(demod, &channel);
12155 if (result != 0) {
12156 pr_err("Failed to set channel!\n");
12157 return -EINVAL;
12158 }
12159 /* Just for giggles, let's shut off the LNA again.... */
12160 drxj_set_lna_state(demod, false);
12161
12162 /* After set_frontend, except for strength, stats aren't available */
12163 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12164
12165 return 0;
12166 }
12167
12168 static int drx39xxj_sleep(struct dvb_frontend *fe)
12169 {
12170 /* power-down the demodulator */
12171 return drx39xxj_set_powerstate(fe, 0);
12172 }
12173
12174 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12175 {
12176 struct drx39xxj_state *state = fe->demodulator_priv;
12177 struct drx_demod_instance *demod = state->demod;
12178 bool i2c_gate_state;
12179 int result;
12180
12181 #ifdef DJH_DEBUG
12182 pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12183 state->i2c_gate_open);
12184 #endif
12185
12186 if (enable)
12187 i2c_gate_state = true;
12188 else
12189 i2c_gate_state = false;
12190
12191 if (state->i2c_gate_open == enable) {
12192 /* We're already in the desired state */
12193 return 0;
12194 }
12195
12196 result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12197 if (result != 0) {
12198 pr_err("drx39xxj: could not open i2c gate [%d]\n",
12199 result);
12200 dump_stack();
12201 } else {
12202 state->i2c_gate_open = enable;
12203 }
12204 return 0;
12205 }
12206
12207 static int drx39xxj_init(struct dvb_frontend *fe)
12208 {
12209 struct drx39xxj_state *state = fe->demodulator_priv;
12210 struct drx_demod_instance *demod = state->demod;
12211 int rc = 0;
12212
12213 if (fe->exit == DVB_FE_DEVICE_RESUME) {
12214 /* so drxj_open() does what it needs to do */
12215 demod->my_common_attr->is_opened = false;
12216 rc = drxj_open(demod);
12217 if (rc != 0)
12218 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12219 } else
12220 drx39xxj_set_powerstate(fe, 1);
12221
12222 return rc;
12223 }
12224
12225 static int drx39xxj_set_lna(struct dvb_frontend *fe)
12226 {
12227 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12228 struct drx39xxj_state *state = fe->demodulator_priv;
12229 struct drx_demod_instance *demod = state->demod;
12230 struct drxj_data *ext_attr = demod->my_ext_attr;
12231
12232 if (c->lna) {
12233 if (!ext_attr->has_lna) {
12234 pr_err("LNA is not supported on this device!\n");
12235 return -EINVAL;
12236
12237 }
12238 }
12239
12240 return drxj_set_lna_state(demod, c->lna);
12241 }
12242
12243 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12244 struct dvb_frontend_tune_settings *tune)
12245 {
12246 tune->min_delay_ms = 1000;
12247 return 0;
12248 }
12249
12250 static void drx39xxj_release(struct dvb_frontend *fe)
12251 {
12252 struct drx39xxj_state *state = fe->demodulator_priv;
12253 struct drx_demod_instance *demod = state->demod;
12254
12255 /* if device is removed don't access it */
12256 if (fe->exit != DVB_FE_DEVICE_REMOVED)
12257 drxj_close(demod);
12258
12259 kfree(demod->my_ext_attr);
12260 kfree(demod->my_common_attr);
12261 kfree(demod->my_i2c_dev_addr);
12262 release_firmware(demod->firmware);
12263 kfree(demod);
12264 kfree(state);
12265 }
12266
12267 static const struct dvb_frontend_ops drx39xxj_ops;
12268
12269 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12270 {
12271 struct drx39xxj_state *state = NULL;
12272 struct i2c_device_addr *demod_addr = NULL;
12273 struct drx_common_attr *demod_comm_attr = NULL;
12274 struct drxj_data *demod_ext_attr = NULL;
12275 struct drx_demod_instance *demod = NULL;
12276 struct dtv_frontend_properties *p;
12277 int result;
12278
12279 /* allocate memory for the internal state */
12280 state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12281 if (state == NULL)
12282 goto error;
12283
12284 demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12285 if (demod == NULL)
12286 goto error;
12287
12288 demod_addr = kmemdup(&drxj_default_addr_g,
12289 sizeof(struct i2c_device_addr), GFP_KERNEL);
12290 if (demod_addr == NULL)
12291 goto error;
12292
12293 demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12294 sizeof(struct drx_common_attr), GFP_KERNEL);
12295 if (demod_comm_attr == NULL)
12296 goto error;
12297
12298 demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12299 GFP_KERNEL);
12300 if (demod_ext_attr == NULL)
12301 goto error;
12302
12303 /* setup the state */
12304 state->i2c = i2c;
12305 state->demod = demod;
12306
12307 /* setup the demod data */
12308 memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12309
12310 demod->my_i2c_dev_addr = demod_addr;
12311 demod->my_common_attr = demod_comm_attr;
12312 demod->my_i2c_dev_addr->user_data = state;
12313 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12314 demod->my_common_attr->verify_microcode = true;
12315 demod->my_common_attr->intermediate_freq = 5000;
12316 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12317 demod->my_ext_attr = demod_ext_attr;
12318 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12319 demod->i2c = i2c;
12320
12321 result = drxj_open(demod);
12322 if (result != 0) {
12323 pr_err("DRX open failed! Aborting\n");
12324 goto error;
12325 }
12326
12327 /* create dvb_frontend */
12328 memcpy(&state->frontend.ops, &drx39xxj_ops,
12329 sizeof(struct dvb_frontend_ops));
12330
12331 state->frontend.demodulator_priv = state;
12332
12333 /* Initialize stats - needed for DVBv5 stats to work */
12334 p = &state->frontend.dtv_property_cache;
12335 p->strength.len = 1;
12336 p->pre_bit_count.len = 1;
12337 p->pre_bit_error.len = 1;
12338 p->post_bit_count.len = 1;
12339 p->post_bit_error.len = 1;
12340 p->block_count.len = 1;
12341 p->block_error.len = 1;
12342 p->cnr.len = 1;
12343
12344 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12345 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12346 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12347 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12348 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12349 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12350 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12351 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12352
12353 return &state->frontend;
12354
12355 error:
12356 kfree(demod_ext_attr);
12357 kfree(demod_comm_attr);
12358 kfree(demod_addr);
12359 kfree(demod);
12360 kfree(state);
12361
12362 return NULL;
12363 }
12364 EXPORT_SYMBOL(drx39xxj_attach);
12365
12366 static const struct dvb_frontend_ops drx39xxj_ops = {
12367 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12368 .info = {
12369 .name = "Micronas DRX39xxj family Frontend",
12370 .frequency_stepsize = 62500,
12371 .frequency_min = 51000000,
12372 .frequency_max = 858000000,
12373 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12374 },
12375
12376 .init = drx39xxj_init,
12377 .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12378 .sleep = drx39xxj_sleep,
12379 .set_frontend = drx39xxj_set_frontend,
12380 .get_tune_settings = drx39xxj_get_tune_settings,
12381 .read_status = drx39xxj_read_status,
12382 .read_ber = drx39xxj_read_ber,
12383 .read_signal_strength = drx39xxj_read_signal_strength,
12384 .read_snr = drx39xxj_read_snr,
12385 .read_ucblocks = drx39xxj_read_ucblocks,
12386 .release = drx39xxj_release,
12387 .set_lna = drx39xxj_set_lna,
12388 };
12389
12390 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12391 MODULE_AUTHOR("Devin Heitmueller");
12392 MODULE_LICENSE("GPL");
12393 MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);
Linux with added FPC-III support