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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / dvb-frontends / s5h1420.c
blobf9a18fe94d88c5324ddd321e30912dbfb59210c5
1 /*
2 * Driver for
3 * Samsung S5H1420 and
4 * PnpNetwork PN1010 QPSK Demodulator
5 *
6 * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
7 * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 *
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/jiffies.h>
32 #include <asm/div64.h>
33
34 #include <linux/i2c.h>
35
36
37 #include "dvb_frontend.h"
38 #include "s5h1420.h"
39 #include "s5h1420_priv.h"
40
41 #define TONE_FREQ 22000
42
43 struct s5h1420_state {
44 struct i2c_adapter* i2c;
45 const struct s5h1420_config* config;
46
47 struct dvb_frontend frontend;
48 struct i2c_adapter tuner_i2c_adapter;
49
50 u8 CON_1_val;
51
52 u8 postlocked:1;
53 u32 fclk;
54 u32 tunedfreq;
55 enum fe_code_rate fec_inner;
56 u32 symbol_rate;
57
58 /* FIXME: ugly workaround for flexcop's incapable i2c-controller
59 * it does not support repeated-start, workaround: write addr-1
60 * and then read
61 */
62 u8 shadow[256];
63 };
64
65 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
66 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
67 struct dvb_frontend_tune_settings* fesettings);
68
69
70 static int debug;
71 module_param(debug, int, 0644);
72 MODULE_PARM_DESC(debug, "enable debugging");
73
74 #define dprintk(x...) do { \
75 if (debug) \
76 printk(KERN_DEBUG "S5H1420: " x); \
77 } while (0)
78
79 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
80 {
81 int ret;
82 u8 b[2];
83 struct i2c_msg msg[] = {
84 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
85 { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
86 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
87 };
88
89 b[0] = (reg - 1) & 0xff;
90 b[1] = state->shadow[(reg - 1) & 0xff];
91
92 if (state->config->repeated_start_workaround) {
93 ret = i2c_transfer(state->i2c, msg, 3);
94 if (ret != 3)
95 return ret;
96 } else {
97 ret = i2c_transfer(state->i2c, &msg[1], 1);
98 if (ret != 1)
99 return ret;
100 ret = i2c_transfer(state->i2c, &msg[2], 1);
101 if (ret != 1)
102 return ret;
103 }
104
105 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
106
107 return b[0];
108 }
109
110 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
111 {
112 u8 buf[] = { reg, data };
113 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
114 int err;
115
116 /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
117 err = i2c_transfer(state->i2c, &msg, 1);
118 if (err != 1) {
119 dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
120 return -EREMOTEIO;
121 }
122 state->shadow[reg] = data;
123
124 return 0;
125 }
126
127 static int s5h1420_set_voltage(struct dvb_frontend *fe,
128 enum fe_sec_voltage voltage)
129 {
130 struct s5h1420_state* state = fe->demodulator_priv;
131
132 dprintk("enter %s\n", __func__);
133
134 switch(voltage) {
135 case SEC_VOLTAGE_13:
136 s5h1420_writereg(state, 0x3c,
137 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
138 break;
139
140 case SEC_VOLTAGE_18:
141 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
142 break;
143
144 case SEC_VOLTAGE_OFF:
145 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
146 break;
147 }
148
149 dprintk("leave %s\n", __func__);
150 return 0;
151 }
152
153 static int s5h1420_set_tone(struct dvb_frontend *fe,
154 enum fe_sec_tone_mode tone)
155 {
156 struct s5h1420_state* state = fe->demodulator_priv;
157
158 dprintk("enter %s\n", __func__);
159 switch(tone) {
160 case SEC_TONE_ON:
161 s5h1420_writereg(state, 0x3b,
162 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
163 break;
164
165 case SEC_TONE_OFF:
166 s5h1420_writereg(state, 0x3b,
167 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
168 break;
169 }
170 dprintk("leave %s\n", __func__);
171
172 return 0;
173 }
174
175 static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
176 struct dvb_diseqc_master_cmd* cmd)
177 {
178 struct s5h1420_state* state = fe->demodulator_priv;
179 u8 val;
180 int i;
181 unsigned long timeout;
182 int result = 0;
183
184 dprintk("enter %s\n", __func__);
185 if (cmd->msg_len > sizeof(cmd->msg))
186 return -EINVAL;
187
188 /* setup for DISEQC */
189 val = s5h1420_readreg(state, 0x3b);
190 s5h1420_writereg(state, 0x3b, 0x02);
191 msleep(15);
192
193 /* write the DISEQC command bytes */
194 for(i=0; i< cmd->msg_len; i++) {
195 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
196 }
197
198 /* kick off transmission */
199 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
200 ((cmd->msg_len-1) << 4) | 0x08);
201
202 /* wait for transmission to complete */
203 timeout = jiffies + ((100*HZ) / 1000);
204 while(time_before(jiffies, timeout)) {
205 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
206 break;
207
208 msleep(5);
209 }
210 if (time_after(jiffies, timeout))
211 result = -ETIMEDOUT;
212
213 /* restore original settings */
214 s5h1420_writereg(state, 0x3b, val);
215 msleep(15);
216 dprintk("leave %s\n", __func__);
217 return result;
218 }
219
220 static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
221 struct dvb_diseqc_slave_reply* reply)
222 {
223 struct s5h1420_state* state = fe->demodulator_priv;
224 u8 val;
225 int i;
226 int length;
227 unsigned long timeout;
228 int result = 0;
229
230 /* setup for DISEQC receive */
231 val = s5h1420_readreg(state, 0x3b);
232 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
233 msleep(15);
234
235 /* wait for reception to complete */
236 timeout = jiffies + ((reply->timeout*HZ) / 1000);
237 while(time_before(jiffies, timeout)) {
238 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
239 break;
240
241 msleep(5);
242 }
243 if (time_after(jiffies, timeout)) {
244 result = -ETIMEDOUT;
245 goto exit;
246 }
247
248 /* check error flag - FIXME: not sure what this does - docs do not describe
249 * beyond "error flag for diseqc receive data :( */
250 if (s5h1420_readreg(state, 0x49)) {
251 result = -EIO;
252 goto exit;
253 }
254
255 /* check length */
256 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
257 if (length > sizeof(reply->msg)) {
258 result = -EOVERFLOW;
259 goto exit;
260 }
261 reply->msg_len = length;
262
263 /* extract data */
264 for(i=0; i< length; i++) {
265 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
266 }
267
268 exit:
269 /* restore original settings */
270 s5h1420_writereg(state, 0x3b, val);
271 msleep(15);
272 return result;
273 }
274
275 static int s5h1420_send_burst(struct dvb_frontend *fe,
276 enum fe_sec_mini_cmd minicmd)
277 {
278 struct s5h1420_state* state = fe->demodulator_priv;
279 u8 val;
280 int result = 0;
281 unsigned long timeout;
282
283 /* setup for tone burst */
284 val = s5h1420_readreg(state, 0x3b);
285 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
286
287 /* set value for B position if requested */
288 if (minicmd == SEC_MINI_B) {
289 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
290 }
291 msleep(15);
292
293 /* start transmission */
294 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
295
296 /* wait for transmission to complete */
297 timeout = jiffies + ((100*HZ) / 1000);
298 while(time_before(jiffies, timeout)) {
299 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
300 break;
301
302 msleep(5);
303 }
304 if (time_after(jiffies, timeout))
305 result = -ETIMEDOUT;
306
307 /* restore original settings */
308 s5h1420_writereg(state, 0x3b, val);
309 msleep(15);
310 return result;
311 }
312
313 static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
314 {
315 u8 val;
316 enum fe_status status = 0;
317
318 val = s5h1420_readreg(state, 0x14);
319 if (val & 0x02)
320 status |= FE_HAS_SIGNAL;
321 if (val & 0x01)
322 status |= FE_HAS_CARRIER;
323 val = s5h1420_readreg(state, 0x36);
324 if (val & 0x01)
325 status |= FE_HAS_VITERBI;
326 if (val & 0x20)
327 status |= FE_HAS_SYNC;
328 if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
329 status |= FE_HAS_LOCK;
330
331 return status;
332 }
333
334 static int s5h1420_read_status(struct dvb_frontend *fe,
335 enum fe_status *status)
336 {
337 struct s5h1420_state* state = fe->demodulator_priv;
338 u8 val;
339
340 dprintk("enter %s\n", __func__);
341
342 if (status == NULL)
343 return -EINVAL;
344
345 /* determine lock state */
346 *status = s5h1420_get_status_bits(state);
347
348 /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
349 the inversion, wait a bit and check again */
350 if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
351 val = s5h1420_readreg(state, Vit10);
352 if ((val & 0x07) == 0x03) {
353 if (val & 0x08)
354 s5h1420_writereg(state, Vit09, 0x13);
355 else
356 s5h1420_writereg(state, Vit09, 0x1b);
357
358 /* wait a bit then update lock status */
359 mdelay(200);
360 *status = s5h1420_get_status_bits(state);
361 }
362 }
363
364 /* perform post lock setup */
365 if ((*status & FE_HAS_LOCK) && !state->postlocked) {
366
367 /* calculate the data rate */
368 u32 tmp = s5h1420_getsymbolrate(state);
369 switch (s5h1420_readreg(state, Vit10) & 0x07) {
370 case 0: tmp = (tmp * 2 * 1) / 2; break;
371 case 1: tmp = (tmp * 2 * 2) / 3; break;
372 case 2: tmp = (tmp * 2 * 3) / 4; break;
373 case 3: tmp = (tmp * 2 * 5) / 6; break;
374 case 4: tmp = (tmp * 2 * 6) / 7; break;
375 case 5: tmp = (tmp * 2 * 7) / 8; break;
376 }
377
378 if (tmp == 0) {
379 printk(KERN_ERR "s5h1420: avoided division by 0\n");
380 tmp = 1;
381 }
382 tmp = state->fclk / tmp;
383
384
385 /* set the MPEG_CLK_INTL for the calculated data rate */
386 if (tmp < 2)
387 val = 0x00;
388 else if (tmp < 5)
389 val = 0x01;
390 else if (tmp < 9)
391 val = 0x02;
392 else if (tmp < 13)
393 val = 0x03;
394 else if (tmp < 17)
395 val = 0x04;
396 else if (tmp < 25)
397 val = 0x05;
398 else if (tmp < 33)
399 val = 0x06;
400 else
401 val = 0x07;
402 dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
403
404 s5h1420_writereg(state, FEC01, 0x18);
405 s5h1420_writereg(state, FEC01, 0x10);
406 s5h1420_writereg(state, FEC01, val);
407
408 /* Enable "MPEG_Out" */
409 val = s5h1420_readreg(state, Mpeg02);
410 s5h1420_writereg(state, Mpeg02, val | (1 << 6));
411
412 /* kicker disable */
413 val = s5h1420_readreg(state, QPSK01) & 0x7f;
414 s5h1420_writereg(state, QPSK01, val);
415
416 /* DC freeze TODO it was never activated by default or it can stay activated */
417
418 if (s5h1420_getsymbolrate(state) >= 20000000) {
419 s5h1420_writereg(state, Loop04, 0x8a);
420 s5h1420_writereg(state, Loop05, 0x6a);
421 } else {
422 s5h1420_writereg(state, Loop04, 0x58);
423 s5h1420_writereg(state, Loop05, 0x27);
424 }
425
426 /* post-lock processing has been done! */
427 state->postlocked = 1;
428 }
429
430 dprintk("leave %s\n", __func__);
431
432 return 0;
433 }
434
435 static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
436 {
437 struct s5h1420_state* state = fe->demodulator_priv;
438
439 s5h1420_writereg(state, 0x46, 0x1d);
440 mdelay(25);
441
442 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
443
444 return 0;
445 }
446
447 static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
448 {
449 struct s5h1420_state* state = fe->demodulator_priv;
450
451 u8 val = s5h1420_readreg(state, 0x15);
452
453 *strength = (u16) ((val << 8) | val);
454
455 return 0;
456 }
457
458 static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
459 {
460 struct s5h1420_state* state = fe->demodulator_priv;
461
462 s5h1420_writereg(state, 0x46, 0x1f);
463 mdelay(25);
464
465 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
466
467 return 0;
468 }
469
470 static void s5h1420_reset(struct s5h1420_state* state)
471 {
472 dprintk("%s\n", __func__);
473 s5h1420_writereg (state, 0x01, 0x08);
474 s5h1420_writereg (state, 0x01, 0x00);
475 udelay(10);
476 }
477
478 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
479 struct dtv_frontend_properties *p)
480 {
481 u8 v;
482 u64 val;
483
484 dprintk("enter %s\n", __func__);
485
486 val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
487 if (p->symbol_rate < 29000000)
488 val *= 2;
489 do_div(val, (state->fclk / 1000));
490
491 dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
492
493 v = s5h1420_readreg(state, Loop01);
494 s5h1420_writereg(state, Loop01, v & 0x7f);
495 s5h1420_writereg(state, Tnco01, val >> 16);
496 s5h1420_writereg(state, Tnco02, val >> 8);
497 s5h1420_writereg(state, Tnco03, val & 0xff);
498 s5h1420_writereg(state, Loop01, v | 0x80);
499 dprintk("leave %s\n", __func__);
500 }
501
502 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
503 {
504 return state->symbol_rate;
505 }
506
507 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
508 {
509 int val;
510 u8 v;
511
512 dprintk("enter %s\n", __func__);
513
514 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
515 * divide fclk by 1000000 to get the correct value. */
516 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
517
518 dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
519
520 v = s5h1420_readreg(state, Loop01);
521 s5h1420_writereg(state, Loop01, v & 0xbf);
522 s5h1420_writereg(state, Pnco01, val >> 16);
523 s5h1420_writereg(state, Pnco02, val >> 8);
524 s5h1420_writereg(state, Pnco03, val & 0xff);
525 s5h1420_writereg(state, Loop01, v | 0x40);
526 dprintk("leave %s\n", __func__);
527 }
528
529 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
530 {
531 int val;
532
533 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
534 val = s5h1420_readreg(state, 0x0e) << 16;
535 val |= s5h1420_readreg(state, 0x0f) << 8;
536 val |= s5h1420_readreg(state, 0x10);
537 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
538
539 if (val & 0x800000)
540 val |= 0xff000000;
541
542 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
543 * divide fclk by 1000000 to get the correct value. */
544 val = (((-val) * (state->fclk/1000000)) / (1<<24));
545
546 return val;
547 }
548
549 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
550 struct dtv_frontend_properties *p)
551 {
552 u8 inversion = 0;
553 u8 vit08, vit09;
554
555 dprintk("enter %s\n", __func__);
556
557 if (p->inversion == INVERSION_OFF)
558 inversion = state->config->invert ? 0x08 : 0;
559 else if (p->inversion == INVERSION_ON)
560 inversion = state->config->invert ? 0 : 0x08;
561
562 if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
563 vit08 = 0x3f;
564 vit09 = 0;
565 } else {
566 switch (p->fec_inner) {
567 case FEC_1_2:
568 vit08 = 0x01;
569 vit09 = 0x10;
570 break;
571
572 case FEC_2_3:
573 vit08 = 0x02;
574 vit09 = 0x11;
575 break;
576
577 case FEC_3_4:
578 vit08 = 0x04;
579 vit09 = 0x12;
580 break;
581
582 case FEC_5_6:
583 vit08 = 0x08;
584 vit09 = 0x13;
585 break;
586
587 case FEC_6_7:
588 vit08 = 0x10;
589 vit09 = 0x14;
590 break;
591
592 case FEC_7_8:
593 vit08 = 0x20;
594 vit09 = 0x15;
595 break;
596
597 default:
598 return;
599 }
600 }
601 vit09 |= inversion;
602 dprintk("fec: %02x %02x\n", vit08, vit09);
603 s5h1420_writereg(state, Vit08, vit08);
604 s5h1420_writereg(state, Vit09, vit09);
605 dprintk("leave %s\n", __func__);
606 }
607
608 static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
609 {
610 switch(s5h1420_readreg(state, 0x32) & 0x07) {
611 case 0:
612 return FEC_1_2;
613
614 case 1:
615 return FEC_2_3;
616
617 case 2:
618 return FEC_3_4;
619
620 case 3:
621 return FEC_5_6;
622
623 case 4:
624 return FEC_6_7;
625
626 case 5:
627 return FEC_7_8;
628 }
629
630 return FEC_NONE;
631 }
632
633 static enum fe_spectral_inversion
634 s5h1420_getinversion(struct s5h1420_state *state)
635 {
636 if (s5h1420_readreg(state, 0x32) & 0x08)
637 return INVERSION_ON;
638
639 return INVERSION_OFF;
640 }
641
642 static int s5h1420_set_frontend(struct dvb_frontend *fe)
643 {
644 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
645 struct s5h1420_state* state = fe->demodulator_priv;
646 int frequency_delta;
647 struct dvb_frontend_tune_settings fesettings;
648
649 dprintk("enter %s\n", __func__);
650
651 /* check if we should do a fast-tune */
652 s5h1420_get_tune_settings(fe, &fesettings);
653 frequency_delta = p->frequency - state->tunedfreq;
654 if ((frequency_delta > -fesettings.max_drift) &&
655 (frequency_delta < fesettings.max_drift) &&
656 (frequency_delta != 0) &&
657 (state->fec_inner == p->fec_inner) &&
658 (state->symbol_rate == p->symbol_rate)) {
659
660 if (fe->ops.tuner_ops.set_params) {
661 fe->ops.tuner_ops.set_params(fe);
662 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
663 }
664 if (fe->ops.tuner_ops.get_frequency) {
665 u32 tmp;
666 fe->ops.tuner_ops.get_frequency(fe, &tmp);
667 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
668 s5h1420_setfreqoffset(state, p->frequency - tmp);
669 } else {
670 s5h1420_setfreqoffset(state, 0);
671 }
672 dprintk("simple tune\n");
673 return 0;
674 }
675 dprintk("tuning demod\n");
676
677 /* first of all, software reset */
678 s5h1420_reset(state);
679
680 /* set s5h1420 fclk PLL according to desired symbol rate */
681 if (p->symbol_rate > 33000000)
682 state->fclk = 80000000;
683 else if (p->symbol_rate > 28500000)
684 state->fclk = 59000000;
685 else if (p->symbol_rate > 25000000)
686 state->fclk = 86000000;
687 else if (p->symbol_rate > 1900000)
688 state->fclk = 88000000;
689 else
690 state->fclk = 44000000;
691
692 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
693 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
694 s5h1420_writereg(state, PLL02, 0x40);
695 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
696
697 /* TODO DC offset removal, config parameter ? */
698 if (p->symbol_rate > 29000000)
699 s5h1420_writereg(state, QPSK01, 0xae | 0x10);
700 else
701 s5h1420_writereg(state, QPSK01, 0xac | 0x10);
702
703 /* set misc registers */
704 s5h1420_writereg(state, CON_1, 0x00);
705 s5h1420_writereg(state, QPSK02, 0x00);
706 s5h1420_writereg(state, Pre01, 0xb0);
707
708 s5h1420_writereg(state, Loop01, 0xF0);
709 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
710 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
711 if (p->symbol_rate > 20000000)
712 s5h1420_writereg(state, Loop04, 0x79);
713 else
714 s5h1420_writereg(state, Loop04, 0x58);
715 s5h1420_writereg(state, Loop05, 0x6b);
716
717 if (p->symbol_rate >= 8000000)
718 s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
719 else if (p->symbol_rate >= 4000000)
720 s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
721 else
722 s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
723
724 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
725
726 s5h1420_writereg(state, Sync01, 0x33);
727 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
728 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
729 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
730
731 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
732 s5h1420_writereg(state, DiS03, 0x00);
733 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
734
735 /* set tuner PLL */
736 if (fe->ops.tuner_ops.set_params) {
737 fe->ops.tuner_ops.set_params(fe);
738 if (fe->ops.i2c_gate_ctrl)
739 fe->ops.i2c_gate_ctrl(fe, 0);
740 s5h1420_setfreqoffset(state, 0);
741 }
742
743 /* set the reset of the parameters */
744 s5h1420_setsymbolrate(state, p);
745 s5h1420_setfec_inversion(state, p);
746
747 /* start QPSK */
748 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
749
750 state->fec_inner = p->fec_inner;
751 state->symbol_rate = p->symbol_rate;
752 state->postlocked = 0;
753 state->tunedfreq = p->frequency;
754
755 dprintk("leave %s\n", __func__);
756 return 0;
757 }
758
759 static int s5h1420_get_frontend(struct dvb_frontend* fe,
760 struct dtv_frontend_properties *p)
761 {
762 struct s5h1420_state* state = fe->demodulator_priv;
763
764 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
765 p->inversion = s5h1420_getinversion(state);
766 p->symbol_rate = s5h1420_getsymbolrate(state);
767 p->fec_inner = s5h1420_getfec(state);
768
769 return 0;
770 }
771
772 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
773 struct dvb_frontend_tune_settings* fesettings)
774 {
775 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
776 if (p->symbol_rate > 20000000) {
777 fesettings->min_delay_ms = 50;
778 fesettings->step_size = 2000;
779 fesettings->max_drift = 8000;
780 } else if (p->symbol_rate > 12000000) {
781 fesettings->min_delay_ms = 100;
782 fesettings->step_size = 1500;
783 fesettings->max_drift = 9000;
784 } else if (p->symbol_rate > 8000000) {
785 fesettings->min_delay_ms = 100;
786 fesettings->step_size = 1000;
787 fesettings->max_drift = 8000;
788 } else if (p->symbol_rate > 4000000) {
789 fesettings->min_delay_ms = 100;
790 fesettings->step_size = 500;
791 fesettings->max_drift = 7000;
792 } else if (p->symbol_rate > 2000000) {
793 fesettings->min_delay_ms = 200;
794 fesettings->step_size = (p->symbol_rate / 8000);
795 fesettings->max_drift = 14 * fesettings->step_size;
796 } else {
797 fesettings->min_delay_ms = 200;
798 fesettings->step_size = (p->symbol_rate / 8000);
799 fesettings->max_drift = 18 * fesettings->step_size;
800 }
801
802 return 0;
803 }
804
805 static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
806 {
807 struct s5h1420_state* state = fe->demodulator_priv;
808
809 if (enable)
810 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
811 else
812 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
813 }
814
815 static int s5h1420_init (struct dvb_frontend* fe)
816 {
817 struct s5h1420_state* state = fe->demodulator_priv;
818
819 /* disable power down and do reset */
820 state->CON_1_val = state->config->serial_mpeg << 4;
821 s5h1420_writereg(state, 0x02, state->CON_1_val);
822 msleep(10);
823 s5h1420_reset(state);
824
825 return 0;
826 }
827
828 static int s5h1420_sleep(struct dvb_frontend* fe)
829 {
830 struct s5h1420_state* state = fe->demodulator_priv;
831 state->CON_1_val = 0x12;
832 return s5h1420_writereg(state, 0x02, state->CON_1_val);
833 }
834
835 static void s5h1420_release(struct dvb_frontend* fe)
836 {
837 struct s5h1420_state* state = fe->demodulator_priv;
838 i2c_del_adapter(&state->tuner_i2c_adapter);
839 kfree(state);
840 }
841
842 static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
843 {
844 return I2C_FUNC_I2C;
845 }
846
847 static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
848 {
849 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
850 struct i2c_msg m[3];
851 u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
852
853 if (1 + num > ARRAY_SIZE(m)) {
854 printk(KERN_WARNING
855 "%s: i2c xfer: num=%d is too big!\n",
856 KBUILD_MODNAME, num);
857 return -EOPNOTSUPP;
858 }
859
860 memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
861
862 m[0].addr = state->config->demod_address;
863 m[0].buf = tx_open;
864 m[0].len = 2;
865
866 memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
867
868 return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
869 }
870
871 static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
872 .master_xfer = s5h1420_tuner_i2c_tuner_xfer,
873 .functionality = s5h1420_tuner_i2c_func,
874 };
875
876 struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
877 {
878 struct s5h1420_state *state = fe->demodulator_priv;
879 return &state->tuner_i2c_adapter;
880 }
881 EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
882
883 static const struct dvb_frontend_ops s5h1420_ops;
884
885 struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
886 struct i2c_adapter *i2c)
887 {
888 /* allocate memory for the internal state */
889 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
890 u8 i;
891
892 if (state == NULL)
893 goto error;
894
895 /* setup the state */
896 state->config = config;
897 state->i2c = i2c;
898 state->postlocked = 0;
899 state->fclk = 88000000;
900 state->tunedfreq = 0;
901 state->fec_inner = FEC_NONE;
902 state->symbol_rate = 0;
903
904 /* check if the demod is there + identify it */
905 i = s5h1420_readreg(state, ID01);
906 if (i != 0x03)
907 goto error;
908
909 memset(state->shadow, 0xff, sizeof(state->shadow));
910
911 for (i = 0; i < 0x50; i++)
912 state->shadow[i] = s5h1420_readreg(state, i);
913
914 /* create dvb_frontend */
915 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
916 state->frontend.demodulator_priv = state;
917
918 /* create tuner i2c adapter */
919 strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
920 sizeof(state->tuner_i2c_adapter.name));
921 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
922 state->tuner_i2c_adapter.algo_data = NULL;
923 i2c_set_adapdata(&state->tuner_i2c_adapter, state);
924 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
925 printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
926 goto error;
927 }
928
929 return &state->frontend;
930
931 error:
932 kfree(state);
933 return NULL;
934 }
935 EXPORT_SYMBOL(s5h1420_attach);
936
937 static const struct dvb_frontend_ops s5h1420_ops = {
938 .delsys = { SYS_DVBS },
939 .info = {
940 .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
941 .frequency_min = 950000,
942 .frequency_max = 2150000,
943 .frequency_stepsize = 125, /* kHz for QPSK frontends */
944 .frequency_tolerance = 29500,
945 .symbol_rate_min = 1000000,
946 .symbol_rate_max = 45000000,
947 /* .symbol_rate_tolerance = ???,*/
948 .caps = FE_CAN_INVERSION_AUTO |
949 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
950 FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
951 FE_CAN_QPSK
952 },
953
954 .release = s5h1420_release,
955
956 .init = s5h1420_init,
957 .sleep = s5h1420_sleep,
958 .i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
959
960 .set_frontend = s5h1420_set_frontend,
961 .get_frontend = s5h1420_get_frontend,
962 .get_tune_settings = s5h1420_get_tune_settings,
963
964 .read_status = s5h1420_read_status,
965 .read_ber = s5h1420_read_ber,
966 .read_signal_strength = s5h1420_read_signal_strength,
967 .read_ucblocks = s5h1420_read_ucblocks,
968
969 .diseqc_send_master_cmd = s5h1420_send_master_cmd,
970 .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
971 .diseqc_send_burst = s5h1420_send_burst,
972 .set_tone = s5h1420_set_tone,
973 .set_voltage = s5h1420_set_voltage,
974 };
975
976 MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
977 MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
978 MODULE_LICENSE("GPL");
Linux with added FPC-III support