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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / dvb-frontends / stb0899_algo.c
blob3012f196e9bd91dd2fa60bdab2866cf784e441e7
1 /*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/bitops.h>
23 #include "stb0899_drv.h"
24 #include "stb0899_priv.h"
25 #include "stb0899_reg.h"
26
27 static inline u32 stb0899_do_div(u64 n, u32 d)
28 {
29 /* wrap do_div() for ease of use */
30
31 do_div(n, d);
32 return n;
33 }
34
35 #if 0
36 /* These functions are currently unused */
37 /*
38 * stb0899_calc_srate
39 * Compute symbol rate
40 */
41 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
42 {
43 u64 tmp;
44
45 /* srate = (SFR * master_clk) >> 20 */
46
47 /* sfr is of size 20 bit, stored with an offset of 4 bit */
48 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
49 tmp &= ~0xf;
50 tmp *= master_clk;
51 tmp >>= 24;
52
53 return tmp;
54 }
55
56 /*
57 * stb0899_get_srate
58 * Get the current symbol rate
59 */
60 static u32 stb0899_get_srate(struct stb0899_state *state)
61 {
62 struct stb0899_internal *internal = &state->internal;
63 u8 sfr[3];
64
65 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
66
67 return stb0899_calc_srate(internal->master_clk, sfr);
68 }
69 #endif
70
71 /*
72 * stb0899_set_srate
73 * Set symbol frequency
74 * MasterClock: master clock frequency (hz)
75 * SymbolRate: symbol rate (bauds)
76 * return symbol frequency
77 */
78 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
79 {
80 u32 tmp;
81 u8 sfr[3];
82
83 dprintk(state->verbose, FE_DEBUG, 1, "-->");
84 /*
85 * in order to have the maximum precision, the symbol rate entered into
86 * the chip is computed as the closest value of the "true value".
87 * In this purpose, the symbol rate value is rounded (1 is added on the bit
88 * below the LSB )
89 *
90 * srate = (SFR * master_clk) >> 20
91 * <=>
92 * SFR = srate << 20 / master_clk
93 *
94 * rounded:
95 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
96 *
97 * stored as 20 bit number with an offset of 4 bit:
98 * sfr = SFR << 4;
99 */
100
101 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
102 tmp <<= 4;
103
104 sfr[0] = tmp >> 16;
105 sfr[1] = tmp >> 8;
106 sfr[2] = tmp;
107
108 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
109
110 return srate;
111 }
112
113 /*
114 * stb0899_calc_derot_time
115 * Compute the amount of time needed by the derotator to lock
116 * SymbolRate: Symbol rate
117 * return: derotator time constant (ms)
118 */
119 static long stb0899_calc_derot_time(long srate)
120 {
121 if (srate > 0)
122 return (100000 / (srate / 1000));
123 else
124 return 0;
125 }
126
127 /*
128 * stb0899_carr_width
129 * Compute the width of the carrier
130 * return: width of carrier (kHz or Mhz)
131 */
132 long stb0899_carr_width(struct stb0899_state *state)
133 {
134 struct stb0899_internal *internal = &state->internal;
135
136 return (internal->srate + (internal->srate * internal->rolloff) / 100);
137 }
138
139 /*
140 * stb0899_first_subrange
141 * Compute the first subrange of the search
142 */
143 static void stb0899_first_subrange(struct stb0899_state *state)
144 {
145 struct stb0899_internal *internal = &state->internal;
146 struct stb0899_params *params = &state->params;
147 struct stb0899_config *config = state->config;
148
149 int range = 0;
150 u32 bandwidth = 0;
151
152 if (config->tuner_get_bandwidth) {
153 stb0899_i2c_gate_ctrl(&state->frontend, 1);
154 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
155 stb0899_i2c_gate_ctrl(&state->frontend, 0);
156 range = bandwidth - stb0899_carr_width(state) / 2;
157 }
158
159 if (range > 0)
160 internal->sub_range = min(internal->srch_range, range);
161 else
162 internal->sub_range = 0;
163
164 internal->freq = params->freq;
165 internal->tuner_offst = 0L;
166 internal->sub_dir = 1;
167 }
168
169 /*
170 * stb0899_check_tmg
171 * check for timing lock
172 * internal.Ttiming: time to wait for loop lock
173 */
174 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
175 {
176 struct stb0899_internal *internal = &state->internal;
177 int lock;
178 u8 reg;
179 s8 timing;
180
181 msleep(internal->t_derot);
182
183 stb0899_write_reg(state, STB0899_RTF, 0xf2);
184 reg = stb0899_read_reg(state, STB0899_TLIR);
185 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
186 timing = stb0899_read_reg(state, STB0899_RTF);
187
188 if (lock >= 42) {
189 if ((lock > 48) && (abs(timing) >= 110)) {
190 internal->status = ANALOGCARRIER;
191 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
192 } else {
193 internal->status = TIMINGOK;
194 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
195 }
196 } else {
197 internal->status = NOTIMING;
198 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
199 }
200 return internal->status;
201 }
202
203 /*
204 * stb0899_search_tmg
205 * perform a fs/2 zig-zag to find timing
206 */
207 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
208 {
209 struct stb0899_internal *internal = &state->internal;
210 struct stb0899_params *params = &state->params;
211
212 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
213 int index = 0;
214 u8 cfr[2];
215
216 internal->status = NOTIMING;
217
218 /* timing loop computation & symbol rate optimisation */
219 derot_limit = (internal->sub_range / 2L) / internal->mclk;
220 derot_step = (params->srate / 2L) / internal->mclk;
221
222 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
223 index++;
224 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
225
226 if (abs(derot_freq) > derot_limit)
227 next_loop--;
228
229 if (next_loop) {
230 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
231 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
232 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
233 }
234 internal->direction = -internal->direction; /* Change zigzag direction */
235 }
236
237 if (internal->status == TIMINGOK) {
238 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
239 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
240 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
241 }
242
243 return internal->status;
244 }
245
246 /*
247 * stb0899_check_carrier
248 * Check for carrier found
249 */
250 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
251 {
252 struct stb0899_internal *internal = &state->internal;
253 u8 reg;
254
255 msleep(internal->t_derot); /* wait for derotator ok */
256
257 reg = stb0899_read_reg(state, STB0899_CFD);
258 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
259 stb0899_write_reg(state, STB0899_CFD, reg);
260
261 reg = stb0899_read_reg(state, STB0899_DSTATUS);
262 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
263 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
264 internal->status = CARRIEROK;
265 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
266 } else {
267 internal->status = NOCARRIER;
268 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
269 }
270
271 return internal->status;
272 }
273
274 /*
275 * stb0899_search_carrier
276 * Search for a QPSK carrier with the derotator
277 */
278 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
279 {
280 struct stb0899_internal *internal = &state->internal;
281
282 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
283 int index = 0;
284 u8 cfr[2];
285 u8 reg;
286
287 internal->status = NOCARRIER;
288 derot_limit = (internal->sub_range / 2L) / internal->mclk;
289 derot_freq = internal->derot_freq;
290
291 reg = stb0899_read_reg(state, STB0899_CFD);
292 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
293 stb0899_write_reg(state, STB0899_CFD, reg);
294
295 do {
296 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
297 if (stb0899_check_carrier(state) == NOCARRIER) {
298 index++;
299 last_derot_freq = derot_freq;
300 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
301
302 if(abs(derot_freq) > derot_limit)
303 next_loop--;
304
305 if (next_loop) {
306 reg = stb0899_read_reg(state, STB0899_CFD);
307 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
308 stb0899_write_reg(state, STB0899_CFD, reg);
309
310 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
311 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
312 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
313 }
314 }
315
316 internal->direction = -internal->direction; /* Change zigzag direction */
317 } while ((internal->status != CARRIEROK) && next_loop);
318
319 if (internal->status == CARRIEROK) {
320 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
321 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
322 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
323 } else {
324 internal->derot_freq = last_derot_freq;
325 }
326
327 return internal->status;
328 }
329
330 /*
331 * stb0899_check_data
332 * Check for data found
333 */
334 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
335 {
336 struct stb0899_internal *internal = &state->internal;
337 struct stb0899_params *params = &state->params;
338
339 int lock = 0, index = 0, dataTime = 500, loop;
340 u8 reg;
341
342 internal->status = NODATA;
343
344 /* RESET FEC */
345 reg = stb0899_read_reg(state, STB0899_TSTRES);
346 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
347 stb0899_write_reg(state, STB0899_TSTRES, reg);
348 msleep(1);
349 reg = stb0899_read_reg(state, STB0899_TSTRES);
350 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
351 stb0899_write_reg(state, STB0899_TSTRES, reg);
352
353 if (params->srate <= 2000000)
354 dataTime = 2000;
355 else if (params->srate <= 5000000)
356 dataTime = 1500;
357 else if (params->srate <= 15000000)
358 dataTime = 1000;
359 else
360 dataTime = 500;
361
362 /* clear previous failed END_LOOPVIT */
363 stb0899_read_reg(state, STB0899_VSTATUS);
364
365 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
366 while (1) {
367 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
368 reg = stb0899_read_reg(state, STB0899_VSTATUS);
369 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
370 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
371
372 if (lock || loop || (index > dataTime))
373 break;
374 index++;
375 }
376
377 if (lock) { /* DATA LOCK indicator */
378 internal->status = DATAOK;
379 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
380 }
381
382 return internal->status;
383 }
384
385 /*
386 * stb0899_search_data
387 * Search for a QPSK carrier with the derotator
388 */
389 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
390 {
391 short int derot_freq, derot_step, derot_limit, next_loop = 3;
392 u8 cfr[2];
393 u8 reg;
394 int index = 1;
395
396 struct stb0899_internal *internal = &state->internal;
397 struct stb0899_params *params = &state->params;
398
399 derot_step = (params->srate / 4L) / internal->mclk;
400 derot_limit = (internal->sub_range / 2L) / internal->mclk;
401 derot_freq = internal->derot_freq;
402
403 do {
404 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
405
406 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
407 if (abs(derot_freq) > derot_limit)
408 next_loop--;
409
410 if (next_loop) {
411 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
412 reg = stb0899_read_reg(state, STB0899_CFD);
413 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
414 stb0899_write_reg(state, STB0899_CFD, reg);
415
416 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
417 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
418 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
419
420 stb0899_check_carrier(state);
421 index++;
422 }
423 }
424 internal->direction = -internal->direction; /* change zig zag direction */
425 } while ((internal->status != DATAOK) && next_loop);
426
427 if (internal->status == DATAOK) {
428 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
429
430 /* store autodetected IQ swapping as default for DVB-S2 tuning */
431 reg = stb0899_read_reg(state, STB0899_IQSWAP);
432 if (STB0899_GETFIELD(SYM, reg))
433 internal->inversion = IQ_SWAP_ON;
434 else
435 internal->inversion = IQ_SWAP_OFF;
436
437 internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
438 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
439 }
440
441 return internal->status;
442 }
443
444 /*
445 * stb0899_check_range
446 * check if the found frequency is in the correct range
447 */
448 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
449 {
450 struct stb0899_internal *internal = &state->internal;
451 struct stb0899_params *params = &state->params;
452
453 int range_offst, tp_freq;
454
455 range_offst = internal->srch_range / 2000;
456 tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
457
458 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
459 internal->status = RANGEOK;
460 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
461 } else {
462 internal->status = OUTOFRANGE;
463 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
464 }
465
466 return internal->status;
467 }
468
469 /*
470 * NextSubRange
471 * Compute the next subrange of the search
472 */
473 static void next_sub_range(struct stb0899_state *state)
474 {
475 struct stb0899_internal *internal = &state->internal;
476 struct stb0899_params *params = &state->params;
477
478 long old_sub_range;
479
480 if (internal->sub_dir > 0) {
481 old_sub_range = internal->sub_range;
482 internal->sub_range = min((internal->srch_range / 2) -
483 (internal->tuner_offst + internal->sub_range / 2),
484 internal->sub_range);
485
486 if (internal->sub_range < 0)
487 internal->sub_range = 0;
488
489 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
490 }
491
492 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
493 internal->sub_dir = -internal->sub_dir;
494 }
495
496 /*
497 * stb0899_dvbs_algo
498 * Search for a signal, timing, carrier and data for a
499 * given frequency in a given range
500 */
501 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
502 {
503 struct stb0899_params *params = &state->params;
504 struct stb0899_internal *internal = &state->internal;
505 struct stb0899_config *config = state->config;
506
507 u8 bclc, reg;
508 u8 cfr[2];
509 u8 eq_const[10];
510 s32 clnI = 3;
511 u32 bandwidth = 0;
512
513 /* BETA values rated @ 99MHz */
514 s32 betaTab[5][4] = {
515 /* 5 10 20 30MBps */
516 { 37, 34, 32, 31 }, /* QPSK 1/2 */
517 { 37, 35, 33, 31 }, /* QPSK 2/3 */
518 { 37, 35, 33, 31 }, /* QPSK 3/4 */
519 { 37, 36, 33, 32 }, /* QPSK 5/6 */
520 { 37, 36, 33, 32 } /* QPSK 7/8 */
521 };
522
523 internal->direction = 1;
524
525 stb0899_set_srate(state, internal->master_clk, params->srate);
526 /* Carrier loop optimization versus symbol rate for acquisition*/
527 if (params->srate <= 5000000) {
528 stb0899_write_reg(state, STB0899_ACLC, 0x89);
529 bclc = stb0899_read_reg(state, STB0899_BCLC);
530 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
531 stb0899_write_reg(state, STB0899_BCLC, bclc);
532 clnI = 0;
533 } else if (params->srate <= 15000000) {
534 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
535 bclc = stb0899_read_reg(state, STB0899_BCLC);
536 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
537 stb0899_write_reg(state, STB0899_BCLC, bclc);
538 clnI = 1;
539 } else if(params->srate <= 25000000) {
540 stb0899_write_reg(state, STB0899_ACLC, 0x89);
541 bclc = stb0899_read_reg(state, STB0899_BCLC);
542 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
543 stb0899_write_reg(state, STB0899_BCLC, bclc);
544 clnI = 2;
545 } else {
546 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
547 bclc = stb0899_read_reg(state, STB0899_BCLC);
548 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
549 stb0899_write_reg(state, STB0899_BCLC, bclc);
550 clnI = 3;
551 }
552
553 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
554 /* Set the timing loop to acquisition */
555 stb0899_write_reg(state, STB0899_RTC, 0x46);
556 stb0899_write_reg(state, STB0899_CFD, 0xee);
557
558 /* !! WARNING !!
559 * Do not read any status variables while acquisition,
560 * If any needed, read before the acquisition starts
561 * querying status while acquiring causes the
562 * acquisition to go bad and hence no locks.
563 */
564 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
565 internal->derot_percent, params->srate, internal->mclk);
566
567 /* Initial calculations */
568 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
569 internal->t_derot = stb0899_calc_derot_time(params->srate);
570 internal->t_data = 500;
571
572 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
573 /* RESET Stream merger */
574 reg = stb0899_read_reg(state, STB0899_TSTRES);
575 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
576 stb0899_write_reg(state, STB0899_TSTRES, reg);
577
578 /*
579 * Set KDIVIDER to an intermediate value between
580 * 1/2 and 7/8 for acquisition
581 */
582 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
583 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
584 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
585
586 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
587 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
588
589 stb0899_first_subrange(state);
590 do {
591 /* Initialisations */
592 cfr[0] = cfr[1] = 0;
593 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
594
595 stb0899_write_reg(state, STB0899_RTF, 0);
596 reg = stb0899_read_reg(state, STB0899_CFD);
597 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
598 stb0899_write_reg(state, STB0899_CFD, reg);
599
600 internal->derot_freq = 0;
601 internal->status = NOAGC1;
602
603 /* enable tuner I/O */
604 stb0899_i2c_gate_ctrl(&state->frontend, 1);
605
606 /* Move tuner to frequency */
607 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
608 if (state->config->tuner_set_frequency)
609 state->config->tuner_set_frequency(&state->frontend, internal->freq);
610
611 if (state->config->tuner_get_frequency)
612 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
613
614 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
615 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
616 internal->status = AGC1OK;
617
618 /* There is signal in the band */
619 if (config->tuner_get_bandwidth)
620 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
621
622 /* disable tuner I/O */
623 stb0899_i2c_gate_ctrl(&state->frontend, 0);
624
625 if (params->srate <= bandwidth / 2)
626 stb0899_search_tmg(state); /* For low rates (SCPC) */
627 else
628 stb0899_check_tmg(state); /* For high rates (MCPC) */
629
630 if (internal->status == TIMINGOK) {
631 dprintk(state->verbose, FE_DEBUG, 1,
632 "TIMING OK ! Derot freq=%d, mclk=%d",
633 internal->derot_freq, internal->mclk);
634
635 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
636 dprintk(state->verbose, FE_DEBUG, 1,
637 "CARRIER OK ! Derot freq=%d, mclk=%d",
638 internal->derot_freq, internal->mclk);
639
640 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
641 dprintk(state->verbose, FE_DEBUG, 1,
642 "DATA OK ! Derot freq=%d, mclk=%d",
643 internal->derot_freq, internal->mclk);
644
645 if (stb0899_check_range(state) == RANGEOK) {
646 dprintk(state->verbose, FE_DEBUG, 1,
647 "RANGE OK ! derot freq=%d, mclk=%d",
648 internal->derot_freq, internal->mclk);
649
650 internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
651 reg = stb0899_read_reg(state, STB0899_PLPARM);
652 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
653 dprintk(state->verbose, FE_DEBUG, 1,
654 "freq=%d, internal resultant freq=%d",
655 params->freq, internal->freq);
656
657 dprintk(state->verbose, FE_DEBUG, 1,
658 "internal puncture rate=%d",
659 internal->fecrate);
660 }
661 }
662 }
663 }
664 if (internal->status != RANGEOK)
665 next_sub_range(state);
666
667 } while (internal->sub_range && internal->status != RANGEOK);
668
669 /* Set the timing loop to tracking */
670 stb0899_write_reg(state, STB0899_RTC, 0x33);
671 stb0899_write_reg(state, STB0899_CFD, 0xf7);
672 /* if locked and range ok, set Kdiv */
673 if (internal->status == RANGEOK) {
674 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
675 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
676 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
677
678 /*
679 * Carrier loop optimization versus
680 * symbol Rate/Puncture Rate for Tracking
681 */
682 reg = stb0899_read_reg(state, STB0899_BCLC);
683 switch (internal->fecrate) {
684 case STB0899_FEC_1_2: /* 13 */
685 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
686 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
687 stb0899_write_reg(state, STB0899_BCLC, reg);
688 break;
689 case STB0899_FEC_2_3: /* 18 */
690 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
691 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
692 stb0899_write_reg(state, STB0899_BCLC, reg);
693 break;
694 case STB0899_FEC_3_4: /* 21 */
695 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
696 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
697 stb0899_write_reg(state, STB0899_BCLC, reg);
698 break;
699 case STB0899_FEC_5_6: /* 24 */
700 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
701 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
702 stb0899_write_reg(state, STB0899_BCLC, reg);
703 break;
704 case STB0899_FEC_6_7: /* 25 */
705 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
706 stb0899_write_reg(state, STB0899_ACLC, 0x88);
707 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
708 break;
709 case STB0899_FEC_7_8: /* 26 */
710 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
711 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
712 stb0899_write_reg(state, STB0899_BCLC, reg);
713 break;
714 default:
715 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
716 break;
717 }
718 /* release stream merger RESET */
719 reg = stb0899_read_reg(state, STB0899_TSTRES);
720 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
721 stb0899_write_reg(state, STB0899_TSTRES, reg);
722
723 /* disable carrier detector */
724 reg = stb0899_read_reg(state, STB0899_CFD);
725 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
726 stb0899_write_reg(state, STB0899_CFD, reg);
727
728 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
729 }
730
731 return internal->status;
732 }
733
734 /*
735 * stb0899_dvbs2_config_uwp
736 * Configure UWP state machine
737 */
738 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
739 {
740 struct stb0899_internal *internal = &state->internal;
741 struct stb0899_config *config = state->config;
742 u32 uwp1, uwp2, uwp3, reg;
743
744 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
745 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
746 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
747
748 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
749 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
750 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
751
752 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
753 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
754 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
755
756 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
757 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
758
759 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
760 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
761 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
762
763 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
764 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
765 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
766 }
767
768 /*
769 * stb0899_dvbs2_config_csm_auto
770 * Set CSM to AUTO mode
771 */
772 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
773 {
774 u32 reg;
775
776 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
777 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
778 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
779 }
780
781 static long Log2Int(int number)
782 {
783 int i;
784
785 i = 0;
786 while ((1 << i) <= abs(number))
787 i++;
788
789 if (number == 0)
790 i = 1;
791
792 return i - 1;
793 }
794
795 /*
796 * stb0899_dvbs2_calc_srate
797 * compute BTR_NOM_FREQ for the symbol rate
798 */
799 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
800 {
801 struct stb0899_internal *internal = &state->internal;
802 struct stb0899_config *config = state->config;
803
804 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
805 u32 master_clk, srate;
806
807 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
808 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
809 dec_rate = Log2Int(dec_ratio);
810 decim = 1 << dec_rate;
811 master_clk = internal->master_clk / 1000;
812 srate = internal->srate / 1000;
813
814 if (decim <= 4) {
815 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
816 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
817 } else {
818 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
819 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
820 }
821 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
822
823 return btr_nom_freq;
824 }
825
826 /*
827 * stb0899_dvbs2_calc_dev
828 * compute the correction to be applied to symbol rate
829 */
830 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
831 {
832 struct stb0899_internal *internal = &state->internal;
833 u32 dec_ratio, correction, master_clk, srate;
834
835 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
836 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
837
838 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
839 srate = internal->srate / 1000; /* for integer Caculation*/
840 correction = (512 * master_clk) / (2 * dec_ratio * srate);
841
842 return correction;
843 }
844
845 /*
846 * stb0899_dvbs2_set_srate
847 * Set DVBS2 symbol rate
848 */
849 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
850 {
851 struct stb0899_internal *internal = &state->internal;
852
853 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
854 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
855 u8 anti_alias;
856
857 /*set decimation to 1*/
858 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
859 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
860 dec_rate = Log2Int(dec_ratio);
861
862 win_sel = 0;
863 if (dec_rate >= 5)
864 win_sel = dec_rate - 4;
865
866 decim = (1 << dec_rate);
867 /* (FSamp/Fsymbol *100) for integer Caculation */
868 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
869
870 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
871 band_lim = 1;
872 else
873 band_lim = 0; /* band limit signal going into btr block*/
874
875 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
876 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
877
878 if (f_sym <= 3450)
879 anti_alias = 0;
880 else if (f_sym <= 4250)
881 anti_alias = 1;
882 else
883 anti_alias = 2;
884
885 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
886 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
887 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
888
889 correction = stb0899_dvbs2_calc_dev(state);
890 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
891 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
892 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
893
894 /* scale UWP+CSM frequency to sample rate*/
895 freq_adj = internal->srate / (internal->master_clk / 4096);
896 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
897 }
898
899 /*
900 * stb0899_dvbs2_set_btr_loopbw
901 * set bit timing loop bandwidth as a percentage of the symbol rate
902 */
903 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
904 {
905 struct stb0899_internal *internal = &state->internal;
906 struct stb0899_config *config = state->config;
907
908 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
909 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
910 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
911 u32 decim, K, wn, k_direct, k_indirect;
912 u32 reg;
913
914 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
915 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
916 dec_rate = Log2Int(dec_ratio);
917 decim = (1 << dec_rate);
918
919 sym_peak *= 576000;
920 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
921 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
922
923 if (K != 0) {
924 K = sym_peak / K;
925 wn = (4 * zeta * zeta) + 1000000;
926 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
927
928 k_indirect = (wn * wn) / K;
929 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
930 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
931 k_direct *= 100;
932
933 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
934 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
935 k_btr1 = k_direct / (1 << k_direct_shift);
936 k_btr1 /= 10000;
937
938 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
939 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
940 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
941 k_btr0 /= 1000000;
942
943 k_btr2_rshft = 0;
944 if (k_btr0_rshft > 15) {
945 k_btr2_rshft = k_btr0_rshft - 15;
946 k_btr0_rshft = 15;
947 }
948 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
949 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
950 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
951 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
952 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
953 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
954 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
955 } else
956 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
957 }
958
959 /*
960 * stb0899_dvbs2_set_carr_freq
961 * set nominal frequency for carrier search
962 */
963 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
964 {
965 struct stb0899_config *config = state->config;
966 s32 crl_nom_freq;
967 u32 reg;
968
969 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
970 crl_nom_freq *= carr_freq;
971 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
972 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
973 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
974 }
975
976 /*
977 * stb0899_dvbs2_init_calc
978 * Initialize DVBS2 UWP, CSM, carrier and timing loops
979 */
980 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
981 {
982 struct stb0899_internal *internal = &state->internal;
983 s32 steps, step_size;
984 u32 range, reg;
985
986 /* config uwp and csm */
987 stb0899_dvbs2_config_uwp(state);
988 stb0899_dvbs2_config_csm_auto(state);
989
990 /* initialize BTR */
991 stb0899_dvbs2_set_srate(state);
992 stb0899_dvbs2_set_btr_loopbw(state);
993
994 if (internal->srate / 1000000 >= 15)
995 step_size = (1 << 17) / 5;
996 else if (internal->srate / 1000000 >= 10)
997 step_size = (1 << 17) / 7;
998 else if (internal->srate / 1000000 >= 5)
999 step_size = (1 << 17) / 10;
1000 else
1001 step_size = (1 << 17) / 4;
1002
1003 range = internal->srch_range / 1000000;
1004 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1005 steps = (steps + 6) / 10;
1006 steps = (steps == 0) ? 1 : steps;
1007 if (steps % 2 == 0)
1008 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1009 (internal->step_size * (internal->srate / 20000000)),
1010 (internal->master_clk) / 1000000);
1011 else
1012 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1013
1014 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1015 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1016 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1017 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1018 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1019 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1020 }
1021
1022 /*
1023 * stb0899_dvbs2_btr_init
1024 * initialize the timing loop
1025 */
1026 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1027 {
1028 u32 reg;
1029
1030 /* set enable BTR loopback */
1031 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1032 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1033 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1034 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1035
1036 /* fix btr freq accum at 0 */
1037 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1038 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1039
1040 /* fix btr freq accum at 0 */
1041 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1042 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1043 }
1044
1045 /*
1046 * stb0899_dvbs2_reacquire
1047 * trigger a DVB-S2 acquisition
1048 */
1049 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1050 {
1051 u32 reg = 0;
1052
1053 /* demod soft reset */
1054 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1056
1057 /*Reset Timing Loop */
1058 stb0899_dvbs2_btr_init(state);
1059
1060 /* reset Carrier loop */
1061 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1062 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1063 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1064 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1065 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1066
1067 /*release demod soft reset */
1068 reg = 0;
1069 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1070 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1071
1072 /* start acquisition process */
1073 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1074 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1075
1076 /* equalizer Init */
1077 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1078
1079 /*Start equilizer */
1080 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1081
1082 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1083 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1084 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1085 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1086 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1087 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1088
1089 /* RESET Packet delineator */
1090 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1091 }
1092
1093 /*
1094 * stb0899_dvbs2_get_dmd_status
1095 * get DVB-S2 Demod LOCK status
1096 */
1097 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1098 {
1099 int time = -10, lock = 0, uwp, csm;
1100 u32 reg;
1101
1102 do {
1103 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1104 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1105 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1106 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1107 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1108 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1109 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1110 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1111 if (uwp && csm)
1112 lock = 1;
1113
1114 time += 10;
1115 msleep(10);
1116
1117 } while ((!lock) && (time <= timeout));
1118
1119 if (lock) {
1120 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1121 return DVBS2_DEMOD_LOCK;
1122 } else {
1123 return DVBS2_DEMOD_NOLOCK;
1124 }
1125 }
1126
1127 /*
1128 * stb0899_dvbs2_get_data_lock
1129 * get FEC status
1130 */
1131 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1132 {
1133 int time = 0, lock = 0;
1134 u8 reg;
1135
1136 while ((!lock) && (time < timeout)) {
1137 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1138 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1139 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1140 time++;
1141 }
1142
1143 return lock;
1144 }
1145
1146 /*
1147 * stb0899_dvbs2_get_fec_status
1148 * get DVB-S2 FEC LOCK status
1149 */
1150 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1151 {
1152 int time = 0, Locked;
1153
1154 do {
1155 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1156 time++;
1157 msleep(1);
1158
1159 } while ((!Locked) && (time < timeout));
1160
1161 if (Locked) {
1162 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1163 return DVBS2_FEC_LOCK;
1164 } else {
1165 return DVBS2_FEC_NOLOCK;
1166 }
1167 }
1168
1169
1170 /*
1171 * stb0899_dvbs2_init_csm
1172 * set parameters for manual mode
1173 */
1174 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1175 {
1176 struct stb0899_internal *internal = &state->internal;
1177
1178 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1179 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1180 u32 csm1, csm2, csm3, csm4;
1181
1182 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1183 switch (modcod) {
1184 case STB0899_QPSK_12:
1185 gamma_acq = 25;
1186 gamma_rho_acq = 2700;
1187 gamma_trk = 12;
1188 gamma_rho_trk = 180;
1189 lock_count_thr = 8;
1190 break;
1191 case STB0899_QPSK_35:
1192 gamma_acq = 38;
1193 gamma_rho_acq = 7182;
1194 gamma_trk = 14;
1195 gamma_rho_trk = 308;
1196 lock_count_thr = 8;
1197 break;
1198 case STB0899_QPSK_23:
1199 gamma_acq = 42;
1200 gamma_rho_acq = 9408;
1201 gamma_trk = 17;
1202 gamma_rho_trk = 476;
1203 lock_count_thr = 8;
1204 break;
1205 case STB0899_QPSK_34:
1206 gamma_acq = 53;
1207 gamma_rho_acq = 16642;
1208 gamma_trk = 19;
1209 gamma_rho_trk = 646;
1210 lock_count_thr = 8;
1211 break;
1212 case STB0899_QPSK_45:
1213 gamma_acq = 53;
1214 gamma_rho_acq = 17119;
1215 gamma_trk = 22;
1216 gamma_rho_trk = 880;
1217 lock_count_thr = 8;
1218 break;
1219 case STB0899_QPSK_56:
1220 gamma_acq = 55;
1221 gamma_rho_acq = 19250;
1222 gamma_trk = 23;
1223 gamma_rho_trk = 989;
1224 lock_count_thr = 8;
1225 break;
1226 case STB0899_QPSK_89:
1227 gamma_acq = 60;
1228 gamma_rho_acq = 24240;
1229 gamma_trk = 24;
1230 gamma_rho_trk = 1176;
1231 lock_count_thr = 8;
1232 break;
1233 case STB0899_QPSK_910:
1234 gamma_acq = 66;
1235 gamma_rho_acq = 29634;
1236 gamma_trk = 24;
1237 gamma_rho_trk = 1176;
1238 lock_count_thr = 8;
1239 break;
1240 default:
1241 gamma_acq = 66;
1242 gamma_rho_acq = 29634;
1243 gamma_trk = 24;
1244 gamma_rho_trk = 1176;
1245 lock_count_thr = 8;
1246 break;
1247 }
1248
1249 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1250 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1251 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1252
1253 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1254 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1255 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1256 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1257
1258 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1259 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1260 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1261 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1262 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1263 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1264 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1265 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1266 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1267 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1268 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1269
1270 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1271 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1272 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1273 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1274 }
1275 }
1276
1277 /*
1278 * stb0899_dvbs2_get_srate
1279 * get DVB-S2 Symbol Rate
1280 */
1281 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1282 {
1283 struct stb0899_internal *internal = &state->internal;
1284 struct stb0899_config *config = state->config;
1285
1286 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1287 int div1, div2, rem1, rem2;
1288
1289 div1 = config->btr_nco_bits / 2;
1290 div2 = config->btr_nco_bits - div1 - 1;
1291
1292 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1293
1294 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1295 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1296 decimRate = (1 << decimRate);
1297
1298 intval1 = internal->master_clk / (1 << div1);
1299 intval2 = bTrNomFreq / (1 << div2);
1300
1301 rem1 = internal->master_clk % (1 << div1);
1302 rem2 = bTrNomFreq % (1 << div2);
1303 /* only for integer calculation */
1304 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1305 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1306
1307 return srate;
1308 }
1309
1310 /*
1311 * stb0899_dvbs2_algo
1312 * Search for signal, timing, carrier and data for a given
1313 * frequency in a given range
1314 */
1315 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1316 {
1317 struct stb0899_internal *internal = &state->internal;
1318 enum stb0899_modcod modcod;
1319
1320 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1321 int i = 0;
1322 u32 reg, csm1;
1323
1324 if (internal->srate <= 2000000) {
1325 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1326 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1327 } else if (internal->srate <= 5000000) {
1328 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1329 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1330 } else if (internal->srate <= 10000000) {
1331 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1332 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1333 } else if (internal->srate <= 15000000) {
1334 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1335 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1336 } else if (internal->srate <= 20000000) {
1337 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1338 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1339 } else if (internal->srate <= 25000000) {
1340 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1341 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1342 } else {
1343 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1344 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1345 }
1346
1347 /* Maintain Stream Merger in reset during acquisition */
1348 reg = stb0899_read_reg(state, STB0899_TSTRES);
1349 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1350 stb0899_write_reg(state, STB0899_TSTRES, reg);
1351
1352 /* enable tuner I/O */
1353 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1354
1355 /* Move tuner to frequency */
1356 if (state->config->tuner_set_frequency)
1357 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1358 if (state->config->tuner_get_frequency)
1359 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1360
1361 /* disable tuner I/O */
1362 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1363
1364 /* Set IF AGC to acquisition */
1365 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1366 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1367 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1368 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1369
1370 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1371 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1372 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1373
1374 /* Initialisation */
1375 stb0899_dvbs2_init_calc(state);
1376
1377 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1378 switch (internal->inversion) {
1379 case IQ_SWAP_OFF:
1380 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1381 break;
1382 case IQ_SWAP_ON:
1383 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1384 break;
1385 }
1386 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1387 stb0899_dvbs2_reacquire(state);
1388
1389 /* Wait for demod lock (UWP and CSM) */
1390 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1391
1392 if (internal->status == DVBS2_DEMOD_LOCK) {
1393 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1394 i = 0;
1395 /* Demod Locked, check FEC status */
1396 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1397
1398 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1399 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1400 /* Read the frequency offset*/
1401 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1402
1403 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1404 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1405 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1406 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1407 stb0899_dvbs2_reacquire(state);
1408 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1409 i++;
1410 }
1411 }
1412
1413 if (internal->status != DVBS2_FEC_LOCK) {
1414 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1415 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1416 /* IQ Spectrum Inversion */
1417 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1418 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1419 /* start acquistion process */
1420 stb0899_dvbs2_reacquire(state);
1421
1422 /* Wait for demod lock (UWP and CSM) */
1423 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1424 if (internal->status == DVBS2_DEMOD_LOCK) {
1425 i = 0;
1426 /* Demod Locked, check FEC */
1427 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1428 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1429 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1430 /* Read the frequency offset*/
1431 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1432
1433 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1434 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1435 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1436 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1437
1438 stb0899_dvbs2_reacquire(state);
1439 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1440 i++;
1441 }
1442 }
1443 /*
1444 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1445 pParams->IQLocked = !iqSpectrum;
1446 */
1447 }
1448 if (internal->status == DVBS2_FEC_LOCK) {
1449 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1450 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1451 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1452 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1453
1454 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1455 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1456 (pilots == 1)) {
1457
1458 stb0899_dvbs2_init_csm(state, pilots, modcod);
1459 /* Wait for UWP,CSM and data LOCK 20ms max */
1460 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1461
1462 i = 0;
1463 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1464 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1465 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1466 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1467 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1468 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1469 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1470
1471 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1472 i++;
1473 }
1474 }
1475
1476 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1477 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1478 (pilots == 1)) {
1479
1480 /* Equalizer Disable update */
1481 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1482 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1483 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1484 }
1485
1486 /* slow down the Equalizer once locked */
1487 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1488 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1489 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1490
1491 /* Store signal parameters */
1492 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1493
1494 offsetfreq = sign_extend32(offsetfreq, 29);
1495
1496 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1497 offsetfreq *= (internal->master_clk / 1000000);
1498
1499 /* store current inversion for next run */
1500 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1501 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1502 internal->inversion = IQ_SWAP_ON;
1503 else
1504 internal->inversion = IQ_SWAP_OFF;
1505
1506 internal->freq = internal->freq + offsetfreq;
1507 internal->srate = stb0899_dvbs2_get_srate(state);
1508
1509 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1510 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1511 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1512 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1513
1514 /* Set IF AGC to tracking */
1515 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1516 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1517
1518 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1519 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1520 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1521
1522 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1523
1524 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1525 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1526 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1527 }
1528
1529 /* Release Stream Merger Reset */
1530 reg = stb0899_read_reg(state, STB0899_TSTRES);
1531 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1532 stb0899_write_reg(state, STB0899_TSTRES, reg);
1533
1534 return internal->status;
1535 }
Linux with added FPC-III support