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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / i2c / adv7842.c
blob2d61f0cc2b5b0b0db0846ac9801b4aea3fed41c8
1 /*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
30 */
31
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <linux/hdmi.h>
42 #include <media/cec.h>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-event.h>
45 #include <media/v4l2-ctrls.h>
46 #include <media/v4l2-dv-timings.h>
47 #include <media/i2c/adv7842.h>
48
49 static int debug;
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
54 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
56 MODULE_LICENSE("GPL");
57
58 /* ADV7842 system clock frequency */
59 #define ADV7842_fsc (28636360)
60
61 #define ADV7842_RGB_OUT (1 << 1)
62
63 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
64 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
65 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
66
67 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
68 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
69 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
70 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
71 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
72 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
73
74 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
75 #define ADV7842_OP_CH_SEL_GRB (1 << 5)
76 #define ADV7842_OP_CH_SEL_BGR (2 << 5)
77 #define ADV7842_OP_CH_SEL_RGB (3 << 5)
78 #define ADV7842_OP_CH_SEL_BRG (4 << 5)
79 #define ADV7842_OP_CH_SEL_RBG (5 << 5)
80
81 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
82
83 #define ADV7842_MAX_ADDRS (3)
84
85 /*
86 **********************************************************************
87 *
88 * Arrays with configuration parameters for the ADV7842
89 *
90 **********************************************************************
91 */
92
93 struct adv7842_format_info {
94 u32 code;
95 u8 op_ch_sel;
96 bool rgb_out;
97 bool swap_cb_cr;
98 u8 op_format_sel;
99 };
100
101 struct adv7842_state {
102 struct adv7842_platform_data pdata;
103 struct v4l2_subdev sd;
104 struct media_pad pad;
105 struct v4l2_ctrl_handler hdl;
106 enum adv7842_mode mode;
107 struct v4l2_dv_timings timings;
108 enum adv7842_vid_std_select vid_std_select;
109
110 const struct adv7842_format_info *format;
111
112 v4l2_std_id norm;
113 struct {
114 u8 edid[256];
115 u32 present;
116 } hdmi_edid;
117 struct {
118 u8 edid[256];
119 u32 present;
120 } vga_edid;
121 struct v4l2_fract aspect_ratio;
122 u32 rgb_quantization_range;
123 bool is_cea_format;
124 struct delayed_work delayed_work_enable_hotplug;
125 bool restart_stdi_once;
126 bool hdmi_port_a;
127
128 /* i2c clients */
129 struct i2c_client *i2c_sdp_io;
130 struct i2c_client *i2c_sdp;
131 struct i2c_client *i2c_cp;
132 struct i2c_client *i2c_vdp;
133 struct i2c_client *i2c_afe;
134 struct i2c_client *i2c_hdmi;
135 struct i2c_client *i2c_repeater;
136 struct i2c_client *i2c_edid;
137 struct i2c_client *i2c_infoframe;
138 struct i2c_client *i2c_cec;
139 struct i2c_client *i2c_avlink;
140
141 /* controls */
142 struct v4l2_ctrl *detect_tx_5v_ctrl;
143 struct v4l2_ctrl *analog_sampling_phase_ctrl;
144 struct v4l2_ctrl *free_run_color_ctrl_manual;
145 struct v4l2_ctrl *free_run_color_ctrl;
146 struct v4l2_ctrl *rgb_quantization_range_ctrl;
147
148 struct cec_adapter *cec_adap;
149 u8 cec_addr[ADV7842_MAX_ADDRS];
150 u8 cec_valid_addrs;
151 bool cec_enabled_adap;
152 };
153
154 /* Unsupported timings. This device cannot support 720p30. */
155 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
156 V4L2_DV_BT_CEA_1280X720P30,
157 { }
158 };
159
160 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
161 {
162 int i;
163
164 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
165 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
166 return false;
167 return true;
168 }
169
170 struct adv7842_video_standards {
171 struct v4l2_dv_timings timings;
172 u8 vid_std;
173 u8 v_freq;
174 };
175
176 /* sorted by number of lines */
177 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
178 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
180 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
181 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 /* TODO add 1920x1080P60_RB (CVT timing) */
188 { },
189 };
190
191 /* sorted by number of lines */
192 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
209 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
211 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
212 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
213 /* TODO add 1600X1200P60_RB (not a DMT timing) */
214 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
215 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
216 { },
217 };
218
219 /* sorted by number of lines */
220 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
221 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
222 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
223 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
224 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
225 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
226 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
227 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
228 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
229 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
230 { },
231 };
232
233 /* sorted by number of lines */
234 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
250 { },
251 };
252
253 static const struct v4l2_event adv7842_ev_fmt = {
254 .type = V4L2_EVENT_SOURCE_CHANGE,
255 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
256 };
257
258 /* ----------------------------------------------------------------------- */
259
260 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
261 {
262 return container_of(sd, struct adv7842_state, sd);
263 }
264
265 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
266 {
267 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
268 }
269
270 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
271 {
272 return V4L2_DV_BT_BLANKING_WIDTH(t);
273 }
274
275 static inline unsigned htotal(const struct v4l2_bt_timings *t)
276 {
277 return V4L2_DV_BT_FRAME_WIDTH(t);
278 }
279
280 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
281 {
282 return V4L2_DV_BT_BLANKING_HEIGHT(t);
283 }
284
285 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
286 {
287 return V4L2_DV_BT_FRAME_HEIGHT(t);
288 }
289
290
291 /* ----------------------------------------------------------------------- */
292
293 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
294 u8 command, bool check)
295 {
296 union i2c_smbus_data data;
297
298 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
299 I2C_SMBUS_READ, command,
300 I2C_SMBUS_BYTE_DATA, &data))
301 return data.byte;
302 if (check)
303 v4l_err(client, "error reading %02x, %02x\n",
304 client->addr, command);
305 return -EIO;
306 }
307
308 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
309 {
310 int i;
311
312 for (i = 0; i < 3; i++) {
313 int ret = adv_smbus_read_byte_data_check(client, command, true);
314
315 if (ret >= 0) {
316 if (i)
317 v4l_err(client, "read ok after %d retries\n", i);
318 return ret;
319 }
320 }
321 v4l_err(client, "read failed\n");
322 return -EIO;
323 }
324
325 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
326 u8 command, u8 value)
327 {
328 union i2c_smbus_data data;
329 int err;
330 int i;
331
332 data.byte = value;
333 for (i = 0; i < 3; i++) {
334 err = i2c_smbus_xfer(client->adapter, client->addr,
335 client->flags,
336 I2C_SMBUS_WRITE, command,
337 I2C_SMBUS_BYTE_DATA, &data);
338 if (!err)
339 break;
340 }
341 if (err < 0)
342 v4l_err(client, "error writing %02x, %02x, %02x\n",
343 client->addr, command, value);
344 return err;
345 }
346
347 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
348 u8 command, u8 value)
349 {
350 union i2c_smbus_data data;
351 data.byte = value;
352
353 i2c_smbus_xfer(client->adapter, client->addr,
354 client->flags,
355 I2C_SMBUS_WRITE, command,
356 I2C_SMBUS_BYTE_DATA, &data);
357 }
358
359 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
360 u8 command, unsigned length, const u8 *values)
361 {
362 union i2c_smbus_data data;
363
364 if (length > I2C_SMBUS_BLOCK_MAX)
365 length = I2C_SMBUS_BLOCK_MAX;
366 data.block[0] = length;
367 memcpy(data.block + 1, values, length);
368 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
369 I2C_SMBUS_WRITE, command,
370 I2C_SMBUS_I2C_BLOCK_DATA, &data);
371 }
372
373 /* ----------------------------------------------------------------------- */
374
375 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
376 {
377 struct i2c_client *client = v4l2_get_subdevdata(sd);
378
379 return adv_smbus_read_byte_data(client, reg);
380 }
381
382 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383 {
384 struct i2c_client *client = v4l2_get_subdevdata(sd);
385
386 return adv_smbus_write_byte_data(client, reg, val);
387 }
388
389 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
390 {
391 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
392 }
393
394 static inline int io_write_clr_set(struct v4l2_subdev *sd,
395 u8 reg, u8 mask, u8 val)
396 {
397 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
398 }
399
400 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
401 {
402 struct adv7842_state *state = to_state(sd);
403
404 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
405 }
406
407 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
408 {
409 struct adv7842_state *state = to_state(sd);
410
411 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
412 }
413
414 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
415 {
416 struct adv7842_state *state = to_state(sd);
417
418 return adv_smbus_read_byte_data(state->i2c_cec, reg);
419 }
420
421 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
422 {
423 struct adv7842_state *state = to_state(sd);
424
425 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
426 }
427
428 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
429 {
430 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
431 }
432
433 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
434 {
435 struct adv7842_state *state = to_state(sd);
436
437 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
438 }
439
440 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
441 {
442 struct adv7842_state *state = to_state(sd);
443
444 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
445 }
446
447 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
448 {
449 struct adv7842_state *state = to_state(sd);
450
451 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
452 }
453
454 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
455 {
456 struct adv7842_state *state = to_state(sd);
457
458 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
459 }
460
461 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
462 {
463 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
464 }
465
466 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
467 {
468 struct adv7842_state *state = to_state(sd);
469
470 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
471 }
472
473 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474 {
475 struct adv7842_state *state = to_state(sd);
476
477 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
478 }
479
480 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
481 {
482 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
483 }
484
485 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
486 {
487 struct adv7842_state *state = to_state(sd);
488
489 return adv_smbus_read_byte_data(state->i2c_afe, reg);
490 }
491
492 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
493 {
494 struct adv7842_state *state = to_state(sd);
495
496 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
497 }
498
499 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
500 {
501 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
502 }
503
504 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
505 {
506 struct adv7842_state *state = to_state(sd);
507
508 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
509 }
510
511 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
512 {
513 struct adv7842_state *state = to_state(sd);
514
515 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
516 }
517
518 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
519 {
520 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
521 }
522
523 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
524 {
525 struct adv7842_state *state = to_state(sd);
526
527 return adv_smbus_read_byte_data(state->i2c_edid, reg);
528 }
529
530 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
531 {
532 struct adv7842_state *state = to_state(sd);
533
534 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
535 }
536
537 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
538 {
539 struct adv7842_state *state = to_state(sd);
540
541 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
542 }
543
544 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
545 {
546 struct adv7842_state *state = to_state(sd);
547
548 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
549 }
550
551 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
552 {
553 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
554 }
555
556 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
557 {
558 struct adv7842_state *state = to_state(sd);
559
560 return adv_smbus_read_byte_data(state->i2c_cp, reg);
561 }
562
563 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
564 {
565 struct adv7842_state *state = to_state(sd);
566
567 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
568 }
569
570 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
571 {
572 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
573 }
574
575 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
576 {
577 struct adv7842_state *state = to_state(sd);
578
579 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
580 }
581
582 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
583 {
584 struct adv7842_state *state = to_state(sd);
585
586 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
587 }
588
589 static void main_reset(struct v4l2_subdev *sd)
590 {
591 struct i2c_client *client = v4l2_get_subdevdata(sd);
592
593 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
594
595 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
596
597 mdelay(5);
598 }
599
600 /* -----------------------------------------------------------------------------
601 * Format helpers
602 */
603
604 static const struct adv7842_format_info adv7842_formats[] = {
605 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
606 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
607 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
608 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
609 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
610 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
611 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
612 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
613 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
614 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
615 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
616 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
617 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
618 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
619 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
620 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
621 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
622 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
623 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
624 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
625 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
626 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
627 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
628 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
629 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
630 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
631 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
632 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
633 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
634 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
635 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
636 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
637 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
638 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
639 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
640 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
641 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
642 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
643 };
644
645 static const struct adv7842_format_info *
646 adv7842_format_info(struct adv7842_state *state, u32 code)
647 {
648 unsigned int i;
649
650 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
651 if (adv7842_formats[i].code == code)
652 return &adv7842_formats[i];
653 }
654
655 return NULL;
656 }
657
658 /* ----------------------------------------------------------------------- */
659
660 static inline bool is_analog_input(struct v4l2_subdev *sd)
661 {
662 struct adv7842_state *state = to_state(sd);
663
664 return ((state->mode == ADV7842_MODE_RGB) ||
665 (state->mode == ADV7842_MODE_COMP));
666 }
667
668 static inline bool is_digital_input(struct v4l2_subdev *sd)
669 {
670 struct adv7842_state *state = to_state(sd);
671
672 return state->mode == ADV7842_MODE_HDMI;
673 }
674
675 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
676 .type = V4L2_DV_BT_656_1120,
677 /* keep this initialization for compatibility with GCC < 4.4.6 */
678 .reserved = { 0 },
679 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
680 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
681 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
682 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
683 V4L2_DV_BT_CAP_CUSTOM)
684 };
685
686 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
687 .type = V4L2_DV_BT_656_1120,
688 /* keep this initialization for compatibility with GCC < 4.4.6 */
689 .reserved = { 0 },
690 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
691 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
692 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
693 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
694 V4L2_DV_BT_CAP_CUSTOM)
695 };
696
697 static inline const struct v4l2_dv_timings_cap *
698 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
699 {
700 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
701 &adv7842_timings_cap_analog;
702 }
703
704 /* ----------------------------------------------------------------------- */
705
706 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
707 {
708 u8 reg = io_read(sd, 0x6f);
709 u16 val = 0;
710
711 if (reg & 0x02)
712 val |= 1; /* port A */
713 if (reg & 0x01)
714 val |= 2; /* port B */
715 return val;
716 }
717
718 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
719 {
720 struct delayed_work *dwork = to_delayed_work(work);
721 struct adv7842_state *state = container_of(dwork,
722 struct adv7842_state, delayed_work_enable_hotplug);
723 struct v4l2_subdev *sd = &state->sd;
724 int present = state->hdmi_edid.present;
725 u8 mask = 0;
726
727 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
728 __func__, present);
729
730 if (present & (0x04 << ADV7842_EDID_PORT_A))
731 mask |= 0x20;
732 if (present & (0x04 << ADV7842_EDID_PORT_B))
733 mask |= 0x10;
734 io_write_and_or(sd, 0x20, 0xcf, mask);
735 }
736
737 static int edid_write_vga_segment(struct v4l2_subdev *sd)
738 {
739 struct i2c_client *client = v4l2_get_subdevdata(sd);
740 struct adv7842_state *state = to_state(sd);
741 const u8 *val = state->vga_edid.edid;
742 int err = 0;
743 int i;
744
745 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
746
747 /* HPA disable on port A and B */
748 io_write_and_or(sd, 0x20, 0xcf, 0x00);
749
750 /* Disable I2C access to internal EDID ram from VGA DDC port */
751 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
752
753 /* edid segment pointer '1' for VGA port */
754 rep_write_and_or(sd, 0x77, 0xef, 0x10);
755
756 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
757 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
758 I2C_SMBUS_BLOCK_MAX, val + i);
759 if (err)
760 return err;
761
762 /* Calculates the checksums and enables I2C access
763 * to internal EDID ram from VGA DDC port.
764 */
765 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
766
767 for (i = 0; i < 1000; i++) {
768 if (rep_read(sd, 0x79) & 0x20)
769 break;
770 mdelay(1);
771 }
772 if (i == 1000) {
773 v4l_err(client, "error enabling edid on VGA port\n");
774 return -EIO;
775 }
776
777 /* enable hotplug after 200 ms */
778 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
779
780 return 0;
781 }
782
783 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
784 {
785 struct i2c_client *client = v4l2_get_subdevdata(sd);
786 struct adv7842_state *state = to_state(sd);
787 const u8 *edid = state->hdmi_edid.edid;
788 int spa_loc;
789 u16 pa;
790 int err = 0;
791 int i;
792
793 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
794 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
795
796 /* HPA disable on port A and B */
797 io_write_and_or(sd, 0x20, 0xcf, 0x00);
798
799 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
800 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
801
802 if (!state->hdmi_edid.present)
803 return 0;
804
805 pa = cec_get_edid_phys_addr(edid, 256, &spa_loc);
806 err = cec_phys_addr_validate(pa, &pa, NULL);
807 if (err)
808 return err;
809
810 /*
811 * Return an error if no location of the source physical address
812 * was found.
813 */
814 if (spa_loc == 0)
815 return -EINVAL;
816
817 /* edid segment pointer '0' for HDMI ports */
818 rep_write_and_or(sd, 0x77, 0xef, 0x00);
819
820 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
821 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
822 I2C_SMBUS_BLOCK_MAX, edid + i);
823 if (err)
824 return err;
825
826 if (port == ADV7842_EDID_PORT_A) {
827 rep_write(sd, 0x72, edid[spa_loc]);
828 rep_write(sd, 0x73, edid[spa_loc + 1]);
829 } else {
830 rep_write(sd, 0x74, edid[spa_loc]);
831 rep_write(sd, 0x75, edid[spa_loc + 1]);
832 }
833 rep_write(sd, 0x76, spa_loc & 0xff);
834 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
835
836 /* Calculates the checksums and enables I2C access to internal
837 * EDID ram from HDMI DDC ports
838 */
839 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
840
841 for (i = 0; i < 1000; i++) {
842 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
843 break;
844 mdelay(1);
845 }
846 if (i == 1000) {
847 v4l_err(client, "error enabling edid on port %c\n",
848 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
849 return -EIO;
850 }
851 cec_s_phys_addr(state->cec_adap, pa, false);
852
853 /* enable hotplug after 200 ms */
854 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
855
856 return 0;
857 }
858
859 /* ----------------------------------------------------------------------- */
860
861 #ifdef CONFIG_VIDEO_ADV_DEBUG
862 static void adv7842_inv_register(struct v4l2_subdev *sd)
863 {
864 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
865 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
866 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
867 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
868 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
869 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
870 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
871 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
872 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
873 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
874 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
875 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
876 }
877
878 static int adv7842_g_register(struct v4l2_subdev *sd,
879 struct v4l2_dbg_register *reg)
880 {
881 reg->size = 1;
882 switch (reg->reg >> 8) {
883 case 0:
884 reg->val = io_read(sd, reg->reg & 0xff);
885 break;
886 case 1:
887 reg->val = avlink_read(sd, reg->reg & 0xff);
888 break;
889 case 2:
890 reg->val = cec_read(sd, reg->reg & 0xff);
891 break;
892 case 3:
893 reg->val = infoframe_read(sd, reg->reg & 0xff);
894 break;
895 case 4:
896 reg->val = sdp_io_read(sd, reg->reg & 0xff);
897 break;
898 case 5:
899 reg->val = sdp_read(sd, reg->reg & 0xff);
900 break;
901 case 6:
902 reg->val = afe_read(sd, reg->reg & 0xff);
903 break;
904 case 7:
905 reg->val = rep_read(sd, reg->reg & 0xff);
906 break;
907 case 8:
908 reg->val = edid_read(sd, reg->reg & 0xff);
909 break;
910 case 9:
911 reg->val = hdmi_read(sd, reg->reg & 0xff);
912 break;
913 case 0xa:
914 reg->val = cp_read(sd, reg->reg & 0xff);
915 break;
916 case 0xb:
917 reg->val = vdp_read(sd, reg->reg & 0xff);
918 break;
919 default:
920 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
921 adv7842_inv_register(sd);
922 break;
923 }
924 return 0;
925 }
926
927 static int adv7842_s_register(struct v4l2_subdev *sd,
928 const struct v4l2_dbg_register *reg)
929 {
930 u8 val = reg->val & 0xff;
931
932 switch (reg->reg >> 8) {
933 case 0:
934 io_write(sd, reg->reg & 0xff, val);
935 break;
936 case 1:
937 avlink_write(sd, reg->reg & 0xff, val);
938 break;
939 case 2:
940 cec_write(sd, reg->reg & 0xff, val);
941 break;
942 case 3:
943 infoframe_write(sd, reg->reg & 0xff, val);
944 break;
945 case 4:
946 sdp_io_write(sd, reg->reg & 0xff, val);
947 break;
948 case 5:
949 sdp_write(sd, reg->reg & 0xff, val);
950 break;
951 case 6:
952 afe_write(sd, reg->reg & 0xff, val);
953 break;
954 case 7:
955 rep_write(sd, reg->reg & 0xff, val);
956 break;
957 case 8:
958 edid_write(sd, reg->reg & 0xff, val);
959 break;
960 case 9:
961 hdmi_write(sd, reg->reg & 0xff, val);
962 break;
963 case 0xa:
964 cp_write(sd, reg->reg & 0xff, val);
965 break;
966 case 0xb:
967 vdp_write(sd, reg->reg & 0xff, val);
968 break;
969 default:
970 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
971 adv7842_inv_register(sd);
972 break;
973 }
974 return 0;
975 }
976 #endif
977
978 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
979 {
980 struct adv7842_state *state = to_state(sd);
981 u16 cable_det = adv7842_read_cable_det(sd);
982
983 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
984
985 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
986 }
987
988 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
989 u8 prim_mode,
990 const struct adv7842_video_standards *predef_vid_timings,
991 const struct v4l2_dv_timings *timings)
992 {
993 int i;
994
995 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
996 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
997 is_digital_input(sd) ? 250000 : 1000000, false))
998 continue;
999 /* video std */
1000 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1001 /* v_freq and prim mode */
1002 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
1003 return 0;
1004 }
1005
1006 return -1;
1007 }
1008
1009 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1010 struct v4l2_dv_timings *timings)
1011 {
1012 struct adv7842_state *state = to_state(sd);
1013 int err;
1014
1015 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1016
1017 /* reset to default values */
1018 io_write(sd, 0x16, 0x43);
1019 io_write(sd, 0x17, 0x5a);
1020 /* disable embedded syncs for auto graphics mode */
1021 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1022 cp_write(sd, 0x26, 0x00);
1023 cp_write(sd, 0x27, 0x00);
1024 cp_write(sd, 0x28, 0x00);
1025 cp_write(sd, 0x29, 0x00);
1026 cp_write(sd, 0x8f, 0x40);
1027 cp_write(sd, 0x90, 0x00);
1028 cp_write(sd, 0xa5, 0x00);
1029 cp_write(sd, 0xa6, 0x00);
1030 cp_write(sd, 0xa7, 0x00);
1031 cp_write(sd, 0xab, 0x00);
1032 cp_write(sd, 0xac, 0x00);
1033
1034 switch (state->mode) {
1035 case ADV7842_MODE_COMP:
1036 case ADV7842_MODE_RGB:
1037 err = find_and_set_predefined_video_timings(sd,
1038 0x01, adv7842_prim_mode_comp, timings);
1039 if (err)
1040 err = find_and_set_predefined_video_timings(sd,
1041 0x02, adv7842_prim_mode_gr, timings);
1042 break;
1043 case ADV7842_MODE_HDMI:
1044 err = find_and_set_predefined_video_timings(sd,
1045 0x05, adv7842_prim_mode_hdmi_comp, timings);
1046 if (err)
1047 err = find_and_set_predefined_video_timings(sd,
1048 0x06, adv7842_prim_mode_hdmi_gr, timings);
1049 break;
1050 default:
1051 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1052 __func__, state->mode);
1053 err = -1;
1054 break;
1055 }
1056
1057
1058 return err;
1059 }
1060
1061 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1062 const struct v4l2_bt_timings *bt)
1063 {
1064 struct adv7842_state *state = to_state(sd);
1065 struct i2c_client *client = v4l2_get_subdevdata(sd);
1066 u32 width = htotal(bt);
1067 u32 height = vtotal(bt);
1068 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1069 u16 cp_start_eav = width - bt->hfrontporch;
1070 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1071 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1072 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1073 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1074 const u8 pll[2] = {
1075 0xc0 | ((width >> 8) & 0x1f),
1076 width & 0xff
1077 };
1078
1079 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1080
1081 switch (state->mode) {
1082 case ADV7842_MODE_COMP:
1083 case ADV7842_MODE_RGB:
1084 /* auto graphics */
1085 io_write(sd, 0x00, 0x07); /* video std */
1086 io_write(sd, 0x01, 0x02); /* prim mode */
1087 /* enable embedded syncs for auto graphics mode */
1088 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1089
1090 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1091 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1092 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1093 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1094 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1095 break;
1096 }
1097
1098 /* active video - horizontal timing */
1099 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1100 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1101 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1102 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1103
1104 /* active video - vertical timing */
1105 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1106 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1107 ((cp_end_vbi >> 8) & 0xf));
1108 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1109 break;
1110 case ADV7842_MODE_HDMI:
1111 /* set default prim_mode/vid_std for HDMI
1112 according to [REF_03, c. 4.2] */
1113 io_write(sd, 0x00, 0x02); /* video std */
1114 io_write(sd, 0x01, 0x06); /* prim mode */
1115 break;
1116 default:
1117 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1118 __func__, state->mode);
1119 break;
1120 }
1121
1122 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1123 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1124 cp_write(sd, 0xab, (height >> 4) & 0xff);
1125 cp_write(sd, 0xac, (height & 0x0f) << 4);
1126 }
1127
1128 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1129 {
1130 struct adv7842_state *state = to_state(sd);
1131 u8 offset_buf[4];
1132
1133 if (auto_offset) {
1134 offset_a = 0x3ff;
1135 offset_b = 0x3ff;
1136 offset_c = 0x3ff;
1137 }
1138
1139 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1140 __func__, auto_offset ? "Auto" : "Manual",
1141 offset_a, offset_b, offset_c);
1142
1143 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1144 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1145 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1146 offset_buf[3] = offset_c & 0x0ff;
1147
1148 /* Registers must be written in this order with no i2c access in between */
1149 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1150 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1151 }
1152
1153 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1154 {
1155 struct adv7842_state *state = to_state(sd);
1156 u8 gain_buf[4];
1157 u8 gain_man = 1;
1158 u8 agc_mode_man = 1;
1159
1160 if (auto_gain) {
1161 gain_man = 0;
1162 agc_mode_man = 0;
1163 gain_a = 0x100;
1164 gain_b = 0x100;
1165 gain_c = 0x100;
1166 }
1167
1168 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1169 __func__, auto_gain ? "Auto" : "Manual",
1170 gain_a, gain_b, gain_c);
1171
1172 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1173 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1174 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1175 gain_buf[3] = ((gain_c & 0x0ff));
1176
1177 /* Registers must be written in this order with no i2c access in between */
1178 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1179 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1180 }
1181
1182 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1183 {
1184 struct adv7842_state *state = to_state(sd);
1185 bool rgb_output = io_read(sd, 0x02) & 0x02;
1186 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1187 u8 y = HDMI_COLORSPACE_RGB;
1188
1189 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1190 y = infoframe_read(sd, 0x01) >> 5;
1191
1192 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1193 __func__, state->rgb_quantization_range,
1194 rgb_output, hdmi_signal);
1195
1196 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1197 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1198 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1199
1200 switch (state->rgb_quantization_range) {
1201 case V4L2_DV_RGB_RANGE_AUTO:
1202 if (state->mode == ADV7842_MODE_RGB) {
1203 /* Receiving analog RGB signal
1204 * Set RGB full range (0-255) */
1205 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1206 break;
1207 }
1208
1209 if (state->mode == ADV7842_MODE_COMP) {
1210 /* Receiving analog YPbPr signal
1211 * Set automode */
1212 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1213 break;
1214 }
1215
1216 if (hdmi_signal) {
1217 /* Receiving HDMI signal
1218 * Set automode */
1219 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1220 break;
1221 }
1222
1223 /* Receiving DVI-D signal
1224 * ADV7842 selects RGB limited range regardless of
1225 * input format (CE/IT) in automatic mode */
1226 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1227 /* RGB limited range (16-235) */
1228 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1229 } else {
1230 /* RGB full range (0-255) */
1231 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1232
1233 if (is_digital_input(sd) && rgb_output) {
1234 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1235 } else {
1236 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1237 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1238 }
1239 }
1240 break;
1241 case V4L2_DV_RGB_RANGE_LIMITED:
1242 if (state->mode == ADV7842_MODE_COMP) {
1243 /* YCrCb limited range (16-235) */
1244 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1245 break;
1246 }
1247
1248 if (y != HDMI_COLORSPACE_RGB)
1249 break;
1250
1251 /* RGB limited range (16-235) */
1252 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1253
1254 break;
1255 case V4L2_DV_RGB_RANGE_FULL:
1256 if (state->mode == ADV7842_MODE_COMP) {
1257 /* YCrCb full range (0-255) */
1258 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1259 break;
1260 }
1261
1262 if (y != HDMI_COLORSPACE_RGB)
1263 break;
1264
1265 /* RGB full range (0-255) */
1266 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1267
1268 if (is_analog_input(sd) || hdmi_signal)
1269 break;
1270
1271 /* Adjust gain/offset for DVI-D signals only */
1272 if (rgb_output) {
1273 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1274 } else {
1275 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1276 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1277 }
1278 break;
1279 }
1280 }
1281
1282 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1283 {
1284 struct v4l2_subdev *sd = to_sd(ctrl);
1285 struct adv7842_state *state = to_state(sd);
1286
1287 /* TODO SDP ctrls
1288 contrast/brightness/hue/free run is acting a bit strange,
1289 not sure if sdp csc is correct.
1290 */
1291 switch (ctrl->id) {
1292 /* standard ctrls */
1293 case V4L2_CID_BRIGHTNESS:
1294 cp_write(sd, 0x3c, ctrl->val);
1295 sdp_write(sd, 0x14, ctrl->val);
1296 /* ignore lsb sdp 0x17[3:2] */
1297 return 0;
1298 case V4L2_CID_CONTRAST:
1299 cp_write(sd, 0x3a, ctrl->val);
1300 sdp_write(sd, 0x13, ctrl->val);
1301 /* ignore lsb sdp 0x17[1:0] */
1302 return 0;
1303 case V4L2_CID_SATURATION:
1304 cp_write(sd, 0x3b, ctrl->val);
1305 sdp_write(sd, 0x15, ctrl->val);
1306 /* ignore lsb sdp 0x17[5:4] */
1307 return 0;
1308 case V4L2_CID_HUE:
1309 cp_write(sd, 0x3d, ctrl->val);
1310 sdp_write(sd, 0x16, ctrl->val);
1311 /* ignore lsb sdp 0x17[7:6] */
1312 return 0;
1313 /* custom ctrls */
1314 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1315 afe_write(sd, 0xc8, ctrl->val);
1316 return 0;
1317 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1318 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1319 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1320 return 0;
1321 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1322 u8 R = (ctrl->val & 0xff0000) >> 16;
1323 u8 G = (ctrl->val & 0x00ff00) >> 8;
1324 u8 B = (ctrl->val & 0x0000ff);
1325 /* RGB -> YUV, numerical approximation */
1326 int Y = 66 * R + 129 * G + 25 * B;
1327 int U = -38 * R - 74 * G + 112 * B;
1328 int V = 112 * R - 94 * G - 18 * B;
1329
1330 /* Scale down to 8 bits with rounding */
1331 Y = (Y + 128) >> 8;
1332 U = (U + 128) >> 8;
1333 V = (V + 128) >> 8;
1334 /* make U,V positive */
1335 Y += 16;
1336 U += 128;
1337 V += 128;
1338
1339 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1340 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1341
1342 /* CP */
1343 cp_write(sd, 0xc1, R);
1344 cp_write(sd, 0xc0, G);
1345 cp_write(sd, 0xc2, B);
1346 /* SDP */
1347 sdp_write(sd, 0xde, Y);
1348 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1349 return 0;
1350 }
1351 case V4L2_CID_DV_RX_RGB_RANGE:
1352 state->rgb_quantization_range = ctrl->val;
1353 set_rgb_quantization_range(sd);
1354 return 0;
1355 }
1356 return -EINVAL;
1357 }
1358
1359 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1360 {
1361 struct v4l2_subdev *sd = to_sd(ctrl);
1362
1363 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1364 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1365 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1366 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1367 return 0;
1368 }
1369 return -EINVAL;
1370 }
1371
1372 static inline bool no_power(struct v4l2_subdev *sd)
1373 {
1374 return io_read(sd, 0x0c) & 0x24;
1375 }
1376
1377 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1378 {
1379 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1380 }
1381
1382 static inline bool is_hdmi(struct v4l2_subdev *sd)
1383 {
1384 return hdmi_read(sd, 0x05) & 0x80;
1385 }
1386
1387 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1388 {
1389 struct adv7842_state *state = to_state(sd);
1390
1391 *status = 0;
1392
1393 if (io_read(sd, 0x0c) & 0x24)
1394 *status |= V4L2_IN_ST_NO_POWER;
1395
1396 if (state->mode == ADV7842_MODE_SDP) {
1397 /* status from SDP block */
1398 if (!(sdp_read(sd, 0x5A) & 0x01))
1399 *status |= V4L2_IN_ST_NO_SIGNAL;
1400
1401 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1402 __func__, *status);
1403 return 0;
1404 }
1405 /* status from CP block */
1406 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1407 !(cp_read(sd, 0xb1) & 0x80))
1408 /* TODO channel 2 */
1409 *status |= V4L2_IN_ST_NO_SIGNAL;
1410
1411 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1412 *status |= V4L2_IN_ST_NO_SIGNAL;
1413
1414 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1415 __func__, *status);
1416
1417 return 0;
1418 }
1419
1420 struct stdi_readback {
1421 u16 bl, lcf, lcvs;
1422 u8 hs_pol, vs_pol;
1423 bool interlaced;
1424 };
1425
1426 static int stdi2dv_timings(struct v4l2_subdev *sd,
1427 struct stdi_readback *stdi,
1428 struct v4l2_dv_timings *timings)
1429 {
1430 struct adv7842_state *state = to_state(sd);
1431 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1432 u32 pix_clk;
1433 int i;
1434
1435 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1436 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1437
1438 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1439 adv7842_get_dv_timings_cap(sd),
1440 adv7842_check_dv_timings, NULL))
1441 continue;
1442 if (vtotal(bt) != stdi->lcf + 1)
1443 continue;
1444 if (bt->vsync != stdi->lcvs)
1445 continue;
1446
1447 pix_clk = hfreq * htotal(bt);
1448
1449 if ((pix_clk < bt->pixelclock + 1000000) &&
1450 (pix_clk > bt->pixelclock - 1000000)) {
1451 *timings = v4l2_dv_timings_presets[i];
1452 return 0;
1453 }
1454 }
1455
1456 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1457 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1458 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1459 false, timings))
1460 return 0;
1461 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1462 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1463 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1464 false, state->aspect_ratio, timings))
1465 return 0;
1466
1467 v4l2_dbg(2, debug, sd,
1468 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1469 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1470 stdi->hs_pol, stdi->vs_pol);
1471 return -1;
1472 }
1473
1474 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1475 {
1476 u32 status;
1477
1478 adv7842_g_input_status(sd, &status);
1479 if (status & V4L2_IN_ST_NO_SIGNAL) {
1480 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1481 return -ENOLINK;
1482 }
1483
1484 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1485 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1486 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1487
1488 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1489 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1490 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1491 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1492 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1493 } else {
1494 stdi->hs_pol = 'x';
1495 stdi->vs_pol = 'x';
1496 }
1497 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1498
1499 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1500 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1501 return -ENOLINK;
1502 }
1503
1504 v4l2_dbg(2, debug, sd,
1505 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1506 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1507 stdi->hs_pol, stdi->vs_pol,
1508 stdi->interlaced ? "interlaced" : "progressive");
1509
1510 return 0;
1511 }
1512
1513 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1514 struct v4l2_enum_dv_timings *timings)
1515 {
1516 if (timings->pad != 0)
1517 return -EINVAL;
1518
1519 return v4l2_enum_dv_timings_cap(timings,
1520 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1521 }
1522
1523 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1524 struct v4l2_dv_timings_cap *cap)
1525 {
1526 if (cap->pad != 0)
1527 return -EINVAL;
1528
1529 *cap = *adv7842_get_dv_timings_cap(sd);
1530 return 0;
1531 }
1532
1533 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1534 if the format is listed in adv7842_timings[] */
1535 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1536 struct v4l2_dv_timings *timings)
1537 {
1538 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1539 is_digital_input(sd) ? 250000 : 1000000,
1540 adv7842_check_dv_timings, NULL);
1541 }
1542
1543 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1544 struct v4l2_dv_timings *timings)
1545 {
1546 struct adv7842_state *state = to_state(sd);
1547 struct v4l2_bt_timings *bt = &timings->bt;
1548 struct stdi_readback stdi = { 0 };
1549
1550 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1551
1552 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1553
1554 /* SDP block */
1555 if (state->mode == ADV7842_MODE_SDP)
1556 return -ENODATA;
1557
1558 /* read STDI */
1559 if (read_stdi(sd, &stdi)) {
1560 state->restart_stdi_once = true;
1561 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1562 return -ENOLINK;
1563 }
1564 bt->interlaced = stdi.interlaced ?
1565 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1566 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1567 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1568
1569 if (is_digital_input(sd)) {
1570 u32 freq;
1571
1572 timings->type = V4L2_DV_BT_656_1120;
1573
1574 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1575 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1576 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1577 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1578 if (is_hdmi(sd)) {
1579 /* adjust for deep color mode */
1580 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1581 }
1582 bt->pixelclock = freq;
1583 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1584 hdmi_read(sd, 0x21);
1585 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1586 hdmi_read(sd, 0x23);
1587 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1588 hdmi_read(sd, 0x25);
1589 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1590 hdmi_read(sd, 0x2b)) / 2;
1591 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1592 hdmi_read(sd, 0x2f)) / 2;
1593 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1594 hdmi_read(sd, 0x33)) / 2;
1595 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1596 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1597 if (bt->interlaced == V4L2_DV_INTERLACED) {
1598 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1599 hdmi_read(sd, 0x0c);
1600 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1601 hdmi_read(sd, 0x2d)) / 2;
1602 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1603 hdmi_read(sd, 0x31)) / 2;
1604 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1605 hdmi_read(sd, 0x35)) / 2;
1606 } else {
1607 bt->il_vfrontporch = 0;
1608 bt->il_vsync = 0;
1609 bt->il_vbackporch = 0;
1610 }
1611 adv7842_fill_optional_dv_timings_fields(sd, timings);
1612 } else {
1613 /* find format
1614 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1615 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1616 */
1617 if (!stdi2dv_timings(sd, &stdi, timings))
1618 goto found;
1619 stdi.lcvs += 1;
1620 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1621 if (!stdi2dv_timings(sd, &stdi, timings))
1622 goto found;
1623 stdi.lcvs -= 2;
1624 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1625 if (stdi2dv_timings(sd, &stdi, timings)) {
1626 /*
1627 * The STDI block may measure wrong values, especially
1628 * for lcvs and lcf. If the driver can not find any
1629 * valid timing, the STDI block is restarted to measure
1630 * the video timings again. The function will return an
1631 * error, but the restart of STDI will generate a new
1632 * STDI interrupt and the format detection process will
1633 * restart.
1634 */
1635 if (state->restart_stdi_once) {
1636 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1637 /* TODO restart STDI for Sync Channel 2 */
1638 /* enter one-shot mode */
1639 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1640 /* trigger STDI restart */
1641 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1642 /* reset to continuous mode */
1643 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1644 state->restart_stdi_once = false;
1645 return -ENOLINK;
1646 }
1647 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1648 return -ERANGE;
1649 }
1650 state->restart_stdi_once = true;
1651 }
1652 found:
1653
1654 if (debug > 1)
1655 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1656 timings, true);
1657 return 0;
1658 }
1659
1660 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1661 struct v4l2_dv_timings *timings)
1662 {
1663 struct adv7842_state *state = to_state(sd);
1664 struct v4l2_bt_timings *bt;
1665 int err;
1666
1667 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1668
1669 if (state->mode == ADV7842_MODE_SDP)
1670 return -ENODATA;
1671
1672 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1673 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1674 return 0;
1675 }
1676
1677 bt = &timings->bt;
1678
1679 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1680 adv7842_check_dv_timings, NULL))
1681 return -ERANGE;
1682
1683 adv7842_fill_optional_dv_timings_fields(sd, timings);
1684
1685 state->timings = *timings;
1686
1687 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1688
1689 /* Use prim_mode and vid_std when available */
1690 err = configure_predefined_video_timings(sd, timings);
1691 if (err) {
1692 /* custom settings when the video format
1693 does not have prim_mode/vid_std */
1694 configure_custom_video_timings(sd, bt);
1695 }
1696
1697 set_rgb_quantization_range(sd);
1698
1699
1700 if (debug > 1)
1701 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1702 timings, true);
1703 return 0;
1704 }
1705
1706 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1707 struct v4l2_dv_timings *timings)
1708 {
1709 struct adv7842_state *state = to_state(sd);
1710
1711 if (state->mode == ADV7842_MODE_SDP)
1712 return -ENODATA;
1713 *timings = state->timings;
1714 return 0;
1715 }
1716
1717 static void enable_input(struct v4l2_subdev *sd)
1718 {
1719 struct adv7842_state *state = to_state(sd);
1720
1721 set_rgb_quantization_range(sd);
1722 switch (state->mode) {
1723 case ADV7842_MODE_SDP:
1724 case ADV7842_MODE_COMP:
1725 case ADV7842_MODE_RGB:
1726 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1727 break;
1728 case ADV7842_MODE_HDMI:
1729 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1730 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1731 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1732 break;
1733 default:
1734 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1735 __func__, state->mode);
1736 break;
1737 }
1738 }
1739
1740 static void disable_input(struct v4l2_subdev *sd)
1741 {
1742 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1743 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1744 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1745 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1746 }
1747
1748 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1749 const struct adv7842_sdp_csc_coeff *c)
1750 {
1751 /* csc auto/manual */
1752 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1753
1754 if (!c->manual)
1755 return;
1756
1757 /* csc scaling */
1758 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1759
1760 /* A coeff */
1761 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1762 sdp_io_write(sd, 0xe1, c->A1);
1763 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1764 sdp_io_write(sd, 0xe3, c->A2);
1765 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1766 sdp_io_write(sd, 0xe5, c->A3);
1767
1768 /* A scale */
1769 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1770 sdp_io_write(sd, 0xe7, c->A4);
1771
1772 /* B coeff */
1773 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1774 sdp_io_write(sd, 0xe9, c->B1);
1775 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1776 sdp_io_write(sd, 0xeb, c->B2);
1777 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1778 sdp_io_write(sd, 0xed, c->B3);
1779
1780 /* B scale */
1781 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1782 sdp_io_write(sd, 0xef, c->B4);
1783
1784 /* C coeff */
1785 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1786 sdp_io_write(sd, 0xf1, c->C1);
1787 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1788 sdp_io_write(sd, 0xf3, c->C2);
1789 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1790 sdp_io_write(sd, 0xf5, c->C3);
1791
1792 /* C scale */
1793 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1794 sdp_io_write(sd, 0xf7, c->C4);
1795 }
1796
1797 static void select_input(struct v4l2_subdev *sd,
1798 enum adv7842_vid_std_select vid_std_select)
1799 {
1800 struct adv7842_state *state = to_state(sd);
1801
1802 switch (state->mode) {
1803 case ADV7842_MODE_SDP:
1804 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1805 io_write(sd, 0x01, 0); /* prim mode */
1806 /* enable embedded syncs for auto graphics mode */
1807 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1808
1809 afe_write(sd, 0x00, 0x00); /* power up ADC */
1810 afe_write(sd, 0xc8, 0x00); /* phase control */
1811
1812 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1813 /* script says register 0xde, which don't exist in manual */
1814
1815 /* Manual analog input muxing mode, CVBS (6.4)*/
1816 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1817 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1818 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1819 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1820 } else {
1821 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1822 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1823 }
1824 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1825 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1826
1827 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1828 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1829
1830 /* SDP recommended settings */
1831 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1832 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1833
1834 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1835 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1836 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1837 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1838 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1839 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1840 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1841
1842 /* deinterlacer enabled and 3D comb */
1843 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1844
1845 break;
1846
1847 case ADV7842_MODE_COMP:
1848 case ADV7842_MODE_RGB:
1849 /* Automatic analog input muxing mode */
1850 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1851 /* set mode and select free run resolution */
1852 io_write(sd, 0x00, vid_std_select); /* video std */
1853 io_write(sd, 0x01, 0x02); /* prim mode */
1854 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1855 for auto graphics mode */
1856
1857 afe_write(sd, 0x00, 0x00); /* power up ADC */
1858 afe_write(sd, 0xc8, 0x00); /* phase control */
1859 if (state->mode == ADV7842_MODE_COMP) {
1860 /* force to YCrCb */
1861 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1862 } else {
1863 /* force to RGB */
1864 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1865 }
1866
1867 /* set ADI recommended settings for digitizer */
1868 /* "ADV7842 Register Settings Recommendations
1869 * (rev. 1.8, November 2010)" p. 9. */
1870 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1871 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1872
1873 /* set to default gain for RGB */
1874 cp_write(sd, 0x73, 0x10);
1875 cp_write(sd, 0x74, 0x04);
1876 cp_write(sd, 0x75, 0x01);
1877 cp_write(sd, 0x76, 0x00);
1878
1879 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1880 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1881 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1882 break;
1883
1884 case ADV7842_MODE_HDMI:
1885 /* Automatic analog input muxing mode */
1886 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1887 /* set mode and select free run resolution */
1888 if (state->hdmi_port_a)
1889 hdmi_write(sd, 0x00, 0x02); /* select port A */
1890 else
1891 hdmi_write(sd, 0x00, 0x03); /* select port B */
1892 io_write(sd, 0x00, vid_std_select); /* video std */
1893 io_write(sd, 0x01, 5); /* prim mode */
1894 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1895 for auto graphics mode */
1896
1897 /* set ADI recommended settings for HDMI: */
1898 /* "ADV7842 Register Settings Recommendations
1899 * (rev. 1.8, November 2010)" p. 3. */
1900 hdmi_write(sd, 0xc0, 0x00);
1901 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1902 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1903 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1904 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1905 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1906 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1907 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1908 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1909 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1910 Improve robustness */
1911 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1912 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1913 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1914 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1915 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1916 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1917 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1918 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1919 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1920 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1921
1922 afe_write(sd, 0x00, 0xff); /* power down ADC */
1923 afe_write(sd, 0xc8, 0x40); /* phase control */
1924
1925 /* set to default gain for HDMI */
1926 cp_write(sd, 0x73, 0x10);
1927 cp_write(sd, 0x74, 0x04);
1928 cp_write(sd, 0x75, 0x01);
1929 cp_write(sd, 0x76, 0x00);
1930
1931 /* reset ADI recommended settings for digitizer */
1932 /* "ADV7842 Register Settings Recommendations
1933 * (rev. 2.5, June 2010)" p. 17. */
1934 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1935 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1936 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1937
1938 /* CP coast control */
1939 cp_write(sd, 0xc3, 0x33); /* Component mode */
1940
1941 /* color space conversion, autodetect color space */
1942 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1943 break;
1944
1945 default:
1946 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1947 __func__, state->mode);
1948 break;
1949 }
1950 }
1951
1952 static int adv7842_s_routing(struct v4l2_subdev *sd,
1953 u32 input, u32 output, u32 config)
1954 {
1955 struct adv7842_state *state = to_state(sd);
1956
1957 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1958
1959 switch (input) {
1960 case ADV7842_SELECT_HDMI_PORT_A:
1961 state->mode = ADV7842_MODE_HDMI;
1962 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1963 state->hdmi_port_a = true;
1964 break;
1965 case ADV7842_SELECT_HDMI_PORT_B:
1966 state->mode = ADV7842_MODE_HDMI;
1967 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1968 state->hdmi_port_a = false;
1969 break;
1970 case ADV7842_SELECT_VGA_COMP:
1971 state->mode = ADV7842_MODE_COMP;
1972 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1973 break;
1974 case ADV7842_SELECT_VGA_RGB:
1975 state->mode = ADV7842_MODE_RGB;
1976 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1977 break;
1978 case ADV7842_SELECT_SDP_CVBS:
1979 state->mode = ADV7842_MODE_SDP;
1980 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1981 break;
1982 case ADV7842_SELECT_SDP_YC:
1983 state->mode = ADV7842_MODE_SDP;
1984 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1985 break;
1986 default:
1987 return -EINVAL;
1988 }
1989
1990 disable_input(sd);
1991 select_input(sd, state->vid_std_select);
1992 enable_input(sd);
1993
1994 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1995
1996 return 0;
1997 }
1998
1999 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
2000 struct v4l2_subdev_pad_config *cfg,
2001 struct v4l2_subdev_mbus_code_enum *code)
2002 {
2003 if (code->index >= ARRAY_SIZE(adv7842_formats))
2004 return -EINVAL;
2005 code->code = adv7842_formats[code->index].code;
2006 return 0;
2007 }
2008
2009 static void adv7842_fill_format(struct adv7842_state *state,
2010 struct v4l2_mbus_framefmt *format)
2011 {
2012 memset(format, 0, sizeof(*format));
2013
2014 format->width = state->timings.bt.width;
2015 format->height = state->timings.bt.height;
2016 format->field = V4L2_FIELD_NONE;
2017 format->colorspace = V4L2_COLORSPACE_SRGB;
2018
2019 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2020 format->colorspace = (state->timings.bt.height <= 576) ?
2021 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2022 }
2023
2024 /*
2025 * Compute the op_ch_sel value required to obtain on the bus the component order
2026 * corresponding to the selected format taking into account bus reordering
2027 * applied by the board at the output of the device.
2028 *
2029 * The following table gives the op_ch_value from the format component order
2030 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2031 * adv7842_bus_order value in row).
2032 *
2033 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2034 * ----------+-------------------------------------------------
2035 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2036 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2037 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2038 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2039 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2040 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2041 */
2042 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2043 {
2044 #define _SEL(a, b, c, d, e, f) { \
2045 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2046 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2047 #define _BUS(x) [ADV7842_BUS_ORDER_##x]
2048
2049 static const unsigned int op_ch_sel[6][6] = {
2050 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2051 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2052 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2053 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2054 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2055 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2056 };
2057
2058 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2059 }
2060
2061 static void adv7842_setup_format(struct adv7842_state *state)
2062 {
2063 struct v4l2_subdev *sd = &state->sd;
2064
2065 io_write_clr_set(sd, 0x02, 0x02,
2066 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2067 io_write(sd, 0x03, state->format->op_format_sel |
2068 state->pdata.op_format_mode_sel);
2069 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2070 io_write_clr_set(sd, 0x05, 0x01,
2071 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2072 set_rgb_quantization_range(sd);
2073 }
2074
2075 static int adv7842_get_format(struct v4l2_subdev *sd,
2076 struct v4l2_subdev_pad_config *cfg,
2077 struct v4l2_subdev_format *format)
2078 {
2079 struct adv7842_state *state = to_state(sd);
2080
2081 if (format->pad != ADV7842_PAD_SOURCE)
2082 return -EINVAL;
2083
2084 if (state->mode == ADV7842_MODE_SDP) {
2085 /* SPD block */
2086 if (!(sdp_read(sd, 0x5a) & 0x01))
2087 return -EINVAL;
2088 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2089 format->format.width = 720;
2090 /* valid signal */
2091 if (state->norm & V4L2_STD_525_60)
2092 format->format.height = 480;
2093 else
2094 format->format.height = 576;
2095 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2096 return 0;
2097 }
2098
2099 adv7842_fill_format(state, &format->format);
2100
2101 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2102 struct v4l2_mbus_framefmt *fmt;
2103
2104 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2105 format->format.code = fmt->code;
2106 } else {
2107 format->format.code = state->format->code;
2108 }
2109
2110 return 0;
2111 }
2112
2113 static int adv7842_set_format(struct v4l2_subdev *sd,
2114 struct v4l2_subdev_pad_config *cfg,
2115 struct v4l2_subdev_format *format)
2116 {
2117 struct adv7842_state *state = to_state(sd);
2118 const struct adv7842_format_info *info;
2119
2120 if (format->pad != ADV7842_PAD_SOURCE)
2121 return -EINVAL;
2122
2123 if (state->mode == ADV7842_MODE_SDP)
2124 return adv7842_get_format(sd, cfg, format);
2125
2126 info = adv7842_format_info(state, format->format.code);
2127 if (info == NULL)
2128 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2129
2130 adv7842_fill_format(state, &format->format);
2131 format->format.code = info->code;
2132
2133 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2134 struct v4l2_mbus_framefmt *fmt;
2135
2136 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2137 fmt->code = format->format.code;
2138 } else {
2139 state->format = info;
2140 adv7842_setup_format(state);
2141 }
2142
2143 return 0;
2144 }
2145
2146 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2147 {
2148 if (enable) {
2149 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2150 io_write(sd, 0x46, 0x9c);
2151 /* ESDP_50HZ_DET interrupt */
2152 io_write(sd, 0x5a, 0x10);
2153 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2154 io_write(sd, 0x73, 0x03);
2155 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2156 io_write(sd, 0x78, 0x03);
2157 /* Enable SDP Standard Detection Change and SDP Video Detected */
2158 io_write(sd, 0xa0, 0x09);
2159 /* Enable HDMI_MODE interrupt */
2160 io_write(sd, 0x69, 0x08);
2161 } else {
2162 io_write(sd, 0x46, 0x0);
2163 io_write(sd, 0x5a, 0x0);
2164 io_write(sd, 0x73, 0x0);
2165 io_write(sd, 0x78, 0x0);
2166 io_write(sd, 0xa0, 0x0);
2167 io_write(sd, 0x69, 0x0);
2168 }
2169 }
2170
2171 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2172 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2173 {
2174 struct adv7842_state *state = to_state(sd);
2175
2176 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2177 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2178 return;
2179 }
2180
2181 if (tx_raw_status & 0x02) {
2182 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2183 __func__);
2184 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2185 1, 0, 0, 0);
2186 return;
2187 }
2188 if (tx_raw_status & 0x04) {
2189 u8 status;
2190 u8 nack_cnt;
2191 u8 low_drive_cnt;
2192
2193 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2194 /*
2195 * We set this status bit since this hardware performs
2196 * retransmissions.
2197 */
2198 status = CEC_TX_STATUS_MAX_RETRIES;
2199 nack_cnt = cec_read(sd, 0x14) & 0xf;
2200 if (nack_cnt)
2201 status |= CEC_TX_STATUS_NACK;
2202 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2203 if (low_drive_cnt)
2204 status |= CEC_TX_STATUS_LOW_DRIVE;
2205 cec_transmit_done(state->cec_adap, status,
2206 0, nack_cnt, low_drive_cnt, 0);
2207 return;
2208 }
2209 if (tx_raw_status & 0x01) {
2210 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2211 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2212 return;
2213 }
2214 }
2215
2216 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2217 {
2218 u8 cec_irq;
2219
2220 /* cec controller */
2221 cec_irq = io_read(sd, 0x93) & 0x0f;
2222 if (!cec_irq)
2223 return;
2224
2225 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2226 adv7842_cec_tx_raw_status(sd, cec_irq);
2227 if (cec_irq & 0x08) {
2228 struct adv7842_state *state = to_state(sd);
2229 struct cec_msg msg;
2230
2231 msg.len = cec_read(sd, 0x25) & 0x1f;
2232 if (msg.len > 16)
2233 msg.len = 16;
2234
2235 if (msg.len) {
2236 u8 i;
2237
2238 for (i = 0; i < msg.len; i++)
2239 msg.msg[i] = cec_read(sd, i + 0x15);
2240 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2241 cec_received_msg(state->cec_adap, &msg);
2242 }
2243 }
2244
2245 io_write(sd, 0x94, cec_irq);
2246
2247 if (handled)
2248 *handled = true;
2249 }
2250
2251 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2252 {
2253 struct adv7842_state *state = adap->priv;
2254 struct v4l2_subdev *sd = &state->sd;
2255
2256 if (!state->cec_enabled_adap && enable) {
2257 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2258 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2259 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2260 /* enabled irqs: */
2261 /* tx: ready */
2262 /* tx: arbitration lost */
2263 /* tx: retry timeout */
2264 /* rx: ready */
2265 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2266 cec_write(sd, 0x26, 0x01); /* enable rx */
2267 } else if (state->cec_enabled_adap && !enable) {
2268 /* disable cec interrupts */
2269 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2270 /* disable address mask 1-3 */
2271 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2272 /* power down cec section */
2273 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2274 state->cec_valid_addrs = 0;
2275 }
2276 state->cec_enabled_adap = enable;
2277 return 0;
2278 }
2279
2280 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2281 {
2282 struct adv7842_state *state = adap->priv;
2283 struct v4l2_subdev *sd = &state->sd;
2284 unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2285
2286 if (!state->cec_enabled_adap)
2287 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2288
2289 if (addr == CEC_LOG_ADDR_INVALID) {
2290 cec_write_clr_set(sd, 0x27, 0x70, 0);
2291 state->cec_valid_addrs = 0;
2292 return 0;
2293 }
2294
2295 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2296 bool is_valid = state->cec_valid_addrs & (1 << i);
2297
2298 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2299 free_idx = i;
2300 if (is_valid && state->cec_addr[i] == addr)
2301 return 0;
2302 }
2303 if (i == ADV7842_MAX_ADDRS) {
2304 i = free_idx;
2305 if (i == ADV7842_MAX_ADDRS)
2306 return -ENXIO;
2307 }
2308 state->cec_addr[i] = addr;
2309 state->cec_valid_addrs |= 1 << i;
2310
2311 switch (i) {
2312 case 0:
2313 /* enable address mask 0 */
2314 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2315 /* set address for mask 0 */
2316 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2317 break;
2318 case 1:
2319 /* enable address mask 1 */
2320 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2321 /* set address for mask 1 */
2322 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2323 break;
2324 case 2:
2325 /* enable address mask 2 */
2326 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2327 /* set address for mask 1 */
2328 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2329 break;
2330 }
2331 return 0;
2332 }
2333
2334 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2335 u32 signal_free_time, struct cec_msg *msg)
2336 {
2337 struct adv7842_state *state = adap->priv;
2338 struct v4l2_subdev *sd = &state->sd;
2339 u8 len = msg->len;
2340 unsigned int i;
2341
2342 /*
2343 * The number of retries is the number of attempts - 1, but retry
2344 * at least once. It's not clear if a value of 0 is allowed, so
2345 * let's do at least one retry.
2346 */
2347 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2348
2349 if (len > 16) {
2350 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2351 return -EINVAL;
2352 }
2353
2354 /* write data */
2355 for (i = 0; i < len; i++)
2356 cec_write(sd, i, msg->msg[i]);
2357
2358 /* set length (data + header) */
2359 cec_write(sd, 0x10, len);
2360 /* start transmit, enable tx */
2361 cec_write(sd, 0x11, 0x01);
2362 return 0;
2363 }
2364
2365 static const struct cec_adap_ops adv7842_cec_adap_ops = {
2366 .adap_enable = adv7842_cec_adap_enable,
2367 .adap_log_addr = adv7842_cec_adap_log_addr,
2368 .adap_transmit = adv7842_cec_adap_transmit,
2369 };
2370 #endif
2371
2372 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2373 {
2374 struct adv7842_state *state = to_state(sd);
2375 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2376 u8 irq_status[6];
2377
2378 adv7842_irq_enable(sd, false);
2379
2380 /* read status */
2381 irq_status[0] = io_read(sd, 0x43);
2382 irq_status[1] = io_read(sd, 0x57);
2383 irq_status[2] = io_read(sd, 0x70);
2384 irq_status[3] = io_read(sd, 0x75);
2385 irq_status[4] = io_read(sd, 0x9d);
2386 irq_status[5] = io_read(sd, 0x66);
2387
2388 /* and clear */
2389 if (irq_status[0])
2390 io_write(sd, 0x44, irq_status[0]);
2391 if (irq_status[1])
2392 io_write(sd, 0x58, irq_status[1]);
2393 if (irq_status[2])
2394 io_write(sd, 0x71, irq_status[2]);
2395 if (irq_status[3])
2396 io_write(sd, 0x76, irq_status[3]);
2397 if (irq_status[4])
2398 io_write(sd, 0x9e, irq_status[4]);
2399 if (irq_status[5])
2400 io_write(sd, 0x67, irq_status[5]);
2401
2402 adv7842_irq_enable(sd, true);
2403
2404 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2405 irq_status[0], irq_status[1], irq_status[2],
2406 irq_status[3], irq_status[4], irq_status[5]);
2407
2408 /* format change CP */
2409 fmt_change_cp = irq_status[0] & 0x9c;
2410
2411 /* format change SDP */
2412 if (state->mode == ADV7842_MODE_SDP)
2413 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2414 else
2415 fmt_change_sdp = 0;
2416
2417 /* digital format CP */
2418 if (is_digital_input(sd))
2419 fmt_change_digital = irq_status[3] & 0x03;
2420 else
2421 fmt_change_digital = 0;
2422
2423 /* format change */
2424 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2425 v4l2_dbg(1, debug, sd,
2426 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2427 __func__, fmt_change_cp, fmt_change_digital,
2428 fmt_change_sdp);
2429 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2430 if (handled)
2431 *handled = true;
2432 }
2433
2434 /* HDMI/DVI mode */
2435 if (irq_status[5] & 0x08) {
2436 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2437 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2438 set_rgb_quantization_range(sd);
2439 if (handled)
2440 *handled = true;
2441 }
2442
2443 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2444 /* cec */
2445 adv7842_cec_isr(sd, handled);
2446 #endif
2447
2448 /* tx 5v detect */
2449 if (irq_status[2] & 0x3) {
2450 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2451 adv7842_s_detect_tx_5v_ctrl(sd);
2452 if (handled)
2453 *handled = true;
2454 }
2455 return 0;
2456 }
2457
2458 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2459 {
2460 struct adv7842_state *state = to_state(sd);
2461 u8 *data = NULL;
2462
2463 memset(edid->reserved, 0, sizeof(edid->reserved));
2464
2465 switch (edid->pad) {
2466 case ADV7842_EDID_PORT_A:
2467 case ADV7842_EDID_PORT_B:
2468 if (state->hdmi_edid.present & (0x04 << edid->pad))
2469 data = state->hdmi_edid.edid;
2470 break;
2471 case ADV7842_EDID_PORT_VGA:
2472 if (state->vga_edid.present)
2473 data = state->vga_edid.edid;
2474 break;
2475 default:
2476 return -EINVAL;
2477 }
2478
2479 if (edid->start_block == 0 && edid->blocks == 0) {
2480 edid->blocks = data ? 2 : 0;
2481 return 0;
2482 }
2483
2484 if (!data)
2485 return -ENODATA;
2486
2487 if (edid->start_block >= 2)
2488 return -EINVAL;
2489
2490 if (edid->start_block + edid->blocks > 2)
2491 edid->blocks = 2 - edid->start_block;
2492
2493 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2494
2495 return 0;
2496 }
2497
2498 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2499 {
2500 struct adv7842_state *state = to_state(sd);
2501 int err = 0;
2502
2503 memset(e->reserved, 0, sizeof(e->reserved));
2504
2505 if (e->pad > ADV7842_EDID_PORT_VGA)
2506 return -EINVAL;
2507 if (e->start_block != 0)
2508 return -EINVAL;
2509 if (e->blocks > 2) {
2510 e->blocks = 2;
2511 return -E2BIG;
2512 }
2513
2514 /* todo, per edid */
2515 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2516 e->edid[0x16]);
2517
2518 switch (e->pad) {
2519 case ADV7842_EDID_PORT_VGA:
2520 memset(&state->vga_edid.edid, 0, 256);
2521 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2522 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2523 err = edid_write_vga_segment(sd);
2524 break;
2525 case ADV7842_EDID_PORT_A:
2526 case ADV7842_EDID_PORT_B:
2527 memset(&state->hdmi_edid.edid, 0, 256);
2528 if (e->blocks) {
2529 state->hdmi_edid.present |= 0x04 << e->pad;
2530 } else {
2531 state->hdmi_edid.present &= ~(0x04 << e->pad);
2532 adv7842_s_detect_tx_5v_ctrl(sd);
2533 }
2534 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2535 err = edid_write_hdmi_segment(sd, e->pad);
2536 break;
2537 default:
2538 return -EINVAL;
2539 }
2540 if (err < 0)
2541 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2542 return err;
2543 }
2544
2545 struct adv7842_cfg_read_infoframe {
2546 const char *desc;
2547 u8 present_mask;
2548 u8 head_addr;
2549 u8 payload_addr;
2550 };
2551
2552 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
2553 {
2554 int i;
2555 u8 buffer[32];
2556 union hdmi_infoframe frame;
2557 u8 len;
2558 struct i2c_client *client = v4l2_get_subdevdata(sd);
2559 struct device *dev = &client->dev;
2560
2561 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2562 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2563 return;
2564 }
2565
2566 for (i = 0; i < 3; i++)
2567 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2568
2569 len = buffer[2] + 1;
2570
2571 if (len + 3 > sizeof(buffer)) {
2572 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2573 return;
2574 }
2575
2576 for (i = 0; i < len; i++)
2577 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2578
2579 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2580 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2581 return;
2582 }
2583
2584 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2585 }
2586
2587 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2588 {
2589 int i;
2590 struct adv7842_cfg_read_infoframe cri[] = {
2591 { "AVI", 0x01, 0xe0, 0x00 },
2592 { "Audio", 0x02, 0xe3, 0x1c },
2593 { "SDP", 0x04, 0xe6, 0x2a },
2594 { "Vendor", 0x10, 0xec, 0x54 }
2595 };
2596
2597 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2598 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2599 return;
2600 }
2601
2602 for (i = 0; i < ARRAY_SIZE(cri); i++)
2603 log_infoframe(sd, &cri[i]);
2604 }
2605
2606 #if 0
2607 /* Let's keep it here for now, as it could be useful for debug */
2608 static const char * const prim_mode_txt[] = {
2609 "SDP",
2610 "Component",
2611 "Graphics",
2612 "Reserved",
2613 "CVBS & HDMI AUDIO",
2614 "HDMI-Comp",
2615 "HDMI-GR",
2616 "Reserved",
2617 "Reserved",
2618 "Reserved",
2619 "Reserved",
2620 "Reserved",
2621 "Reserved",
2622 "Reserved",
2623 "Reserved",
2624 "Reserved",
2625 };
2626 #endif
2627
2628 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2629 {
2630 /* SDP (Standard definition processor) block */
2631 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2632
2633 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2634 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2635 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2636
2637 v4l2_info(sd, "SDP: free run: %s\n",
2638 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2639 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2640 "valid SD/PR signal detected" : "invalid/no signal");
2641 if (sdp_signal_detected) {
2642 static const char * const sdp_std_txt[] = {
2643 "NTSC-M/J",
2644 "1?",
2645 "NTSC-443",
2646 "60HzSECAM",
2647 "PAL-M",
2648 "5?",
2649 "PAL-60",
2650 "7?", "8?", "9?", "a?", "b?",
2651 "PAL-CombN",
2652 "d?",
2653 "PAL-BGHID",
2654 "SECAM"
2655 };
2656 v4l2_info(sd, "SDP: standard %s\n",
2657 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2658 v4l2_info(sd, "SDP: %s\n",
2659 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2660 v4l2_info(sd, "SDP: %s\n",
2661 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2662 v4l2_info(sd, "SDP: deinterlacer %s\n",
2663 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2664 v4l2_info(sd, "SDP: csc %s mode\n",
2665 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2666 }
2667 return 0;
2668 }
2669
2670 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2671 {
2672 /* CP block */
2673 struct adv7842_state *state = to_state(sd);
2674 struct v4l2_dv_timings timings;
2675 u8 reg_io_0x02 = io_read(sd, 0x02);
2676 u8 reg_io_0x21 = io_read(sd, 0x21);
2677 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2678 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2679 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2680 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2681 bool audio_mute = io_read(sd, 0x65) & 0x40;
2682
2683 static const char * const csc_coeff_sel_rb[16] = {
2684 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2685 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2686 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2687 "reserved", "reserved", "reserved", "reserved", "manual"
2688 };
2689 static const char * const input_color_space_txt[16] = {
2690 "RGB limited range (16-235)", "RGB full range (0-255)",
2691 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2692 "xvYCC Bt.601", "xvYCC Bt.709",
2693 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2694 "invalid", "invalid", "invalid", "invalid", "invalid",
2695 "invalid", "invalid", "automatic"
2696 };
2697 static const char * const rgb_quantization_range_txt[] = {
2698 "Automatic",
2699 "RGB limited range (16-235)",
2700 "RGB full range (0-255)",
2701 };
2702 static const char * const deep_color_mode_txt[4] = {
2703 "8-bits per channel",
2704 "10-bits per channel",
2705 "12-bits per channel",
2706 "16-bits per channel (not supported)"
2707 };
2708
2709 v4l2_info(sd, "-----Chip status-----\n");
2710 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2711 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2712 state->hdmi_port_a ? "A" : "B");
2713 v4l2_info(sd, "EDID A %s, B %s\n",
2714 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2715 "enabled" : "disabled",
2716 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2717 "enabled" : "disabled");
2718 v4l2_info(sd, "HPD A %s, B %s\n",
2719 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2720 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2721 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2722 "enabled" : "disabled");
2723 if (state->cec_enabled_adap) {
2724 int i;
2725
2726 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2727 bool is_valid = state->cec_valid_addrs & (1 << i);
2728
2729 if (is_valid)
2730 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2731 state->cec_addr[i]);
2732 }
2733 }
2734
2735 v4l2_info(sd, "-----Signal status-----\n");
2736 if (state->hdmi_port_a) {
2737 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2738 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2739 v4l2_info(sd, "TMDS signal detected: %s\n",
2740 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2741 v4l2_info(sd, "TMDS signal locked: %s\n",
2742 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2743 } else {
2744 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2745 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2746 v4l2_info(sd, "TMDS signal detected: %s\n",
2747 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2748 v4l2_info(sd, "TMDS signal locked: %s\n",
2749 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2750 }
2751 v4l2_info(sd, "CP free run: %s\n",
2752 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2753 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2754 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2755 (io_read(sd, 0x01) & 0x70) >> 4);
2756
2757 v4l2_info(sd, "-----Video Timings-----\n");
2758 if (no_cp_signal(sd)) {
2759 v4l2_info(sd, "STDI: not locked\n");
2760 } else {
2761 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2762 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2763 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2764 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2765 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2766 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2767 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2768 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2769 v4l2_info(sd,
2770 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2771 lcf, bl, lcvs, fcl,
2772 (cp_read(sd, 0xb1) & 0x40) ?
2773 "interlaced" : "progressive",
2774 hs_pol, vs_pol);
2775 }
2776 if (adv7842_query_dv_timings(sd, &timings))
2777 v4l2_info(sd, "No video detected\n");
2778 else
2779 v4l2_print_dv_timings(sd->name, "Detected format: ",
2780 &timings, true);
2781 v4l2_print_dv_timings(sd->name, "Configured format: ",
2782 &state->timings, true);
2783
2784 if (no_cp_signal(sd))
2785 return 0;
2786
2787 v4l2_info(sd, "-----Color space-----\n");
2788 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2789 rgb_quantization_range_txt[state->rgb_quantization_range]);
2790 v4l2_info(sd, "Input color space: %s\n",
2791 input_color_space_txt[reg_io_0x02 >> 4]);
2792 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2793 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2794 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2795 "(16-235)" : "(0-255)",
2796 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2797 v4l2_info(sd, "Color space conversion: %s\n",
2798 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2799
2800 if (!is_digital_input(sd))
2801 return 0;
2802
2803 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2804 v4l2_info(sd, "HDCP encrypted content: %s\n",
2805 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2806 v4l2_info(sd, "HDCP keys read: %s%s\n",
2807 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2808 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2809 if (!is_hdmi(sd))
2810 return 0;
2811
2812 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2813 audio_pll_locked ? "locked" : "not locked",
2814 audio_sample_packet_detect ? "detected" : "not detected",
2815 audio_mute ? "muted" : "enabled");
2816 if (audio_pll_locked && audio_sample_packet_detect) {
2817 v4l2_info(sd, "Audio format: %s\n",
2818 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2819 }
2820 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2821 (hdmi_read(sd, 0x5c) << 8) +
2822 (hdmi_read(sd, 0x5d) & 0xf0));
2823 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2824 (hdmi_read(sd, 0x5e) << 8) +
2825 hdmi_read(sd, 0x5f));
2826 v4l2_info(sd, "AV Mute: %s\n",
2827 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2828 v4l2_info(sd, "Deep color mode: %s\n",
2829 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2830
2831 adv7842_log_infoframes(sd);
2832
2833 return 0;
2834 }
2835
2836 static int adv7842_log_status(struct v4l2_subdev *sd)
2837 {
2838 struct adv7842_state *state = to_state(sd);
2839
2840 if (state->mode == ADV7842_MODE_SDP)
2841 return adv7842_sdp_log_status(sd);
2842 return adv7842_cp_log_status(sd);
2843 }
2844
2845 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2846 {
2847 struct adv7842_state *state = to_state(sd);
2848
2849 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2850
2851 if (state->mode != ADV7842_MODE_SDP)
2852 return -ENODATA;
2853
2854 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2855 *std = 0;
2856 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2857 return 0;
2858 }
2859
2860 switch (sdp_read(sd, 0x52) & 0x0f) {
2861 case 0:
2862 /* NTSC-M/J */
2863 *std &= V4L2_STD_NTSC;
2864 break;
2865 case 2:
2866 /* NTSC-443 */
2867 *std &= V4L2_STD_NTSC_443;
2868 break;
2869 case 3:
2870 /* 60HzSECAM */
2871 *std &= V4L2_STD_SECAM;
2872 break;
2873 case 4:
2874 /* PAL-M */
2875 *std &= V4L2_STD_PAL_M;
2876 break;
2877 case 6:
2878 /* PAL-60 */
2879 *std &= V4L2_STD_PAL_60;
2880 break;
2881 case 0xc:
2882 /* PAL-CombN */
2883 *std &= V4L2_STD_PAL_Nc;
2884 break;
2885 case 0xe:
2886 /* PAL-BGHID */
2887 *std &= V4L2_STD_PAL;
2888 break;
2889 case 0xf:
2890 /* SECAM */
2891 *std &= V4L2_STD_SECAM;
2892 break;
2893 default:
2894 *std &= V4L2_STD_ALL;
2895 break;
2896 }
2897 return 0;
2898 }
2899
2900 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2901 {
2902 if (s && s->adjust) {
2903 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2904 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2905 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2906 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2907 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2908 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2909 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2910 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2911 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2912 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2913 sdp_io_write(sd, 0xaa, s->vs_end_o);
2914 sdp_io_write(sd, 0xab, s->vs_end_e);
2915 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2916 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2917 sdp_io_write(sd, 0xae, s->de_v_end_o);
2918 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2919 } else {
2920 /* set to default */
2921 sdp_io_write(sd, 0x94, 0x00);
2922 sdp_io_write(sd, 0x95, 0x00);
2923 sdp_io_write(sd, 0x96, 0x00);
2924 sdp_io_write(sd, 0x97, 0x20);
2925 sdp_io_write(sd, 0x98, 0x00);
2926 sdp_io_write(sd, 0x99, 0x00);
2927 sdp_io_write(sd, 0x9a, 0x00);
2928 sdp_io_write(sd, 0x9b, 0x00);
2929 sdp_io_write(sd, 0xa8, 0x04);
2930 sdp_io_write(sd, 0xa9, 0x04);
2931 sdp_io_write(sd, 0xaa, 0x04);
2932 sdp_io_write(sd, 0xab, 0x04);
2933 sdp_io_write(sd, 0xac, 0x04);
2934 sdp_io_write(sd, 0xad, 0x04);
2935 sdp_io_write(sd, 0xae, 0x04);
2936 sdp_io_write(sd, 0xaf, 0x04);
2937 }
2938 }
2939
2940 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2941 {
2942 struct adv7842_state *state = to_state(sd);
2943 struct adv7842_platform_data *pdata = &state->pdata;
2944
2945 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2946
2947 if (state->mode != ADV7842_MODE_SDP)
2948 return -ENODATA;
2949
2950 if (norm & V4L2_STD_625_50)
2951 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2952 else if (norm & V4L2_STD_525_60)
2953 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2954 else
2955 adv7842_s_sdp_io(sd, NULL);
2956
2957 if (norm & V4L2_STD_ALL) {
2958 state->norm = norm;
2959 return 0;
2960 }
2961 return -EINVAL;
2962 }
2963
2964 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2965 {
2966 struct adv7842_state *state = to_state(sd);
2967
2968 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2969
2970 if (state->mode != ADV7842_MODE_SDP)
2971 return -ENODATA;
2972
2973 *norm = state->norm;
2974 return 0;
2975 }
2976
2977 /* ----------------------------------------------------------------------- */
2978
2979 static int adv7842_core_init(struct v4l2_subdev *sd)
2980 {
2981 struct adv7842_state *state = to_state(sd);
2982 struct adv7842_platform_data *pdata = &state->pdata;
2983 hdmi_write(sd, 0x48,
2984 (pdata->disable_pwrdnb ? 0x80 : 0) |
2985 (pdata->disable_cable_det_rst ? 0x40 : 0));
2986
2987 disable_input(sd);
2988
2989 /*
2990 * Disable I2C access to internal EDID ram from HDMI DDC ports
2991 * Disable auto edid enable when leaving powerdown mode
2992 */
2993 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2994
2995 /* power */
2996 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2997 io_write(sd, 0x15, 0x80); /* Power up pads */
2998
2999 /* video format */
3000 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
3001 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3002 pdata->insert_av_codes << 2 |
3003 pdata->replicate_av_codes << 1);
3004 adv7842_setup_format(state);
3005
3006 /* HDMI audio */
3007 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3008
3009 /* Drive strength */
3010 io_write_and_or(sd, 0x14, 0xc0,
3011 pdata->dr_str_data << 4 |
3012 pdata->dr_str_clk << 2 |
3013 pdata->dr_str_sync);
3014
3015 /* HDMI free run */
3016 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3017 (pdata->hdmi_free_run_mode << 1));
3018
3019 /* SPD free run */
3020 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3021 (pdata->sdp_free_run_cbar_en << 1) |
3022 (pdata->sdp_free_run_man_col_en << 2) |
3023 (pdata->sdp_free_run_auto << 3));
3024
3025 /* TODO from platform data */
3026 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3027 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3028 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3029 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3030
3031 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3032 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3033
3034 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3035
3036 /* todo, improve settings for sdram */
3037 if (pdata->sd_ram_size >= 128) {
3038 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3039 if (pdata->sd_ram_ddr) {
3040 /* SDP setup for the AD eval board */
3041 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3042 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3043 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3044 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3045 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3046 } else {
3047 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3048 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3049 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3050 depends on memory */
3051 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3052 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3053 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3054 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3055 }
3056 } else {
3057 /*
3058 * Manual UG-214, rev 0 is bit confusing on this bit
3059 * but a '1' disables any signal if the Ram is active.
3060 */
3061 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3062 }
3063
3064 select_input(sd, pdata->vid_std_select);
3065
3066 enable_input(sd);
3067
3068 if (pdata->hpa_auto) {
3069 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
3070 hdmi_write(sd, 0x69, 0x5c);
3071 } else {
3072 /* HPA manual */
3073 hdmi_write(sd, 0x69, 0xa3);
3074 /* HPA disable on port A and B */
3075 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3076 }
3077
3078 /* LLC */
3079 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3080 io_write(sd, 0x33, 0x40);
3081
3082 /* interrupts */
3083 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3084
3085 adv7842_irq_enable(sd, true);
3086
3087 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3088 }
3089
3090 /* ----------------------------------------------------------------------- */
3091
3092 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3093 {
3094 /*
3095 * From ADV784x external Memory test.pdf
3096 *
3097 * Reset must just been performed before running test.
3098 * Recommended to reset after test.
3099 */
3100 int i;
3101 int pass = 0;
3102 int fail = 0;
3103 int complete = 0;
3104
3105 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3106 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3107 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
3108 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
3109 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
3110 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
3111 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
3112 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3113 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3114 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3115 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3116 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3117
3118 mdelay(5);
3119
3120 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3121 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3122 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3123 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3124 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3125 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3126 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3127 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3128 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3129 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3130 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3131
3132 mdelay(5);
3133
3134 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3135 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3136
3137 mdelay(20);
3138
3139 for (i = 0; i < 10; i++) {
3140 u8 result = sdp_io_read(sd, 0xdb);
3141 if (result & 0x10) {
3142 complete++;
3143 if (result & 0x20)
3144 fail++;
3145 else
3146 pass++;
3147 }
3148 mdelay(20);
3149 }
3150
3151 v4l2_dbg(1, debug, sd,
3152 "Ram Test: completed %d of %d: pass %d, fail %d\n",
3153 complete, i, pass, fail);
3154
3155 if (!complete || fail)
3156 return -EIO;
3157 return 0;
3158 }
3159
3160 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3161 struct adv7842_platform_data *pdata)
3162 {
3163 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3164 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3165 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3166 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3167 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3168
3169 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3170 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3171 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3172 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3173
3174 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3175 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3176 }
3177
3178 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3179 {
3180 struct i2c_client *client = v4l2_get_subdevdata(sd);
3181 struct adv7842_state *state = to_state(sd);
3182 struct adv7842_platform_data *pdata = client->dev.platform_data;
3183 struct v4l2_dv_timings timings;
3184 int ret = 0;
3185
3186 if (!pdata)
3187 return -ENODEV;
3188
3189 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3190 v4l2_info(sd, "no sdram or no ddr sdram\n");
3191 return -EINVAL;
3192 }
3193
3194 main_reset(sd);
3195
3196 adv7842_rewrite_i2c_addresses(sd, pdata);
3197
3198 /* run ram test */
3199 ret = adv7842_ddr_ram_test(sd);
3200
3201 main_reset(sd);
3202
3203 adv7842_rewrite_i2c_addresses(sd, pdata);
3204
3205 /* and re-init chip and state */
3206 adv7842_core_init(sd);
3207
3208 disable_input(sd);
3209
3210 select_input(sd, state->vid_std_select);
3211
3212 enable_input(sd);
3213
3214 edid_write_vga_segment(sd);
3215 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3216 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3217
3218 timings = state->timings;
3219
3220 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3221
3222 adv7842_s_dv_timings(sd, &timings);
3223
3224 return ret;
3225 }
3226
3227 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3228 {
3229 switch (cmd) {
3230 case ADV7842_CMD_RAM_TEST:
3231 return adv7842_command_ram_test(sd);
3232 }
3233 return -ENOTTY;
3234 }
3235
3236 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3237 struct v4l2_fh *fh,
3238 struct v4l2_event_subscription *sub)
3239 {
3240 switch (sub->type) {
3241 case V4L2_EVENT_SOURCE_CHANGE:
3242 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3243 case V4L2_EVENT_CTRL:
3244 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3245 default:
3246 return -EINVAL;
3247 }
3248 }
3249
3250 static int adv7842_registered(struct v4l2_subdev *sd)
3251 {
3252 struct adv7842_state *state = to_state(sd);
3253 struct i2c_client *client = v4l2_get_subdevdata(sd);
3254 int err;
3255
3256 err = cec_register_adapter(state->cec_adap, &client->dev);
3257 if (err)
3258 cec_delete_adapter(state->cec_adap);
3259 return err;
3260 }
3261
3262 static void adv7842_unregistered(struct v4l2_subdev *sd)
3263 {
3264 struct adv7842_state *state = to_state(sd);
3265
3266 cec_unregister_adapter(state->cec_adap);
3267 }
3268
3269 /* ----------------------------------------------------------------------- */
3270
3271 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3272 .s_ctrl = adv7842_s_ctrl,
3273 .g_volatile_ctrl = adv7842_g_volatile_ctrl,
3274 };
3275
3276 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3277 .log_status = adv7842_log_status,
3278 .ioctl = adv7842_ioctl,
3279 .interrupt_service_routine = adv7842_isr,
3280 .subscribe_event = adv7842_subscribe_event,
3281 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3282 #ifdef CONFIG_VIDEO_ADV_DEBUG
3283 .g_register = adv7842_g_register,
3284 .s_register = adv7842_s_register,
3285 #endif
3286 };
3287
3288 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3289 .g_std = adv7842_g_std,
3290 .s_std = adv7842_s_std,
3291 .s_routing = adv7842_s_routing,
3292 .querystd = adv7842_querystd,
3293 .g_input_status = adv7842_g_input_status,
3294 .s_dv_timings = adv7842_s_dv_timings,
3295 .g_dv_timings = adv7842_g_dv_timings,
3296 .query_dv_timings = adv7842_query_dv_timings,
3297 };
3298
3299 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3300 .enum_mbus_code = adv7842_enum_mbus_code,
3301 .get_fmt = adv7842_get_format,
3302 .set_fmt = adv7842_set_format,
3303 .get_edid = adv7842_get_edid,
3304 .set_edid = adv7842_set_edid,
3305 .enum_dv_timings = adv7842_enum_dv_timings,
3306 .dv_timings_cap = adv7842_dv_timings_cap,
3307 };
3308
3309 static const struct v4l2_subdev_ops adv7842_ops = {
3310 .core = &adv7842_core_ops,
3311 .video = &adv7842_video_ops,
3312 .pad = &adv7842_pad_ops,
3313 };
3314
3315 static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3316 .registered = adv7842_registered,
3317 .unregistered = adv7842_unregistered,
3318 };
3319
3320 /* -------------------------- custom ctrls ---------------------------------- */
3321
3322 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3323 .ops = &adv7842_ctrl_ops,
3324 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3325 .name = "Analog Sampling Phase",
3326 .type = V4L2_CTRL_TYPE_INTEGER,
3327 .min = 0,
3328 .max = 0x1f,
3329 .step = 1,
3330 .def = 0,
3331 };
3332
3333 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3334 .ops = &adv7842_ctrl_ops,
3335 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3336 .name = "Free Running Color, Manual",
3337 .type = V4L2_CTRL_TYPE_BOOLEAN,
3338 .max = 1,
3339 .step = 1,
3340 .def = 1,
3341 };
3342
3343 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3344 .ops = &adv7842_ctrl_ops,
3345 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3346 .name = "Free Running Color",
3347 .type = V4L2_CTRL_TYPE_INTEGER,
3348 .max = 0xffffff,
3349 .step = 0x1,
3350 };
3351
3352
3353 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3354 {
3355 struct adv7842_state *state = to_state(sd);
3356 if (state->i2c_avlink)
3357 i2c_unregister_device(state->i2c_avlink);
3358 if (state->i2c_cec)
3359 i2c_unregister_device(state->i2c_cec);
3360 if (state->i2c_infoframe)
3361 i2c_unregister_device(state->i2c_infoframe);
3362 if (state->i2c_sdp_io)
3363 i2c_unregister_device(state->i2c_sdp_io);
3364 if (state->i2c_sdp)
3365 i2c_unregister_device(state->i2c_sdp);
3366 if (state->i2c_afe)
3367 i2c_unregister_device(state->i2c_afe);
3368 if (state->i2c_repeater)
3369 i2c_unregister_device(state->i2c_repeater);
3370 if (state->i2c_edid)
3371 i2c_unregister_device(state->i2c_edid);
3372 if (state->i2c_hdmi)
3373 i2c_unregister_device(state->i2c_hdmi);
3374 if (state->i2c_cp)
3375 i2c_unregister_device(state->i2c_cp);
3376 if (state->i2c_vdp)
3377 i2c_unregister_device(state->i2c_vdp);
3378
3379 state->i2c_avlink = NULL;
3380 state->i2c_cec = NULL;
3381 state->i2c_infoframe = NULL;
3382 state->i2c_sdp_io = NULL;
3383 state->i2c_sdp = NULL;
3384 state->i2c_afe = NULL;
3385 state->i2c_repeater = NULL;
3386 state->i2c_edid = NULL;
3387 state->i2c_hdmi = NULL;
3388 state->i2c_cp = NULL;
3389 state->i2c_vdp = NULL;
3390 }
3391
3392 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3393 u8 addr, u8 io_reg)
3394 {
3395 struct i2c_client *client = v4l2_get_subdevdata(sd);
3396 struct i2c_client *cp;
3397
3398 io_write(sd, io_reg, addr << 1);
3399
3400 if (addr == 0) {
3401 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3402 return NULL;
3403 }
3404
3405 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3406 if (!cp)
3407 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3408
3409 return cp;
3410 }
3411
3412 static int adv7842_register_clients(struct v4l2_subdev *sd)
3413 {
3414 struct adv7842_state *state = to_state(sd);
3415 struct adv7842_platform_data *pdata = &state->pdata;
3416
3417 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3418 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3419 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3420 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3421 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3422 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3423 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3424 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3425 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3426 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3427 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3428
3429 if (!state->i2c_avlink ||
3430 !state->i2c_cec ||
3431 !state->i2c_infoframe ||
3432 !state->i2c_sdp_io ||
3433 !state->i2c_sdp ||
3434 !state->i2c_afe ||
3435 !state->i2c_repeater ||
3436 !state->i2c_edid ||
3437 !state->i2c_hdmi ||
3438 !state->i2c_cp ||
3439 !state->i2c_vdp)
3440 return -1;
3441
3442 return 0;
3443 }
3444
3445 static int adv7842_probe(struct i2c_client *client,
3446 const struct i2c_device_id *id)
3447 {
3448 struct adv7842_state *state;
3449 static const struct v4l2_dv_timings cea640x480 =
3450 V4L2_DV_BT_CEA_640X480P59_94;
3451 struct adv7842_platform_data *pdata = client->dev.platform_data;
3452 struct v4l2_ctrl_handler *hdl;
3453 struct v4l2_ctrl *ctrl;
3454 struct v4l2_subdev *sd;
3455 u16 rev;
3456 int err;
3457
3458 /* Check if the adapter supports the needed features */
3459 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3460 return -EIO;
3461
3462 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3463 client->addr << 1);
3464
3465 if (!pdata) {
3466 v4l_err(client, "No platform data!\n");
3467 return -ENODEV;
3468 }
3469
3470 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3471 if (!state) {
3472 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3473 return -ENOMEM;
3474 }
3475
3476 /* platform data */
3477 state->pdata = *pdata;
3478 state->timings = cea640x480;
3479 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3480
3481 sd = &state->sd;
3482 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3483 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3484 sd->internal_ops = &adv7842_int_ops;
3485 state->mode = pdata->mode;
3486
3487 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3488 state->restart_stdi_once = true;
3489
3490 /* i2c access to adv7842? */
3491 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3492 adv_smbus_read_byte_data_check(client, 0xeb, false);
3493 if (rev != 0x2012) {
3494 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3495 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3496 adv_smbus_read_byte_data_check(client, 0xeb, false);
3497 }
3498 if (rev != 0x2012) {
3499 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3500 client->addr << 1, rev);
3501 return -ENODEV;
3502 }
3503
3504 if (pdata->chip_reset)
3505 main_reset(sd);
3506
3507 /* control handlers */
3508 hdl = &state->hdl;
3509 v4l2_ctrl_handler_init(hdl, 6);
3510
3511 /* add in ascending ID order */
3512 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3513 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3514 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3515 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3516 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3517 V4L2_CID_SATURATION, 0, 255, 1, 128);
3518 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3519 V4L2_CID_HUE, 0, 128, 1, 0);
3520 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3521 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3522 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3523 if (ctrl)
3524 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3525
3526 /* custom controls */
3527 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3528 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3529 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3530 &adv7842_ctrl_analog_sampling_phase, NULL);
3531 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3532 &adv7842_ctrl_free_run_color_manual, NULL);
3533 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3534 &adv7842_ctrl_free_run_color, NULL);
3535 state->rgb_quantization_range_ctrl =
3536 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3537 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3538 0, V4L2_DV_RGB_RANGE_AUTO);
3539 sd->ctrl_handler = hdl;
3540 if (hdl->error) {
3541 err = hdl->error;
3542 goto err_hdl;
3543 }
3544 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3545 err = -ENODEV;
3546 goto err_hdl;
3547 }
3548
3549 if (adv7842_register_clients(sd) < 0) {
3550 err = -ENOMEM;
3551 v4l2_err(sd, "failed to create all i2c clients\n");
3552 goto err_i2c;
3553 }
3554
3555
3556 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3557 adv7842_delayed_work_enable_hotplug);
3558
3559 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3560 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
3561 if (err)
3562 goto err_work_queues;
3563
3564 err = adv7842_core_init(sd);
3565 if (err)
3566 goto err_entity;
3567
3568 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3569 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3570 state, dev_name(&client->dev),
3571 CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
3572 CEC_CAP_PASSTHROUGH | CEC_CAP_RC, ADV7842_MAX_ADDRS);
3573 err = PTR_ERR_OR_ZERO(state->cec_adap);
3574 if (err)
3575 goto err_entity;
3576 #endif
3577
3578 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3579 client->addr << 1, client->adapter->name);
3580 return 0;
3581
3582 err_entity:
3583 media_entity_cleanup(&sd->entity);
3584 err_work_queues:
3585 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3586 err_i2c:
3587 adv7842_unregister_clients(sd);
3588 err_hdl:
3589 v4l2_ctrl_handler_free(hdl);
3590 return err;
3591 }
3592
3593 /* ----------------------------------------------------------------------- */
3594
3595 static int adv7842_remove(struct i2c_client *client)
3596 {
3597 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3598 struct adv7842_state *state = to_state(sd);
3599
3600 adv7842_irq_enable(sd, false);
3601 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3602 v4l2_device_unregister_subdev(sd);
3603 media_entity_cleanup(&sd->entity);
3604 adv7842_unregister_clients(sd);
3605 v4l2_ctrl_handler_free(sd->ctrl_handler);
3606 return 0;
3607 }
3608
3609 /* ----------------------------------------------------------------------- */
3610
3611 static struct i2c_device_id adv7842_id[] = {
3612 { "adv7842", 0 },
3613 { }
3614 };
3615 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3616
3617 /* ----------------------------------------------------------------------- */
3618
3619 static struct i2c_driver adv7842_driver = {
3620 .driver = {
3621 .name = "adv7842",
3622 },
3623 .probe = adv7842_probe,
3624 .remove = adv7842_remove,
3625 .id_table = adv7842_id,
3626 };
3627
3628 module_i2c_driver(adv7842_driver);
Linux with added FPC-III support