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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / pci / cx18 / cx18-mailbox.c
blobd3cf3588879f5740aa16fff3f04c487182a21b66
1 /*
2 * cx18 mailbox functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307 USA
21 */
22
23 #include <stdarg.h>
24
25 #include "cx18-driver.h"
26 #include "cx18-io.h"
27 #include "cx18-scb.h"
28 #include "cx18-irq.h"
29 #include "cx18-mailbox.h"
30 #include "cx18-queue.h"
31 #include "cx18-streams.h"
32 #include "cx18-alsa-pcm.h" /* FIXME make configurable */
33
34 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
35
36 #define API_FAST (1 << 2) /* Short timeout */
37 #define API_SLOW (1 << 3) /* Additional 300ms timeout */
38
39 struct cx18_api_info {
40 u32 cmd;
41 u8 flags; /* Flags, see above */
42 u8 rpu; /* Processing unit */
43 const char *name; /* The name of the command */
44 };
45
46 #define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
47
48 static const struct cx18_api_info api_info[] = {
49 /* MPEG encoder API */
50 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
51 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
52 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
53 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
57 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
70 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
71 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
72 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
81 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
82 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
83 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
84 API_ENTRY(CPU, CX18_CPU_SET_VFC_PARAM, 0),
85 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
86 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
87 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
88 API_ENTRY(APU, CX18_APU_START, 0),
89 API_ENTRY(APU, CX18_APU_STOP, 0),
90 API_ENTRY(APU, CX18_APU_RESETAI, 0),
91 API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
92 API_ENTRY(0, 0, 0),
93 };
94
95 static const struct cx18_api_info *find_api_info(u32 cmd)
96 {
97 int i;
98
99 for (i = 0; api_info[i].cmd; i++)
100 if (api_info[i].cmd == cmd)
101 return &api_info[i];
102 return NULL;
103 }
104
105 /* Call with buf of n*11+1 bytes */
106 static char *u32arr2hex(u32 data[], int n, char *buf)
107 {
108 char *p;
109 int i;
110
111 for (i = 0, p = buf; i < n; i++, p += 11) {
112 /* kernel snprintf() appends '\0' always */
113 snprintf(p, 12, " %#010x", data[i]);
114 }
115 *p = '\0';
116 return buf;
117 }
118
119 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
120 {
121 char argstr[MAX_MB_ARGUMENTS*11+1];
122
123 if (!(cx18_debug & CX18_DBGFLG_API))
124 return;
125
126 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s\n",
127 name, mb->request, mb->ack, mb->cmd, mb->error,
128 u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
129 }
130
131
132 /*
133 * Functions that run in a work_queue work handling context
134 */
135
136 static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
137 {
138 struct cx18_buffer *buf;
139
140 if (s->dvb == NULL || !s->dvb->enabled || mdl->bytesused == 0)
141 return;
142
143 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
144
145 /* The likely case */
146 if (list_is_singular(&mdl->buf_list)) {
147 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
148 list);
149 if (buf->bytesused)
150 dvb_dmx_swfilter(&s->dvb->demux,
151 buf->buf, buf->bytesused);
152 return;
153 }
154
155 list_for_each_entry(buf, &mdl->buf_list, list) {
156 if (buf->bytesused == 0)
157 break;
158 dvb_dmx_swfilter(&s->dvb->demux, buf->buf, buf->bytesused);
159 }
160 }
161
162 static void cx18_mdl_send_to_videobuf(struct cx18_stream *s,
163 struct cx18_mdl *mdl)
164 {
165 struct cx18_videobuf_buffer *vb_buf;
166 struct cx18_buffer *buf;
167 u8 *p;
168 u32 offset = 0;
169 int dispatch = 0;
170
171 if (mdl->bytesused == 0)
172 return;
173
174 /* Acquire a videobuf buffer, clone to and and release it */
175 spin_lock(&s->vb_lock);
176 if (list_empty(&s->vb_capture))
177 goto out;
178
179 vb_buf = list_first_entry(&s->vb_capture, struct cx18_videobuf_buffer,
180 vb.queue);
181
182 p = videobuf_to_vmalloc(&vb_buf->vb);
183 if (!p)
184 goto out;
185
186 offset = vb_buf->bytes_used;
187 list_for_each_entry(buf, &mdl->buf_list, list) {
188 if (buf->bytesused == 0)
189 break;
190
191 if ((offset + buf->bytesused) <= vb_buf->vb.bsize) {
192 memcpy(p + offset, buf->buf, buf->bytesused);
193 offset += buf->bytesused;
194 vb_buf->bytes_used += buf->bytesused;
195 }
196 }
197
198 /* If we've filled the buffer as per the callers res then dispatch it */
199 if (vb_buf->bytes_used >= s->vb_bytes_per_frame) {
200 dispatch = 1;
201 vb_buf->bytes_used = 0;
202 }
203
204 if (dispatch) {
205 v4l2_get_timestamp(&vb_buf->vb.ts);
206 list_del(&vb_buf->vb.queue);
207 vb_buf->vb.state = VIDEOBUF_DONE;
208 wake_up(&vb_buf->vb.done);
209 }
210
211 mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
212
213 out:
214 spin_unlock(&s->vb_lock);
215 }
216
217 static void cx18_mdl_send_to_alsa(struct cx18 *cx, struct cx18_stream *s,
218 struct cx18_mdl *mdl)
219 {
220 struct cx18_buffer *buf;
221
222 if (mdl->bytesused == 0)
223 return;
224
225 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
226
227 /* The likely case */
228 if (list_is_singular(&mdl->buf_list)) {
229 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
230 list);
231 if (buf->bytesused)
232 cx->pcm_announce_callback(cx->alsa, buf->buf,
233 buf->bytesused);
234 return;
235 }
236
237 list_for_each_entry(buf, &mdl->buf_list, list) {
238 if (buf->bytesused == 0)
239 break;
240 cx->pcm_announce_callback(cx->alsa, buf->buf, buf->bytesused);
241 }
242 }
243
244 static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
245 {
246 u32 handle, mdl_ack_count, id;
247 struct cx18_mailbox *mb;
248 struct cx18_mdl_ack *mdl_ack;
249 struct cx18_stream *s;
250 struct cx18_mdl *mdl;
251 int i;
252
253 mb = &order->mb;
254 handle = mb->args[0];
255 s = cx18_handle_to_stream(cx, handle);
256
257 if (s == NULL) {
258 CX18_WARN("Got DMA done notification for unknown/inactive handle %d, %s mailbox seq no %d\n",
259 handle,
260 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
261 "stale" : "good", mb->request);
262 return;
263 }
264
265 mdl_ack_count = mb->args[2];
266 mdl_ack = order->mdl_ack;
267 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
268 id = mdl_ack->id;
269 /*
270 * Simple integrity check for processing a stale (and possibly
271 * inconsistent mailbox): make sure the MDL id is in the
272 * valid range for the stream.
273 *
274 * We go through the trouble of dealing with stale mailboxes
275 * because most of the time, the mailbox data is still valid and
276 * unchanged (and in practice the firmware ping-pongs the
277 * two mdl_ack buffers so mdl_acks are not stale).
278 *
279 * There are occasions when we get a half changed mailbox,
280 * which this check catches for a handle & id mismatch. If the
281 * handle and id do correspond, the worst case is that we
282 * completely lost the old MDL, but pick up the new MDL
283 * early (but the new mdl_ack is guaranteed to be good in this
284 * case as the firmware wouldn't point us to a new mdl_ack until
285 * it's filled in).
286 *
287 * cx18_queue_get_mdl() will detect the lost MDLs
288 * and send them back to q_free for fw rotation eventually.
289 */
290 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
291 !(id >= s->mdl_base_idx &&
292 id < (s->mdl_base_idx + s->buffers))) {
293 CX18_WARN("Fell behind! Ignoring stale mailbox with inconsistent data. Lost MDL for mailbox seq no %d\n",
294 mb->request);
295 break;
296 }
297 mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
298
299 CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
300 if (mdl == NULL) {
301 CX18_WARN("Could not find MDL %d for stream %s\n",
302 id, s->name);
303 continue;
304 }
305
306 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
307 s->name, mdl->bytesused);
308
309 if (s->type == CX18_ENC_STREAM_TYPE_TS) {
310 cx18_mdl_send_to_dvb(s, mdl);
311 cx18_enqueue(s, mdl, &s->q_free);
312 } else if (s->type == CX18_ENC_STREAM_TYPE_PCM) {
313 /* Pass the data to cx18-alsa */
314 if (cx->pcm_announce_callback != NULL) {
315 cx18_mdl_send_to_alsa(cx, s, mdl);
316 cx18_enqueue(s, mdl, &s->q_free);
317 } else {
318 cx18_enqueue(s, mdl, &s->q_full);
319 }
320 } else if (s->type == CX18_ENC_STREAM_TYPE_YUV) {
321 cx18_mdl_send_to_videobuf(s, mdl);
322 cx18_enqueue(s, mdl, &s->q_free);
323 } else {
324 cx18_enqueue(s, mdl, &s->q_full);
325 if (s->type == CX18_ENC_STREAM_TYPE_IDX)
326 cx18_stream_rotate_idx_mdls(cx);
327 }
328 }
329 /* Put as many MDLs as possible back into fw use */
330 cx18_stream_load_fw_queue(s);
331
332 wake_up(&cx->dma_waitq);
333 if (s->id != -1)
334 wake_up(&s->waitq);
335 }
336
337 static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
338 {
339 char *p;
340 char *str = order->str;
341
342 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
343 p = strchr(str, '.');
344 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
345 CX18_INFO("FW version: %s\n", p - 1);
346 }
347
348 static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
349 {
350 switch (order->rpu) {
351 case CPU:
352 {
353 switch (order->mb.cmd) {
354 case CX18_EPU_DMA_DONE:
355 epu_dma_done(cx, order);
356 break;
357 case CX18_EPU_DEBUG:
358 epu_debug(cx, order);
359 break;
360 default:
361 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
362 order->mb.cmd);
363 break;
364 }
365 break;
366 }
367 case APU:
368 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
369 order->mb.cmd);
370 break;
371 default:
372 break;
373 }
374 }
375
376 static
377 void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
378 {
379 atomic_set(&order->pending, 0);
380 }
381
382 void cx18_in_work_handler(struct work_struct *work)
383 {
384 struct cx18_in_work_order *order =
385 container_of(work, struct cx18_in_work_order, work);
386 struct cx18 *cx = order->cx;
387 epu_cmd(cx, order);
388 free_in_work_order(cx, order);
389 }
390
391
392 /*
393 * Functions that run in an interrupt handling context
394 */
395
396 static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
397 {
398 struct cx18_mailbox __iomem *ack_mb;
399 u32 ack_irq, req;
400
401 switch (order->rpu) {
402 case APU:
403 ack_irq = IRQ_EPU_TO_APU_ACK;
404 ack_mb = &cx->scb->apu2epu_mb;
405 break;
406 case CPU:
407 ack_irq = IRQ_EPU_TO_CPU_ACK;
408 ack_mb = &cx->scb->cpu2epu_mb;
409 break;
410 default:
411 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
412 order->rpu, order->mb.cmd);
413 return;
414 }
415
416 req = order->mb.request;
417 /* Don't ack if the RPU has gotten impatient and timed us out */
418 if (req != cx18_readl(cx, &ack_mb->request) ||
419 req == cx18_readl(cx, &ack_mb->ack)) {
420 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u) while processing\n",
421 rpu_str[order->rpu], rpu_str[order->rpu], req);
422 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
423 return;
424 }
425 cx18_writel(cx, req, &ack_mb->ack);
426 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
427 return;
428 }
429
430 static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
431 {
432 u32 handle, mdl_ack_offset, mdl_ack_count;
433 struct cx18_mailbox *mb;
434 int i;
435
436 mb = &order->mb;
437 handle = mb->args[0];
438 mdl_ack_offset = mb->args[1];
439 mdl_ack_count = mb->args[2];
440
441 if (handle == CX18_INVALID_TASK_HANDLE ||
442 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
443 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
444 mb_ack_irq(cx, order);
445 return -1;
446 }
447
448 for (i = 0; i < sizeof(struct cx18_mdl_ack) * mdl_ack_count; i += sizeof(u32))
449 ((u32 *)order->mdl_ack)[i / sizeof(u32)] =
450 cx18_readl(cx, cx->enc_mem + mdl_ack_offset + i);
451
452 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
453 mb_ack_irq(cx, order);
454 return 1;
455 }
456
457 static
458 int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
459 {
460 u32 str_offset;
461 char *str = order->str;
462
463 str[0] = '\0';
464 str_offset = order->mb.args[1];
465 if (str_offset) {
466 cx18_setup_page(cx, str_offset);
467 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
468 str[252] = '\0';
469 cx18_setup_page(cx, SCB_OFFSET);
470 }
471
472 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
473 mb_ack_irq(cx, order);
474
475 return str_offset ? 1 : 0;
476 }
477
478 static inline
479 int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
480 {
481 int ret = -1;
482
483 switch (order->rpu) {
484 case CPU:
485 {
486 switch (order->mb.cmd) {
487 case CX18_EPU_DMA_DONE:
488 ret = epu_dma_done_irq(cx, order);
489 break;
490 case CX18_EPU_DEBUG:
491 ret = epu_debug_irq(cx, order);
492 break;
493 default:
494 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
495 order->mb.cmd);
496 break;
497 }
498 break;
499 }
500 case APU:
501 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
502 order->mb.cmd);
503 break;
504 default:
505 break;
506 }
507 return ret;
508 }
509
510 static inline
511 struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
512 {
513 int i;
514 struct cx18_in_work_order *order = NULL;
515
516 for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
517 /*
518 * We only need "pending" atomic to inspect its contents,
519 * and need not do a check and set because:
520 * 1. Any work handler thread only clears "pending" and only
521 * on one, particular work order at a time, per handler thread.
522 * 2. "pending" is only set here, and we're serialized because
523 * we're called in an IRQ handler context.
524 */
525 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
526 order = &cx->in_work_order[i];
527 atomic_set(&order->pending, 1);
528 break;
529 }
530 }
531 return order;
532 }
533
534 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
535 {
536 struct cx18_mailbox __iomem *mb;
537 struct cx18_mailbox *order_mb;
538 struct cx18_in_work_order *order;
539 int submit;
540 int i;
541
542 switch (rpu) {
543 case CPU:
544 mb = &cx->scb->cpu2epu_mb;
545 break;
546 case APU:
547 mb = &cx->scb->apu2epu_mb;
548 break;
549 default:
550 return;
551 }
552
553 order = alloc_in_work_order_irq(cx);
554 if (order == NULL) {
555 CX18_WARN("Unable to find blank work order form to schedule incoming mailbox command processing\n");
556 return;
557 }
558
559 order->flags = 0;
560 order->rpu = rpu;
561 order_mb = &order->mb;
562
563 /* mb->cmd and mb->args[0] through mb->args[2] */
564 for (i = 0; i < 4; i++)
565 (&order_mb->cmd)[i] = cx18_readl(cx, &mb->cmd + i);
566
567 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
568 for (i = 0; i < 2; i++)
569 (&order_mb->request)[i] = cx18_readl(cx, &mb->request + i);
570
571 if (order_mb->request == order_mb->ack) {
572 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our incoming %s to EPU mailbox (sequence no. %u)\n",
573 rpu_str[rpu], rpu_str[rpu], order_mb->request);
574 if (cx18_debug & CX18_DBGFLG_WARN)
575 dump_mb(cx, order_mb, "incoming");
576 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
577 }
578
579 /*
580 * Individual EPU command processing is responsible for ack-ing
581 * a non-stale mailbox as soon as possible
582 */
583 submit = epu_cmd_irq(cx, order);
584 if (submit > 0) {
585 queue_work(cx->in_work_queue, &order->work);
586 }
587 }
588
589
590 /*
591 * Functions called from a non-interrupt, non work_queue context
592 */
593
594 static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
595 {
596 const struct cx18_api_info *info = find_api_info(cmd);
597 u32 irq, req, ack, err;
598 struct cx18_mailbox __iomem *mb;
599 wait_queue_head_t *waitq;
600 struct mutex *mb_lock;
601 unsigned long int t0, timeout, ret;
602 int i;
603 char argstr[MAX_MB_ARGUMENTS*11+1];
604 DEFINE_WAIT(w);
605
606 if (info == NULL) {
607 CX18_WARN("unknown cmd %x\n", cmd);
608 return -EINVAL;
609 }
610
611 if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
612 if (cmd == CX18_CPU_DE_SET_MDL) {
613 if (cx18_debug & CX18_DBGFLG_HIGHVOL)
614 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
615 info->name, cmd,
616 u32arr2hex(data, args, argstr));
617 } else
618 CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
619 info->name, cmd,
620 u32arr2hex(data, args, argstr));
621 }
622
623 switch (info->rpu) {
624 case APU:
625 waitq = &cx->mb_apu_waitq;
626 mb_lock = &cx->epu2apu_mb_lock;
627 irq = IRQ_EPU_TO_APU;
628 mb = &cx->scb->epu2apu_mb;
629 break;
630 case CPU:
631 waitq = &cx->mb_cpu_waitq;
632 mb_lock = &cx->epu2cpu_mb_lock;
633 irq = IRQ_EPU_TO_CPU;
634 mb = &cx->scb->epu2cpu_mb;
635 break;
636 default:
637 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
638 return -EINVAL;
639 }
640
641 mutex_lock(mb_lock);
642 /*
643 * Wait for an in-use mailbox to complete
644 *
645 * If the XPU is responding with Ack's, the mailbox shouldn't be in
646 * a busy state, since we serialize access to it on our end.
647 *
648 * If the wait for ack after sending a previous command was interrupted
649 * by a signal, we may get here and find a busy mailbox. After waiting,
650 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
651 */
652 req = cx18_readl(cx, &mb->request);
653 timeout = msecs_to_jiffies(10);
654 ret = wait_event_timeout(*waitq,
655 (ack = cx18_readl(cx, &mb->ack)) == req,
656 timeout);
657 if (req != ack) {
658 /* waited long enough, make the mbox "not busy" from our end */
659 cx18_writel(cx, req, &mb->ack);
660 CX18_ERR("mbox was found stuck busy when setting up for %s; clearing busy and trying to proceed\n",
661 info->name);
662 } else if (ret != timeout)
663 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
664 jiffies_to_msecs(timeout-ret));
665
666 /* Build the outgoing mailbox */
667 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
668
669 cx18_writel(cx, cmd, &mb->cmd);
670 for (i = 0; i < args; i++)
671 cx18_writel(cx, data[i], &mb->args[i]);
672 cx18_writel(cx, 0, &mb->error);
673 cx18_writel(cx, req, &mb->request);
674 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
675
676 /*
677 * Notify the XPU and wait for it to send an Ack back
678 */
679 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
680
681 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
682 irq, info->name);
683
684 /* So we don't miss the wakeup, prepare to wait before notifying fw */
685 prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
686 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
687
688 t0 = jiffies;
689 ack = cx18_readl(cx, &mb->ack);
690 if (ack != req) {
691 schedule_timeout(timeout);
692 ret = jiffies - t0;
693 ack = cx18_readl(cx, &mb->ack);
694 } else {
695 ret = jiffies - t0;
696 }
697
698 finish_wait(waitq, &w);
699
700 if (req != ack) {
701 mutex_unlock(mb_lock);
702 if (ret >= timeout) {
703 /* Timed out */
704 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU acknowledgment\n",
705 info->name, jiffies_to_msecs(ret));
706 } else {
707 CX18_DEBUG_WARN("woken up before mailbox ack was ready after submitting %s to RPU. only waited %d msecs on req %u but awakened with unmatched ack %u\n",
708 info->name,
709 jiffies_to_msecs(ret),
710 req, ack);
711 }
712 return -EINVAL;
713 }
714
715 if (ret >= timeout)
716 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment sending %s; timed out waiting %d msecs\n",
717 info->name, jiffies_to_msecs(ret));
718 else
719 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
720 jiffies_to_msecs(ret), info->name);
721
722 /* Collect data returned by the XPU */
723 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
724 data[i] = cx18_readl(cx, &mb->args[i]);
725 err = cx18_readl(cx, &mb->error);
726 mutex_unlock(mb_lock);
727
728 /*
729 * Wait for XPU to perform extra actions for the caller in some cases.
730 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
731 * back in a burst shortly thereafter
732 */
733 if (info->flags & API_SLOW)
734 cx18_msleep_timeout(300, 0);
735
736 if (err)
737 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
738 info->name);
739 return err ? -EIO : 0;
740 }
741
742 int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
743 {
744 return cx18_api_call(cx, cmd, args, data);
745 }
746
747 static int cx18_set_filter_param(struct cx18_stream *s)
748 {
749 struct cx18 *cx = s->cx;
750 u32 mode;
751 int ret;
752
753 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
754 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
755 s->handle, 1, mode, cx->spatial_strength);
756 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
757 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
758 s->handle, 0, mode, cx->temporal_strength);
759 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
760 s->handle, 2, cx->filter_mode >> 2, 0);
761 return ret;
762 }
763
764 int cx18_api_func(void *priv, u32 cmd, int in, int out,
765 u32 data[CX2341X_MBOX_MAX_DATA])
766 {
767 struct cx18_stream *s = priv;
768 struct cx18 *cx = s->cx;
769
770 switch (cmd) {
771 case CX2341X_ENC_SET_OUTPUT_PORT:
772 return 0;
773 case CX2341X_ENC_SET_FRAME_RATE:
774 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
775 s->handle, 0, 0, 0, 0, data[0]);
776 case CX2341X_ENC_SET_FRAME_SIZE:
777 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
778 s->handle, data[1], data[0]);
779 case CX2341X_ENC_SET_STREAM_TYPE:
780 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
781 s->handle, data[0]);
782 case CX2341X_ENC_SET_ASPECT_RATIO:
783 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
784 s->handle, data[0]);
785
786 case CX2341X_ENC_SET_GOP_PROPERTIES:
787 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
788 s->handle, data[0], data[1]);
789 case CX2341X_ENC_SET_GOP_CLOSURE:
790 return 0;
791 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
792 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
793 s->handle, data[0]);
794 case CX2341X_ENC_MUTE_AUDIO:
795 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
796 s->handle, data[0]);
797 case CX2341X_ENC_SET_BIT_RATE:
798 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
799 s->handle, data[0], data[1], data[2], data[3]);
800 case CX2341X_ENC_MUTE_VIDEO:
801 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
802 s->handle, data[0]);
803 case CX2341X_ENC_SET_FRAME_DROP_RATE:
804 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
805 s->handle, data[0]);
806 case CX2341X_ENC_MISC:
807 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
808 s->handle, data[0], data[1], data[2]);
809 case CX2341X_ENC_SET_DNR_FILTER_MODE:
810 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
811 return cx18_set_filter_param(s);
812 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
813 cx->spatial_strength = data[0];
814 cx->temporal_strength = data[1];
815 return cx18_set_filter_param(s);
816 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
817 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
818 s->handle, data[0], data[1]);
819 case CX2341X_ENC_SET_CORING_LEVELS:
820 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
821 s->handle, data[0], data[1], data[2], data[3]);
822 }
823 CX18_WARN("Unknown cmd %x\n", cmd);
824 return 0;
825 }
826
827 int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
828 u32 cmd, int args, ...)
829 {
830 va_list ap;
831 int i;
832
833 va_start(ap, args);
834 for (i = 0; i < args; i++)
835 data[i] = va_arg(ap, u32);
836 va_end(ap);
837 return cx18_api(cx, cmd, args, data);
838 }
839
840 int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
841 {
842 u32 data[MAX_MB_ARGUMENTS];
843 va_list ap;
844 int i;
845
846 if (cx == NULL) {
847 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
848 return 0;
849 }
850 if (args > MAX_MB_ARGUMENTS) {
851 CX18_ERR("args too big (cmd=%x)\n", cmd);
852 args = MAX_MB_ARGUMENTS;
853 }
854 va_start(ap, args);
855 for (i = 0; i < args; i++)
856 data[i] = va_arg(ap, u32);
857 va_end(ap);
858 return cx18_api(cx, cmd, args, data);
859 }
Linux with added FPC-III support