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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / pci / cx23885 / cx23885-cards.c
blob0350f13c5a9fe7b77d9cb1d7cb04311fc6bde6dc
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 */
17
18 #include "cx23885.h"
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <media/drv-intf/cx25840.h>
25 #include <linux/firmware.h>
26 #include <misc/altera.h>
27
28 #include "tuner-xc2028.h"
29 #include "netup-eeprom.h"
30 #include "netup-init.h"
31 #include "altera-ci.h"
32 #include "xc4000.h"
33 #include "xc5000.h"
34 #include "cx23888-ir.h"
35
36 static unsigned int netup_card_rev = 4;
37 module_param(netup_card_rev, int, 0644);
38 MODULE_PARM_DESC(netup_card_rev,
39 "NetUP Dual DVB-T/C CI card revision");
40 static unsigned int enable_885_ir;
41 module_param(enable_885_ir, int, 0644);
42 MODULE_PARM_DESC(enable_885_ir,
43 "Enable integrated IR controller for supported\n"
44 "\t\t CX2388[57] boards that are wired for it:\n"
45 "\t\t\tHVR-1250 (reported safe)\n"
46 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
47 "\t\t\tTeVii S470 (reported unsafe)\n"
48 "\t\t This can cause an interrupt storm with some cards.\n"
49 "\t\t Default: 0 [Disabled]");
50
51 /* ------------------------------------------------------------------ */
52 /* board config info */
53
54 struct cx23885_board cx23885_boards[] = {
55 [CX23885_BOARD_UNKNOWN] = {
56 .name = "UNKNOWN/GENERIC",
57 /* Ensure safe default for unknown boards */
58 .clk_freq = 0,
59 .input = {{
60 .type = CX23885_VMUX_COMPOSITE1,
61 .vmux = 0,
62 }, {
63 .type = CX23885_VMUX_COMPOSITE2,
64 .vmux = 1,
65 }, {
66 .type = CX23885_VMUX_COMPOSITE3,
67 .vmux = 2,
68 }, {
69 .type = CX23885_VMUX_COMPOSITE4,
70 .vmux = 3,
71 } },
72 },
73 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
74 .name = "Hauppauge WinTV-HVR1800lp",
75 .portc = CX23885_MPEG_DVB,
76 .input = {{
77 .type = CX23885_VMUX_TELEVISION,
78 .vmux = 0,
79 .gpio0 = 0xff00,
80 }, {
81 .type = CX23885_VMUX_DEBUG,
82 .vmux = 0,
83 .gpio0 = 0xff01,
84 }, {
85 .type = CX23885_VMUX_COMPOSITE1,
86 .vmux = 1,
87 .gpio0 = 0xff02,
88 }, {
89 .type = CX23885_VMUX_SVIDEO,
90 .vmux = 2,
91 .gpio0 = 0xff02,
92 } },
93 },
94 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
95 .name = "Hauppauge WinTV-HVR1800",
96 .porta = CX23885_ANALOG_VIDEO,
97 .portb = CX23885_MPEG_ENCODER,
98 .portc = CX23885_MPEG_DVB,
99 .tuner_type = TUNER_PHILIPS_TDA8290,
100 .tuner_addr = 0x42, /* 0x84 >> 1 */
101 .tuner_bus = 1,
102 .input = {{
103 .type = CX23885_VMUX_TELEVISION,
104 .vmux = CX25840_VIN7_CH3 |
105 CX25840_VIN5_CH2 |
106 CX25840_VIN2_CH1,
107 .amux = CX25840_AUDIO8,
108 .gpio0 = 0,
109 }, {
110 .type = CX23885_VMUX_COMPOSITE1,
111 .vmux = CX25840_VIN7_CH3 |
112 CX25840_VIN4_CH2 |
113 CX25840_VIN6_CH1,
114 .amux = CX25840_AUDIO7,
115 .gpio0 = 0,
116 }, {
117 .type = CX23885_VMUX_SVIDEO,
118 .vmux = CX25840_VIN7_CH3 |
119 CX25840_VIN4_CH2 |
120 CX25840_VIN8_CH1 |
121 CX25840_SVIDEO_ON,
122 .amux = CX25840_AUDIO7,
123 .gpio0 = 0,
124 } },
125 },
126 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
127 .name = "Hauppauge WinTV-HVR1250",
128 .porta = CX23885_ANALOG_VIDEO,
129 .portc = CX23885_MPEG_DVB,
130 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
131 .tuner_type = TUNER_PHILIPS_TDA8290,
132 .tuner_addr = 0x42, /* 0x84 >> 1 */
133 .tuner_bus = 1,
134 #endif
135 .force_bff = 1,
136 .input = {{
137 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
138 .type = CX23885_VMUX_TELEVISION,
139 .vmux = CX25840_VIN7_CH3 |
140 CX25840_VIN5_CH2 |
141 CX25840_VIN2_CH1,
142 .amux = CX25840_AUDIO8,
143 .gpio0 = 0xff00,
144 }, {
145 #endif
146 .type = CX23885_VMUX_COMPOSITE1,
147 .vmux = CX25840_VIN7_CH3 |
148 CX25840_VIN4_CH2 |
149 CX25840_VIN6_CH1,
150 .amux = CX25840_AUDIO7,
151 .gpio0 = 0xff02,
152 }, {
153 .type = CX23885_VMUX_SVIDEO,
154 .vmux = CX25840_VIN7_CH3 |
155 CX25840_VIN4_CH2 |
156 CX25840_VIN8_CH1 |
157 CX25840_SVIDEO_ON,
158 .amux = CX25840_AUDIO7,
159 .gpio0 = 0xff02,
160 } },
161 },
162 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
163 .name = "DViCO FusionHDTV5 Express",
164 .portb = CX23885_MPEG_DVB,
165 },
166 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
167 .name = "Hauppauge WinTV-HVR1500Q",
168 .portc = CX23885_MPEG_DVB,
169 },
170 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
171 .name = "Hauppauge WinTV-HVR1500",
172 .porta = CX23885_ANALOG_VIDEO,
173 .portc = CX23885_MPEG_DVB,
174 .tuner_type = TUNER_XC2028,
175 .tuner_addr = 0x61, /* 0xc2 >> 1 */
176 .input = {{
177 .type = CX23885_VMUX_TELEVISION,
178 .vmux = CX25840_VIN7_CH3 |
179 CX25840_VIN5_CH2 |
180 CX25840_VIN2_CH1,
181 .gpio0 = 0,
182 }, {
183 .type = CX23885_VMUX_COMPOSITE1,
184 .vmux = CX25840_VIN7_CH3 |
185 CX25840_VIN4_CH2 |
186 CX25840_VIN6_CH1,
187 .gpio0 = 0,
188 }, {
189 .type = CX23885_VMUX_SVIDEO,
190 .vmux = CX25840_VIN7_CH3 |
191 CX25840_VIN4_CH2 |
192 CX25840_VIN8_CH1 |
193 CX25840_SVIDEO_ON,
194 .gpio0 = 0,
195 } },
196 },
197 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
198 .name = "Hauppauge WinTV-HVR1200",
199 .portc = CX23885_MPEG_DVB,
200 },
201 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
202 .name = "Hauppauge WinTV-HVR1700",
203 .portc = CX23885_MPEG_DVB,
204 },
205 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
206 .name = "Hauppauge WinTV-HVR1400",
207 .portc = CX23885_MPEG_DVB,
208 },
209 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
210 .name = "DViCO FusionHDTV7 Dual Express",
211 .portb = CX23885_MPEG_DVB,
212 .portc = CX23885_MPEG_DVB,
213 },
214 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
215 .name = "DViCO FusionHDTV DVB-T Dual Express",
216 .portb = CX23885_MPEG_DVB,
217 .portc = CX23885_MPEG_DVB,
218 },
219 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
220 .name = "Leadtek Winfast PxDVR3200 H",
221 .portc = CX23885_MPEG_DVB,
222 },
223 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
224 .name = "Leadtek Winfast PxPVR2200",
225 .porta = CX23885_ANALOG_VIDEO,
226 .tuner_type = TUNER_XC2028,
227 .tuner_addr = 0x61,
228 .tuner_bus = 1,
229 .input = {{
230 .type = CX23885_VMUX_TELEVISION,
231 .vmux = CX25840_VIN2_CH1 |
232 CX25840_VIN5_CH2,
233 .amux = CX25840_AUDIO8,
234 .gpio0 = 0x704040,
235 }, {
236 .type = CX23885_VMUX_COMPOSITE1,
237 .vmux = CX25840_COMPOSITE1,
238 .amux = CX25840_AUDIO7,
239 .gpio0 = 0x704040,
240 }, {
241 .type = CX23885_VMUX_SVIDEO,
242 .vmux = CX25840_SVIDEO_LUMA3 |
243 CX25840_SVIDEO_CHROMA4,
244 .amux = CX25840_AUDIO7,
245 .gpio0 = 0x704040,
246 }, {
247 .type = CX23885_VMUX_COMPONENT,
248 .vmux = CX25840_VIN7_CH1 |
249 CX25840_VIN6_CH2 |
250 CX25840_VIN8_CH3 |
251 CX25840_COMPONENT_ON,
252 .amux = CX25840_AUDIO7,
253 .gpio0 = 0x704040,
254 } },
255 },
256 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
257 .name = "Leadtek Winfast PxDVR3200 H XC4000",
258 .porta = CX23885_ANALOG_VIDEO,
259 .portc = CX23885_MPEG_DVB,
260 .tuner_type = TUNER_XC4000,
261 .tuner_addr = 0x61,
262 .radio_type = UNSET,
263 .radio_addr = ADDR_UNSET,
264 .input = {{
265 .type = CX23885_VMUX_TELEVISION,
266 .vmux = CX25840_VIN2_CH1 |
267 CX25840_VIN5_CH2 |
268 CX25840_NONE0_CH3,
269 }, {
270 .type = CX23885_VMUX_COMPOSITE1,
271 .vmux = CX25840_COMPOSITE1,
272 }, {
273 .type = CX23885_VMUX_SVIDEO,
274 .vmux = CX25840_SVIDEO_LUMA3 |
275 CX25840_SVIDEO_CHROMA4,
276 }, {
277 .type = CX23885_VMUX_COMPONENT,
278 .vmux = CX25840_VIN7_CH1 |
279 CX25840_VIN6_CH2 |
280 CX25840_VIN8_CH3 |
281 CX25840_COMPONENT_ON,
282 } },
283 },
284 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
285 .name = "Compro VideoMate E650F",
286 .portc = CX23885_MPEG_DVB,
287 },
288 [CX23885_BOARD_TBS_6920] = {
289 .name = "TurboSight TBS 6920",
290 .portb = CX23885_MPEG_DVB,
291 },
292 [CX23885_BOARD_TBS_6980] = {
293 .name = "TurboSight TBS 6980",
294 .portb = CX23885_MPEG_DVB,
295 .portc = CX23885_MPEG_DVB,
296 },
297 [CX23885_BOARD_TBS_6981] = {
298 .name = "TurboSight TBS 6981",
299 .portb = CX23885_MPEG_DVB,
300 .portc = CX23885_MPEG_DVB,
301 },
302 [CX23885_BOARD_TEVII_S470] = {
303 .name = "TeVii S470",
304 .portb = CX23885_MPEG_DVB,
305 },
306 [CX23885_BOARD_DVBWORLD_2005] = {
307 .name = "DVBWorld DVB-S2 2005",
308 .portb = CX23885_MPEG_DVB,
309 },
310 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
311 .ci_type = 1,
312 .name = "NetUP Dual DVB-S2 CI",
313 .portb = CX23885_MPEG_DVB,
314 .portc = CX23885_MPEG_DVB,
315 },
316 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
317 .name = "Hauppauge WinTV-HVR1270",
318 .portc = CX23885_MPEG_DVB,
319 },
320 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
321 .name = "Hauppauge WinTV-HVR1275",
322 .portc = CX23885_MPEG_DVB,
323 },
324 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
325 .name = "Hauppauge WinTV-HVR1255",
326 .porta = CX23885_ANALOG_VIDEO,
327 .portc = CX23885_MPEG_DVB,
328 .tuner_type = TUNER_ABSENT,
329 .tuner_addr = 0x42, /* 0x84 >> 1 */
330 .force_bff = 1,
331 .input = {{
332 .type = CX23885_VMUX_TELEVISION,
333 .vmux = CX25840_VIN7_CH3 |
334 CX25840_VIN5_CH2 |
335 CX25840_VIN2_CH1 |
336 CX25840_DIF_ON,
337 .amux = CX25840_AUDIO8,
338 }, {
339 .type = CX23885_VMUX_COMPOSITE1,
340 .vmux = CX25840_VIN7_CH3 |
341 CX25840_VIN4_CH2 |
342 CX25840_VIN6_CH1,
343 .amux = CX25840_AUDIO7,
344 }, {
345 .type = CX23885_VMUX_SVIDEO,
346 .vmux = CX25840_VIN7_CH3 |
347 CX25840_VIN4_CH2 |
348 CX25840_VIN8_CH1 |
349 CX25840_SVIDEO_ON,
350 .amux = CX25840_AUDIO7,
351 } },
352 },
353 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
354 .name = "Hauppauge WinTV-HVR1255",
355 .porta = CX23885_ANALOG_VIDEO,
356 .portc = CX23885_MPEG_DVB,
357 .tuner_type = TUNER_ABSENT,
358 .tuner_addr = 0x42, /* 0x84 >> 1 */
359 .force_bff = 1,
360 .input = {{
361 .type = CX23885_VMUX_TELEVISION,
362 .vmux = CX25840_VIN7_CH3 |
363 CX25840_VIN5_CH2 |
364 CX25840_VIN2_CH1 |
365 CX25840_DIF_ON,
366 .amux = CX25840_AUDIO8,
367 }, {
368 .type = CX23885_VMUX_SVIDEO,
369 .vmux = CX25840_VIN7_CH3 |
370 CX25840_VIN4_CH2 |
371 CX25840_VIN8_CH1 |
372 CX25840_SVIDEO_ON,
373 .amux = CX25840_AUDIO7,
374 } },
375 },
376 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
377 .name = "Hauppauge WinTV-HVR1210",
378 .portc = CX23885_MPEG_DVB,
379 },
380 [CX23885_BOARD_MYGICA_X8506] = {
381 .name = "Mygica X8506 DMB-TH",
382 .tuner_type = TUNER_XC5000,
383 .tuner_addr = 0x61,
384 .tuner_bus = 1,
385 .porta = CX23885_ANALOG_VIDEO,
386 .portb = CX23885_MPEG_DVB,
387 .input = {
388 {
389 .type = CX23885_VMUX_TELEVISION,
390 .vmux = CX25840_COMPOSITE2,
391 },
392 {
393 .type = CX23885_VMUX_COMPOSITE1,
394 .vmux = CX25840_COMPOSITE8,
395 },
396 {
397 .type = CX23885_VMUX_SVIDEO,
398 .vmux = CX25840_SVIDEO_LUMA3 |
399 CX25840_SVIDEO_CHROMA4,
400 },
401 {
402 .type = CX23885_VMUX_COMPONENT,
403 .vmux = CX25840_COMPONENT_ON |
404 CX25840_VIN1_CH1 |
405 CX25840_VIN6_CH2 |
406 CX25840_VIN7_CH3,
407 },
408 },
409 },
410 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
411 .name = "Magic-Pro ProHDTV Extreme 2",
412 .tuner_type = TUNER_XC5000,
413 .tuner_addr = 0x61,
414 .tuner_bus = 1,
415 .porta = CX23885_ANALOG_VIDEO,
416 .portb = CX23885_MPEG_DVB,
417 .input = {
418 {
419 .type = CX23885_VMUX_TELEVISION,
420 .vmux = CX25840_COMPOSITE2,
421 },
422 {
423 .type = CX23885_VMUX_COMPOSITE1,
424 .vmux = CX25840_COMPOSITE8,
425 },
426 {
427 .type = CX23885_VMUX_SVIDEO,
428 .vmux = CX25840_SVIDEO_LUMA3 |
429 CX25840_SVIDEO_CHROMA4,
430 },
431 {
432 .type = CX23885_VMUX_COMPONENT,
433 .vmux = CX25840_COMPONENT_ON |
434 CX25840_VIN1_CH1 |
435 CX25840_VIN6_CH2 |
436 CX25840_VIN7_CH3,
437 },
438 },
439 },
440 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
441 .name = "Hauppauge WinTV-HVR1850",
442 .porta = CX23885_ANALOG_VIDEO,
443 .portb = CX23885_MPEG_ENCODER,
444 .portc = CX23885_MPEG_DVB,
445 .tuner_type = TUNER_ABSENT,
446 .tuner_addr = 0x42, /* 0x84 >> 1 */
447 .force_bff = 1,
448 .input = {{
449 .type = CX23885_VMUX_TELEVISION,
450 .vmux = CX25840_VIN7_CH3 |
451 CX25840_VIN5_CH2 |
452 CX25840_VIN2_CH1 |
453 CX25840_DIF_ON,
454 .amux = CX25840_AUDIO8,
455 }, {
456 .type = CX23885_VMUX_COMPOSITE1,
457 .vmux = CX25840_VIN7_CH3 |
458 CX25840_VIN4_CH2 |
459 CX25840_VIN6_CH1,
460 .amux = CX25840_AUDIO7,
461 }, {
462 .type = CX23885_VMUX_SVIDEO,
463 .vmux = CX25840_VIN7_CH3 |
464 CX25840_VIN4_CH2 |
465 CX25840_VIN8_CH1 |
466 CX25840_SVIDEO_ON,
467 .amux = CX25840_AUDIO7,
468 } },
469 },
470 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
471 .name = "Compro VideoMate E800",
472 .portc = CX23885_MPEG_DVB,
473 },
474 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
475 .name = "Hauppauge WinTV-HVR1290",
476 .portc = CX23885_MPEG_DVB,
477 },
478 [CX23885_BOARD_MYGICA_X8558PRO] = {
479 .name = "Mygica X8558 PRO DMB-TH",
480 .portb = CX23885_MPEG_DVB,
481 .portc = CX23885_MPEG_DVB,
482 },
483 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
484 .name = "LEADTEK WinFast PxTV1200",
485 .porta = CX23885_ANALOG_VIDEO,
486 .tuner_type = TUNER_XC2028,
487 .tuner_addr = 0x61,
488 .tuner_bus = 1,
489 .input = {{
490 .type = CX23885_VMUX_TELEVISION,
491 .vmux = CX25840_VIN2_CH1 |
492 CX25840_VIN5_CH2 |
493 CX25840_NONE0_CH3,
494 }, {
495 .type = CX23885_VMUX_COMPOSITE1,
496 .vmux = CX25840_COMPOSITE1,
497 }, {
498 .type = CX23885_VMUX_SVIDEO,
499 .vmux = CX25840_SVIDEO_LUMA3 |
500 CX25840_SVIDEO_CHROMA4,
501 }, {
502 .type = CX23885_VMUX_COMPONENT,
503 .vmux = CX25840_VIN7_CH1 |
504 CX25840_VIN6_CH2 |
505 CX25840_VIN8_CH3 |
506 CX25840_COMPONENT_ON,
507 } },
508 },
509 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
510 .name = "GoTView X5 3D Hybrid",
511 .tuner_type = TUNER_XC5000,
512 .tuner_addr = 0x64,
513 .tuner_bus = 1,
514 .porta = CX23885_ANALOG_VIDEO,
515 .portb = CX23885_MPEG_DVB,
516 .input = {{
517 .type = CX23885_VMUX_TELEVISION,
518 .vmux = CX25840_VIN2_CH1 |
519 CX25840_VIN5_CH2,
520 .gpio0 = 0x02,
521 }, {
522 .type = CX23885_VMUX_COMPOSITE1,
523 .vmux = CX23885_VMUX_COMPOSITE1,
524 }, {
525 .type = CX23885_VMUX_SVIDEO,
526 .vmux = CX25840_SVIDEO_LUMA3 |
527 CX25840_SVIDEO_CHROMA4,
528 } },
529 },
530 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
531 .ci_type = 2,
532 .name = "NetUP Dual DVB-T/C-CI RF",
533 .porta = CX23885_ANALOG_VIDEO,
534 .portb = CX23885_MPEG_DVB,
535 .portc = CX23885_MPEG_DVB,
536 .num_fds_portb = 2,
537 .num_fds_portc = 2,
538 .tuner_type = TUNER_XC5000,
539 .tuner_addr = 0x64,
540 .input = { {
541 .type = CX23885_VMUX_TELEVISION,
542 .vmux = CX25840_COMPOSITE1,
543 } },
544 },
545 [CX23885_BOARD_MPX885] = {
546 .name = "MPX-885",
547 .porta = CX23885_ANALOG_VIDEO,
548 .input = {{
549 .type = CX23885_VMUX_COMPOSITE1,
550 .vmux = CX25840_COMPOSITE1,
551 .amux = CX25840_AUDIO6,
552 .gpio0 = 0,
553 }, {
554 .type = CX23885_VMUX_COMPOSITE2,
555 .vmux = CX25840_COMPOSITE2,
556 .amux = CX25840_AUDIO6,
557 .gpio0 = 0,
558 }, {
559 .type = CX23885_VMUX_COMPOSITE3,
560 .vmux = CX25840_COMPOSITE3,
561 .amux = CX25840_AUDIO7,
562 .gpio0 = 0,
563 }, {
564 .type = CX23885_VMUX_COMPOSITE4,
565 .vmux = CX25840_COMPOSITE4,
566 .amux = CX25840_AUDIO7,
567 .gpio0 = 0,
568 } },
569 },
570 [CX23885_BOARD_MYGICA_X8507] = {
571 .name = "Mygica X8502/X8507 ISDB-T",
572 .tuner_type = TUNER_XC5000,
573 .tuner_addr = 0x61,
574 .tuner_bus = 1,
575 .porta = CX23885_ANALOG_VIDEO,
576 .portb = CX23885_MPEG_DVB,
577 .input = {
578 {
579 .type = CX23885_VMUX_TELEVISION,
580 .vmux = CX25840_COMPOSITE2,
581 .amux = CX25840_AUDIO8,
582 },
583 {
584 .type = CX23885_VMUX_COMPOSITE1,
585 .vmux = CX25840_COMPOSITE8,
586 .amux = CX25840_AUDIO7,
587 },
588 {
589 .type = CX23885_VMUX_SVIDEO,
590 .vmux = CX25840_SVIDEO_LUMA3 |
591 CX25840_SVIDEO_CHROMA4,
592 .amux = CX25840_AUDIO7,
593 },
594 {
595 .type = CX23885_VMUX_COMPONENT,
596 .vmux = CX25840_COMPONENT_ON |
597 CX25840_VIN1_CH1 |
598 CX25840_VIN6_CH2 |
599 CX25840_VIN7_CH3,
600 .amux = CX25840_AUDIO7,
601 },
602 },
603 },
604 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
605 .name = "TerraTec Cinergy T PCIe Dual",
606 .portb = CX23885_MPEG_DVB,
607 .portc = CX23885_MPEG_DVB,
608 },
609 [CX23885_BOARD_TEVII_S471] = {
610 .name = "TeVii S471",
611 .portb = CX23885_MPEG_DVB,
612 },
613 [CX23885_BOARD_PROF_8000] = {
614 .name = "Prof Revolution DVB-S2 8000",
615 .portb = CX23885_MPEG_DVB,
616 },
617 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
618 .name = "Hauppauge WinTV-HVR4400/HVR5500",
619 .porta = CX23885_ANALOG_VIDEO,
620 .portb = CX23885_MPEG_DVB,
621 .portc = CX23885_MPEG_DVB,
622 .tuner_type = TUNER_NXP_TDA18271,
623 .tuner_addr = 0x60, /* 0xc0 >> 1 */
624 .tuner_bus = 1,
625 },
626 [CX23885_BOARD_HAUPPAUGE_STARBURST] = {
627 .name = "Hauppauge WinTV Starburst",
628 .portb = CX23885_MPEG_DVB,
629 },
630 [CX23885_BOARD_AVERMEDIA_HC81R] = {
631 .name = "AVerTV Hybrid Express Slim HC81R",
632 .tuner_type = TUNER_XC2028,
633 .tuner_addr = 0x61, /* 0xc2 >> 1 */
634 .tuner_bus = 1,
635 .porta = CX23885_ANALOG_VIDEO,
636 .input = {{
637 .type = CX23885_VMUX_TELEVISION,
638 .vmux = CX25840_VIN2_CH1 |
639 CX25840_VIN5_CH2 |
640 CX25840_NONE0_CH3 |
641 CX25840_NONE1_CH3,
642 .amux = CX25840_AUDIO8,
643 }, {
644 .type = CX23885_VMUX_SVIDEO,
645 .vmux = CX25840_VIN8_CH1 |
646 CX25840_NONE_CH2 |
647 CX25840_VIN7_CH3 |
648 CX25840_SVIDEO_ON,
649 .amux = CX25840_AUDIO6,
650 }, {
651 .type = CX23885_VMUX_COMPONENT,
652 .vmux = CX25840_VIN1_CH1 |
653 CX25840_NONE_CH2 |
654 CX25840_NONE0_CH3 |
655 CX25840_NONE1_CH3,
656 .amux = CX25840_AUDIO6,
657 } },
658 },
659 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
660 .name = "DViCO FusionHDTV DVB-T Dual Express2",
661 .portb = CX23885_MPEG_DVB,
662 .portc = CX23885_MPEG_DVB,
663 },
664 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
665 .name = "Hauppauge ImpactVCB-e",
666 .tuner_type = TUNER_ABSENT,
667 .porta = CX23885_ANALOG_VIDEO,
668 .input = {{
669 .type = CX23885_VMUX_COMPOSITE1,
670 .vmux = CX25840_VIN7_CH3 |
671 CX25840_VIN4_CH2 |
672 CX25840_VIN6_CH1,
673 .amux = CX25840_AUDIO7,
674 }, {
675 .type = CX23885_VMUX_SVIDEO,
676 .vmux = CX25840_VIN7_CH3 |
677 CX25840_VIN4_CH2 |
678 CX25840_VIN8_CH1 |
679 CX25840_SVIDEO_ON,
680 .amux = CX25840_AUDIO7,
681 } },
682 },
683 [CX23885_BOARD_DVBSKY_T9580] = {
684 .name = "DVBSky T9580",
685 .portb = CX23885_MPEG_DVB,
686 .portc = CX23885_MPEG_DVB,
687 },
688 [CX23885_BOARD_DVBSKY_T980C] = {
689 .name = "DVBSky T980C",
690 .portb = CX23885_MPEG_DVB,
691 },
692 [CX23885_BOARD_DVBSKY_S950C] = {
693 .name = "DVBSky S950C",
694 .portb = CX23885_MPEG_DVB,
695 },
696 [CX23885_BOARD_TT_CT2_4500_CI] = {
697 .name = "Technotrend TT-budget CT2-4500 CI",
698 .portb = CX23885_MPEG_DVB,
699 },
700 [CX23885_BOARD_DVBSKY_S950] = {
701 .name = "DVBSky S950",
702 .portb = CX23885_MPEG_DVB,
703 },
704 [CX23885_BOARD_DVBSKY_S952] = {
705 .name = "DVBSky S952",
706 .portb = CX23885_MPEG_DVB,
707 .portc = CX23885_MPEG_DVB,
708 },
709 [CX23885_BOARD_DVBSKY_T982] = {
710 .name = "DVBSky T982",
711 .portb = CX23885_MPEG_DVB,
712 .portc = CX23885_MPEG_DVB,
713 },
714 [CX23885_BOARD_HAUPPAUGE_HVR5525] = {
715 .name = "Hauppauge WinTV-HVR5525",
716 .portb = CX23885_MPEG_DVB,
717 .portc = CX23885_MPEG_DVB,
718 },
719 [CX23885_BOARD_VIEWCAST_260E] = {
720 .name = "ViewCast 260e",
721 .porta = CX23885_ANALOG_VIDEO,
722 .force_bff = 1,
723 .input = {{
724 .type = CX23885_VMUX_COMPOSITE1,
725 .vmux = CX25840_VIN6_CH1,
726 .amux = CX25840_AUDIO7,
727 }, {
728 .type = CX23885_VMUX_SVIDEO,
729 .vmux = CX25840_VIN7_CH3 |
730 CX25840_VIN5_CH1 |
731 CX25840_SVIDEO_ON,
732 .amux = CX25840_AUDIO7,
733 }, {
734 .type = CX23885_VMUX_COMPONENT,
735 .vmux = CX25840_VIN7_CH3 |
736 CX25840_VIN6_CH2 |
737 CX25840_VIN5_CH1 |
738 CX25840_COMPONENT_ON,
739 .amux = CX25840_AUDIO7,
740 } },
741 },
742 [CX23885_BOARD_VIEWCAST_460E] = {
743 .name = "ViewCast 460e",
744 .porta = CX23885_ANALOG_VIDEO,
745 .force_bff = 1,
746 .input = {{
747 .type = CX23885_VMUX_COMPOSITE1,
748 .vmux = CX25840_VIN4_CH1,
749 .amux = CX25840_AUDIO7,
750 }, {
751 .type = CX23885_VMUX_SVIDEO,
752 .vmux = CX25840_VIN7_CH3 |
753 CX25840_VIN6_CH1 |
754 CX25840_SVIDEO_ON,
755 .amux = CX25840_AUDIO7,
756 }, {
757 .type = CX23885_VMUX_COMPONENT,
758 .vmux = CX25840_VIN7_CH3 |
759 CX25840_VIN6_CH1 |
760 CX25840_VIN5_CH2 |
761 CX25840_COMPONENT_ON,
762 .amux = CX25840_AUDIO7,
763 }, {
764 .type = CX23885_VMUX_COMPOSITE2,
765 .vmux = CX25840_VIN6_CH1,
766 .amux = CX25840_AUDIO7,
767 } },
768 },
769 [CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = {
770 .name = "Hauppauge WinTV-QuadHD-DVB",
771 .portb = CX23885_MPEG_DVB,
772 .portc = CX23885_MPEG_DVB,
773 },
774 [CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = {
775 .name = "Hauppauge WinTV-QuadHD-ATSC",
776 .portb = CX23885_MPEG_DVB,
777 .portc = CX23885_MPEG_DVB,
778 },
779 };
780 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
781
782 /* ------------------------------------------------------------------ */
783 /* PCI subsystem IDs */
784
785 struct cx23885_subid cx23885_subids[] = {
786 {
787 .subvendor = 0x0070,
788 .subdevice = 0x3400,
789 .card = CX23885_BOARD_UNKNOWN,
790 }, {
791 .subvendor = 0x0070,
792 .subdevice = 0x7600,
793 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
794 }, {
795 .subvendor = 0x0070,
796 .subdevice = 0x7800,
797 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
798 }, {
799 .subvendor = 0x0070,
800 .subdevice = 0x7801,
801 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
802 }, {
803 .subvendor = 0x0070,
804 .subdevice = 0x7809,
805 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
806 }, {
807 .subvendor = 0x0070,
808 .subdevice = 0x7911,
809 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
810 }, {
811 .subvendor = 0x18ac,
812 .subdevice = 0xd500,
813 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
814 }, {
815 .subvendor = 0x0070,
816 .subdevice = 0x7790,
817 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
818 }, {
819 .subvendor = 0x0070,
820 .subdevice = 0x7797,
821 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
822 }, {
823 .subvendor = 0x0070,
824 .subdevice = 0x7710,
825 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
826 }, {
827 .subvendor = 0x0070,
828 .subdevice = 0x7717,
829 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
830 }, {
831 .subvendor = 0x0070,
832 .subdevice = 0x71d1,
833 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
834 }, {
835 .subvendor = 0x0070,
836 .subdevice = 0x71d3,
837 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
838 }, {
839 .subvendor = 0x0070,
840 .subdevice = 0x8101,
841 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
842 }, {
843 .subvendor = 0x0070,
844 .subdevice = 0x8010,
845 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
846 }, {
847 .subvendor = 0x18ac,
848 .subdevice = 0xd618,
849 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
850 }, {
851 .subvendor = 0x18ac,
852 .subdevice = 0xdb78,
853 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
854 }, {
855 .subvendor = 0x107d,
856 .subdevice = 0x6681,
857 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
858 }, {
859 .subvendor = 0x107d,
860 .subdevice = 0x6f21,
861 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
862 }, {
863 .subvendor = 0x107d,
864 .subdevice = 0x6f39,
865 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
866 }, {
867 .subvendor = 0x185b,
868 .subdevice = 0xe800,
869 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
870 }, {
871 .subvendor = 0x6920,
872 .subdevice = 0x8888,
873 .card = CX23885_BOARD_TBS_6920,
874 }, {
875 .subvendor = 0x6980,
876 .subdevice = 0x8888,
877 .card = CX23885_BOARD_TBS_6980,
878 }, {
879 .subvendor = 0x6981,
880 .subdevice = 0x8888,
881 .card = CX23885_BOARD_TBS_6981,
882 }, {
883 .subvendor = 0xd470,
884 .subdevice = 0x9022,
885 .card = CX23885_BOARD_TEVII_S470,
886 }, {
887 .subvendor = 0x0001,
888 .subdevice = 0x2005,
889 .card = CX23885_BOARD_DVBWORLD_2005,
890 }, {
891 .subvendor = 0x1b55,
892 .subdevice = 0x2a2c,
893 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
894 }, {
895 .subvendor = 0x0070,
896 .subdevice = 0x2211,
897 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
898 }, {
899 .subvendor = 0x0070,
900 .subdevice = 0x2215,
901 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
902 }, {
903 .subvendor = 0x0070,
904 .subdevice = 0x221d,
905 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
906 }, {
907 .subvendor = 0x0070,
908 .subdevice = 0x2251,
909 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
910 }, {
911 .subvendor = 0x0070,
912 .subdevice = 0x2259,
913 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
914 }, {
915 .subvendor = 0x0070,
916 .subdevice = 0x2291,
917 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
918 }, {
919 .subvendor = 0x0070,
920 .subdevice = 0x2295,
921 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
922 }, {
923 .subvendor = 0x0070,
924 .subdevice = 0x2299,
925 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
926 }, {
927 .subvendor = 0x0070,
928 .subdevice = 0x229d,
929 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
930 }, {
931 .subvendor = 0x0070,
932 .subdevice = 0x22f0,
933 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
934 }, {
935 .subvendor = 0x0070,
936 .subdevice = 0x22f1,
937 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
938 }, {
939 .subvendor = 0x0070,
940 .subdevice = 0x22f2,
941 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
942 }, {
943 .subvendor = 0x0070,
944 .subdevice = 0x22f3,
945 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
946 }, {
947 .subvendor = 0x0070,
948 .subdevice = 0x22f4,
949 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
950 }, {
951 .subvendor = 0x0070,
952 .subdevice = 0x22f5,
953 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
954 }, {
955 .subvendor = 0x14f1,
956 .subdevice = 0x8651,
957 .card = CX23885_BOARD_MYGICA_X8506,
958 }, {
959 .subvendor = 0x14f1,
960 .subdevice = 0x8657,
961 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
962 }, {
963 .subvendor = 0x0070,
964 .subdevice = 0x8541,
965 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
966 }, {
967 .subvendor = 0x1858,
968 .subdevice = 0xe800,
969 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
970 }, {
971 .subvendor = 0x0070,
972 .subdevice = 0x8551,
973 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
974 }, {
975 .subvendor = 0x14f1,
976 .subdevice = 0x8578,
977 .card = CX23885_BOARD_MYGICA_X8558PRO,
978 }, {
979 .subvendor = 0x107d,
980 .subdevice = 0x6f22,
981 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
982 }, {
983 .subvendor = 0x5654,
984 .subdevice = 0x2390,
985 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
986 }, {
987 .subvendor = 0x1b55,
988 .subdevice = 0xe2e4,
989 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
990 }, {
991 .subvendor = 0x14f1,
992 .subdevice = 0x8502,
993 .card = CX23885_BOARD_MYGICA_X8507,
994 }, {
995 .subvendor = 0x153b,
996 .subdevice = 0x117e,
997 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
998 }, {
999 .subvendor = 0xd471,
1000 .subdevice = 0x9022,
1001 .card = CX23885_BOARD_TEVII_S471,
1002 }, {
1003 .subvendor = 0x8000,
1004 .subdevice = 0x3034,
1005 .card = CX23885_BOARD_PROF_8000,
1006 }, {
1007 .subvendor = 0x0070,
1008 .subdevice = 0xc108,
1009 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
1010 }, {
1011 .subvendor = 0x0070,
1012 .subdevice = 0xc138,
1013 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1014 }, {
1015 .subvendor = 0x0070,
1016 .subdevice = 0xc12a,
1017 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
1018 }, {
1019 .subvendor = 0x0070,
1020 .subdevice = 0xc1f8,
1021 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1022 }, {
1023 .subvendor = 0x1461,
1024 .subdevice = 0xd939,
1025 .card = CX23885_BOARD_AVERMEDIA_HC81R,
1026 }, {
1027 .subvendor = 0x0070,
1028 .subdevice = 0x7133,
1029 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
1030 }, {
1031 .subvendor = 0x18ac,
1032 .subdevice = 0xdb98,
1033 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
1034 }, {
1035 .subvendor = 0x4254,
1036 .subdevice = 0x9580,
1037 .card = CX23885_BOARD_DVBSKY_T9580,
1038 }, {
1039 .subvendor = 0x4254,
1040 .subdevice = 0x980c,
1041 .card = CX23885_BOARD_DVBSKY_T980C,
1042 }, {
1043 .subvendor = 0x4254,
1044 .subdevice = 0x950c,
1045 .card = CX23885_BOARD_DVBSKY_S950C,
1046 }, {
1047 .subvendor = 0x13c2,
1048 .subdevice = 0x3013,
1049 .card = CX23885_BOARD_TT_CT2_4500_CI,
1050 }, {
1051 .subvendor = 0x4254,
1052 .subdevice = 0x0950,
1053 .card = CX23885_BOARD_DVBSKY_S950,
1054 }, {
1055 .subvendor = 0x4254,
1056 .subdevice = 0x0952,
1057 .card = CX23885_BOARD_DVBSKY_S952,
1058 }, {
1059 .subvendor = 0x4254,
1060 .subdevice = 0x0982,
1061 .card = CX23885_BOARD_DVBSKY_T982,
1062 }, {
1063 .subvendor = 0x0070,
1064 .subdevice = 0xf038,
1065 .card = CX23885_BOARD_HAUPPAUGE_HVR5525,
1066 }, {
1067 .subvendor = 0x1576,
1068 .subdevice = 0x0260,
1069 .card = CX23885_BOARD_VIEWCAST_260E,
1070 }, {
1071 .subvendor = 0x1576,
1072 .subdevice = 0x0460,
1073 .card = CX23885_BOARD_VIEWCAST_460E,
1074 }, {
1075 .subvendor = 0x0070,
1076 .subdevice = 0x6a28,
1077 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */
1078 }, {
1079 .subvendor = 0x0070,
1080 .subdevice = 0x6b28,
1081 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */
1082 }, {
1083 .subvendor = 0x0070,
1084 .subdevice = 0x6a18,
1085 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */
1086 }, {
1087 .subvendor = 0x0070,
1088 .subdevice = 0x6b18,
1089 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */
1090 },
1091 };
1092 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
1093
1094 void cx23885_card_list(struct cx23885_dev *dev)
1095 {
1096 int i;
1097
1098 if (0 == dev->pci->subsystem_vendor &&
1099 0 == dev->pci->subsystem_device) {
1100 pr_info("%s: Board has no valid PCIe Subsystem ID and can't\n"
1101 "%s: be autodetected. Pass card=<n> insmod option\n"
1102 "%s: to workaround that. Redirect complaints to the\n"
1103 "%s: vendor of the TV card. Best regards,\n"
1104 "%s: -- tux\n",
1105 dev->name, dev->name, dev->name, dev->name, dev->name);
1106 } else {
1107 pr_info("%s: Your board isn't known (yet) to the driver.\n"
1108 "%s: Try to pick one of the existing card configs via\n"
1109 "%s: card=<n> insmod option. Updating to the latest\n"
1110 "%s: version might help as well.\n",
1111 dev->name, dev->name, dev->name, dev->name);
1112 }
1113 pr_info("%s: Here is a list of valid choices for the card=<n> insmod option:\n",
1114 dev->name);
1115 for (i = 0; i < cx23885_bcount; i++)
1116 pr_info("%s: card=%d -> %s\n",
1117 dev->name, i, cx23885_boards[i].name);
1118 }
1119
1120 static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1121 {
1122 u32 sn;
1123
1124 /* The serial number record begins with tag 0x59 */
1125 if (*(eeprom_data + 0x00) != 0x59) {
1126 pr_info("%s() eeprom records are undefined, no serial number\n",
1127 __func__);
1128 return;
1129 }
1130
1131 sn = (*(eeprom_data + 0x06) << 24) |
1132 (*(eeprom_data + 0x05) << 16) |
1133 (*(eeprom_data + 0x04) << 8) |
1134 (*(eeprom_data + 0x03));
1135
1136 pr_info("%s: card '%s' sn# MM%d\n",
1137 dev->name,
1138 cx23885_boards[dev->board].name,
1139 sn);
1140 }
1141
1142 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1143 {
1144 struct tveeprom tv;
1145
1146 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
1147 eeprom_data);
1148
1149 /* Make sure we support the board model */
1150 switch (tv.model) {
1151 case 22001:
1152 /* WinTV-HVR1270 (PCIe, Retail, half height)
1153 * ATSC/QAM and basic analog, IR Blast */
1154 case 22009:
1155 /* WinTV-HVR1210 (PCIe, Retail, half height)
1156 * DVB-T and basic analog, IR Blast */
1157 case 22011:
1158 /* WinTV-HVR1270 (PCIe, Retail, half height)
1159 * ATSC/QAM and basic analog, IR Recv */
1160 case 22019:
1161 /* WinTV-HVR1210 (PCIe, Retail, half height)
1162 * DVB-T and basic analog, IR Recv */
1163 case 22021:
1164 /* WinTV-HVR1275 (PCIe, Retail, half height)
1165 * ATSC/QAM and basic analog, IR Recv */
1166 case 22029:
1167 /* WinTV-HVR1210 (PCIe, Retail, half height)
1168 * DVB-T and basic analog, IR Recv */
1169 case 22101:
1170 /* WinTV-HVR1270 (PCIe, Retail, full height)
1171 * ATSC/QAM and basic analog, IR Blast */
1172 case 22109:
1173 /* WinTV-HVR1210 (PCIe, Retail, full height)
1174 * DVB-T and basic analog, IR Blast */
1175 case 22111:
1176 /* WinTV-HVR1270 (PCIe, Retail, full height)
1177 * ATSC/QAM and basic analog, IR Recv */
1178 case 22119:
1179 /* WinTV-HVR1210 (PCIe, Retail, full height)
1180 * DVB-T and basic analog, IR Recv */
1181 case 22121:
1182 /* WinTV-HVR1275 (PCIe, Retail, full height)
1183 * ATSC/QAM and basic analog, IR Recv */
1184 case 22129:
1185 /* WinTV-HVR1210 (PCIe, Retail, full height)
1186 * DVB-T and basic analog, IR Recv */
1187 case 71009:
1188 /* WinTV-HVR1200 (PCIe, Retail, full height)
1189 * DVB-T and basic analog */
1190 case 71100:
1191 /* WinTV-ImpactVCB-e (PCIe, Retail, half height)
1192 * Basic analog */
1193 case 71359:
1194 /* WinTV-HVR1200 (PCIe, OEM, half height)
1195 * DVB-T and basic analog */
1196 case 71439:
1197 /* WinTV-HVR1200 (PCIe, OEM, half height)
1198 * DVB-T and basic analog */
1199 case 71449:
1200 /* WinTV-HVR1200 (PCIe, OEM, full height)
1201 * DVB-T and basic analog */
1202 case 71939:
1203 /* WinTV-HVR1200 (PCIe, OEM, half height)
1204 * DVB-T and basic analog */
1205 case 71949:
1206 /* WinTV-HVR1200 (PCIe, OEM, full height)
1207 * DVB-T and basic analog */
1208 case 71959:
1209 /* WinTV-HVR1200 (PCIe, OEM, full height)
1210 * DVB-T and basic analog */
1211 case 71979:
1212 /* WinTV-HVR1200 (PCIe, OEM, half height)
1213 * DVB-T and basic analog */
1214 case 71999:
1215 /* WinTV-HVR1200 (PCIe, OEM, full height)
1216 * DVB-T and basic analog */
1217 case 76601:
1218 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1219 channel ATSC and MPEG2 HW Encoder */
1220 case 77001:
1221 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1222 and Basic analog */
1223 case 77011:
1224 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1225 and Basic analog */
1226 case 77041:
1227 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1228 and Basic analog */
1229 case 77051:
1230 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1231 and Basic analog */
1232 case 78011:
1233 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1234 Dual channel ATSC and MPEG2 HW Encoder */
1235 case 78501:
1236 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1237 Dual channel ATSC and MPEG2 HW Encoder */
1238 case 78521:
1239 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1240 Dual channel ATSC and MPEG2 HW Encoder */
1241 case 78531:
1242 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1243 Dual channel ATSC and MPEG2 HW Encoder */
1244 case 78631:
1245 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1246 Dual channel ATSC and MPEG2 HW Encoder */
1247 case 79001:
1248 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1249 ATSC and Basic analog */
1250 case 79101:
1251 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1252 ATSC and Basic analog */
1253 case 79501:
1254 /* WinTV-HVR1250 (PCIe, No IR, half height,
1255 ATSC [at least] and Basic analog) */
1256 case 79561:
1257 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1258 ATSC and Basic analog */
1259 case 79571:
1260 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1261 ATSC and Basic analog */
1262 case 79671:
1263 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1264 ATSC and Basic analog */
1265 case 80019:
1266 /* WinTV-HVR1400 (Express Card, Retail, IR,
1267 * DVB-T and Basic analog */
1268 case 81509:
1269 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1270 * DVB-T and MPEG2 HW Encoder */
1271 case 81519:
1272 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1273 * DVB-T and MPEG2 HW Encoder */
1274 break;
1275 case 85021:
1276 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1277 Dual channel ATSC and MPEG2 HW Encoder */
1278 break;
1279 case 85721:
1280 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1281 Dual channel ATSC and Basic analog */
1282 case 150329:
1283 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */
1284 break;
1285 case 166100:
1286 /* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height,
1287 DVB-T/T2/C, DVB-T/T2/C */
1288 break;
1289 case 166101:
1290 /* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
1291 DVB-T/T2/C, DVB-T/T2/C */
1292 break;
1293 case 165100:
1294 /*
1295 * WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height,
1296 * ATSC, ATSC
1297 */
1298 break;
1299 case 165101:
1300 /*
1301 * WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
1302 * ATSC, ATSC
1303 */
1304 break;
1305 default:
1306 pr_warn("%s: warning: unknown hauppauge model #%d\n",
1307 dev->name, tv.model);
1308 break;
1309 }
1310
1311 pr_info("%s: hauppauge eeprom: model=%d\n",
1312 dev->name, tv.model);
1313 }
1314
1315 /* Some TBS cards require initing a chip using a bitbanged SPI attached
1316 to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1317 doesn't respond to any command. */
1318 static void tbs_card_init(struct cx23885_dev *dev)
1319 {
1320 int i;
1321 const u8 buf[] = {
1322 0xe0, 0x06, 0x66, 0x33, 0x65,
1323 0x01, 0x17, 0x06, 0xde};
1324
1325 switch (dev->board) {
1326 case CX23885_BOARD_TBS_6980:
1327 case CX23885_BOARD_TBS_6981:
1328 cx_set(GP0_IO, 0x00070007);
1329 usleep_range(1000, 10000);
1330 cx_clear(GP0_IO, 2);
1331 usleep_range(1000, 10000);
1332 for (i = 0; i < 9 * 8; i++) {
1333 cx_clear(GP0_IO, 7);
1334 usleep_range(1000, 10000);
1335 cx_set(GP0_IO,
1336 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1337 usleep_range(1000, 10000);
1338 }
1339 cx_set(GP0_IO, 7);
1340 break;
1341 }
1342 }
1343
1344 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1345 {
1346 struct cx23885_tsport *port = priv;
1347 struct cx23885_dev *dev = port->dev;
1348 u32 bitmask = 0;
1349
1350 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1351 return 0;
1352
1353 if (command != 0) {
1354 pr_err("%s(): Unknown command 0x%x.\n",
1355 __func__, command);
1356 return -EINVAL;
1357 }
1358
1359 switch (dev->board) {
1360 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1361 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1362 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1363 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1364 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1365 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1366 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1367 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1368 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1369 /* Tuner Reset Command */
1370 bitmask = 0x04;
1371 break;
1372 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1373 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1374 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1375 /* Two identical tuners on two different i2c buses,
1376 * we need to reset the correct gpio. */
1377 if (port->nr == 1)
1378 bitmask = 0x01;
1379 else if (port->nr == 2)
1380 bitmask = 0x04;
1381 break;
1382 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1383 /* Tuner Reset Command */
1384 bitmask = 0x02;
1385 break;
1386 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1387 altera_ci_tuner_reset(dev, port->nr);
1388 break;
1389 case CX23885_BOARD_AVERMEDIA_HC81R:
1390 /* XC3028L Reset Command */
1391 bitmask = 1 << 2;
1392 break;
1393 }
1394
1395 if (bitmask) {
1396 /* Drive the tuner into reset and back out */
1397 cx_clear(GP0_IO, bitmask);
1398 mdelay(200);
1399 cx_set(GP0_IO, bitmask);
1400 }
1401
1402 return 0;
1403 }
1404
1405 void cx23885_gpio_setup(struct cx23885_dev *dev)
1406 {
1407 switch (dev->board) {
1408 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1409 /* GPIO-0 cx24227 demodulator reset */
1410 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1411 break;
1412 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1413 /* GPIO-0 cx24227 demodulator */
1414 /* GPIO-2 xc3028 tuner */
1415
1416 /* Put the parts into reset */
1417 cx_set(GP0_IO, 0x00050000);
1418 cx_clear(GP0_IO, 0x00000005);
1419 msleep(5);
1420
1421 /* Bring the parts out of reset */
1422 cx_set(GP0_IO, 0x00050005);
1423 break;
1424 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1425 /* GPIO-0 cx24227 demodulator reset */
1426 /* GPIO-2 xc5000 tuner reset */
1427 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1428 break;
1429 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1430 /* GPIO-0 656_CLK */
1431 /* GPIO-1 656_D0 */
1432 /* GPIO-2 8295A Reset */
1433 /* GPIO-3-10 cx23417 data0-7 */
1434 /* GPIO-11-14 cx23417 addr0-3 */
1435 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1436 /* GPIO-19 IR_RX */
1437
1438 /* CX23417 GPIO's */
1439 /* EIO15 Zilog Reset */
1440 /* EIO14 S5H1409/CX24227 Reset */
1441 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1442
1443 /* Put the demod into reset and protect the eeprom */
1444 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1445 mdelay(100);
1446
1447 /* Bring the demod and blaster out of reset */
1448 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1449 mdelay(100);
1450
1451 /* Force the TDA8295A into reset and back */
1452 cx23885_gpio_enable(dev, GPIO_2, 1);
1453 cx23885_gpio_set(dev, GPIO_2);
1454 mdelay(20);
1455 cx23885_gpio_clear(dev, GPIO_2);
1456 mdelay(20);
1457 cx23885_gpio_set(dev, GPIO_2);
1458 mdelay(20);
1459 break;
1460 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1461 /* GPIO-0 tda10048 demodulator reset */
1462 /* GPIO-2 tda18271 tuner reset */
1463
1464 /* Put the parts into reset and back */
1465 cx_set(GP0_IO, 0x00050000);
1466 mdelay(20);
1467 cx_clear(GP0_IO, 0x00000005);
1468 mdelay(20);
1469 cx_set(GP0_IO, 0x00050005);
1470 break;
1471 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1472 /* GPIO-0 TDA10048 demodulator reset */
1473 /* GPIO-2 TDA8295A Reset */
1474 /* GPIO-3-10 cx23417 data0-7 */
1475 /* GPIO-11-14 cx23417 addr0-3 */
1476 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1477
1478 /* The following GPIO's are on the interna AVCore (cx25840) */
1479 /* GPIO-19 IR_RX */
1480 /* GPIO-20 IR_TX 416/DVBT Select */
1481 /* GPIO-21 IIS DAT */
1482 /* GPIO-22 IIS WCLK */
1483 /* GPIO-23 IIS BCLK */
1484
1485 /* Put the parts into reset and back */
1486 cx_set(GP0_IO, 0x00050000);
1487 mdelay(20);
1488 cx_clear(GP0_IO, 0x00000005);
1489 mdelay(20);
1490 cx_set(GP0_IO, 0x00050005);
1491 break;
1492 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1493 /* GPIO-0 Dibcom7000p demodulator reset */
1494 /* GPIO-2 xc3028L tuner reset */
1495 /* GPIO-13 LED */
1496
1497 /* Put the parts into reset and back */
1498 cx_set(GP0_IO, 0x00050000);
1499 mdelay(20);
1500 cx_clear(GP0_IO, 0x00000005);
1501 mdelay(20);
1502 cx_set(GP0_IO, 0x00050005);
1503 break;
1504 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1505 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1506 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1507 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1508 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1509
1510 /* Put the parts into reset and back */
1511 cx_set(GP0_IO, 0x000f0000);
1512 mdelay(20);
1513 cx_clear(GP0_IO, 0x0000000f);
1514 mdelay(20);
1515 cx_set(GP0_IO, 0x000f000f);
1516 break;
1517 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1518 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1519 /* GPIO-0 portb xc3028 reset */
1520 /* GPIO-1 portb zl10353 reset */
1521 /* GPIO-2 portc xc3028 reset */
1522 /* GPIO-3 portc zl10353 reset */
1523
1524 /* Put the parts into reset and back */
1525 cx_set(GP0_IO, 0x000f0000);
1526 mdelay(20);
1527 cx_clear(GP0_IO, 0x0000000f);
1528 mdelay(20);
1529 cx_set(GP0_IO, 0x000f000f);
1530 break;
1531 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1532 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1533 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1534 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1535 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1536 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1537 /* GPIO-2 xc3028 tuner reset */
1538
1539 /* The following GPIO's are on the internal AVCore (cx25840) */
1540 /* GPIO-? zl10353 demod reset */
1541
1542 /* Put the parts into reset and back */
1543 cx_set(GP0_IO, 0x00040000);
1544 mdelay(20);
1545 cx_clear(GP0_IO, 0x00000004);
1546 mdelay(20);
1547 cx_set(GP0_IO, 0x00040004);
1548 break;
1549 case CX23885_BOARD_TBS_6920:
1550 case CX23885_BOARD_TBS_6980:
1551 case CX23885_BOARD_TBS_6981:
1552 case CX23885_BOARD_PROF_8000:
1553 cx_write(MC417_CTL, 0x00000036);
1554 cx_write(MC417_OEN, 0x00001000);
1555 cx_set(MC417_RWD, 0x00000002);
1556 mdelay(200);
1557 cx_clear(MC417_RWD, 0x00000800);
1558 mdelay(200);
1559 cx_set(MC417_RWD, 0x00000800);
1560 mdelay(200);
1561 break;
1562 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1563 /* GPIO-0 INTA from CiMax1
1564 GPIO-1 INTB from CiMax2
1565 GPIO-2 reset chips
1566 GPIO-3 to GPIO-10 data/addr for CA
1567 GPIO-11 ~CS0 to CiMax1
1568 GPIO-12 ~CS1 to CiMax2
1569 GPIO-13 ADL0 load LSB addr
1570 GPIO-14 ADL1 load MSB addr
1571 GPIO-15 ~RDY from CiMax
1572 GPIO-17 ~RD to CiMax
1573 GPIO-18 ~WR to CiMax
1574 */
1575 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1576 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1577 cx_clear(GP0_IO, 0x00030004);
1578 mdelay(100);/* reset delay */
1579 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1580 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1581 /* GPIO-15 IN as ~ACK, rest as OUT */
1582 cx_write(MC417_OEN, 0x00001000);
1583 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1584 cx_write(MC417_RWD, 0x0000c300);
1585 /* enable irq */
1586 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1587 break;
1588 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1589 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1590 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1591 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1592 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1593 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1594 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1595 /* GPIO-9 Demod reset */
1596
1597 /* Put the parts into reset and back */
1598 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1599 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1600 cx23885_gpio_clear(dev, GPIO_9);
1601 mdelay(20);
1602 cx23885_gpio_set(dev, GPIO_9);
1603 break;
1604 case CX23885_BOARD_MYGICA_X8506:
1605 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1606 case CX23885_BOARD_MYGICA_X8507:
1607 /* GPIO-0 (0)Analog / (1)Digital TV */
1608 /* GPIO-1 reset XC5000 */
1609 /* GPIO-2 demod reset */
1610 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1611 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1612 mdelay(100);
1613 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1614 mdelay(100);
1615 break;
1616 case CX23885_BOARD_MYGICA_X8558PRO:
1617 /* GPIO-0 reset first ATBM8830 */
1618 /* GPIO-1 reset second ATBM8830 */
1619 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1620 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1621 mdelay(100);
1622 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1623 mdelay(100);
1624 break;
1625 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1626 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1627 /* GPIO-0 656_CLK */
1628 /* GPIO-1 656_D0 */
1629 /* GPIO-2 Wake# */
1630 /* GPIO-3-10 cx23417 data0-7 */
1631 /* GPIO-11-14 cx23417 addr0-3 */
1632 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1633 /* GPIO-19 IR_RX */
1634 /* GPIO-20 C_IR_TX */
1635 /* GPIO-21 I2S DAT */
1636 /* GPIO-22 I2S WCLK */
1637 /* GPIO-23 I2S BCLK */
1638 /* ALT GPIO: EXP GPIO LATCH */
1639
1640 /* CX23417 GPIO's */
1641 /* GPIO-14 S5H1411/CX24228 Reset */
1642 /* GPIO-13 EEPROM write protect */
1643 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1644
1645 /* Put the demod into reset and protect the eeprom */
1646 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1647 mdelay(100);
1648
1649 /* Bring the demod out of reset */
1650 mc417_gpio_set(dev, GPIO_14);
1651 mdelay(100);
1652
1653 /* CX24228 GPIO */
1654 /* Connected to IF / Mux */
1655 break;
1656 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1657 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1658 break;
1659 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1660 /* GPIO-0 ~INT in
1661 GPIO-1 TMS out
1662 GPIO-2 ~reset chips out
1663 GPIO-3 to GPIO-10 data/addr for CA in/out
1664 GPIO-11 ~CS out
1665 GPIO-12 ADDR out
1666 GPIO-13 ~WR out
1667 GPIO-14 ~RD out
1668 GPIO-15 ~RDY in
1669 GPIO-16 TCK out
1670 GPIO-17 TDO in
1671 GPIO-18 TDI out
1672 */
1673 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1674 /* GPIO-0 as INT, reset & TMS low */
1675 cx_clear(GP0_IO, 0x00010006);
1676 mdelay(100);/* reset delay */
1677 cx_set(GP0_IO, 0x00000004); /* reset high */
1678 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1679 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1680 cx_write(MC417_OEN, 0x00005000);
1681 /* ~RD, ~WR high; ADDR low; ~CS high */
1682 cx_write(MC417_RWD, 0x00000d00);
1683 /* enable irq */
1684 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1685 break;
1686 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1687 case CX23885_BOARD_HAUPPAUGE_STARBURST:
1688 /* GPIO-8 tda10071 demod reset */
1689 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
1690
1691 /* Put the parts into reset and back */
1692 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1693
1694 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1695 mdelay(100);
1696 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1697 mdelay(100);
1698
1699 break;
1700 case CX23885_BOARD_AVERMEDIA_HC81R:
1701 cx_clear(MC417_CTL, 1);
1702 /* GPIO-0,1,2 setup direction as output */
1703 cx_set(GP0_IO, 0x00070000);
1704 mdelay(10);
1705 /* AF9013 demod reset */
1706 cx_set(GP0_IO, 0x00010001);
1707 mdelay(10);
1708 cx_clear(GP0_IO, 0x00010001);
1709 mdelay(10);
1710 cx_set(GP0_IO, 0x00010001);
1711 mdelay(10);
1712 /* demod tune? */
1713 cx_clear(GP0_IO, 0x00030003);
1714 mdelay(10);
1715 cx_set(GP0_IO, 0x00020002);
1716 mdelay(10);
1717 cx_set(GP0_IO, 0x00010001);
1718 mdelay(10);
1719 cx_clear(GP0_IO, 0x00020002);
1720 /* XC3028L tuner reset */
1721 cx_set(GP0_IO, 0x00040004);
1722 cx_clear(GP0_IO, 0x00040004);
1723 cx_set(GP0_IO, 0x00040004);
1724 mdelay(60);
1725 break;
1726 case CX23885_BOARD_DVBSKY_T9580:
1727 case CX23885_BOARD_DVBSKY_S952:
1728 case CX23885_BOARD_DVBSKY_T982:
1729 /* enable GPIO3-18 pins */
1730 cx_write(MC417_CTL, 0x00000037);
1731 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
1732 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
1733 mdelay(100);
1734 cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
1735 break;
1736 case CX23885_BOARD_DVBSKY_T980C:
1737 case CX23885_BOARD_DVBSKY_S950C:
1738 case CX23885_BOARD_TT_CT2_4500_CI:
1739 /*
1740 * GPIO-0 INTA from CiMax, input
1741 * GPIO-1 reset CiMax, output, high active
1742 * GPIO-2 reset demod, output, low active
1743 * GPIO-3 to GPIO-10 data/addr for CAM
1744 * GPIO-11 ~CS0 to CiMax1
1745 * GPIO-12 ~CS1 to CiMax2
1746 * GPIO-13 ADL0 load LSB addr
1747 * GPIO-14 ADL1 load MSB addr
1748 * GPIO-15 ~RDY from CiMax
1749 * GPIO-17 ~RD to CiMax
1750 * GPIO-18 ~WR to CiMax
1751 */
1752
1753 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
1754 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
1755 mdelay(100); /* reset delay */
1756 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
1757 cx_clear(GP0_IO, 0x00010002);
1758 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
1759
1760 /* GPIO-15 IN as ~ACK, rest as OUT */
1761 cx_write(MC417_OEN, 0x00001000);
1762
1763 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1764 cx_write(MC417_RWD, 0x0000c300);
1765
1766 /* enable irq */
1767 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
1768 break;
1769 case CX23885_BOARD_DVBSKY_S950:
1770 cx23885_gpio_enable(dev, GPIO_2, 1);
1771 cx23885_gpio_clear(dev, GPIO_2);
1772 msleep(100);
1773 cx23885_gpio_set(dev, GPIO_2);
1774 break;
1775 case CX23885_BOARD_HAUPPAUGE_HVR5525:
1776 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1777 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1778 /*
1779 * HVR5525 GPIO Details:
1780 * GPIO-00 IR_WIDE
1781 * GPIO-02 wake#
1782 * GPIO-03 VAUX Pres.
1783 * GPIO-07 PROG#
1784 * GPIO-08 SAT_RESN
1785 * GPIO-09 TER_RESN
1786 * GPIO-10 B2_SENSE
1787 * GPIO-11 B1_SENSE
1788 * GPIO-15 IR_LED_STATUS
1789 * GPIO-19 IR_NARROW
1790 * GPIO-20 Blauster1
1791 * ALTGPIO VAUX_SWITCH
1792 * AUX_PLL_CLK : Blaster2
1793 */
1794 /* Put the parts into reset and back */
1795 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1796 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1797 msleep(100);
1798 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1799 msleep(100);
1800 break;
1801 case CX23885_BOARD_VIEWCAST_260E:
1802 case CX23885_BOARD_VIEWCAST_460E:
1803 /* For documentation purposes, it's worth noting that this
1804 * card does not have any GPIO's connected to subcomponents.
1805 */
1806 break;
1807 }
1808 }
1809
1810 int cx23885_ir_init(struct cx23885_dev *dev)
1811 {
1812 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1813 {
1814 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1815 .pin = CX23885_PIN_IR_RX_GPIO19,
1816 .function = CX23885_PAD_IR_RX,
1817 .value = 0,
1818 .strength = CX25840_PIN_DRIVE_MEDIUM,
1819 }, {
1820 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1821 .pin = CX23885_PIN_IR_TX_GPIO20,
1822 .function = CX23885_PAD_IR_TX,
1823 .value = 0,
1824 .strength = CX25840_PIN_DRIVE_MEDIUM,
1825 }
1826 };
1827 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1828
1829 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1830 {
1831 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1832 .pin = CX23885_PIN_IR_RX_GPIO19,
1833 .function = CX23885_PAD_IR_RX,
1834 .value = 0,
1835 .strength = CX25840_PIN_DRIVE_MEDIUM,
1836 }
1837 };
1838 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1839
1840 struct v4l2_subdev_ir_parameters params;
1841 int ret = 0;
1842 switch (dev->board) {
1843 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1844 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1845 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1846 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1847 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1848 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1849 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1850 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1851 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1852 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1853 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1854 /* FIXME: Implement me */
1855 break;
1856 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1857 ret = cx23888_ir_probe(dev);
1858 if (ret)
1859 break;
1860 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1861 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1862 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1863 break;
1864 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1865 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1866 ret = cx23888_ir_probe(dev);
1867 if (ret)
1868 break;
1869 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1870 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1871 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1872 /*
1873 * For these boards we need to invert the Tx output via the
1874 * IR controller to have the LED off while idle
1875 */
1876 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1877 params.enable = false;
1878 params.shutdown = false;
1879 params.invert_level = true;
1880 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1881 params.shutdown = true;
1882 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1883 break;
1884 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1885 case CX23885_BOARD_TEVII_S470:
1886 case CX23885_BOARD_MYGICA_X8507:
1887 case CX23885_BOARD_TBS_6980:
1888 case CX23885_BOARD_TBS_6981:
1889 case CX23885_BOARD_DVBSKY_T9580:
1890 case CX23885_BOARD_DVBSKY_T980C:
1891 case CX23885_BOARD_DVBSKY_S950C:
1892 case CX23885_BOARD_TT_CT2_4500_CI:
1893 case CX23885_BOARD_DVBSKY_S950:
1894 case CX23885_BOARD_DVBSKY_S952:
1895 case CX23885_BOARD_DVBSKY_T982:
1896 if (!enable_885_ir)
1897 break;
1898 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1899 if (dev->sd_ir == NULL) {
1900 ret = -ENODEV;
1901 break;
1902 }
1903 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1904 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1905 break;
1906 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1907 if (!enable_885_ir)
1908 break;
1909 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1910 if (dev->sd_ir == NULL) {
1911 ret = -ENODEV;
1912 break;
1913 }
1914 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1915 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1916 break;
1917 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1918 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1919 request_module("ir-kbd-i2c");
1920 break;
1921 }
1922
1923 return ret;
1924 }
1925
1926 void cx23885_ir_fini(struct cx23885_dev *dev)
1927 {
1928 switch (dev->board) {
1929 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1930 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1931 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1932 cx23885_irq_remove(dev, PCI_MSK_IR);
1933 cx23888_ir_remove(dev);
1934 dev->sd_ir = NULL;
1935 break;
1936 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1937 case CX23885_BOARD_TEVII_S470:
1938 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1939 case CX23885_BOARD_MYGICA_X8507:
1940 case CX23885_BOARD_TBS_6980:
1941 case CX23885_BOARD_TBS_6981:
1942 case CX23885_BOARD_DVBSKY_T9580:
1943 case CX23885_BOARD_DVBSKY_T980C:
1944 case CX23885_BOARD_DVBSKY_S950C:
1945 case CX23885_BOARD_TT_CT2_4500_CI:
1946 case CX23885_BOARD_DVBSKY_S950:
1947 case CX23885_BOARD_DVBSKY_S952:
1948 case CX23885_BOARD_DVBSKY_T982:
1949 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1950 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1951 dev->sd_ir = NULL;
1952 break;
1953 }
1954 }
1955
1956 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1957 {
1958 int data;
1959 int tdo = 0;
1960 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1961 /*TMS*/
1962 data = ((cx_read(GP0_IO)) & (~0x00000002));
1963 data |= (tms ? 0x00020002 : 0x00020000);
1964 cx_write(GP0_IO, data);
1965
1966 /*TDI*/
1967 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1968 data |= (tdi ? 0x00008000 : 0);
1969 cx_write(MC417_RWD, data);
1970 if (read_tdo)
1971 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1972
1973 cx_write(MC417_RWD, data | 0x00002000);
1974 udelay(1);
1975 /*TCK*/
1976 cx_write(MC417_RWD, data);
1977
1978 return tdo;
1979 }
1980
1981 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1982 {
1983 switch (dev->board) {
1984 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1985 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1986 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1987 if (dev->sd_ir)
1988 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1989 break;
1990 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1991 case CX23885_BOARD_TEVII_S470:
1992 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1993 case CX23885_BOARD_MYGICA_X8507:
1994 case CX23885_BOARD_TBS_6980:
1995 case CX23885_BOARD_TBS_6981:
1996 case CX23885_BOARD_DVBSKY_T9580:
1997 case CX23885_BOARD_DVBSKY_T980C:
1998 case CX23885_BOARD_DVBSKY_S950C:
1999 case CX23885_BOARD_TT_CT2_4500_CI:
2000 case CX23885_BOARD_DVBSKY_S950:
2001 case CX23885_BOARD_DVBSKY_S952:
2002 case CX23885_BOARD_DVBSKY_T982:
2003 if (dev->sd_ir)
2004 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
2005 break;
2006 }
2007 }
2008
2009 void cx23885_card_setup(struct cx23885_dev *dev)
2010 {
2011 struct cx23885_tsport *ts1 = &dev->ts1;
2012 struct cx23885_tsport *ts2 = &dev->ts2;
2013
2014 static u8 eeprom[256];
2015
2016 if (dev->i2c_bus[0].i2c_rc == 0) {
2017 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
2018 tveeprom_read(&dev->i2c_bus[0].i2c_client,
2019 eeprom, sizeof(eeprom));
2020 }
2021
2022 switch (dev->board) {
2023 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2024 if (dev->i2c_bus[0].i2c_rc == 0) {
2025 if (eeprom[0x80] != 0x84)
2026 hauppauge_eeprom(dev, eeprom+0xc0);
2027 else
2028 hauppauge_eeprom(dev, eeprom+0x80);
2029 }
2030 break;
2031 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2032 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2033 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2034 if (dev->i2c_bus[0].i2c_rc == 0)
2035 hauppauge_eeprom(dev, eeprom+0x80);
2036 break;
2037 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2038 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2039 case CX23885_BOARD_HAUPPAUGE_HVR1200:
2040 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2041 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2042 case CX23885_BOARD_HAUPPAUGE_HVR1275:
2043 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2044 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2045 case CX23885_BOARD_HAUPPAUGE_HVR1210:
2046 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2047 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2048 case CX23885_BOARD_HAUPPAUGE_HVR4400:
2049 case CX23885_BOARD_HAUPPAUGE_STARBURST:
2050 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2051 case CX23885_BOARD_HAUPPAUGE_HVR5525:
2052 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2053 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2054 if (dev->i2c_bus[0].i2c_rc == 0)
2055 hauppauge_eeprom(dev, eeprom+0xc0);
2056 break;
2057 case CX23885_BOARD_VIEWCAST_260E:
2058 case CX23885_BOARD_VIEWCAST_460E:
2059 dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1;
2060 tveeprom_read(&dev->i2c_bus[1].i2c_client,
2061 eeprom, sizeof(eeprom));
2062 if (dev->i2c_bus[0].i2c_rc == 0)
2063 viewcast_eeprom(dev, eeprom);
2064 break;
2065 }
2066
2067 switch (dev->board) {
2068 case CX23885_BOARD_AVERMEDIA_HC81R:
2069 /* Defaults for VID B */
2070 ts1->gen_ctrl_val = 0x4; /* Parallel */
2071 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2072 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2073 /* Defaults for VID C */
2074 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2075 ts2->gen_ctrl_val = 0x10e;
2076 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2077 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2078 break;
2079 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
2080 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
2081 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
2082 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2083 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2084 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2085 /* break omitted intentionally */
2086 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
2087 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2088 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2089 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2090 break;
2091 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2092 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2093 /* Defaults for VID B - Analog encoder */
2094 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2095 ts1->gen_ctrl_val = 0x10e;
2096 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2097 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2098
2099 /* APB_TSVALERR_POL (active low)*/
2100 ts1->vld_misc_val = 0x2000;
2101 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
2102 cx_write(0x130184, 0xc);
2103
2104 /* Defaults for VID C */
2105 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2106 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2107 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2108 break;
2109 case CX23885_BOARD_TBS_6920:
2110 ts1->gen_ctrl_val = 0x4; /* Parallel */
2111 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2112 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2113 break;
2114 case CX23885_BOARD_TEVII_S470:
2115 case CX23885_BOARD_TEVII_S471:
2116 case CX23885_BOARD_DVBWORLD_2005:
2117 case CX23885_BOARD_PROF_8000:
2118 case CX23885_BOARD_DVBSKY_T980C:
2119 case CX23885_BOARD_DVBSKY_S950C:
2120 case CX23885_BOARD_TT_CT2_4500_CI:
2121 case CX23885_BOARD_DVBSKY_S950:
2122 ts1->gen_ctrl_val = 0x5; /* Parallel */
2123 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2124 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2125 break;
2126 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2127 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2128 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2129 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2130 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2131 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2132 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2133 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2134 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2135 break;
2136 case CX23885_BOARD_TBS_6980:
2137 case CX23885_BOARD_TBS_6981:
2138 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2139 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2140 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2141 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2142 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2143 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2144 tbs_card_init(dev);
2145 break;
2146 case CX23885_BOARD_MYGICA_X8506:
2147 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2148 case CX23885_BOARD_MYGICA_X8507:
2149 ts1->gen_ctrl_val = 0x5; /* Parallel */
2150 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2151 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2152 break;
2153 case CX23885_BOARD_MYGICA_X8558PRO:
2154 ts1->gen_ctrl_val = 0x5; /* Parallel */
2155 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2156 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2157 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2158 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2159 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2160 break;
2161 case CX23885_BOARD_HAUPPAUGE_HVR4400:
2162 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2163 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2164 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2165 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2166 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2167 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2168 break;
2169 case CX23885_BOARD_HAUPPAUGE_STARBURST:
2170 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2171 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2172 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2173 break;
2174 case CX23885_BOARD_DVBSKY_T9580:
2175 case CX23885_BOARD_DVBSKY_T982:
2176 ts1->gen_ctrl_val = 0x5; /* Parallel */
2177 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2178 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2179 ts2->gen_ctrl_val = 0x8; /* Serial bus */
2180 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2181 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2182 break;
2183 case CX23885_BOARD_DVBSKY_S952:
2184 ts1->gen_ctrl_val = 0x5; /* Parallel */
2185 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2186 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2187 ts2->gen_ctrl_val = 0xe; /* Serial bus */
2188 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2189 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2190 break;
2191 case CX23885_BOARD_HAUPPAUGE_HVR5525:
2192 ts1->gen_ctrl_val = 0x5; /* Parallel */
2193 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2194 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2195 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2196 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2197 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2198 break;
2199 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2200 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2201 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2202 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2203 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2204 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2205 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2206 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2207 break;
2208 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2209 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2210 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2211 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2212 case CX23885_BOARD_HAUPPAUGE_HVR1200:
2213 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2214 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2215 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2216 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2217 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2218 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2219 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2220 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2221 case CX23885_BOARD_HAUPPAUGE_HVR1275:
2222 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2223 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2224 case CX23885_BOARD_HAUPPAUGE_HVR1210:
2225 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2226 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2227 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2228 default:
2229 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2230 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2231 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2232 }
2233
2234 /* Certain boards support analog, or require the avcore to be
2235 * loaded, ensure this happens.
2236 */
2237 switch (dev->board) {
2238 case CX23885_BOARD_TEVII_S470:
2239 /* Currently only enabled for the integrated IR controller */
2240 if (!enable_885_ir)
2241 break;
2242 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2243 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2244 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2245 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2246 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2247 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2248 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2249 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2250 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2251 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2252 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2253 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2254 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2255 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2256 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2257 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2258 case CX23885_BOARD_MYGICA_X8506:
2259 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2260 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2261 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
2262 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2263 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2264 case CX23885_BOARD_MPX885:
2265 case CX23885_BOARD_MYGICA_X8507:
2266 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2267 case CX23885_BOARD_AVERMEDIA_HC81R:
2268 case CX23885_BOARD_TBS_6980:
2269 case CX23885_BOARD_TBS_6981:
2270 case CX23885_BOARD_DVBSKY_T9580:
2271 case CX23885_BOARD_DVBSKY_T980C:
2272 case CX23885_BOARD_DVBSKY_S950C:
2273 case CX23885_BOARD_TT_CT2_4500_CI:
2274 case CX23885_BOARD_DVBSKY_S950:
2275 case CX23885_BOARD_DVBSKY_S952:
2276 case CX23885_BOARD_DVBSKY_T982:
2277 case CX23885_BOARD_VIEWCAST_260E:
2278 case CX23885_BOARD_VIEWCAST_460E:
2279 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
2280 &dev->i2c_bus[2].i2c_adap,
2281 "cx25840", 0x88 >> 1, NULL);
2282 if (dev->sd_cx25840) {
2283 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
2284 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
2285 }
2286 break;
2287 }
2288
2289 switch (dev->board) {
2290 case CX23885_BOARD_VIEWCAST_260E:
2291 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2292 &dev->i2c_bus[0].i2c_adap,
2293 "cs3308", 0x82 >> 1, NULL);
2294 break;
2295 case CX23885_BOARD_VIEWCAST_460E:
2296 /* This cs3308 controls the audio from the breakout cable */
2297 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2298 &dev->i2c_bus[0].i2c_adap,
2299 "cs3308", 0x80 >> 1, NULL);
2300 /* This cs3308 controls the audio from the onboard header */
2301 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2302 &dev->i2c_bus[0].i2c_adap,
2303 "cs3308", 0x82 >> 1, NULL);
2304 break;
2305 }
2306
2307 /* AUX-PLL 27MHz CLK */
2308 switch (dev->board) {
2309 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2310 netup_initialize(dev);
2311 break;
2312 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
2313 int ret;
2314 const struct firmware *fw;
2315 const char *filename = "dvb-netup-altera-01.fw";
2316 char *action = "configure";
2317 static struct netup_card_info cinfo;
2318 struct altera_config netup_config = {
2319 .dev = dev,
2320 .action = action,
2321 .jtag_io = netup_jtag_io,
2322 };
2323
2324 netup_initialize(dev);
2325
2326 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2327 if (netup_card_rev)
2328 cinfo.rev = netup_card_rev;
2329
2330 switch (cinfo.rev) {
2331 case 0x4:
2332 filename = "dvb-netup-altera-04.fw";
2333 break;
2334 default:
2335 filename = "dvb-netup-altera-01.fw";
2336 break;
2337 }
2338 pr_info("NetUP card rev=0x%x fw_filename=%s\n",
2339 cinfo.rev, filename);
2340
2341 ret = request_firmware(&fw, filename, &dev->pci->dev);
2342 if (ret != 0)
2343 pr_err("did not find the firmware file. (%s) Please see linux/Documentation/dvb/ for more details on firmware-problems.",
2344 filename);
2345 else
2346 altera_init(&netup_config, fw);
2347
2348 release_firmware(fw);
2349 break;
2350 }
2351 }
2352 }
Linux with added FPC-III support