sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / pci / cx88 / cx88-vbi.c
blob2d0ef19e6d65c7d20067332d65f378292ec66455
1 /*
2 */
4 #include "cx88.h"
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
10 static unsigned int vbi_debug;
11 module_param(vbi_debug, int, 0644);
12 MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
14 #define dprintk(level, fmt, arg...) do { \
15 if (vbi_debug >= level) \
16 printk(KERN_DEBUG pr_fmt("%s: vbi:" fmt), \
17 __func__, ##arg); \
18 } while (0)
20 /* ------------------------------------------------------------------ */
22 int cx8800_vbi_fmt(struct file *file, void *priv,
23 struct v4l2_format *f)
25 struct cx8800_dev *dev = video_drvdata(file);
27 f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
28 f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
29 f->fmt.vbi.offset = 244;
31 if (dev->core->tvnorm & V4L2_STD_525_60) {
32 /* ntsc */
33 f->fmt.vbi.sampling_rate = 28636363;
34 f->fmt.vbi.start[0] = 10;
35 f->fmt.vbi.start[1] = 273;
36 f->fmt.vbi.count[0] = VBI_LINE_NTSC_COUNT;
37 f->fmt.vbi.count[1] = VBI_LINE_NTSC_COUNT;
39 } else if (dev->core->tvnorm & V4L2_STD_625_50) {
40 /* pal */
41 f->fmt.vbi.sampling_rate = 35468950;
42 f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
43 f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
44 f->fmt.vbi.count[0] = VBI_LINE_PAL_COUNT;
45 f->fmt.vbi.count[1] = VBI_LINE_PAL_COUNT;
47 return 0;
50 static int cx8800_start_vbi_dma(struct cx8800_dev *dev,
51 struct cx88_dmaqueue *q,
52 struct cx88_buffer *buf)
54 struct cx88_core *core = dev->core;
56 /* setup fifo + format */
57 cx88_sram_channel_setup(dev->core, &cx88_sram_channels[SRAM_CH24],
58 VBI_LINE_LENGTH, buf->risc.dma);
60 cx_write(MO_VBOS_CONTROL, (1 << 18) | /* comb filter delay fixup */
61 (1 << 15) | /* enable vbi capture */
62 (1 << 11));
64 /* reset counter */
65 cx_write(MO_VBI_GPCNTRL, GP_COUNT_CONTROL_RESET);
66 q->count = 0;
68 /* enable irqs */
69 cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
70 cx_set(MO_VID_INTMSK, 0x0f0088);
72 /* enable capture */
73 cx_set(VID_CAPTURE_CONTROL, 0x18);
75 /* start dma */
76 cx_set(MO_DEV_CNTRL2, (1 << 5));
77 cx_set(MO_VID_DMACNTRL, 0x88);
79 return 0;
82 void cx8800_stop_vbi_dma(struct cx8800_dev *dev)
84 struct cx88_core *core = dev->core;
86 /* stop dma */
87 cx_clear(MO_VID_DMACNTRL, 0x88);
89 /* disable capture */
90 cx_clear(VID_CAPTURE_CONTROL, 0x18);
92 /* disable irqs */
93 cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
94 cx_clear(MO_VID_INTMSK, 0x0f0088);
97 int cx8800_restart_vbi_queue(struct cx8800_dev *dev,
98 struct cx88_dmaqueue *q)
100 struct cx88_buffer *buf;
102 if (list_empty(&q->active))
103 return 0;
105 buf = list_entry(q->active.next, struct cx88_buffer, list);
106 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
107 buf, buf->vb.vb2_buf.index);
108 cx8800_start_vbi_dma(dev, q, buf);
109 return 0;
112 /* ------------------------------------------------------------------ */
114 static int queue_setup(struct vb2_queue *q,
115 unsigned int *num_buffers, unsigned int *num_planes,
116 unsigned int sizes[], struct device *alloc_devs[])
118 struct cx8800_dev *dev = q->drv_priv;
120 *num_planes = 1;
121 if (dev->core->tvnorm & V4L2_STD_525_60)
122 sizes[0] = VBI_LINE_NTSC_COUNT * VBI_LINE_LENGTH * 2;
123 else
124 sizes[0] = VBI_LINE_PAL_COUNT * VBI_LINE_LENGTH * 2;
125 return 0;
128 static int buffer_prepare(struct vb2_buffer *vb)
130 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
131 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
132 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
133 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
134 unsigned int lines;
135 unsigned int size;
137 if (dev->core->tvnorm & V4L2_STD_525_60)
138 lines = VBI_LINE_NTSC_COUNT;
139 else
140 lines = VBI_LINE_PAL_COUNT;
141 size = lines * VBI_LINE_LENGTH * 2;
142 if (vb2_plane_size(vb, 0) < size)
143 return -EINVAL;
144 vb2_set_plane_payload(vb, 0, size);
146 cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl,
147 0, VBI_LINE_LENGTH * lines,
148 VBI_LINE_LENGTH, 0,
149 lines);
150 return 0;
153 static void buffer_finish(struct vb2_buffer *vb)
155 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
156 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
157 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
158 struct cx88_riscmem *risc = &buf->risc;
160 if (risc->cpu)
161 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
162 memset(risc, 0, sizeof(*risc));
165 static void buffer_queue(struct vb2_buffer *vb)
167 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
168 struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
169 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
170 struct cx88_buffer *prev;
171 struct cx88_dmaqueue *q = &dev->vbiq;
173 /* add jump to start */
174 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
175 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
176 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
178 if (list_empty(&q->active)) {
179 list_add_tail(&buf->list, &q->active);
180 cx8800_start_vbi_dma(dev, q, buf);
181 dprintk(2, "[%p/%d] vbi_queue - first active\n",
182 buf, buf->vb.vb2_buf.index);
184 } else {
185 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
186 prev = list_entry(q->active.prev, struct cx88_buffer, list);
187 list_add_tail(&buf->list, &q->active);
188 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
189 dprintk(2, "[%p/%d] buffer_queue - append to active\n",
190 buf, buf->vb.vb2_buf.index);
194 static int start_streaming(struct vb2_queue *q, unsigned int count)
196 struct cx8800_dev *dev = q->drv_priv;
197 struct cx88_dmaqueue *dmaq = &dev->vbiq;
198 struct cx88_buffer *buf = list_entry(dmaq->active.next,
199 struct cx88_buffer, list);
201 cx8800_start_vbi_dma(dev, dmaq, buf);
202 return 0;
205 static void stop_streaming(struct vb2_queue *q)
207 struct cx8800_dev *dev = q->drv_priv;
208 struct cx88_core *core = dev->core;
209 struct cx88_dmaqueue *dmaq = &dev->vbiq;
210 unsigned long flags;
212 cx_clear(MO_VID_DMACNTRL, 0x11);
213 cx_clear(VID_CAPTURE_CONTROL, 0x06);
214 cx8800_stop_vbi_dma(dev);
215 spin_lock_irqsave(&dev->slock, flags);
216 while (!list_empty(&dmaq->active)) {
217 struct cx88_buffer *buf = list_entry(dmaq->active.next,
218 struct cx88_buffer, list);
220 list_del(&buf->list);
221 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
223 spin_unlock_irqrestore(&dev->slock, flags);
226 const struct vb2_ops cx8800_vbi_qops = {
227 .queue_setup = queue_setup,
228 .buf_prepare = buffer_prepare,
229 .buf_finish = buffer_finish,
230 .buf_queue = buffer_queue,
231 .wait_prepare = vb2_ops_wait_prepare,
232 .wait_finish = vb2_ops_wait_finish,
233 .start_streaming = start_streaming,
234 .stop_streaming = stop_streaming,