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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / pci / ddbridge / ddbridge-core.c
bloba6c9fe235974a81dd9f761182a1948d09a95ad1e
1 /*
2 * ddbridge.c: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/poll.h>
30 #include <linux/io.h>
31 #include <linux/pci.h>
32 #include <linux/pci_ids.h>
33 #include <linux/timer.h>
34 #include <linux/i2c.h>
35 #include <linux/swab.h>
36 #include <linux/vmalloc.h>
37 #include "ddbridge.h"
38
39 #include "ddbridge-regs.h"
40
41 #include "tda18271c2dd.h"
42 #include "stv6110x.h"
43 #include "stv090x.h"
44 #include "lnbh24.h"
45 #include "drxk.h"
46
47 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
48
49 /* MSI had problems with lost interrupts, fixed but needs testing */
50 #undef CONFIG_PCI_MSI
51
52 /******************************************************************************/
53
54 static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
55 {
56 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
57 .buf = val, .len = 1 } };
58 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
59 }
60
61 static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
62 {
63 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
64 .buf = &reg, .len = 1 },
65 {.addr = adr, .flags = I2C_M_RD,
66 .buf = val, .len = 1 } };
67 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
68 }
69
70 static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
71 u16 reg, u8 *val)
72 {
73 u8 msg[2] = {reg>>8, reg&0xff};
74 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
75 .buf = msg, .len = 2},
76 {.addr = adr, .flags = I2C_M_RD,
77 .buf = val, .len = 1} };
78 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
79 }
80
81 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
82 {
83 struct ddb *dev = i2c->dev;
84 long stat;
85 u32 val;
86
87 i2c->done = 0;
88 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
89 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
90 if (stat == 0) {
91 printk(KERN_ERR "I2C timeout\n");
92 { /* MSI debugging*/
93 u32 istat = ddbreadl(INTERRUPT_STATUS);
94 printk(KERN_ERR "IRS %08x\n", istat);
95 ddbwritel(istat, INTERRUPT_ACK);
96 }
97 return -EIO;
98 }
99 val = ddbreadl(i2c->regs+I2C_COMMAND);
100 if (val & 0x70000)
101 return -EIO;
102 return 0;
103 }
104
105 static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
106 struct i2c_msg msg[], int num)
107 {
108 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
109 struct ddb *dev = i2c->dev;
110 u8 addr = 0;
111
112 if (num)
113 addr = msg[0].addr;
114
115 if (num == 2 && msg[1].flags & I2C_M_RD &&
116 !(msg[0].flags & I2C_M_RD)) {
117 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
118 msg[0].buf, msg[0].len);
119 ddbwritel(msg[0].len|(msg[1].len << 16),
120 i2c->regs+I2C_TASKLENGTH);
121 if (!ddb_i2c_cmd(i2c, addr, 1)) {
122 memcpy_fromio(msg[1].buf,
123 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
124 msg[1].len);
125 return num;
126 }
127 }
128
129 if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
130 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
131 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
132 if (!ddb_i2c_cmd(i2c, addr, 2))
133 return num;
134 }
135 if (num == 1 && (msg[0].flags & I2C_M_RD)) {
136 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
137 if (!ddb_i2c_cmd(i2c, addr, 3)) {
138 ddbcpyfrom(msg[0].buf,
139 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
140 return num;
141 }
142 }
143 return -EIO;
144 }
145
146
147 static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
148 {
149 return I2C_FUNC_SMBUS_EMUL;
150 }
151
152 static struct i2c_algorithm ddb_i2c_algo = {
153 .master_xfer = ddb_i2c_master_xfer,
154 .functionality = ddb_i2c_functionality,
155 };
156
157 static void ddb_i2c_release(struct ddb *dev)
158 {
159 int i;
160 struct ddb_i2c *i2c;
161 struct i2c_adapter *adap;
162
163 for (i = 0; i < dev->info->port_num; i++) {
164 i2c = &dev->i2c[i];
165 adap = &i2c->adap;
166 i2c_del_adapter(adap);
167 }
168 }
169
170 static int ddb_i2c_init(struct ddb *dev)
171 {
172 int i, j, stat = 0;
173 struct ddb_i2c *i2c;
174 struct i2c_adapter *adap;
175
176 for (i = 0; i < dev->info->port_num; i++) {
177 i2c = &dev->i2c[i];
178 i2c->dev = dev;
179 i2c->nr = i;
180 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
181 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
182 i2c->regs = 0x80 + i * 0x20;
183 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
184 ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
185 i2c->regs + I2C_TASKADDRESS);
186 init_waitqueue_head(&i2c->wq);
187
188 adap = &i2c->adap;
189 i2c_set_adapdata(adap, i2c);
190 #ifdef I2C_ADAP_CLASS_TV_DIGITAL
191 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
192 #else
193 #ifdef I2C_CLASS_TV_ANALOG
194 adap->class = I2C_CLASS_TV_ANALOG;
195 #endif
196 #endif
197 strcpy(adap->name, "ddbridge");
198 adap->algo = &ddb_i2c_algo;
199 adap->algo_data = (void *)i2c;
200 adap->dev.parent = &dev->pdev->dev;
201 stat = i2c_add_adapter(adap);
202 if (stat)
203 break;
204 }
205 if (stat)
206 for (j = 0; j < i; j++) {
207 i2c = &dev->i2c[j];
208 adap = &i2c->adap;
209 i2c_del_adapter(adap);
210 }
211 return stat;
212 }
213
214
215 /******************************************************************************/
216 /******************************************************************************/
217 /******************************************************************************/
218
219 #if 0
220 static void set_table(struct ddb *dev, u32 off,
221 dma_addr_t *pbuf, u32 num)
222 {
223 u32 i, base;
224 u64 mem;
225
226 base = DMA_BASE_ADDRESS_TABLE + off;
227 for (i = 0; i < num; i++) {
228 mem = pbuf[i];
229 ddbwritel(mem & 0xffffffff, base + i * 8);
230 ddbwritel(mem >> 32, base + i * 8 + 4);
231 }
232 }
233 #endif
234
235 static void ddb_address_table(struct ddb *dev)
236 {
237 u32 i, j, base;
238 u64 mem;
239 dma_addr_t *pbuf;
240
241 for (i = 0; i < dev->info->port_num * 2; i++) {
242 base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
243 pbuf = dev->input[i].pbuf;
244 for (j = 0; j < dev->input[i].dma_buf_num; j++) {
245 mem = pbuf[j];
246 ddbwritel(mem & 0xffffffff, base + j * 8);
247 ddbwritel(mem >> 32, base + j * 8 + 4);
248 }
249 }
250 for (i = 0; i < dev->info->port_num; i++) {
251 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
252 pbuf = dev->output[i].pbuf;
253 for (j = 0; j < dev->output[i].dma_buf_num; j++) {
254 mem = pbuf[j];
255 ddbwritel(mem & 0xffffffff, base + j * 8);
256 ddbwritel(mem >> 32, base + j * 8 + 4);
257 }
258 }
259 }
260
261 static void io_free(struct pci_dev *pdev, u8 **vbuf,
262 dma_addr_t *pbuf, u32 size, int num)
263 {
264 int i;
265
266 for (i = 0; i < num; i++) {
267 if (vbuf[i]) {
268 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
269 vbuf[i] = NULL;
270 }
271 }
272 }
273
274 static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
275 dma_addr_t *pbuf, u32 size, int num)
276 {
277 int i;
278
279 for (i = 0; i < num; i++) {
280 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
281 if (!vbuf[i])
282 return -ENOMEM;
283 }
284 return 0;
285 }
286
287 static int ddb_buffers_alloc(struct ddb *dev)
288 {
289 int i;
290 struct ddb_port *port;
291
292 for (i = 0; i < dev->info->port_num; i++) {
293 port = &dev->port[i];
294 switch (port->class) {
295 case DDB_PORT_TUNER:
296 if (io_alloc(dev->pdev, port->input[0]->vbuf,
297 port->input[0]->pbuf,
298 port->input[0]->dma_buf_size,
299 port->input[0]->dma_buf_num) < 0)
300 return -1;
301 if (io_alloc(dev->pdev, port->input[1]->vbuf,
302 port->input[1]->pbuf,
303 port->input[1]->dma_buf_size,
304 port->input[1]->dma_buf_num) < 0)
305 return -1;
306 break;
307 case DDB_PORT_CI:
308 if (io_alloc(dev->pdev, port->input[0]->vbuf,
309 port->input[0]->pbuf,
310 port->input[0]->dma_buf_size,
311 port->input[0]->dma_buf_num) < 0)
312 return -1;
313 if (io_alloc(dev->pdev, port->output->vbuf,
314 port->output->pbuf,
315 port->output->dma_buf_size,
316 port->output->dma_buf_num) < 0)
317 return -1;
318 break;
319 default:
320 break;
321 }
322 }
323 ddb_address_table(dev);
324 return 0;
325 }
326
327 static void ddb_buffers_free(struct ddb *dev)
328 {
329 int i;
330 struct ddb_port *port;
331
332 for (i = 0; i < dev->info->port_num; i++) {
333 port = &dev->port[i];
334 io_free(dev->pdev, port->input[0]->vbuf,
335 port->input[0]->pbuf,
336 port->input[0]->dma_buf_size,
337 port->input[0]->dma_buf_num);
338 io_free(dev->pdev, port->input[1]->vbuf,
339 port->input[1]->pbuf,
340 port->input[1]->dma_buf_size,
341 port->input[1]->dma_buf_num);
342 io_free(dev->pdev, port->output->vbuf,
343 port->output->pbuf,
344 port->output->dma_buf_size,
345 port->output->dma_buf_num);
346 }
347 }
348
349 static void ddb_input_start(struct ddb_input *input)
350 {
351 struct ddb *dev = input->port->dev;
352
353 spin_lock_irq(&input->lock);
354 input->cbuf = 0;
355 input->coff = 0;
356
357 /* reset */
358 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
359 ddbwritel(2, TS_INPUT_CONTROL(input->nr));
360 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
361
362 ddbwritel((1 << 16) |
363 (input->dma_buf_num << 11) |
364 (input->dma_buf_size >> 7),
365 DMA_BUFFER_SIZE(input->nr));
366 ddbwritel(0, DMA_BUFFER_ACK(input->nr));
367
368 ddbwritel(1, DMA_BASE_WRITE);
369 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
370 ddbwritel(9, TS_INPUT_CONTROL(input->nr));
371 input->running = 1;
372 spin_unlock_irq(&input->lock);
373 }
374
375 static void ddb_input_stop(struct ddb_input *input)
376 {
377 struct ddb *dev = input->port->dev;
378
379 spin_lock_irq(&input->lock);
380 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
381 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
382 input->running = 0;
383 spin_unlock_irq(&input->lock);
384 }
385
386 static void ddb_output_start(struct ddb_output *output)
387 {
388 struct ddb *dev = output->port->dev;
389
390 spin_lock_irq(&output->lock);
391 output->cbuf = 0;
392 output->coff = 0;
393 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
394 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
395 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
396 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
397 ddbwritel((1 << 16) |
398 (output->dma_buf_num << 11) |
399 (output->dma_buf_size >> 7),
400 DMA_BUFFER_SIZE(output->nr + 8));
401 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
402
403 ddbwritel(1, DMA_BASE_READ);
404 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
405 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
406 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
407 output->running = 1;
408 spin_unlock_irq(&output->lock);
409 }
410
411 static void ddb_output_stop(struct ddb_output *output)
412 {
413 struct ddb *dev = output->port->dev;
414
415 spin_lock_irq(&output->lock);
416 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
417 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
418 output->running = 0;
419 spin_unlock_irq(&output->lock);
420 }
421
422 static u32 ddb_output_free(struct ddb_output *output)
423 {
424 u32 idx, off, stat = output->stat;
425 s32 diff;
426
427 idx = (stat >> 11) & 0x1f;
428 off = (stat & 0x7ff) << 7;
429
430 if (output->cbuf != idx) {
431 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
432 (output->dma_buf_size - output->coff <= 188))
433 return 0;
434 return 188;
435 }
436 diff = off - output->coff;
437 if (diff <= 0 || diff > 188)
438 return 188;
439 return 0;
440 }
441
442 static ssize_t ddb_output_write(struct ddb_output *output,
443 const __user u8 *buf, size_t count)
444 {
445 struct ddb *dev = output->port->dev;
446 u32 idx, off, stat = output->stat;
447 u32 left = count, len;
448
449 idx = (stat >> 11) & 0x1f;
450 off = (stat & 0x7ff) << 7;
451
452 while (left) {
453 len = output->dma_buf_size - output->coff;
454 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
455 (off == 0)) {
456 if (len <= 188)
457 break;
458 len -= 188;
459 }
460 if (output->cbuf == idx) {
461 if (off > output->coff) {
462 #if 1
463 len = off - output->coff;
464 len -= (len % 188);
465 if (len <= 188)
466
467 #endif
468 break;
469 len -= 188;
470 }
471 }
472 if (len > left)
473 len = left;
474 if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
475 buf, len))
476 return -EIO;
477 left -= len;
478 buf += len;
479 output->coff += len;
480 if (output->coff == output->dma_buf_size) {
481 output->coff = 0;
482 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
483 }
484 ddbwritel((output->cbuf << 11) | (output->coff >> 7),
485 DMA_BUFFER_ACK(output->nr + 8));
486 }
487 return count - left;
488 }
489
490 static u32 ddb_input_avail(struct ddb_input *input)
491 {
492 struct ddb *dev = input->port->dev;
493 u32 idx, off, stat = input->stat;
494 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
495
496 idx = (stat >> 11) & 0x1f;
497 off = (stat & 0x7ff) << 7;
498
499 if (ctrl & 4) {
500 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
501 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
502 return 0;
503 }
504 if (input->cbuf != idx)
505 return 188;
506 return 0;
507 }
508
509 static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count)
510 {
511 struct ddb *dev = input->port->dev;
512 u32 left = count;
513 u32 idx, free, stat = input->stat;
514 int ret;
515
516 idx = (stat >> 11) & 0x1f;
517
518 while (left) {
519 if (input->cbuf == idx)
520 return count - left;
521 free = input->dma_buf_size - input->coff;
522 if (free > left)
523 free = left;
524 ret = copy_to_user(buf, input->vbuf[input->cbuf] +
525 input->coff, free);
526 if (ret)
527 return -EFAULT;
528 input->coff += free;
529 if (input->coff == input->dma_buf_size) {
530 input->coff = 0;
531 input->cbuf = (input->cbuf+1) % input->dma_buf_num;
532 }
533 left -= free;
534 ddbwritel((input->cbuf << 11) | (input->coff >> 7),
535 DMA_BUFFER_ACK(input->nr));
536 }
537 return count;
538 }
539
540 /******************************************************************************/
541 /******************************************************************************/
542 /******************************************************************************/
543
544 #if 0
545 static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
546 {
547 int i;
548
549 for (i = 0; i < dev->info->port_num * 2; i++) {
550 if (dev->input[i].fe == fe)
551 return &dev->input[i];
552 }
553 return NULL;
554 }
555 #endif
556
557 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
558 {
559 struct ddb_input *input = fe->sec_priv;
560 struct ddb_port *port = input->port;
561 int status;
562
563 if (enable) {
564 mutex_lock(&port->i2c_gate_lock);
565 status = input->gate_ctrl(fe, 1);
566 } else {
567 status = input->gate_ctrl(fe, 0);
568 mutex_unlock(&port->i2c_gate_lock);
569 }
570 return status;
571 }
572
573 static int demod_attach_drxk(struct ddb_input *input)
574 {
575 struct i2c_adapter *i2c = &input->port->i2c->adap;
576 struct dvb_frontend *fe;
577 struct drxk_config config;
578
579 memset(&config, 0, sizeof(config));
580 config.microcode_name = "drxk_a3.mc";
581 config.qam_demod_parameter_count = 4;
582 config.adr = 0x29 + (input->nr & 1);
583
584 fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
585 if (!input->fe) {
586 printk(KERN_ERR "No DRXK found!\n");
587 return -ENODEV;
588 }
589 fe->sec_priv = input;
590 input->gate_ctrl = fe->ops.i2c_gate_ctrl;
591 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
592 return 0;
593 }
594
595 static int tuner_attach_tda18271(struct ddb_input *input)
596 {
597 struct i2c_adapter *i2c = &input->port->i2c->adap;
598 struct dvb_frontend *fe;
599
600 if (input->fe->ops.i2c_gate_ctrl)
601 input->fe->ops.i2c_gate_ctrl(input->fe, 1);
602 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
603 if (!fe) {
604 printk(KERN_ERR "No TDA18271 found!\n");
605 return -ENODEV;
606 }
607 if (input->fe->ops.i2c_gate_ctrl)
608 input->fe->ops.i2c_gate_ctrl(input->fe, 0);
609 return 0;
610 }
611
612 /******************************************************************************/
613 /******************************************************************************/
614 /******************************************************************************/
615
616 static struct stv090x_config stv0900 = {
617 .device = STV0900,
618 .demod_mode = STV090x_DUAL,
619 .clk_mode = STV090x_CLK_EXT,
620
621 .xtal = 27000000,
622 .address = 0x69,
623
624 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
625 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
626
627 .repeater_level = STV090x_RPTLEVEL_16,
628
629 .adc1_range = STV090x_ADC_1Vpp,
630 .adc2_range = STV090x_ADC_1Vpp,
631
632 .diseqc_envelope_mode = true,
633 };
634
635 static struct stv090x_config stv0900_aa = {
636 .device = STV0900,
637 .demod_mode = STV090x_DUAL,
638 .clk_mode = STV090x_CLK_EXT,
639
640 .xtal = 27000000,
641 .address = 0x68,
642
643 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
644 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
645
646 .repeater_level = STV090x_RPTLEVEL_16,
647
648 .adc1_range = STV090x_ADC_1Vpp,
649 .adc2_range = STV090x_ADC_1Vpp,
650
651 .diseqc_envelope_mode = true,
652 };
653
654 static struct stv6110x_config stv6110a = {
655 .addr = 0x60,
656 .refclk = 27000000,
657 .clk_div = 1,
658 };
659
660 static struct stv6110x_config stv6110b = {
661 .addr = 0x63,
662 .refclk = 27000000,
663 .clk_div = 1,
664 };
665
666 static int demod_attach_stv0900(struct ddb_input *input, int type)
667 {
668 struct i2c_adapter *i2c = &input->port->i2c->adap;
669 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
670
671 input->fe = dvb_attach(stv090x_attach, feconf, i2c,
672 (input->nr & 1) ? STV090x_DEMODULATOR_1
673 : STV090x_DEMODULATOR_0);
674 if (!input->fe) {
675 printk(KERN_ERR "No STV0900 found!\n");
676 return -ENODEV;
677 }
678 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
679 0, (input->nr & 1) ?
680 (0x09 - type) : (0x0b - type))) {
681 printk(KERN_ERR "No LNBH24 found!\n");
682 return -ENODEV;
683 }
684 return 0;
685 }
686
687 static int tuner_attach_stv6110(struct ddb_input *input, int type)
688 {
689 struct i2c_adapter *i2c = &input->port->i2c->adap;
690 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
691 struct stv6110x_config *tunerconf = (input->nr & 1) ?
692 &stv6110b : &stv6110a;
693 const struct stv6110x_devctl *ctl;
694
695 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
696 if (!ctl) {
697 printk(KERN_ERR "No STV6110X found!\n");
698 return -ENODEV;
699 }
700 printk(KERN_INFO "attach tuner input %d adr %02x\n",
701 input->nr, tunerconf->addr);
702
703 feconf->tuner_init = ctl->tuner_init;
704 feconf->tuner_sleep = ctl->tuner_sleep;
705 feconf->tuner_set_mode = ctl->tuner_set_mode;
706 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
707 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
708 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
709 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
710 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
711 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
712 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
713 feconf->tuner_get_status = ctl->tuner_get_status;
714
715 return 0;
716 }
717
718 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
719 int (*start_feed)(struct dvb_demux_feed *),
720 int (*stop_feed)(struct dvb_demux_feed *),
721 void *priv)
722 {
723 dvbdemux->priv = priv;
724
725 dvbdemux->filternum = 256;
726 dvbdemux->feednum = 256;
727 dvbdemux->start_feed = start_feed;
728 dvbdemux->stop_feed = stop_feed;
729 dvbdemux->write_to_decoder = NULL;
730 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
731 DMX_SECTION_FILTERING |
732 DMX_MEMORY_BASED_FILTERING);
733 return dvb_dmx_init(dvbdemux);
734 }
735
736 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
737 struct dvb_demux *dvbdemux,
738 struct dmx_frontend *hw_frontend,
739 struct dmx_frontend *mem_frontend,
740 struct dvb_adapter *dvb_adapter)
741 {
742 int ret;
743
744 dmxdev->filternum = 256;
745 dmxdev->demux = &dvbdemux->dmx;
746 dmxdev->capabilities = 0;
747 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
748 if (ret < 0)
749 return ret;
750
751 hw_frontend->source = DMX_FRONTEND_0;
752 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
753 mem_frontend->source = DMX_MEMORY_FE;
754 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
755 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
756 }
757
758 static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
759 {
760 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
761 struct ddb_input *input = dvbdmx->priv;
762
763 if (!input->users)
764 ddb_input_start(input);
765
766 return ++input->users;
767 }
768
769 static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
770 {
771 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
772 struct ddb_input *input = dvbdmx->priv;
773
774 if (--input->users)
775 return input->users;
776
777 ddb_input_stop(input);
778 return 0;
779 }
780
781
782 static void dvb_input_detach(struct ddb_input *input)
783 {
784 struct dvb_adapter *adap = &input->adap;
785 struct dvb_demux *dvbdemux = &input->demux;
786
787 switch (input->attached) {
788 case 5:
789 if (input->fe2)
790 dvb_unregister_frontend(input->fe2);
791 if (input->fe) {
792 dvb_unregister_frontend(input->fe);
793 dvb_frontend_detach(input->fe);
794 input->fe = NULL;
795 }
796 case 4:
797 dvb_net_release(&input->dvbnet);
798
799 case 3:
800 dvbdemux->dmx.close(&dvbdemux->dmx);
801 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
802 &input->hw_frontend);
803 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
804 &input->mem_frontend);
805 dvb_dmxdev_release(&input->dmxdev);
806
807 case 2:
808 dvb_dmx_release(&input->demux);
809
810 case 1:
811 dvb_unregister_adapter(adap);
812 }
813 input->attached = 0;
814 }
815
816 static int dvb_input_attach(struct ddb_input *input)
817 {
818 int ret;
819 struct ddb_port *port = input->port;
820 struct dvb_adapter *adap = &input->adap;
821 struct dvb_demux *dvbdemux = &input->demux;
822
823 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
824 &input->port->dev->pdev->dev,
825 adapter_nr);
826 if (ret < 0) {
827 printk(KERN_ERR "ddbridge: Could not register adapter.Check if you enabled enough adapters in dvb-core!\n");
828 return ret;
829 }
830 input->attached = 1;
831
832 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
833 start_feed,
834 stop_feed, input);
835 if (ret < 0)
836 return ret;
837 input->attached = 2;
838
839 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
840 &input->hw_frontend,
841 &input->mem_frontend, adap);
842 if (ret < 0)
843 return ret;
844 input->attached = 3;
845
846 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
847 if (ret < 0)
848 return ret;
849 input->attached = 4;
850
851 input->fe = NULL;
852 switch (port->type) {
853 case DDB_TUNER_DVBS_ST:
854 if (demod_attach_stv0900(input, 0) < 0)
855 return -ENODEV;
856 if (tuner_attach_stv6110(input, 0) < 0)
857 return -ENODEV;
858 if (input->fe) {
859 if (dvb_register_frontend(adap, input->fe) < 0)
860 return -ENODEV;
861 }
862 break;
863 case DDB_TUNER_DVBS_ST_AA:
864 if (demod_attach_stv0900(input, 1) < 0)
865 return -ENODEV;
866 if (tuner_attach_stv6110(input, 1) < 0)
867 return -ENODEV;
868 if (input->fe) {
869 if (dvb_register_frontend(adap, input->fe) < 0)
870 return -ENODEV;
871 }
872 break;
873 case DDB_TUNER_DVBCT_TR:
874 if (demod_attach_drxk(input) < 0)
875 return -ENODEV;
876 if (tuner_attach_tda18271(input) < 0)
877 return -ENODEV;
878 if (dvb_register_frontend(adap, input->fe) < 0)
879 return -ENODEV;
880 if (input->fe2) {
881 if (dvb_register_frontend(adap, input->fe2) < 0)
882 return -ENODEV;
883 input->fe2->tuner_priv = input->fe->tuner_priv;
884 memcpy(&input->fe2->ops.tuner_ops,
885 &input->fe->ops.tuner_ops,
886 sizeof(struct dvb_tuner_ops));
887 }
888 break;
889 }
890 input->attached = 5;
891 return 0;
892 }
893
894 /****************************************************************************/
895 /****************************************************************************/
896
897 static ssize_t ts_write(struct file *file, const __user char *buf,
898 size_t count, loff_t *ppos)
899 {
900 struct dvb_device *dvbdev = file->private_data;
901 struct ddb_output *output = dvbdev->priv;
902 size_t left = count;
903 int stat;
904
905 while (left) {
906 if (ddb_output_free(output) < 188) {
907 if (file->f_flags & O_NONBLOCK)
908 break;
909 if (wait_event_interruptible(
910 output->wq, ddb_output_free(output) >= 188) < 0)
911 break;
912 }
913 stat = ddb_output_write(output, buf, left);
914 if (stat < 0)
915 break;
916 buf += stat;
917 left -= stat;
918 }
919 return (left == count) ? -EAGAIN : (count - left);
920 }
921
922 static ssize_t ts_read(struct file *file, __user char *buf,
923 size_t count, loff_t *ppos)
924 {
925 struct dvb_device *dvbdev = file->private_data;
926 struct ddb_output *output = dvbdev->priv;
927 struct ddb_input *input = output->port->input[0];
928 int left, read;
929
930 count -= count % 188;
931 left = count;
932 while (left) {
933 if (ddb_input_avail(input) < 188) {
934 if (file->f_flags & O_NONBLOCK)
935 break;
936 if (wait_event_interruptible(
937 input->wq, ddb_input_avail(input) >= 188) < 0)
938 break;
939 }
940 read = ddb_input_read(input, buf, left);
941 if (read < 0)
942 return read;
943 left -= read;
944 buf += read;
945 }
946 return (left == count) ? -EAGAIN : (count - left);
947 }
948
949 static unsigned int ts_poll(struct file *file, poll_table *wait)
950 {
951 /*
952 struct dvb_device *dvbdev = file->private_data;
953 struct ddb_output *output = dvbdev->priv;
954 struct ddb_input *input = output->port->input[0];
955 */
956 unsigned int mask = 0;
957
958 #if 0
959 if (data_avail_to_read)
960 mask |= POLLIN | POLLRDNORM;
961 if (data_avail_to_write)
962 mask |= POLLOUT | POLLWRNORM;
963
964 poll_wait(file, &read_queue, wait);
965 poll_wait(file, &write_queue, wait);
966 #endif
967 return mask;
968 }
969
970 static const struct file_operations ci_fops = {
971 .owner = THIS_MODULE,
972 .read = ts_read,
973 .write = ts_write,
974 .open = dvb_generic_open,
975 .release = dvb_generic_release,
976 .poll = ts_poll,
977 };
978
979 static struct dvb_device dvbdev_ci = {
980 .readers = -1,
981 .writers = -1,
982 .users = -1,
983 .fops = &ci_fops,
984 };
985
986 /****************************************************************************/
987 /****************************************************************************/
988 /****************************************************************************/
989
990 static void input_tasklet(unsigned long data)
991 {
992 struct ddb_input *input = (struct ddb_input *) data;
993 struct ddb *dev = input->port->dev;
994
995 spin_lock(&input->lock);
996 if (!input->running) {
997 spin_unlock(&input->lock);
998 return;
999 }
1000 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1001
1002 if (input->port->class == DDB_PORT_TUNER) {
1003 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
1004 printk(KERN_ERR "Overflow input %d\n", input->nr);
1005 while (input->cbuf != ((input->stat >> 11) & 0x1f)
1006 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
1007 dvb_dmx_swfilter_packets(&input->demux,
1008 input->vbuf[input->cbuf],
1009 input->dma_buf_size / 188);
1010
1011 input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
1012 ddbwritel((input->cbuf << 11),
1013 DMA_BUFFER_ACK(input->nr));
1014 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1015 }
1016 }
1017 if (input->port->class == DDB_PORT_CI)
1018 wake_up(&input->wq);
1019 spin_unlock(&input->lock);
1020 }
1021
1022 static void output_tasklet(unsigned long data)
1023 {
1024 struct ddb_output *output = (struct ddb_output *) data;
1025 struct ddb *dev = output->port->dev;
1026
1027 spin_lock(&output->lock);
1028 if (!output->running) {
1029 spin_unlock(&output->lock);
1030 return;
1031 }
1032 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
1033 wake_up(&output->wq);
1034 spin_unlock(&output->lock);
1035 }
1036
1037
1038 static struct cxd2099_cfg cxd_cfg = {
1039 .bitrate = 62000,
1040 .adr = 0x40,
1041 .polarity = 1,
1042 .clock_mode = 1,
1043 };
1044
1045 static int ddb_ci_attach(struct ddb_port *port)
1046 {
1047 int ret;
1048
1049 ret = dvb_register_adapter(&port->output->adap,
1050 "DDBridge",
1051 THIS_MODULE,
1052 &port->dev->pdev->dev,
1053 adapter_nr);
1054 if (ret < 0)
1055 return ret;
1056 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
1057 if (!port->en) {
1058 dvb_unregister_adapter(&port->output->adap);
1059 return -ENODEV;
1060 }
1061 ddb_input_start(port->input[0]);
1062 ddb_output_start(port->output);
1063 dvb_ca_en50221_init(&port->output->adap,
1064 port->en, 0, 1);
1065 ret = dvb_register_device(&port->output->adap, &port->output->dev,
1066 &dvbdev_ci, (void *) port->output,
1067 DVB_DEVICE_SEC, 0);
1068 return ret;
1069 }
1070
1071 static int ddb_port_attach(struct ddb_port *port)
1072 {
1073 int ret = 0;
1074
1075 switch (port->class) {
1076 case DDB_PORT_TUNER:
1077 ret = dvb_input_attach(port->input[0]);
1078 if (ret < 0)
1079 break;
1080 ret = dvb_input_attach(port->input[1]);
1081 break;
1082 case DDB_PORT_CI:
1083 ret = ddb_ci_attach(port);
1084 break;
1085 default:
1086 break;
1087 }
1088 if (ret < 0)
1089 printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
1090 return ret;
1091 }
1092
1093 static int ddb_ports_attach(struct ddb *dev)
1094 {
1095 int i, ret = 0;
1096 struct ddb_port *port;
1097
1098 for (i = 0; i < dev->info->port_num; i++) {
1099 port = &dev->port[i];
1100 ret = ddb_port_attach(port);
1101 if (ret < 0)
1102 break;
1103 }
1104 return ret;
1105 }
1106
1107 static void ddb_ports_detach(struct ddb *dev)
1108 {
1109 int i;
1110 struct ddb_port *port;
1111
1112 for (i = 0; i < dev->info->port_num; i++) {
1113 port = &dev->port[i];
1114 switch (port->class) {
1115 case DDB_PORT_TUNER:
1116 dvb_input_detach(port->input[0]);
1117 dvb_input_detach(port->input[1]);
1118 break;
1119 case DDB_PORT_CI:
1120 dvb_unregister_device(port->output->dev);
1121 if (port->en) {
1122 ddb_input_stop(port->input[0]);
1123 ddb_output_stop(port->output);
1124 dvb_ca_en50221_release(port->en);
1125 kfree(port->en);
1126 port->en = NULL;
1127 dvb_unregister_adapter(&port->output->adap);
1128 }
1129 break;
1130 }
1131 }
1132 }
1133
1134 /****************************************************************************/
1135 /****************************************************************************/
1136
1137 static int port_has_ci(struct ddb_port *port)
1138 {
1139 u8 val;
1140 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
1141 }
1142
1143 static int port_has_stv0900(struct ddb_port *port)
1144 {
1145 u8 val;
1146 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
1147 return 0;
1148 return 1;
1149 }
1150
1151 static int port_has_stv0900_aa(struct ddb_port *port)
1152 {
1153 u8 val;
1154 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
1155 return 0;
1156 return 1;
1157 }
1158
1159 static int port_has_drxks(struct ddb_port *port)
1160 {
1161 u8 val;
1162 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
1163 return 0;
1164 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
1165 return 0;
1166 return 1;
1167 }
1168
1169 static void ddb_port_probe(struct ddb_port *port)
1170 {
1171 struct ddb *dev = port->dev;
1172 char *modname = "NO MODULE";
1173
1174 port->class = DDB_PORT_NONE;
1175
1176 if (port_has_ci(port)) {
1177 modname = "CI";
1178 port->class = DDB_PORT_CI;
1179 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1180 } else if (port_has_stv0900(port)) {
1181 modname = "DUAL DVB-S2";
1182 port->class = DDB_PORT_TUNER;
1183 port->type = DDB_TUNER_DVBS_ST;
1184 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1185 } else if (port_has_stv0900_aa(port)) {
1186 modname = "DUAL DVB-S2";
1187 port->class = DDB_PORT_TUNER;
1188 port->type = DDB_TUNER_DVBS_ST_AA;
1189 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1190 } else if (port_has_drxks(port)) {
1191 modname = "DUAL DVB-C/T";
1192 port->class = DDB_PORT_TUNER;
1193 port->type = DDB_TUNER_DVBCT_TR;
1194 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1195 }
1196 printk(KERN_INFO "Port %d (TAB %d): %s\n",
1197 port->nr, port->nr+1, modname);
1198 }
1199
1200 static void ddb_input_init(struct ddb_port *port, int nr)
1201 {
1202 struct ddb *dev = port->dev;
1203 struct ddb_input *input = &dev->input[nr];
1204
1205 input->nr = nr;
1206 input->port = port;
1207 input->dma_buf_num = INPUT_DMA_BUFS;
1208 input->dma_buf_size = INPUT_DMA_SIZE;
1209 ddbwritel(0, TS_INPUT_CONTROL(nr));
1210 ddbwritel(2, TS_INPUT_CONTROL(nr));
1211 ddbwritel(0, TS_INPUT_CONTROL(nr));
1212 ddbwritel(0, DMA_BUFFER_ACK(nr));
1213 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
1214 spin_lock_init(&input->lock);
1215 init_waitqueue_head(&input->wq);
1216 }
1217
1218 static void ddb_output_init(struct ddb_port *port, int nr)
1219 {
1220 struct ddb *dev = port->dev;
1221 struct ddb_output *output = &dev->output[nr];
1222 output->nr = nr;
1223 output->port = port;
1224 output->dma_buf_num = OUTPUT_DMA_BUFS;
1225 output->dma_buf_size = OUTPUT_DMA_SIZE;
1226
1227 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1228 ddbwritel(2, TS_OUTPUT_CONTROL(nr));
1229 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1230 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
1231 init_waitqueue_head(&output->wq);
1232 }
1233
1234 static void ddb_ports_init(struct ddb *dev)
1235 {
1236 int i;
1237 struct ddb_port *port;
1238
1239 for (i = 0; i < dev->info->port_num; i++) {
1240 port = &dev->port[i];
1241 port->dev = dev;
1242 port->nr = i;
1243 port->i2c = &dev->i2c[i];
1244 port->input[0] = &dev->input[2 * i];
1245 port->input[1] = &dev->input[2 * i + 1];
1246 port->output = &dev->output[i];
1247
1248 mutex_init(&port->i2c_gate_lock);
1249 ddb_port_probe(port);
1250 ddb_input_init(port, 2 * i);
1251 ddb_input_init(port, 2 * i + 1);
1252 ddb_output_init(port, i);
1253 }
1254 }
1255
1256 static void ddb_ports_release(struct ddb *dev)
1257 {
1258 int i;
1259 struct ddb_port *port;
1260
1261 for (i = 0; i < dev->info->port_num; i++) {
1262 port = &dev->port[i];
1263 port->dev = dev;
1264 tasklet_kill(&port->input[0]->tasklet);
1265 tasklet_kill(&port->input[1]->tasklet);
1266 tasklet_kill(&port->output->tasklet);
1267 }
1268 }
1269
1270 /****************************************************************************/
1271 /****************************************************************************/
1272 /****************************************************************************/
1273
1274 static void irq_handle_i2c(struct ddb *dev, int n)
1275 {
1276 struct ddb_i2c *i2c = &dev->i2c[n];
1277
1278 i2c->done = 1;
1279 wake_up(&i2c->wq);
1280 }
1281
1282 static irqreturn_t irq_handler(int irq, void *dev_id)
1283 {
1284 struct ddb *dev = (struct ddb *) dev_id;
1285 u32 s = ddbreadl(INTERRUPT_STATUS);
1286
1287 if (!s)
1288 return IRQ_NONE;
1289
1290 do {
1291 ddbwritel(s, INTERRUPT_ACK);
1292
1293 if (s & 0x00000001)
1294 irq_handle_i2c(dev, 0);
1295 if (s & 0x00000002)
1296 irq_handle_i2c(dev, 1);
1297 if (s & 0x00000004)
1298 irq_handle_i2c(dev, 2);
1299 if (s & 0x00000008)
1300 irq_handle_i2c(dev, 3);
1301
1302 if (s & 0x00000100)
1303 tasklet_schedule(&dev->input[0].tasklet);
1304 if (s & 0x00000200)
1305 tasklet_schedule(&dev->input[1].tasklet);
1306 if (s & 0x00000400)
1307 tasklet_schedule(&dev->input[2].tasklet);
1308 if (s & 0x00000800)
1309 tasklet_schedule(&dev->input[3].tasklet);
1310 if (s & 0x00001000)
1311 tasklet_schedule(&dev->input[4].tasklet);
1312 if (s & 0x00002000)
1313 tasklet_schedule(&dev->input[5].tasklet);
1314 if (s & 0x00004000)
1315 tasklet_schedule(&dev->input[6].tasklet);
1316 if (s & 0x00008000)
1317 tasklet_schedule(&dev->input[7].tasklet);
1318
1319 if (s & 0x00010000)
1320 tasklet_schedule(&dev->output[0].tasklet);
1321 if (s & 0x00020000)
1322 tasklet_schedule(&dev->output[1].tasklet);
1323 if (s & 0x00040000)
1324 tasklet_schedule(&dev->output[2].tasklet);
1325 if (s & 0x00080000)
1326 tasklet_schedule(&dev->output[3].tasklet);
1327
1328 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
1329 } while ((s = ddbreadl(INTERRUPT_STATUS)));
1330
1331 return IRQ_HANDLED;
1332 }
1333
1334 /******************************************************************************/
1335 /******************************************************************************/
1336 /******************************************************************************/
1337
1338 static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
1339 {
1340 u32 data, shift;
1341
1342 if (wlen > 4)
1343 ddbwritel(1, SPI_CONTROL);
1344 while (wlen > 4) {
1345 /* FIXME: check for big-endian */
1346 data = swab32(*(u32 *)wbuf);
1347 wbuf += 4;
1348 wlen -= 4;
1349 ddbwritel(data, SPI_DATA);
1350 while (ddbreadl(SPI_CONTROL) & 0x0004)
1351 ;
1352 }
1353
1354 if (rlen)
1355 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1356 else
1357 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1358
1359 data = 0;
1360 shift = ((4 - wlen) * 8);
1361 while (wlen) {
1362 data <<= 8;
1363 data |= *wbuf;
1364 wlen--;
1365 wbuf++;
1366 }
1367 if (shift)
1368 data <<= shift;
1369 ddbwritel(data, SPI_DATA);
1370 while (ddbreadl(SPI_CONTROL) & 0x0004)
1371 ;
1372
1373 if (!rlen) {
1374 ddbwritel(0, SPI_CONTROL);
1375 return 0;
1376 }
1377 if (rlen > 4)
1378 ddbwritel(1, SPI_CONTROL);
1379
1380 while (rlen > 4) {
1381 ddbwritel(0xffffffff, SPI_DATA);
1382 while (ddbreadl(SPI_CONTROL) & 0x0004)
1383 ;
1384 data = ddbreadl(SPI_DATA);
1385 *(u32 *) rbuf = swab32(data);
1386 rbuf += 4;
1387 rlen -= 4;
1388 }
1389 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
1390 ddbwritel(0xffffffff, SPI_DATA);
1391 while (ddbreadl(SPI_CONTROL) & 0x0004)
1392 ;
1393
1394 data = ddbreadl(SPI_DATA);
1395 ddbwritel(0, SPI_CONTROL);
1396
1397 if (rlen < 4)
1398 data <<= ((4 - rlen) * 8);
1399
1400 while (rlen > 0) {
1401 *rbuf = ((data >> 24) & 0xff);
1402 data <<= 8;
1403 rbuf++;
1404 rlen--;
1405 }
1406 return 0;
1407 }
1408
1409 #define DDB_MAGIC 'd'
1410
1411 struct ddb_flashio {
1412 __user __u8 *write_buf;
1413 __u32 write_len;
1414 __user __u8 *read_buf;
1415 __u32 read_len;
1416 };
1417
1418 #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
1419
1420 #define DDB_NAME "ddbridge"
1421
1422 static u32 ddb_num;
1423 static struct ddb *ddbs[32];
1424 static struct class *ddb_class;
1425 static int ddb_major;
1426
1427 static int ddb_open(struct inode *inode, struct file *file)
1428 {
1429 struct ddb *dev = ddbs[iminor(inode)];
1430
1431 file->private_data = dev;
1432 return 0;
1433 }
1434
1435 static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1436 {
1437 struct ddb *dev = file->private_data;
1438 __user void *parg = (__user void *)arg;
1439 int res;
1440
1441 switch (cmd) {
1442 case IOCTL_DDB_FLASHIO:
1443 {
1444 struct ddb_flashio fio;
1445 u8 *rbuf, *wbuf;
1446
1447 if (copy_from_user(&fio, parg, sizeof(fio)))
1448 return -EFAULT;
1449
1450 if (fio.write_len > 1028 || fio.read_len > 1028)
1451 return -EINVAL;
1452 if (fio.write_len + fio.read_len > 1028)
1453 return -EINVAL;
1454
1455 wbuf = &dev->iobuf[0];
1456 rbuf = wbuf + fio.write_len;
1457
1458 if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
1459 return -EFAULT;
1460 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
1461 if (res)
1462 return res;
1463 if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
1464 return -EFAULT;
1465 break;
1466 }
1467 default:
1468 return -ENOTTY;
1469 }
1470 return 0;
1471 }
1472
1473 static const struct file_operations ddb_fops = {
1474 .unlocked_ioctl = ddb_ioctl,
1475 .open = ddb_open,
1476 };
1477
1478 static char *ddb_devnode(struct device *device, umode_t *mode)
1479 {
1480 struct ddb *dev = dev_get_drvdata(device);
1481
1482 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
1483 }
1484
1485 static int ddb_class_create(void)
1486 {
1487 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
1488 if (ddb_major < 0)
1489 return ddb_major;
1490
1491 ddb_class = class_create(THIS_MODULE, DDB_NAME);
1492 if (IS_ERR(ddb_class)) {
1493 unregister_chrdev(ddb_major, DDB_NAME);
1494 return PTR_ERR(ddb_class);
1495 }
1496 ddb_class->devnode = ddb_devnode;
1497 return 0;
1498 }
1499
1500 static void ddb_class_destroy(void)
1501 {
1502 class_destroy(ddb_class);
1503 unregister_chrdev(ddb_major, DDB_NAME);
1504 }
1505
1506 static int ddb_device_create(struct ddb *dev)
1507 {
1508 dev->nr = ddb_num++;
1509 dev->ddb_dev = device_create(ddb_class, NULL,
1510 MKDEV(ddb_major, dev->nr),
1511 dev, "ddbridge%d", dev->nr);
1512 ddbs[dev->nr] = dev;
1513 if (IS_ERR(dev->ddb_dev))
1514 return -1;
1515 return 0;
1516 }
1517
1518 static void ddb_device_destroy(struct ddb *dev)
1519 {
1520 ddb_num--;
1521 if (IS_ERR(dev->ddb_dev))
1522 return;
1523 device_destroy(ddb_class, MKDEV(ddb_major, 0));
1524 }
1525
1526
1527 /****************************************************************************/
1528 /****************************************************************************/
1529 /****************************************************************************/
1530
1531 static void ddb_unmap(struct ddb *dev)
1532 {
1533 if (dev->regs)
1534 iounmap(dev->regs);
1535 vfree(dev);
1536 }
1537
1538
1539 static void ddb_remove(struct pci_dev *pdev)
1540 {
1541 struct ddb *dev = pci_get_drvdata(pdev);
1542
1543 ddb_ports_detach(dev);
1544 ddb_i2c_release(dev);
1545
1546 ddbwritel(0, INTERRUPT_ENABLE);
1547 free_irq(dev->pdev->irq, dev);
1548 #ifdef CONFIG_PCI_MSI
1549 if (dev->msi)
1550 pci_disable_msi(dev->pdev);
1551 #endif
1552 ddb_ports_release(dev);
1553 ddb_buffers_free(dev);
1554 ddb_device_destroy(dev);
1555
1556 ddb_unmap(dev);
1557 pci_set_drvdata(pdev, NULL);
1558 pci_disable_device(pdev);
1559 }
1560
1561
1562 static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1563 {
1564 struct ddb *dev;
1565 int stat = 0;
1566 int irq_flag = IRQF_SHARED;
1567
1568 if (pci_enable_device(pdev) < 0)
1569 return -ENODEV;
1570
1571 dev = vzalloc(sizeof(struct ddb));
1572 if (dev == NULL)
1573 return -ENOMEM;
1574
1575 dev->pdev = pdev;
1576 pci_set_drvdata(pdev, dev);
1577 dev->info = (struct ddb_info *) id->driver_data;
1578 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
1579
1580 dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
1581 pci_resource_len(dev->pdev, 0));
1582 if (!dev->regs) {
1583 stat = -ENOMEM;
1584 goto fail;
1585 }
1586 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
1587
1588 #ifdef CONFIG_PCI_MSI
1589 if (pci_msi_enabled())
1590 stat = pci_enable_msi(dev->pdev);
1591 if (stat) {
1592 printk(KERN_INFO ": MSI not available.\n");
1593 } else {
1594 irq_flag = 0;
1595 dev->msi = 1;
1596 }
1597 #endif
1598 stat = request_irq(dev->pdev->irq, irq_handler,
1599 irq_flag, "DDBridge", (void *) dev);
1600 if (stat < 0)
1601 goto fail1;
1602 ddbwritel(0, DMA_BASE_WRITE);
1603 ddbwritel(0, DMA_BASE_READ);
1604 ddbwritel(0xffffffff, INTERRUPT_ACK);
1605 ddbwritel(0xfff0f, INTERRUPT_ENABLE);
1606 ddbwritel(0, MSI1_ENABLE);
1607
1608 if (ddb_i2c_init(dev) < 0)
1609 goto fail1;
1610 ddb_ports_init(dev);
1611 if (ddb_buffers_alloc(dev) < 0) {
1612 printk(KERN_INFO ": Could not allocate buffer memory\n");
1613 goto fail2;
1614 }
1615 if (ddb_ports_attach(dev) < 0)
1616 goto fail3;
1617 ddb_device_create(dev);
1618 return 0;
1619
1620 fail3:
1621 ddb_ports_detach(dev);
1622 printk(KERN_ERR "fail3\n");
1623 ddb_ports_release(dev);
1624 fail2:
1625 printk(KERN_ERR "fail2\n");
1626 ddb_buffers_free(dev);
1627 fail1:
1628 printk(KERN_ERR "fail1\n");
1629 if (dev->msi)
1630 pci_disable_msi(dev->pdev);
1631 if (stat == 0)
1632 free_irq(dev->pdev->irq, dev);
1633 fail:
1634 printk(KERN_ERR "fail\n");
1635 ddb_unmap(dev);
1636 pci_set_drvdata(pdev, NULL);
1637 pci_disable_device(pdev);
1638 return -1;
1639 }
1640
1641 /******************************************************************************/
1642 /******************************************************************************/
1643 /******************************************************************************/
1644
1645 static const struct ddb_info ddb_none = {
1646 .type = DDB_NONE,
1647 .name = "Digital Devices PCIe bridge",
1648 };
1649
1650 static const struct ddb_info ddb_octopus = {
1651 .type = DDB_OCTOPUS,
1652 .name = "Digital Devices Octopus DVB adapter",
1653 .port_num = 4,
1654 };
1655
1656 static const struct ddb_info ddb_octopus_le = {
1657 .type = DDB_OCTOPUS,
1658 .name = "Digital Devices Octopus LE DVB adapter",
1659 .port_num = 2,
1660 };
1661
1662 static const struct ddb_info ddb_octopus_mini = {
1663 .type = DDB_OCTOPUS,
1664 .name = "Digital Devices Octopus Mini",
1665 .port_num = 4,
1666 };
1667
1668 static const struct ddb_info ddb_v6 = {
1669 .type = DDB_OCTOPUS,
1670 .name = "Digital Devices Cine S2 V6 DVB adapter",
1671 .port_num = 3,
1672 };
1673 static const struct ddb_info ddb_v6_5 = {
1674 .type = DDB_OCTOPUS,
1675 .name = "Digital Devices Cine S2 V6.5 DVB adapter",
1676 .port_num = 4,
1677 };
1678
1679 static const struct ddb_info ddb_dvbct = {
1680 .type = DDB_OCTOPUS,
1681 .name = "Digital Devices DVBCT V6.1 DVB adapter",
1682 .port_num = 3,
1683 };
1684
1685 static const struct ddb_info ddb_satixS2v3 = {
1686 .type = DDB_OCTOPUS,
1687 .name = "Mystique SaTiX-S2 V3 DVB adapter",
1688 .port_num = 3,
1689 };
1690
1691 static const struct ddb_info ddb_octopusv3 = {
1692 .type = DDB_OCTOPUS,
1693 .name = "Digital Devices Octopus V3 DVB adapter",
1694 .port_num = 4,
1695 };
1696
1697 #define DDVID 0xdd01 /* Digital Devices Vendor ID */
1698
1699 #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
1700 .vendor = _vend, .device = _dev, \
1701 .subvendor = _subvend, .subdevice = _subdev, \
1702 .driver_data = (unsigned long)&_driverdata }
1703
1704 static const struct pci_device_id ddb_id_tbl[] = {
1705 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
1706 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
1707 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
1708 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
1709 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
1710 DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
1711 DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
1712 DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
1713 DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
1714 /* in case sub-ids got deleted in flash */
1715 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
1716 {0}
1717 };
1718 MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
1719
1720
1721 static struct pci_driver ddb_pci_driver = {
1722 .name = "DDBridge",
1723 .id_table = ddb_id_tbl,
1724 .probe = ddb_probe,
1725 .remove = ddb_remove,
1726 };
1727
1728 static __init int module_init_ddbridge(void)
1729 {
1730 int ret;
1731
1732 printk(KERN_INFO "Digital Devices PCIE bridge driver, Copyright (C) 2010-11 Digital Devices GmbH\n");
1733
1734 ret = ddb_class_create();
1735 if (ret < 0)
1736 return ret;
1737 ret = pci_register_driver(&ddb_pci_driver);
1738 if (ret < 0)
1739 ddb_class_destroy();
1740 return ret;
1741 }
1742
1743 static __exit void module_exit_ddbridge(void)
1744 {
1745 pci_unregister_driver(&ddb_pci_driver);
1746 ddb_class_destroy();
1747 }
1748
1749 module_init(module_init_ddbridge);
1750 module_exit(module_exit_ddbridge);
1751
1752 MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
1753 MODULE_AUTHOR("Ralph Metzler");
1754 MODULE_LICENSE("GPL");
1755 MODULE_VERSION("0.5");
Linux with added FPC-III support