| blob | 30ac14210e91f956e4434e88448067e9032db586 |
1 /*
2 * TW5864 driver - registers description
3 *
4 * Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
19 /* Register Description - Direct Map Space */
20 /* 0x0000 ~ 0x1ffc - H264 Register Map */
21 /* [15:0] The Version register for H264 core (Read Only) */
22 #define TW5864_H264REV 0x0000
24 #define TW5864_EMU 0x0004
25 /* Define controls in register TW5864_EMU */
26 /* DDR controller enabled */
27 #define TW5864_EMU_EN_DDR BIT(0)
28 /* Enable bit for Inter module */
29 #define TW5864_EMU_EN_ME BIT(1)
30 /* Enable bit for Sensor Interface module */
31 #define TW5864_EMU_EN_SEN BIT(2)
32 /* Enable bit for Host Burst Access */
33 #define TW5864_EMU_EN_BHOST BIT(3)
34 /* Enable bit for Loop Filter module */
35 #define TW5864_EMU_EN_LPF BIT(4)
36 /* Enable bit for PLBK module */
37 #define TW5864_EMU_EN_PLBK BIT(5)
38 /*
39 * Video Frame mapping in DDR
40 * 00 CIF
41 * 01 D1
42 * 10 Reserved
43 * 11 Reserved
44 *
45 */
46 #define TW5864_DSP_FRAME_TYPE (3 << 6)
47 #define TW5864_DSP_FRAME_TYPE_D1 BIT(6)
49 #define TW5864_UNDECLARED_H264REV_PART2 0x0008
51 #define TW5864_SLICE 0x000c
52 /* Define controls in register TW5864_SLICE */
53 /* VLC Slice end flag */
54 #define TW5864_VLC_SLICE_END BIT(0)
55 /* Master Slice End Flag */
56 #define TW5864_MAS_SLICE_END BIT(4)
57 /* Host to start a new slice Address */
58 #define TW5864_START_NSLICE BIT(15)
60 /*
61 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
62 * pointer for the last encoded frame of the corresponding channel.
63 */
64 #define TW5864_ENC_BUF_PTR_REC1 0x0010
66 /* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
67 #define TW5864_DSP_QP 0x0018
68 /* Define controls in register TW5864_DSP_QP */
69 /* [5:0] H264 QP Value for codec */
70 #define TW5864_DSP_MB_QP 0x003f
71 /*
72 * [15:10] H264 LPF_OFFSET Address
73 * (Default 0)
74 */
75 #define TW5864_DSP_LPF_OFFSET 0xfc00
77 #define TW5864_DSP_CODEC 0x001c
78 /* Define controls in register TW5864_DSP_CODEC */
79 /*
80 * 0: Encode (TW5864 Default)
81 * 1: Decode
82 */
83 #define TW5864_DSP_CODEC_MODE BIT(0)
84 /*
85 * 0->3 4 VLC data buffer in DDR (1M each)
86 * 0->7 8 VLC data buffer in DDR (512k each)
87 */
88 #define TW5864_VLC_BUF_ID (7 << 2)
89 /*
90 * 0 4CIF in 1 MB
91 * 1 1CIF in 1 MB
92 */
93 #define TW5864_CIF_MAP_MD BIT(6)
94 /*
95 * 0 2 falf D1 in 1 MB
96 * 1 1 half D1 in 1 MB
97 */
98 #define TW5864_HD1_MAP_MD BIT(7)
99 /* VLC Stream valid */
100 #define TW5864_VLC_VLD BIT(8)
101 /* MV Vector Valid */
102 #define TW5864_MV_VECT_VLD BIT(9)
103 /* MV Flag Valid */
104 #define TW5864_MV_FLAG_VLD BIT(10)
106 #define TW5864_DSP_SEN 0x0020
107 /* Define controls in register TW5864_DSP_SEN */
108 /* Org Buffer Base for Luma (default 0) */
109 #define TW5864_DSP_SEN_PIC_LU 0x000f
110 /* Org Buffer Base for Chroma (default 4) */
111 #define TW5864_DSP_SEN_PIC_CHM 0x00f0
112 /* Maximum Number of Buffers (default 4) */
113 #define TW5864_DSP_SEN_PIC_MAX 0x0700
114 /*
115 * Original Frame D1 or HD1 switch
116 * (Default 0)
117 */
118 #define TW5864_DSP_SEN_HFULL 0x1000
120 #define TW5864_DSP_REF_PIC 0x0024
121 /* Define controls in register TW5864_DSP_REF_PIC */
122 /* Ref Buffer Base for Luma (default 0) */
123 #define TW5864_DSP_REF_PIC_LU 0x000f
124 /* Ref Buffer Base for Chroma (default 4) */
125 #define TW5864_DSP_REF_PIC_CHM 0x00f0
126 /* Maximum Number of Buffers (default 4) */
127 #define TW5864_DSP_REF_PIC_MAX 0x0700
129 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
130 #define TW5864_SEN_EN_CH 0x0028
132 #define TW5864_DSP 0x002c
133 /* Define controls in register TW5864_DSP */
134 /* The ID for channel selected for encoding operation */
135 #define TW5864_DSP_ENC_CHN 0x000f
136 /* See DSP_MB_DELAY below */
137 #define TW5864_DSP_MB_WAIT 0x0010
138 /*
139 * DSP Chroma Switch
140 * 0 DDRB
141 * 1 DDRA
142 */
143 #define TW5864_DSP_CHROM_SW 0x0020
144 /* VLC Flow Control: 1 for enable */
145 #define TW5864_DSP_FLW_CNTL 0x0040
146 /*
147 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
148 * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128
149 */
150 #define TW5864_DSP_MB_DELAY 0x0f00
152 #define TW5864_DDR 0x0030
153 /* Define controls in register TW5864_DDR */
154 /* DDR Single Access Page Number */
155 #define TW5864_DDR_PAGE_CNTL 0x00ff
156 /* DDR-DPR Burst Read Enable */
157 #define TW5864_DDR_BRST_EN BIT(13)
158 /*
159 * DDR A/B Select as HOST access
160 * 0 Select DDRA
161 * 1 Select DDRB
162 */
163 #define TW5864_DDR_AB_SEL BIT(14)
164 /*
165 * DDR Access Mode Select
166 * 0 Single R/W Access (Host <-> DDR)
167 * 1 Burst R/W Access (Host <-> DPR)
168 */
169 #define TW5864_DDR_MODE BIT(15)
171 /* The original frame capture pointer. Two bits for each channel */
172 /* SENIF_ORG_FRM_PTR [15:0] */
173 #define TW5864_SENIF_ORG_FRM_PTR1 0x0038
174 /* SENIF_ORG_FRM_PTR [31:16] */
175 #define TW5864_SENIF_ORG_FRM_PTR2 0x003c
177 #define TW5864_DSP_SEN_MODE 0x0040
178 /* Define controls in register TW5864_DSP_SEN_MODE */
179 #define TW5864_DSP_SEN_MODE_CH0 0x000f
180 #define TW5864_DSP_SEN_MODE_CH1 0x00f0
182 /*
183 * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
184 * Each two bits are the buffer pointer for the last encoded frame of a channel
185 */
186 #define TW5864_ENC_BUF_PTR_REC2 0x004c
188 /* Current MV Flag Status Pointer for Channel n. (Read only) */
189 /*
190 * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR
191 */
192 #define TW5864_CH_MV_PTR1 0x0060
193 /*
194 * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR
195 */
196 #define TW5864_CH_MV_PTR2 0x0064
198 /*
199 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
200 */
201 #define TW5864_RST_MV_PTR 0x0068
202 #define TW5864_INTERLACING 0x0200
203 /* Define controls in register TW5864_INTERLACING */
204 /*
205 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
206 * set, the output video is interlaced (stripy).
207 */
208 #define TW5864_DSP_INTER_ST BIT(1)
209 /* Deinterlacer Enable */
210 #define TW5864_DI_EN BIT(2)
211 /*
212 * De-interlacer Mode
213 * 1 Shuffled frame
214 * 0 Normal Un-Shuffled Frame
215 */
216 #define TW5864_DI_MD BIT(3)
217 /*
218 * Down scale original frame in X direction
219 * 11: Un-used
220 * 10: down-sample to 1/4
221 * 01: down-sample to 1/2
222 * 00: down-sample disabled
223 */
224 #define TW5864_DSP_DWN_X (3 << 4)
225 /*
226 * Down scale original frame in Y direction
227 * 11: Un-used
228 * 10: down-sample to 1/4
229 * 01: down-sample to 1/2
230 * 00: down-sample disabled
231 */
232 #define TW5864_DSP_DWN_Y (3 << 6)
233 /*
234 * 1 Dual Stream
235 * 0 Single Stream
236 */
237 #define TW5864_DUAL_STR BIT(8)
239 #define TW5864_DSP_REF 0x0204
240 /* Define controls in register TW5864_DSP_REF */
241 /* Number of reference frame (Default 1 for TW5864B) */
242 #define TW5864_DSP_REF_FRM 0x000f
243 /* Window size */
244 #define TW5864_DSP_WIN_SIZE 0x02f0
246 #define TW5864_DSP_SKIP 0x0208
247 /* Define controls in register TW5864_DSP_SKIP */
248 /*
249 * Skip Offset Enable bit
250 * 0 DSP_SKIP_OFFSET value is not used (default 8)
251 * 1 DSP_SKIP_OFFSET value is used in HW
252 */
253 #define TW5864_DSP_SKIP_OFEN 0x0080
254 /* Skip mode cost offset (default 8) */
255 #define TW5864_DSP_SKIP_OFFSET 0x007f
257 #define TW5864_MOTION_SEARCH_ETC 0x020c
258 /* Define controls in register TW5864_MOTION_SEARCH_ETC */
259 /* Enable quarter pel search mode */
260 #define TW5864_QPEL_EN BIT(0)
261 /* Enable half pel search mode */
262 #define TW5864_HPEL_EN BIT(1)
263 /* Enable motion search mode */
264 #define TW5864_ME_EN BIT(2)
265 /* Enable Intra mode */
266 #define TW5864_INTRA_EN BIT(3)
267 /* Enable Skip Mode */
268 #define TW5864_SKIP_EN BIT(4)
269 /* Search Option (Default 2"b01) */
270 #define TW5864_SRCH_OPT (3 << 5)
272 #define TW5864_DSP_ENC_REC 0x0210
273 /* Define controls in register TW5864_DSP_ENC_REC */
274 /* Reference Buffer Pointer for encoding */
275 #define TW5864_DSP_ENC_REF_PTR 0x0007
276 /* Reconstruct Buffer pointer */
277 #define TW5864_DSP_REC_BUF_PTR 0x7000
279 /* [15:0] Lambda Value for H264 */
280 #define TW5864_DSP_REF_MVP_LAMBDA 0x0214
282 #define TW5864_DSP_PIC_MAX_MB 0x0218
283 /* Define controls in register TW5864_DSP_PIC_MAX_MB */
284 /* The MB number in Y direction for a frame */
285 #define TW5864_DSP_PIC_MAX_MB_Y 0x007f
286 /* The MB number in X direction for a frame */
287 #define TW5864_DSP_PIC_MAX_MB_X 0x7f00
289 /* The original frame pointer for encoding */
290 #define TW5864_DSP_ENC_ORG_PTR_REG 0x021c
291 /* Mask to use with TW5864_DSP_ENC_ORG_PTR */
292 #define TW5864_DSP_ENC_ORG_PTR_MASK 0x7000
293 /* Number of bits to shift with TW5864_DSP_ENC_ORG_PTR */
294 #define TW5864_DSP_ENC_ORG_PTR_SHIFT 12
296 /* DDR base address of OSD rectangle attribute data */
297 #define TW5864_DSP_OSD_ATTRI_BASE 0x0220
298 /* OSD enable bit for each channel */
299 #define TW5864_DSP_OSD_ENABLE 0x0228
301 /* 0x0280 ~ 0x029c – Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
302 #define TW5864_ME_MV_VEC1 0x0280
303 /* 0x02a0 ~ 0x02bc – Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
304 #define TW5864_ME_MV_VEC2 0x02a0
305 /* 0x02c0 ~ 0x02dc – Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
306 #define TW5864_ME_MV_VEC3 0x02c0
307 /* 0x02e0 ~ 0x02fc – Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
308 #define TW5864_ME_MV_VEC4 0x02e0
310 /*
311 * [5:0]
312 * if (intra16x16_cost < (intra4x4_cost+dsp_i4x4_offset))
313 * Intra_mode = intra16x16_mode
314 * Else
315 * Intra_mode = intra4x4_mode
316 */
317 #define TW5864_DSP_I4x4_OFFSET 0x040c
319 /*
320 * [6:4]
321 * 0x5 Only 4x4
322 * 0x6 Only 16x16
323 * 0x7 16x16 & 4x4
324 */
325 #define TW5864_DSP_INTRA_MODE 0x0410
326 #define TW5864_DSP_INTRA_MODE_SHIFT 4
327 #define TW5864_DSP_INTRA_MODE_MASK (7 << 4)
328 #define TW5864_DSP_INTRA_MODE_4x4 0x5
329 #define TW5864_DSP_INTRA_MODE_16x16 0x6
330 #define TW5864_DSP_INTRA_MODE_4x4_AND_16x16 0x7
331 /*
332 * [5:0] WEIGHT Factor for I4x4 cost calculation (QP dependent)
333 */
334 #define TW5864_DSP_I4x4_WEIGHT 0x0414
336 /*
337 * [7:0] Offset used to affect Intra/ME model decision
338 * If (me_cost < intra_cost + dsp_resid_mode_offset)
339 * Pred_Mode = me_mode
340 * Else
341 * Pred_mode = intra_mode
342 */
343 #define TW5864_DSP_RESID_MODE_OFFSET 0x0604
345 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
346 #define TW5864_QUAN_TAB 0x0800
348 /* Valid channel value [0; f], frame value [0; 3] */
349 #define TW5864_RT_CNTR_CH_FRM(channel, frame) \
350 (0x0c00 | (channel << 4) | (frame << 2))
352 #define TW5864_FRAME_BUS1 0x0d00
353 /*
354 * 1 Progressive in part A in bus n
355 * 0 Interlaced in part A in bus n
356 */
357 #define TW5864_PROG_A BIT(0)
358 /*
359 * 1 Progressive in part B in bus n
360 * 0 Interlaced in part B in bus n
361 */
362 #define TW5864_PROG_B BIT(1)
363 /*
364 * 1 Frame Mode in bus n
365 * 0 Field Mode in bus n
366 */
367 #define TW5864_FRAME BIT(2)
368 /*
369 * 0 4CIF in bus n
370 * 1 1D1 + 4 CIF in bus n
371 * 2 2D1 in bus n
372 */
373 #define TW5864_BUS_D1 (3 << 3)
374 /* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */
375 /* Bus 2 goes in TW5864_FRAME_BUS1 in [12:8] */
376 #define TW5864_FRAME_BUS2 0x0d04
377 /* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */
378 /* Bus 4 goes in TW5864_FRAME_BUS2 in [12:8] */
380 /* [15:0] Horizontal Mirror for channel n */
381 #define TW5864_SENIF_HOR_MIR 0x0d08
382 /* [15:0] Vertical Mirror for channel n */
383 #define TW5864_SENIF_VER_MIR 0x0d0c
385 /*
386 * FRAME_WIDTH_BUSn_A
387 * 0x15f: 4 CIF
388 * 0x2cf: 1 D1 + 3 CIF
389 * 0x2cf: 2 D1
390 * FRAME_WIDTH_BUSn_B
391 * 0x15f: 4 CIF
392 * 0x2cf: 1 D1 + 3 CIF
393 * 0x2cf: 2 D1
394 * FRAME_HEIGHT_BUSn_A
395 * 0x11f: 4CIF (PAL)
396 * 0x23f: 1D1 + 3CIF (PAL)
397 * 0x23f: 2 D1 (PAL)
398 * 0x0ef: 4CIF (NTSC)
399 * 0x1df: 1D1 + 3CIF (NTSC)
400 * 0x1df: 2 D1 (NTSC)
401 * FRAME_HEIGHT_BUSn_B
402 * 0x11f: 4CIF (PAL)
403 * 0x23f: 1D1 + 3CIF (PAL)
404 * 0x23f: 2 D1 (PAL)
405 * 0x0ef: 4CIF (NTSC)
406 * 0x1df: 1D1 + 3CIF (NTSC)
407 * 0x1df: 2 D1 (NTSC)
408 */
409 #define TW5864_FRAME_WIDTH_BUS_A(bus) (0x0d10 + 0x0010 * bus)
410 #define TW5864_FRAME_WIDTH_BUS_B(bus) (0x0d14 + 0x0010 * bus)
411 #define TW5864_FRAME_HEIGHT_BUS_A(bus) (0x0d18 + 0x0010 * bus)
412 #define TW5864_FRAME_HEIGHT_BUS_B(bus) (0x0d1c + 0x0010 * bus)
414 /*
415 * 1: the bus mapped Channel n Full D1
416 * 0: the bus mapped Channel n Half D1
417 */
418 #define TW5864_FULL_HALF_FLAG 0x0d50
420 /*
421 * 0 The bus mapped Channel select partA Mode
422 * 1 The bus mapped Channel select partB Mode
423 */
424 #define TW5864_FULL_HALF_MODE_SEL 0x0d54
426 #define TW5864_VLC 0x1000
427 /* Define controls in register TW5864_VLC */
428 /* QP Value used by H264 CAVLC */
429 #define TW5864_VLC_SLICE_QP 0x003f
430 /*
431 * Swap byte order of VLC stream in d-word.
432 * 1 Normal (VLC output= [31:0])
433 * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]})
434 */
435 #define TW5864_VLC_BYTE_SWP BIT(6)
436 /* Enable Adding 03 circuit for VLC stream */
437 #define TW5864_VLC_ADD03_EN BIT(7)
438 /* Number of bit for VLC bit Align */
439 #define TW5864_VLC_BIT_ALIGN_SHIFT 8
440 #define TW5864_VLC_BIT_ALIGN_MASK (0x1f << 8)
441 /*
442 * Synchronous Interface select for VLC Stream
443 * 1 CDC_VLCS_MAS read VLC stream
444 * 0 CPU read VLC stream
445 */
446 #define TW5864_VLC_INF_SEL BIT(13)
447 /* Enable VLC overflow control */
448 #define TW5864_VLC_OVFL_CNTL BIT(14)
449 /*
450 * 1 PCI Master Mode
451 * 0 Non PCI Master Mode
452 */
453 #define TW5864_VLC_PCI_SEL BIT(15)
454 /*
455 * 0 Enable Adding 03 to VLC header and stream
456 * 1 Disable Adding 03 to VLC header of "00000001"
457 */
458 #define TW5864_VLC_A03_DISAB BIT(16)
459 /*
460 * Status of VLC stream in DDR (one bit for each buffer)
461 * 1 VLC is ready in buffer n (HW set)
462 * 0 VLC is not ready in buffer n (SW clear)
463 */
464 #define TW5864_VLC_BUF_RDY_SHIFT 24
465 #define TW5864_VLC_BUF_RDY_MASK (0xff << 24)
467 /* Total number of bit in the slice */
468 #define TW5864_SLICE_TOTAL_BIT 0x1004
469 /* Total number of bit in the residue */
470 #define TW5864_RES_TOTAL_BIT 0x1008
472 #define TW5864_VLC_BUF 0x100c
473 /* Define controls in register TW5864_VLC_BUF */
474 /* VLC BK0 full status, write ‘1’ to clear */
475 #define TW5864_VLC_BK0_FULL BIT(0)
476 /* VLC BK1 full status, write ‘1’ to clear */
477 #define TW5864_VLC_BK1_FULL BIT(1)
478 /* VLC end slice status, write ‘1’ to clear */
479 #define TW5864_VLC_END_SLICE BIT(2)
480 /* VLC Buffer overflow status, write ‘1’ to clear */
481 #define TW5864_DSP_RD_OF BIT(3)
482 /* VLC string length in either buffer 0 or 1 at end of frame */
483 #define TW5864_VLC_STREAM_LEN_SHIFT 4
484 #define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4)
486 /* [15:0] Total coefficient number in a frame */
487 #define TW5864_TOTAL_COEF_NO 0x1010
488 /* [0] VLC Encoder Interrupt. Write ‘1’ to clear */
489 #define TW5864_VLC_DSP_INTR 0x1014
490 /* [31:0] VLC stream CRC checksum */
491 #define TW5864_VLC_STREAM_CRC 0x1018
493 #define TW5864_VLC_RD 0x101c
494 /* Define controls in register TW5864_VLC_RD */
495 /*
496 * 1 Read VLC lookup Memory
497 * 0 Read VLC Stream Memory
498 */
499 #define TW5864_VLC_RD_MEM BIT(0)
500 /*
501 * 1 Read VLC Stream Memory in burst mode
502 * 0 Read VLC Stream Memory in single mode
503 */
504 #define TW5864_VLC_RD_BRST BIT(1)
506 /* 0x2000 ~ 0x2ffc -- H264 Stream Memory Map */
507 /*
508 * A word is 4 bytes. I.e.,
509 * VLC_STREAM_MEM[0] address: 0x2000
510 * VLC_STREAM_MEM[1] address: 0x2004
511 * ...
512 * VLC_STREAM_MEM[3FF] address: 0x2ffc
513 */
514 #define TW5864_VLC_STREAM_MEM_START 0x2000
515 #define TW5864_VLC_STREAM_MEM_MAX_OFFSET 0x3ff
516 #define TW5864_VLC_STREAM_MEM(offset) (TW5864_VLC_STREAM_MEM_START + 4 * offset)
518 /* 0x4000 ~ 0x4ffc -- Audio Register Map */
519 /* [31:0] config 1ms cnt = Realtime clk/1000 */
520 #define TW5864_CFG_1MS_CNT 0x4000
522 #define TW5864_ADPCM 0x4004
523 /* Define controls in register TW5864_ADPCM */
524 /* ADPCM decoder enable */
525 #define TW5864_ADPCM_DEC BIT(0)
526 /* ADPCM input data enable */
527 #define TW5864_ADPCM_IN_DATA BIT(1)
528 /* ADPCM encoder enable */
529 #define TW5864_ADPCM_ENC BIT(2)
531 #define TW5864_AUD 0x4008
532 /* Define controls in register TW5864_AUD */
533 /* Record path PCM Audio enable bit for each channel */
534 #define TW5864_AUD_ORG_CH_EN 0x00ff
535 /* Speaker path PCM Audio Enable */
536 #define TW5864_SPK_ORG_EN BIT(16)
537 /*
538 * 0 16bit
539 * 1 8bit
540 */
541 #define TW5864_AD_BIT_MODE BIT(17)
542 #define TW5864_AUD_TYPE_SHIFT 18
543 /*
544 * 0 PCM
545 * 3 ADPCM
546 */
547 #define TW5864_AUD_TYPE (0xf << 18)
548 #define TW5864_AUD_SAMPLE_RATE_SHIFT 22
549 /*
550 * 0 8K
551 * 1 16K
552 */
553 #define TW5864_AUD_SAMPLE_RATE (3 << 22)
554 /* Channel ID used to select audio channel (0 to 16) for loopback */
555 #define TW5864_TESTLOOP_CHID_SHIFT 24
556 #define TW5864_TESTLOOP_CHID (0x1f << 24)
557 /* Enable AD Loopback Test */
558 #define TW5864_TEST_ADLOOP_EN BIT(30)
559 /*
560 * 0 Asynchronous Mode or PCI target mode
561 * 1 PCI Initiator Mode
562 */
563 #define TW5864_AUD_MODE BIT(31)
565 #define TW5864_AUD_ADPCM 0x400c
566 /* Define controls in register TW5864_AUD_ADPCM */
567 /* Record path ADPCM audio channel enable, one bit for each */
568 #define TW5864_AUD_ADPCM_CH_EN 0x00ff
569 /* Speaker path ADPCM audio channel enable */
570 #define TW5864_SPK_ADPCM_EN BIT(16)
572 #define TW5864_PC_BLOCK_ADPCM_RD_NO 0x4018
573 #define TW5864_PC_BLOCK_ADPCM_RD_NO_MASK 0x1f
575 /*
576 * For ADPCM_ENC_WR_PTR, ADPCM_ENC_RD_PTR (see below):
577 * Bit[2:0] ch0
578 * Bit[5:3] ch1
579 * Bit[8:6] ch2
580 * Bit[11:9] ch3
581 * Bit[14:12] ch4
582 * Bit[17:15] ch5
583 * Bit[20:18] ch6
584 * Bit[23:21] ch7
585 * Bit[26:24] ch8
586 * Bit[29:27] ch9
587 * Bit[32:30] ch10
588 * Bit[35:33] ch11
589 * Bit[38:36] ch12
590 * Bit[41:39] ch13
591 * Bit[44:42] ch14
592 * Bit[47:45] ch15
593 * Bit[50:48] ch16
594 */
595 #define TW5864_ADPCM_ENC_XX_MASK 0x3fff
596 #define TW5864_ADPCM_ENC_XX_PTR2_SHIFT 30
597 /* ADPCM_ENC_WR_PTR[29:0] */
598 #define TW5864_ADPCM_ENC_WR_PTR1 0x401c
599 /* ADPCM_ENC_WR_PTR[50:30] */
600 #define TW5864_ADPCM_ENC_WR_PTR2 0x4020
602 /* ADPCM_ENC_RD_PTR[29:0] */
603 #define TW5864_ADPCM_ENC_RD_PTR1 0x4024
604 /* ADPCM_ENC_RD_PTR[50:30] */
605 #define TW5864_ADPCM_ENC_RD_PTR2 0x4028
607 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
608 #define TW5864_ADPCM_DEC_RD_WR_PTR 0x402c
610 /*
611 * For TW5864_AD_ORIG_WR_PTR, TW5864_AD_ORIG_RD_PTR:
612 * Bit[3:0] ch0
613 * Bit[7:4] ch1
614 * Bit[11:8] ch2
615 * Bit[15:12] ch3
616 * Bit[19:16] ch4
617 * Bit[23:20] ch5
618 * Bit[27:24] ch6
619 * Bit[31:28] ch7
620 * Bit[35:32] ch8
621 * Bit[39:36] ch9
622 * Bit[43:40] ch10
623 * Bit[47:44] ch11
624 * Bit[51:48] ch12
625 * Bit[55:52] ch13
626 * Bit[59:56] ch14
627 * Bit[63:60] ch15
628 * Bit[67:64] ch16
629 */
630 /* AD_ORIG_WR_PTR[31:0] */
631 #define TW5864_AD_ORIG_WR_PTR1 0x4030
632 /* AD_ORIG_WR_PTR[63:32] */
633 #define TW5864_AD_ORIG_WR_PTR2 0x4034
634 /* AD_ORIG_WR_PTR[67:64] */
635 #define TW5864_AD_ORIG_WR_PTR3 0x4038
637 /* AD_ORIG_RD_PTR[31:0] */
638 #define TW5864_AD_ORIG_RD_PTR1 0x403c
639 /* AD_ORIG_RD_PTR[63:32] */
640 #define TW5864_AD_ORIG_RD_PTR2 0x4040
641 /* AD_ORIG_RD_PTR[67:64] */
642 #define TW5864_AD_ORIG_RD_PTR3 0x4044
644 #define TW5864_PC_BLOCK_ORIG_RD_NO 0x4048
645 #define TW5864_PC_BLOCK_ORIG_RD_NO_MASK 0x1f
647 #define TW5864_PCI_AUD 0x404c
648 /* Define controls in register TW5864_PCI_AUD */
649 /*
650 * The register is applicable to PCI initiator mode only. Used to select PCM(0)
651 * or ADPCM(1) audio data sent to PC. One bit for each channel
652 */
653 #define TW5864_PCI_DATA_SEL 0xffff
654 /*
655 * Audio flow control mode selection bit.
656 * 0 Flow control disabled. TW5864 continuously sends audio frame to PC
657 * (initiator mode)
658 * 1 Flow control enabled
659 */
660 #define TW5864_PCI_FLOW_EN BIT(16)
661 /*
662 * When PCI_FLOW_EN is set, PCI need to toggle this bit to send an audio frame
663 * to PC. One toggle to send one frame.
664 */
665 #define TW5864_PCI_AUD_FRM_EN BIT(17)
667 /* [1:0] CS valid to data valid CLK cycles when writing operation */
668 #define TW5864_CS2DAT_CNT 0x8000
669 /* [2:0] Data valid signal width by system clock cycles */
670 #define TW5864_DATA_VLD_WIDTH 0x8004
672 #define TW5864_SYNC 0x8008
673 /* Define controls in register TW5864_SYNC */
674 /*
675 * 0 vlc stream to syncrous port
676 * 1 vlc stream to ddr buffers
677 */
678 #define TW5864_SYNC_CFG BIT(7)
679 /*
680 * 0 SYNC Address sampled on Rising edge
681 * 1 SYNC Address sampled on Falling edge
682 */
683 #define TW5864_SYNC_ADR_EDGE BIT(0)
684 #define TW5864_VLC_STR_DELAY_SHIFT 1
685 /*
686 * 0 No system delay
687 * 1 One system clock delay
688 * 2 Two system clock delay
689 * 3 Three system clock delay
690 */
691 #define TW5864_VLC_STR_DELAY (3 << 1)
692 /*
693 * 0 Rising edge output
694 * 1 Falling edge output
695 */
696 #define TW5864_VLC_OUT_EDGE BIT(3)
698 /*
699 * [1:0]
700 * 2’b00 phase set to 180 degree
701 * 2’b01 phase set to 270 degree
702 * 2’b10 phase set to 0 degree
703 * 2’b11 phase set to 90 degree
704 */
705 #define TW5864_I2C_PHASE_CFG 0x800c
707 /*
708 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
709 * PLL (SYSPLL) using input crystal clock of 27 MHz. The system clock PLL
710 * frequency is controlled with the following equation.
711 * CLK_OUT = CLK_IN * (M+1) / ((N+1) * P)
712 * SYSPLL_M M parameter
713 * SYSPLL_N N parameter
714 * SYSPLL_P P parameter
715 */
716 /* SYSPLL_M[7:0] */
717 #define TW5864_SYSPLL1 0x8018
718 /* Define controls in register TW5864_SYSPLL1 */
719 #define TW5864_SYSPLL_M_LOW 0x00ff
721 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
722 #define TW5864_SYSPLL2 0x8019
723 /* Define controls in register TW5864_SYSPLL2 */
724 #define TW5864_SYSPLL_M_HI 0x07
725 #define TW5864_SYSPLL_N_LOW_SHIFT 3
726 #define TW5864_SYSPLL_N_LOW (0x1f << 3)
728 /*
729 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
730 */
731 #define TW5864_SYSPLL3 0x8020
732 /* Define controls in register TW5864_SYSPLL3 */
733 #define TW5864_SYSPLL_N_HI 0x03
734 #define TW5864_SYSPLL_P_SHIFT 2
735 #define TW5864_SYSPLL_P (0x03 << 2)
736 /*
737 * SYSPLL bias current control
738 * 0 Lower current (default)
739 * 1 30% higher current
740 */
741 #define TW5864_SYSPLL_IREF BIT(4)
742 /*
743 * SYSPLL charge pump current selection
744 * 0 1,5 uA
745 * 1 4 uA
746 * 2 9 uA
747 * 3 19 uA
748 * 4 39 uA
749 * 5 79 uA
750 * 6 159 uA
751 * 7 319 uA
752 */
753 #define TW5864_SYSPLL_CP_SEL_SHIFT 5
754 #define TW5864_SYSPLL_CP_SEL (0x07 << 5)
756 /*
757 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
758 * [6]: SYSPLL_LPF_5PF, [7]: SYSPLL_ED_SEL
759 */
760 #define TW5864_SYSPLL4 0x8021
761 /* Define controls in register TW5864_SYSPLL4 */
762 /*
763 * SYSPLL_VCO VCO Range selection
764 * 00 5 ~ 75 MHz
765 * 01 50 ~ 140 MHz
766 * 10 110 ~ 320 MHz
767 * 11 270 ~ 700 MHz
768 */
769 #define TW5864_SYSPLL_VCO 0x03
770 #define TW5864_SYSPLL_LP_X8_SHIFT 2
771 /*
772 * Loop resister
773 * 0 38.5K ohms
774 * 1 6.6K ohms (default)
775 * 2 2.2K ohms
776 * 3 1.1K ohms
777 */
778 #define TW5864_SYSPLL_LP_X8 (0x03 << 2)
779 #define TW5864_SYSPLL_ICP_SEL_SHIFT 4
780 /*
781 * PLL charge pump fine tune
782 * 00 x1 (default)
783 * 01 x1/2
784 * 10 x1/7
785 * 11 x1/8
786 */
787 #define TW5864_SYSPLL_ICP_SEL (0x03 << 4)
788 /*
789 * PLL low pass filter phase margin adjustment
790 * 0 no 5pF (default)
791 * 1 5pF added
792 */
793 #define TW5864_SYSPLL_LPF_5PF BIT(6)
794 /*
795 * PFD select edge for detection
796 * 0 Falling edge (default)
797 * 1 Rising edge
798 */
799 #define TW5864_SYSPLL_ED_SEL BIT(7)
801 /* [0]: SYSPLL_RST, [4]: SYSPLL_PD */
802 #define TW5864_SYSPLL5 0x8024
803 /* Define controls in register TW5864_SYSPLL5 */
804 /* Reset SYSPLL */
805 #define TW5864_SYSPLL_RST BIT(0)
806 /* Power down SYSPLL */
807 #define TW5864_SYSPLL_PD BIT(4)
809 #define TW5864_PLL_CFG 0x801c
810 /* Define controls in register TW5864_PLL_CFG */
811 /*
812 * Issue Soft Reset from Async Host Interface / PCI Interface clock domain.
813 * Become valid after sync to the xtal clock domain. This bit is set only if
814 * LOAD register bit is also set to 1.
815 */
816 #define TW5864_SRST BIT(0)
817 /*
818 * Issue SYSPLL (166 MHz) configuration latch from Async host interface / PCI
819 * Interface clock domain. The configuration setting becomes effective only if
820 * LOAD register bit is also set to 1.
821 */
822 #define TW5864_SYSPLL_CFG BIT(2)
823 /*
824 * Issue SPLL (108 MHz) configuration load from Async host interface / PCI
825 * Interface clock domain. The configuration setting becomes effective only if
826 * the LOAD register bit is also set to 1.
827 */
828 #define TW5864_SPLL_CFG BIT(4)
829 /*
830 * Set this bit to latch the SRST, SYSPLL_CFG, SPLL_CFG setting into the xtal
831 * clock domain to restart the PLL. This bit is self cleared.
832 */
833 #define TW5864_LOAD BIT(3)
835 /* SPLL_IREF, SPLL_LPX4, SPLL_CPX4, SPLL_PD, SPLL_DBG */
836 #define TW5864_SPLL 0x8028
838 /* 0x8800 ~ 0x88fc -- Interrupt Register Map */
839 /*
840 * Trigger mode of interrupt source 0 ~ 15
841 * 1 Edge trigger mode
842 * 0 Level trigger mode
843 */
844 #define TW5864_TRIGGER_MODE_L 0x8800
845 /* Trigger mode of interrupt source 16 ~ 31 */
846 #define TW5864_TRIGGER_MODE_H 0x8804
847 /* Enable of interrupt source 0 ~ 15 */
848 #define TW5864_INTR_ENABLE_L 0x8808
849 /* Enable of interrupt source 16 ~ 31 */
850 #define TW5864_INTR_ENABLE_H 0x880c
851 /* Clear interrupt command of interrupt source 0 ~ 15 */
852 #define TW5864_INTR_CLR_L 0x8810
853 /* Clear interrupt command of interrupt source 16 ~ 31 */
854 #define TW5864_INTR_CLR_H 0x8814
855 /*
856 * Assertion of interrupt source 0 ~ 15
857 * 1 High level or pos-edge is assertion
858 * 0 Low level or neg-edge is assertion
859 */
860 #define TW5864_INTR_ASSERT_L 0x8818
861 /* Assertion of interrupt source 16 ~ 31 */
862 #define TW5864_INTR_ASSERT_H 0x881c
863 /*
864 * Output level of interrupt
865 * 1 Interrupt output is high assertion
866 * 0 Interrupt output is low assertion
867 */
868 #define TW5864_INTR_OUT_LEVEL 0x8820
869 /*
870 * Status of interrupt source 0 ~ 15
871 * Bit[0]: VLC 4k RAM interrupt
872 * Bit[1]: BURST DDR RAM interrupt
873 * Bit[2]: MV DSP interrupt
874 * Bit[3]: video lost interrupt
875 * Bit[4]: gpio 0 interrupt
876 * Bit[5]: gpio 1 interrupt
877 * Bit[6]: gpio 2 interrupt
878 * Bit[7]: gpio 3 interrupt
879 * Bit[8]: gpio 4 interrupt
880 * Bit[9]: gpio 5 interrupt
881 * Bit[10]: gpio 6 interrupt
882 * Bit[11]: gpio 7 interrupt
883 * Bit[12]: JPEG interrupt
884 * Bit[13:15]: Reserved
885 */
886 #define TW5864_INTR_STATUS_L 0x8838
887 /*
888 * Status of interrupt source 16 ~ 31
889 * Bit[0]: Reserved
890 * Bit[1]: VLC done interrupt
891 * Bit[2]: Reserved
892 * Bit[3]: AD Vsync interrupt
893 * Bit[4]: Preview eof interrupt
894 * Bit[5]: Preview overflow interrupt
895 * Bit[6]: Timer interrupt
896 * Bit[7]: Reserved
897 * Bit[8]: Audio eof interrupt
898 * Bit[9]: I2C done interrupt
899 * Bit[10]: AD interrupt
900 * Bit[11:15]: Reserved
901 */
902 #define TW5864_INTR_STATUS_H 0x883c
904 /* Defines of interrupt bits, united for both low and high word registers */
905 #define TW5864_INTR_VLC_RAM BIT(0)
906 #define TW5864_INTR_BURST BIT(1)
907 #define TW5864_INTR_MV_DSP BIT(2)
908 #define TW5864_INTR_VIN_LOST BIT(3)
909 /* n belongs to [0; 7] */
910 #define TW5864_INTR_GPIO(n) (1 << (4 + n))
911 #define TW5864_INTR_JPEG BIT(12)
912 #define TW5864_INTR_VLC_DONE BIT(17)
913 #define TW5864_INTR_AD_VSYNC BIT(19)
914 #define TW5864_INTR_PV_EOF BIT(20)
915 #define TW5864_INTR_PV_OVERFLOW BIT(21)
916 #define TW5864_INTR_TIMER BIT(22)
917 #define TW5864_INTR_AUD_EOF BIT(24)
918 #define TW5864_INTR_I2C_DONE BIT(25)
919 #define TW5864_INTR_AD BIT(26)
921 /* 0x9000 ~ 0x920c -- Video Capture (VIF) Register Map */
922 /*
923 * H264EN_CH_STATUS[n] Status of Vsync synchronized H264EN_CH_EN (Read Only)
924 * 1 Channel Enabled
925 * 0 Channel Disabled
926 */
927 #define TW5864_H264EN_CH_STATUS 0x9000
928 /*
929 * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
930 * 1 Channel Enabled
931 * 0 Channel Disabled
932 */
933 #define TW5864_H264EN_CH_EN 0x9004
934 /*
935 * H264EN_CH_DNS[n] H264 Encoding Path Downscale Video Decoder Input for
936 * channel n
937 * 1 Downscale Y to 1/2
938 * 0 Does not downscale
939 */
940 #define TW5864_H264EN_CH_DNS 0x9008
941 /*
942 * H264EN_CH_PROG[n] H264 Encoding Path channel n is progressive
943 * 1 Progressive (Not valid for TW5864)
944 * 0 Interlaced (TW5864 default)
945 */
946 #define TW5864_H264EN_CH_PROG 0x900c
947 /*
948 * [3:0] H264EN_BUS_MAX_CH[n]
949 * H264 Encoding Path maximum number of channel on BUS n
950 * 0 Max 4 channels
951 * 1 Max 2 channels
952 */
953 #define TW5864_H264EN_BUS_MAX_CH 0x9010
955 /*
956 * H264EN_RATE_MAX_LINE_n H264 Encoding path Rate Mapping Maximum Line Number
957 * on Bus n
958 */
959 #define TW5864_H264EN_RATE_MAX_LINE_EVEN 0x1f
960 #define TW5864_H264EN_RATE_MAX_LINE_ODD_SHIFT 5
961 #define TW5864_H264EN_RATE_MAX_LINE_ODD (0x1f << 5)
962 /*
963 * [4:0] H264EN_RATE_MAX_LINE_0
964 * [9:5] H264EN_RATE_MAX_LINE_1
965 */
966 #define TW5864_H264EN_RATE_MAX_LINE_REG1 0x9014
967 /*
968 * [4:0] H264EN_RATE_MAX_LINE_2
969 * [9:5] H264EN_RATE_MAX_LINE_3
970 */
971 #define TW5864_H264EN_RATE_MAX_LINE_REG2 0x9018
973 /*
974 * H264EN_CHn_FMT H264 Encoding Path Format configuration of Channel n
975 * 00 D1 (For D1 and hD1 frame)
976 * 01 (Reserved)
977 * 10 (Reserved)
978 * 11 D1 with 1/2 size in X (for CIF frame)
979 * Note: To be used with 0x9008 register to configure the frame size
980 */
981 /*
982 * [1:0]: H264EN_CH0_FMT,
983 * ..., [15:14]: H264EN_CH7_FMT
984 */
985 #define TW5864_H264EN_CH_FMT_REG1 0x9020
986 /*
987 * [1:0]: H264EN_CH8_FMT (?),
988 * ..., [15:14]: H264EN_CH15_FMT (?)
989 */
990 #define TW5864_H264EN_CH_FMT_REG2 0x9024
992 /*
993 * H264EN_RATE_CNTL_BUSm_CHn H264 Encoding Path BUS m Rate Control for Channel n
994 */
995 #define TW5864_H264EN_RATE_CNTL_LO_WORD(bus, channel) \
996 (0x9100 + bus * 0x20 + channel * 0x08)
997 #define TW5864_H264EN_RATE_CNTL_HI_WORD(bus, channel) \
998 (0x9104 + bus * 0x20 + channel * 0x08)
1000 /*
1001 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1002 * channel (total of 16 channels). Four bits for each channel.
1003 */
1004 #define TW5864_H264EN_BUS0_MAP 0x9200
1005 #define TW5864_H264EN_BUS1_MAP 0x9204
1006 #define TW5864_H264EN_BUS2_MAP 0x9208
1007 #define TW5864_H264EN_BUS3_MAP 0x920c
1009 /* This register is not defined in datasheet, but used in reference driver */
1010 #define TW5864_UNDECLARED_ERROR_FLAGS_0x9218 0x9218
1012 #define TW5864_GPIO1 0x9800
1013 #define TW5864_GPIO2 0x9804
1014 /* Define controls in registers TW5864_GPIO1, TW5864_GPIO2 */
1015 /* GPIO DATA of Group n */
1016 #define TW5864_GPIO_DATA 0x00ff
1017 #define TW5864_GPIO_OEN_SHIFT 8
1018 /* GPIO Output Enable of Group n */
1019 #define TW5864_GPIO_OEN (0xff << 8)
1021 /* 0xa000 ~ 0xa8ff – DDR Controller Register Map */
1022 /* DDR Controller A */
1023 /*
1024 * [2:0] Data valid counter after read command to DDR. This is the delay value
1025 * to show how many cycles the data will be back from DDR after we issue a read
1026 * command.
1027 */
1028 #define TW5864_RD_ACK_VLD_MUX 0xa000
1030 #define TW5864_DDR_PERIODS 0xa004
1031 /* Define controls in register TW5864_DDR_PERIODS */
1032 /*
1033 * Tras value, the minimum cycle of active to precharge command period,
1034 * default is 7
1035 */
1036 #define TW5864_TRAS_CNT_MAX 0x000f
1037 /*
1038 * Trfc value, the minimum cycle of refresh to active or refresh command period,
1039 * default is 4"hf
1040 */
1041 #define TW5864_RFC_CNT_MAX_SHIFT 8
1042 #define TW5864_RFC_CNT_MAX (0x0f << 8)
1043 /*
1044 * Trcd value, the minimum cycle of active to internal read/write command
1045 * period, default is 4"h2
1046 */
1047 #define TW5864_TCD_CNT_MAX_SHIFT 4
1048 #define TW5864_TCD_CNT_MAX (0x0f << 4)
1049 /* Twr value, write recovery time, default is 4"h3 */
1050 #define TW5864_TWR_CNT_MAX_SHIFT 12
1051 #define TW5864_TWR_CNT_MAX (0x0f << 12)
1053 /*
1054 * [2:0] CAS latency, the delay cycle between internal read command and the
1055 * availability of the first bit of output data, default is 3
1056 */
1057 #define TW5864_CAS_LATENCY 0xa008
1058 /*
1059 * [15:0] Maximum average periodic refresh, the value is based on the current
1060 * frequency to match 7.8mcs
1061 */
1062 #define TW5864_DDR_REF_CNTR_MAX 0xa00c
1063 /*
1064 * DDR_ON_CHIP_MAP [1:0]
1065 * 0 256M DDR on board
1066 * 1 512M DDR on board
1067 * 2 1G DDR on board
1068 * DDR_ON_CHIP_MAP [2]
1069 * 0 Only one DDR chip
1070 * 1 Two DDR chips
1071 */
1072 #define TW5864_DDR_ON_CHIP_MAP 0xa01c
1073 #define TW5864_DDR_SELFTEST_MODE 0xa020
1074 /* Define controls in register TW5864_DDR_SELFTEST_MODE */
1075 /*
1076 * 0 Common read/write mode
1077 * 1 DDR self-test mode
1078 */
1079 #define TW5864_MASTER_MODE BIT(0)
1080 /*
1081 * 0 DDR self-test single read/write
1082 * 1 DDR self-test burst read/write
1083 */
1084 #define TW5864_SINGLE_PROC BIT(1)
1085 /*
1086 * 0 DDR self-test write command
1087 * 1 DDR self-test read command
1088 */
1089 #define TW5864_WRITE_FLAG BIT(2)
1090 #define TW5864_DATA_MODE_SHIFT 4
1091 /*
1092 * 0 write 32'haaaa5555 to DDR
1093 * 1 write 32'hffffffff to DDR
1094 * 2 write 32'hha5a55a5a to DDR
1095 * 3 write increasing data to DDR
1096 */
1097 #define TW5864_DATA_MODE (0x3 << 4)
1099 /* [7:0] The maximum data of one burst in DDR self-test mode */
1100 #define TW5864_BURST_CNTR_MAX 0xa024
1101 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1102 #define TW5864_DDR_PROC_CNTR_MAX_L 0xa028
1103 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1104 #define TW5864_DDR_PROC_CNTR_MAX_H 0xa02c
1105 /* [0]: Start one DDR self-test */
1106 #define TW5864_DDR_SELF_TEST_CMD 0xa030
1107 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1108 #define TW5864_ERR_CNTR_L 0xa034
1110 #define TW5864_ERR_CNTR_H_AND_FLAG 0xa038
1111 /* Define controls in register TW5864_ERR_CNTR_H_AND_FLAG */
1112 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1113 #define TW5864_ERR_CNTR_H_MASK 0x3fff
1114 /* DDR self-test end flag */
1115 #define TW5864_END_FLAG 0x8000
1117 /*
1118 * DDR Controller B: same as 0xa000 ~ 0xa038, but add TW5864_DDR_B_OFFSET to all
1119 * addresses
1120 */
1121 #define TW5864_DDR_B_OFFSET 0x0800
1123 /* 0xb004 ~ 0xb018 – HW version/ARB12 Register Map */
1124 /* [15:0] Default is C013 */
1125 #define TW5864_HW_VERSION 0xb004
1127 #define TW5864_REQS_ENABLE 0xb010
1128 /* Define controls in register TW5864_REQS_ENABLE */
1129 /* Audio data in to DDR enable (default 1) */
1130 #define TW5864_AUD_DATA_IN_ENB BIT(0)
1131 /* Audio encode request to DDR enable (default 1) */
1132 #define TW5864_AUD_ENC_REQ_ENB BIT(1)
1133 /* Audio decode request0 to DDR enable (default 1) */
1134 #define TW5864_AUD_DEC_REQ0_ENB BIT(2)
1135 /* Audio decode request1 to DDR enable (default 1) */
1136 #define TW5864_AUD_DEC_REQ1_ENB BIT(3)
1137 /* VLC stream request to DDR enable (default 1) */
1138 #define TW5864_VLC_STRM_REQ_ENB BIT(4)
1139 /* H264 MV request to DDR enable (default 1) */
1140 #define TW5864_DVM_MV_REQ_ENB BIT(5)
1141 /* mux_core MVD request to DDR enable (default 1) */
1142 #define TW5864_MVD_REQ_ENB BIT(6)
1143 /* mux_core MVD temp data request to DDR enable (default 1) */
1144 #define TW5864_MVD_TMP_REQ_ENB BIT(7)
1145 /* JPEG request to DDR enable (default 1) */
1146 #define TW5864_JPEG_REQ_ENB BIT(8)
1147 /* mv_flag request to DDR enable (default 1) */
1148 #define TW5864_MV_FLAG_REQ_ENB BIT(9)
1150 #define TW5864_ARB12 0xb018
1151 /* Define controls in register TW5864_ARB12 */
1152 /* ARB12 Enable (default 1) */
1153 #define TW5864_ARB12_ENB BIT(15)
1154 /* ARB12 maximum value of time out counter (default 15"h1FF) */
1155 #define TW5864_ARB12_TIME_OUT_CNT 0x7fff
1157 /* 0xb800 ~ 0xb80c -- Indirect Access Register Map */
1158 /*
1159 * Spec says:
1160 * In order to access the indirect register space, the following procedure is
1161 * followed.
1162 * But reference driver implementation, and current driver, too, does it
1163 * differently.
1164 *
1165 * Write Registers:
1166 * (1) Write IND_DATA at 0xb804 ~ 0xb807
1167 * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1168 * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1"
1169 * Read Registers:
1170 * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1171 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1172 * (3) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1173 * (4) Read IND_DATA from 0xb804 ~ 0xb807
1174 */
1175 #define TW5864_IND_CTL 0xb800
1176 /* Define controls in register TW5864_IND_CTL */
1177 /* Address used to access indirect register space */
1178 #define TW5864_IND_ADDR 0x0000ffff
1179 /* Wait until this bit is "0" before using indirect access */
1180 #define TW5864_BUSY BIT(31)
1181 /* Activate the indirect access. This bit is self cleared */
1182 #define TW5864_ENABLE BIT(25)
1183 /* Read/Write command */
1184 #define TW5864_RW BIT(24)
1186 /* [31:0] Data used to read/write indirect register space */
1187 #define TW5864_IND_DATA 0xb804
1189 /* 0xc000 ~ 0xc7fc -- Preview Register Map */
1190 /* Mostly skipped this section. */
1191 /*
1192 * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only)
1193 * 1 Channel Enabled
1194 * 0 Channel Disabled
1195 */
1196 #define TW5864_PCI_PV_CH_STATUS 0xc000
1197 /*
1198 * [15:0] PCI Preview Path Enable for channel n
1199 * 1 Channel Enable
1200 * 0 Channel Disable
1201 */
1202 #define TW5864_PCI_PV_CH_EN 0xc004
1204 /* 0xc800 ~ 0xc804 -- JPEG Capture Register Map */
1205 /* Skipped. */
1206 /* 0xd000 ~ 0xd0fc -- JPEG Control Register Map */
1207 /* Skipped. */
1209 /* 0xe000 ~ 0xfc04 – Motion Vector Register Map */
1211 /* ME Motion Vector data (Four Byte Each) 0xe000 ~ 0xe7fc */
1212 #define TW5864_ME_MV_VEC_START 0xe000
1213 #define TW5864_ME_MV_VEC_MAX_OFFSET 0x1ff
1214 #define TW5864_ME_MV_VEC(offset) (TW5864_ME_MV_VEC_START + 4 * offset)
1216 #define TW5864_MV 0xfc00
1217 /* Define controls in register TW5864_MV */
1218 /* mv bank0 full status , write "1" to clear */
1219 #define TW5864_MV_BK0_FULL BIT(0)
1220 /* mv bank1 full status , write "1" to clear */
1221 #define TW5864_MV_BK1_FULL BIT(1)
1222 /* slice end status; write "1" to clear */
1223 #define TW5864_MV_EOF BIT(2)
1224 /* mv encode interrupt status; write "1" to clear */
1225 #define TW5864_MV_DSP_INTR BIT(3)
1226 /* mv write memory overflow, write "1" to clear */
1227 #define TW5864_DSP_WR_OF BIT(4)
1228 #define TW5864_MV_LEN_SHIFT 5
1229 /* mv stream length */
1230 #define TW5864_MV_LEN (0xff << 5)
1231 /* The configured status bit written into bit 15 of 0xfc04 */
1232 #define TW5864_MPI_DDR_SEL BIT(13)
1234 #define TW5864_MPI_DDR_SEL_REG 0xfc04
1235 /* Define controls in register TW5864_MPI_DDR_SEL_REG */
1236 /*
1237 * SW configure register
1238 * 0 MV is saved in internal DPR
1239 * 1 MV is saved in DDR
1240 */
1241 #define TW5864_MPI_DDR_SEL2 BIT(15)
1243 /* 0x18000 ~ 0x181fc – PCI Master/Slave Control Map */
1244 #define TW5864_PCI_INTR_STATUS 0x18000
1245 /* Define controls in register TW5864_PCI_INTR_STATUS */
1246 /* vlc done */
1247 #define TW5864_VLC_DONE_INTR BIT(1)
1248 /* ad vsync */
1249 #define TW5864_AD_VSYNC_INTR BIT(3)
1250 /* preview eof */
1251 #define TW5864_PREV_EOF_INTR BIT(4)
1252 /* preview overflow interrupt */
1253 #define TW5864_PREV_OVERFLOW_INTR BIT(5)
1254 /* timer interrupt */
1255 #define TW5864_TIMER_INTR BIT(6)
1256 /* audio eof */
1257 #define TW5864_AUDIO_EOF_INTR BIT(8)
1258 /* IIC done */
1259 #define TW5864_IIC_DONE_INTR BIT(24)
1260 /* ad interrupt (e.g.: video lost, video format changed) */
1261 #define TW5864_AD_INTR_REG BIT(25)
1263 #define TW5864_PCI_INTR_CTL 0x18004
1264 /* Define controls in register TW5864_PCI_INTR_CTL */
1265 /* master enable */
1266 #define TW5864_PCI_MAST_ENB BIT(0)
1267 /* mvd&vlc master enable */
1268 #define TW5864_MVD_VLC_MAST_ENB 0x06
1269 /* (Need to set 0 in TW5864A) */
1270 #define TW5864_AD_MAST_ENB BIT(3)
1271 /* preview master enable */
1272 #define TW5864_PREV_MAST_ENB BIT(4)
1273 /* preview overflow enable */
1274 #define TW5864_PREV_OVERFLOW_ENB BIT(5)
1275 /* timer interrupt enable */
1276 #define TW5864_TIMER_INTR_ENB BIT(6)
1277 /* JPEG master (push mode) enable */
1278 #define TW5864_JPEG_MAST_ENB BIT(7)
1279 #define TW5864_AU_MAST_ENB_CHN_SHIFT 8
1280 /* audio master channel enable */
1281 #define TW5864_AU_MAST_ENB_CHN (0xffff << 8)
1282 /* IIC interrupt enable */
1283 #define TW5864_IIC_INTR_ENB BIT(24)
1284 /* ad interrupt enable */
1285 #define TW5864_AD_INTR_ENB BIT(25)
1286 /* target burst enable */
1287 #define TW5864_PCI_TAR_BURST_ENB BIT(26)
1288 /* vlc stream burst enable */
1289 #define TW5864_PCI_VLC_BURST_ENB BIT(27)
1290 /* ddr burst enable (1 enable, and must set DDR_BRST_EN) */
1291 #define TW5864_PCI_DDR_BURST_ENB BIT(28)
1293 /*
1294 * Because preview and audio have 16 channels separately, so using this
1295 * registers to indicate interrupt status for every channels. This is secondary
1296 * interrupt status register. OR operating of the PREV_INTR_REG is
1297 * PREV_EOF_INTR, OR operating of the AU_INTR_REG bits is AUDIO_EOF_INTR
1298 */
1299 #define TW5864_PREV_AND_AU_INTR 0x18008
1300 /* Define controls in register TW5864_PREV_AND_AU_INTR */
1301 /* preview eof interrupt flag */
1302 #define TW5864_PREV_INTR_REG 0x0000ffff
1303 #define TW5864_AU_INTR_REG_SHIFT 16
1304 /* audio eof interrupt flag */
1305 #define TW5864_AU_INTR_REG (0xffff << 16)
1307 #define TW5864_MASTER_ENB_REG 0x1800c
1308 /* Define controls in register TW5864_MASTER_ENB_REG */
1309 /* master enable */
1310 #define TW5864_PCI_VLC_INTR_ENB BIT(1)
1311 /* mvd and vlc master enable */
1312 #define TW5864_PCI_PREV_INTR_ENB BIT(4)
1313 /* ad vsync master enable */
1314 #define TW5864_PCI_PREV_OF_INTR_ENB BIT(5)
1315 /* jpeg master enable */
1316 #define TW5864_PCI_JPEG_INTR_ENB BIT(7)
1317 /* preview master enable */
1318 #define TW5864_PCI_AUD_INTR_ENB BIT(8)
1320 /*
1321 * Every channel of preview and audio have ping-pong buffers in system memory,
1322 * this register is the buffer flag to notify software which buffer is been
1323 * operated.
1324 */
1325 #define TW5864_PREV_AND_AU_BUF_FLAG 0x18010
1326 /* Define controls in register TW5864_PREV_AND_AU_BUF_FLAG */
1327 /* preview buffer A/B flag */
1328 #define TW5864_PREV_BUF_FLAG 0xffff
1329 #define TW5864_AUDIO_BUF_FLAG_SHIFT 16
1330 /* audio buffer A/B flag */
1331 #define TW5864_AUDIO_BUF_FLAG (0xffff << 16)
1333 #define TW5864_IIC 0x18014
1334 /* Define controls in register TW5864_IIC */
1335 /* register data */
1336 #define TW5864_IIC_DATA 0x00ff
1337 #define TW5864_IIC_REG_ADDR_SHIFT 8
1338 /* register addr */
1339 #define TW5864_IIC_REG_ADDR (0xff << 8)
1340 /* rd/wr flag rd=1,wr=0 */
1341 #define TW5864_IIC_RW BIT(16)
1342 #define TW5864_IIC_DEV_ADDR_SHIFT 17
1343 /* device addr */
1344 #define TW5864_IIC_DEV_ADDR (0x7f << 17)
1345 /*
1346 * iic done, software kick off one time iic transaction through setting this
1347 * bit to 1. Then poll this bit, value 1 indicate iic transaction have
1348 * completed, if read, valid data have been stored in iic_data
1349 */
1350 #define TW5864_IIC_DONE BIT(24)
1352 #define TW5864_RST_AND_IF_INFO 0x18018
1353 /* Define controls in register TW5864_RST_AND_IF_INFO */
1354 /* application software soft reset */
1355 #define TW5864_APP_SOFT_RST BIT(0)
1356 #define TW5864_PCI_INF_VERSION_SHIFT 16
1357 /* PCI interface version, read only */
1358 #define TW5864_PCI_INF_VERSION (0xffff << 16)
1360 /* vlc stream crc value, it is calculated in pci module */
1361 #define TW5864_VLC_CRC_REG 0x1801c
1362 /*
1363 * vlc max length, it is defined by software based on software assign memory
1364 * space for vlc
1365 */
1366 #define TW5864_VLC_MAX_LENGTH 0x18020
1367 /* vlc length of one frame */
1368 #define TW5864_VLC_LENGTH 0x18024
1369 /* vlc original crc value */
1370 #define TW5864_VLC_INTRA_CRC_I_REG 0x18028
1371 /* vlc original crc value */
1372 #define TW5864_VLC_INTRA_CRC_O_REG 0x1802c
1373 /* mv stream crc value, it is calculated in pci module */
1374 #define TW5864_VLC_PAR_CRC_REG 0x18030
1375 /* mv length */
1376 #define TW5864_VLC_PAR_LENGTH_REG 0x18034
1377 /* mv original crc value */
1378 #define TW5864_VLC_PAR_I_REG 0x18038
1379 /* mv original crc value */
1380 #define TW5864_VLC_PAR_O_REG 0x1803c
1382 /*
1383 * Configuration register for 9[or 10] CIFs or 1D1+15QCIF Preview mode.
1384 * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1385 * (1D1+15QCIF prev)
1386 * PREV_PCI_ENB_CHN[1] Enable 10th preview channel
1387 */
1388 #define TW5864_PREV_PCI_ENB_CHN 0x18040
1389 /* Description skipped. */
1390 #define TW5864_PREV_FRAME_FORMAT_IN 0x18044
1391 /* IIC enable */
1392 #define TW5864_IIC_ENB 0x18048
1393 /*
1394 * Timer interrupt interval
1395 * 0 1ms
1396 * 1 2ms
1397 * 2 4ms
1398 * 3 8ms
1399 */
1400 #define TW5864_PCI_INTTM_SCALE 0x1804c
1402 /*
1403 * The above register is pci base address registers. Application software will
1404 * initialize them to tell chip where the corresponding stream will be dumped
1405 * to. Application software will select appropriate base address interval based
1406 * on the stream length.
1407 */
1408 /* VLC stream base address */
1409 #define TW5864_VLC_STREAM_BASE_ADDR 0x18080
1410 /* MV stream base address */
1411 #define TW5864_MV_STREAM_BASE_ADDR 0x18084
1412 /* 0x180a0 – 0x180bc: audio burst base address. Skipped. */
1413 /* 0x180c0 ~ 0x180dc – JPEG Push Mode Buffer Base Address. Skipped. */
1414 /* 0x18100 – 0x1817c: preview burst base address. Skipped. */
1416 /* 0x80000 ~ 0x87fff -- DDR Burst RW Register Map */
1417 #define TW5864_DDR_CTL 0x80000
1418 /* Define controls in register TW5864_DDR_CTL */
1419 #define TW5864_BRST_LENGTH_SHIFT 2
1420 /* Length of 32-bit data burst */
1421 #define TW5864_BRST_LENGTH (0x3fff << 2)
1422 /*
1423 * Burst Read/Write
1424 * 0 Read Burst from DDR
1425 * 1 Write Burst to DDR
1426 */
1427 #define TW5864_BRST_RW BIT(16)
1428 /* Begin a new DDR Burst. This bit is self cleared */
1429 #define TW5864_NEW_BRST_CMD BIT(17)
1430 /* DDR Burst End Flag */
1431 #define TW5864_BRST_END BIT(24)
1432 /* Enable Error Interrupt for Single DDR Access */
1433 #define TW5864_SING_ERR_INTR BIT(25)
1434 /* Enable Error Interrupt for Burst DDR Access */
1435 #define TW5864_BRST_ERR_INTR BIT(26)
1436 /* Enable Interrupt for End of DDR Burst Access */
1437 #define TW5864_BRST_END_INTR BIT(27)
1438 /* DDR Single Access Error Flag */
1439 #define TW5864_SINGLE_ERR BIT(28)
1440 /* DDR Single Access Busy Flag */
1441 #define TW5864_SINGLE_BUSY BIT(29)
1442 /* DDR Burst Access Error Flag */
1443 #define TW5864_BRST_ERR BIT(30)
1444 /* DDR Burst Access Busy Flag */
1445 #define TW5864_BRST_BUSY BIT(31)
1447 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1448 #define TW5864_DDR_ADDR 0x80004
1449 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
1450 #define TW5864_DPR_BUF_ADDR 0x80008
1451 /* SRAM Buffer MPI Access Space. Totally 16 KB */
1452 #define TW5864_DPR_BUF_START 0x84000
1453 /* 0x84000 - 0x87ffc */
1454 #define TW5864_DPR_BUF_SIZE 0x4000
1456 /* Indirect Map Space */
1457 /*
1458 * The indirect space is accessed through 0xb800 ~ 0xb807 registers in direct
1459 * access space
1460 */
1461 /* Analog Video / Audio Decoder / Encoder */
1462 /* Allowed channel values: [0; 3] */
1463 /* Read-only register */
1464 #define TW5864_INDIR_VIN_0(channel) (0x000 + channel * 0x010)
1465 /* Define controls in register TW5864_INDIR_VIN_0 */
1466 /*
1467 * 1 Video not present. (sync is not detected in number of consecutive line
1468 * periods specified by MISSCNT register)
1469 * 0 Video detected.
1470 */
1471 #define TW5864_INDIR_VIN_0_VDLOSS BIT(7)
1472 /*
1473 * 1 Horizontal sync PLL is locked to the incoming video source.
1474 * 0 Horizontal sync PLL is not locked.
1475 */
1476 #define TW5864_INDIR_VIN_0_HLOCK BIT(6)
1477 /*
1478 * 1 Sub-carrier PLL is locked to the incoming video source.
1479 * 0 Sub-carrier PLL is not locked.
1480 */
1481 #define TW5864_INDIR_VIN_0_SLOCK BIT(5)
1482 /*
1483 * 1 Even field is being decoded.
1484 * 0 Odd field is being decoded.
1485 */
1486 #define TW5864_INDIR_VIN_0_FLD BIT(4)
1487 /*
1488 * 1 Vertical logic is locked to the incoming video source.
1489 * 0 Vertical logic is not locked.
1490 */
1491 #define TW5864_INDIR_VIN_0_VLOCK BIT(3)
1492 /*
1493 * 1 No color burst signal detected.
1494 * 0 Color burst signal detected.
1495 */
1496 #define TW5864_INDIR_VIN_0_MONO BIT(1)
1497 /*
1498 * 0 60Hz source detected
1499 * 1 50Hz source detected
1500 * The actual vertical scanning frequency depends on the current standard
1501 * invoked.
1502 */
1503 #define TW5864_INDIR_VIN_0_DET50 BIT(0)
1505 #define TW5864_INDIR_VIN_1(channel) (0x001 + channel * 0x010)
1506 /* VCR signal indicator. Read-only. */
1507 #define TW5864_INDIR_VIN_1_VCR BIT(7)
1508 /* Weak signal indicator 2. Read-only. */
1509 #define TW5864_INDIR_VIN_1_WKAIR BIT(6)
1510 /* Weak signal indicator controlled by WKTH. Read-only. */
1511 #define TW5864_INDIR_VIN_1_WKAIR1 BIT(5)
1512 /*
1513 * 1 = Standard signal
1514 * 0 = Non-standard signal
1515 * Read-only
1516 */
1517 #define TW5864_INDIR_VIN_1_VSTD BIT(4)
1518 /*
1519 * 1 = Non-interlaced signal
1520 * 0 = interlaced signal
1521 * Read-only
1522 */
1523 #define TW5864_INDIR_VIN_1_NINTL BIT(3)
1524 /*
1525 * Vertical Sharpness Control. Writable.
1526 * 0 = None (default)
1527 * 7 = Highest
1528 * **Note: VSHP must be set to ‘0’ if COMB = 0
1529 */
1530 #define TW5864_INDIR_VIN_1_VSHP 0x07
1532 /* HDELAY_XY[7:0] */
1533 #define TW5864_INDIR_VIN_2_HDELAY_XY_LO(channel) (0x002 + channel * 0x010)
1534 /* HACTIVE_XY[7:0] */
1535 #define TW5864_INDIR_VIN_3_HACTIVE_XY_LO(channel) (0x003 + channel * 0x010)
1536 /* VDELAY_XY[7:0] */
1537 #define TW5864_INDIR_VIN_4_VDELAY_XY_LO(channel) (0x004 + channel * 0x010)
1538 /* VACTIVE_XY[7:0] */
1539 #define TW5864_INDIR_VIN_5_VACTIVE_XY_LO(channel) (0x005 + channel * 0x010)
1541 #define TW5864_INDIR_VIN_6(channel) (0x006 + channel * 0x010)
1542 /* Define controls in register TW5864_INDIR_VIN_6 */
1543 #define TW5864_INDIR_VIN_6_HDELAY_XY_HI 0x03
1544 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI_SHIFT 2
1545 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI (0x03 << 2)
1546 #define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4)
1547 #define TW5864_INDIR_VIN_6_VACTIVE_XY_HI BIT(5)
1549 /*
1550 * HDELAY_XY This 10bit register defines the starting location of horizontal
1551 * active pixel for display / record path. A unit is 1 pixel. The default value
1552 * is 0x00f for NTSC and 0x00a for PAL.
1553 *
1554 * HACTIVE_XY This 10bit register defines the number of horizontal active pixel
1555 * for display / record path. A unit is 1 pixel. The default value is decimal
1556 * 720.
1557 *
1558 * VDELAY_XY This 9bit register defines the starting location of vertical
1559 * active for display / record path. A unit is 1 line. The default value is
1560 * decimal 6.
1561 *
1562 * VACTIVE_XY This 9bit register defines the number of vertical active lines
1563 * for display / record path. A unit is 1 line. The default value is decimal
1564 * 240.
1565 */
1567 /* HUE These bits control the color hue as 2's complement number. They have
1568 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1569 * no effect. The positive value gives greenish tone and negative value gives
1570 * purplish tone. The default value is 0o (00h). This is effective only on NTSC
1571 * system. The default is 00h.
1572 */
1573 #define TW5864_INDIR_VIN_7_HUE(channel) (0x007 + channel * 0x010)
1575 #define TW5864_INDIR_VIN_8(channel) (0x008 + channel * 0x010)
1576 /* Define controls in register TW5864_INDIR_VIN_8 */
1577 /*
1578 * This bit controls the center frequency of the peaking filter.
1579 * The corresponding gain adjustment is HFLT.
1580 * 0 Low
1581 * 1 center
1582 */
1583 #define TW5864_INDIR_VIN_8_SCURVE BIT(7)
1584 /* CTI level selection. The default is 1.
1585 * 0 None
1586 * 3 Highest
1587 */
1588 #define TW5864_INDIR_VIN_8_CTI_SHIFT 4
1589 #define TW5864_INDIR_VIN_8_CTI (0x03 << 4)
1591 /*
1592 * These bits control the amount of sharpness enhancement on the luminance
1593 * signals. There are 16 levels of control with "0" having no effect on the
1594 * output image. 1 through 15 provides sharpness enhancement with "F" being the
1595 * strongest. The default is 1.
1596 */
1597 #define TW5864_INDIR_VIN_8_SHARPNESS 0x0f
1599 /*
1600 * These bits control the luminance contrast gain. A value of 100 (64h) has a
1601 * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The
1602 * default is 64h.
1603 */
1604 #define TW5864_INDIR_VIN_9_CNTRST(channel) (0x009 + channel * 0x010)
1606 /*
1607 * These bits control the brightness. They have value of –128 to 127 in 2's
1608 * complement form. Positive value increases brightness. A value 0 has no
1609 * effect on the data. The default is 00h.
1610 */
1611 #define TW5864_INDIR_VIN_A_BRIGHT(channel) (0x00a + channel * 0x010)
1613 /*
1614 * These bits control the digital gain adjustment to the U (or Cb) component of
1615 * the digital video signal. The color saturation can be adjusted by adjusting
1616 * the U and V color gain components by the same amount in the normal
1617 * situation. The U and V can also be adjusted independently to provide greater
1618 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1619 * gain of 100%. The default is 80h.
1620 */
1621 #define TW5864_INDIR_VIN_B_SAT_U(channel) (0x00b + channel * 0x010)
1623 /*
1624 * These bits control the digital gain adjustment to the V (or Cr) component of
1625 * the digital video signal. The color saturation can be adjusted by adjusting
1626 * the U and V color gain components by the same amount in the normal
1627 * situation. The U and V can also be adjusted independently to provide greater
1628 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1629 * gain of 100%. The default is 80h.
1630 */
1631 #define TW5864_INDIR_VIN_C_SAT_V(channel) (0x00c + channel * 0x010)
1633 /* Read-only */
1634 #define TW5864_INDIR_VIN_D(channel) (0x00d + channel * 0x010)
1635 /* Define controls in register TW5864_INDIR_VIN_D */
1636 /* Macrovision color stripe detection may be un-reliable */
1637 #define TW5864_INDIR_VIN_D_CSBAD BIT(3)
1638 /* Macrovision AGC pulse detected */
1639 #define TW5864_INDIR_VIN_D_MCVSN BIT(2)
1640 /* Macrovision color stripe protection burst detected */
1641 #define TW5864_INDIR_VIN_D_CSTRIPE BIT(1)
1642 /*
1643 * This bit is valid only when color stripe protection is detected, i.e. if
1644 * CSTRIPE=1,
1645 * 1 Type 2 color stripe protection
1646 * 0 Type 3 color stripe protection
1647 */
1648 #define TW5864_INDIR_VIN_D_CTYPE2 BIT(0)
1650 /* Read-only */
1651 #define TW5864_INDIR_VIN_E(channel) (0x00e + channel * 0x010)
1652 /* Define controls in register TW5864_INDIR_VIN_E */
1653 /*
1654 * Read-only.
1655 * 0 Idle
1656 * 1 Detection in progress
1657 */
1658 #define TW5864_INDIR_VIN_E_DETSTUS BIT(7)
1659 /*
1660 * STDNOW Current standard invoked
1661 * 0 NTSC (M)
1662 * 1 PAL (B, D, G, H, I)
1663 * 2 SECAM
1664 * 3 NTSC4.43
1665 * 4 PAL (M)
1666 * 5 PAL (CN)
1667 * 6 PAL 60
1668 * 7 Not valid
1669 */
1670 #define TW5864_INDIR_VIN_E_STDNOW_SHIFT 4
1671 #define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4)
1673 /*
1674 * 1 Disable the shadow registers
1675 * 0 Enable VACTIVE and HDELAY shadow registers value depending on STANDARD.
1676 * (Default)
1677 */
1678 #define TW5864_INDIR_VIN_E_ATREG BIT(3)
1679 /*
1680 * STANDARD Standard selection
1681 * 0 NTSC (M)
1682 * 1 PAL (B, D, G, H, I)
1683 * 2 SECAM
1684 * 3 NTSC4.43
1685 * 4 PAL (M)
1686 * 5 PAL (CN)
1687 * 6 PAL 60
1688 * 7 Auto detection (Default)
1689 */
1690 #define TW5864_INDIR_VIN_E_STANDARD 0x07
1692 #define TW5864_INDIR_VIN_F(channel) (0x00f + channel * 0x010)
1693 /* Define controls in register TW5864_INDIR_VIN_F */
1694 /*
1695 * 1 Writing 1 to this bit will manually initiate the auto format detection
1696 * process. This bit is a self-clearing bit
1697 * 0 Manual initiation of auto format detection is done. (Default)
1698 */
1699 #define TW5864_INDIR_VIN_F_ATSTART BIT(7)
1700 /* Enable recognition of PAL60 (Default) */
1701 #define TW5864_INDIR_VIN_F_PAL60EN BIT(6)
1702 /* Enable recognition of PAL (CN). (Default) */
1703 #define TW5864_INDIR_VIN_F_PALCNEN BIT(5)
1704 /* Enable recognition of PAL (M). (Default) */
1705 #define TW5864_INDIR_VIN_F_PALMEN BIT(4)
1706 /* Enable recognition of NTSC 4.43. (Default) */
1707 #define TW5864_INDIR_VIN_F_NTSC44EN BIT(3)
1708 /* Enable recognition of SECAM. (Default) */
1709 #define TW5864_INDIR_VIN_F_SECAMEN BIT(2)
1710 /* Enable recognition of PAL (B, D, G, H, I). (Default) */
1711 #define TW5864_INDIR_VIN_F_PALBEN BIT(1)
1712 /* Enable recognition of NTSC (M). (Default) */
1713 #define TW5864_INDIR_VIN_F_NTSCEN BIT(0)
1715 /* Some registers skipped. */
1717 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1718 #define TW5864_INDIR_VD_108_POL 0x041
1719 #define TW5864_INDIR_VD_108_POL_VD12 BIT(0)
1720 #define TW5864_INDIR_VD_108_POL_VD34 BIT(1)
1721 #define TW5864_INDIR_VD_108_POL_BOTH \
1722 (TW5864_INDIR_VD_108_POL_VD12 | TW5864_INDIR_VD_108_POL_VD34)
1724 /* Some registers skipped. */
1726 /*
1727 * Audio Input ADC gain control
1728 * 0 0.25
1729 * 1 0.31
1730 * 2 0.38
1731 * 3 0.44
1732 * 4 0.50
1733 * 5 0.63
1734 * 6 0.75
1735 * 7 0.88
1736 * 8 1.00 (default)
1737 * 9 1.25
1738 * 10 1.50
1739 * 11 1.75
1740 * 12 2.00
1741 * 13 2.25
1742 * 14 2.50
1743 * 15 2.75
1744 */
1745 /* [3:0] channel 0, [7:4] channel 1 */
1746 #define TW5864_INDIR_AIGAIN1 0x060
1747 /* [3:0] channel 2, [7:4] channel 3 */
1748 #define TW5864_INDIR_AIGAIN2 0x061
1750 /* Some registers skipped */
1752 #define TW5864_INDIR_AIN_0x06D 0x06d
1753 /* Define controls in register TW5864_INDIR_AIN_0x06D */
1754 /*
1755 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1756 * 0 PCM output (default)
1757 * 1 SB (Signed MSB bit in PCM data is inverted) output
1758 * 2 u-Law output
1759 * 3 A-Law output
1760 */
1761 #define TW5864_INDIR_AIN_LAWMD_SHIFT 6
1762 #define TW5864_INDIR_AIN_LAWMD (0x03 << 6)
1763 /*
1764 * Disable the mixing ratio value for all audio.
1765 * 0 Apply individual mixing ratio value for each audio (default)
1766 * 1 Apply nominal value for all audio commonly
1767 */
1768 #define TW5864_INDIR_AIN_MIX_DERATIO BIT(5)
1769 /*
1770 * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1771 * only for mixing. When n = 4, it enable the mute function of the playback
1772 * audio input. It effects only for single chip or the last stage chip
1773 * 0 Normal
1774 * 1 Muted (default)
1775 */
1776 #define TW5864_INDIR_AIN_MIX_MUTE 0x1f
1778 /* Some registers skipped */
1780 #define TW5864_INDIR_AIN_0x0E3 0x0e3
1781 /* Define controls in register TW5864_INDIR_AIN_0x0E3 */
1782 /*
1783 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1784 * decoder
1785 */
1786 #define TW5864_INDIR_AIN_0x0E3_EXT_ADATP BIT(7)
1787 /* ACLKP output signal polarity inverse */
1788 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLO BIT(6)
1789 /*
1790 * ACLKR input signal polarity inverse.
1791 * 0 Not inversed (Default)
1792 * 1 Inversed
1793 */
1794 #define TW5864_INDIR_AIN_0x0E3_ACLKRPOL BIT(5)
1795 /*
1796 * ACLKP input signal polarity inverse.
1797 * 0 Not inversed (Default)
1798 * 1 Inversed
1799 */
1800 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4)
1801 /*
1802 * ACKI [21:0] control automatic set up with AFMD registers
1803 * This mode is only effective when ACLKRMASTER=1
1804 * 0 ACKI [21:0] registers set up ACKI control
1805 * 1 ACKI control is automatically set up by AFMD register values
1806 */
1807 #define TW5864_INDIR_AIN_0x0E3_AFAUTO BIT(3)
1808 /*
1809 * AFAUTO control mode
1810 * 0 8kHz setting (Default)
1811 * 1 16kHz setting
1812 * 2 32kHz setting
1813 * 3 44.1kHz setting
1814 * 4 48kHz setting
1815 */
1816 #define TW5864_INDIR_AIN_0x0E3_AFMD 0x07
1818 #define TW5864_INDIR_AIN_0x0E4 0x0e4
1819 /* Define controls in register TW5864_INDIR_AIN_0x0ED */
1820 /*
1821 * 8bit I2S Record output mode.
1822 * 0 L/R half length separated output (Default).
1823 * 1 One continuous packed output equal to DSP output format.
1824 */
1825 #define TW5864_INDIR_AIN_0x0E4_I2S8MODE BIT(7)
1826 /*
1827 * Audio Clock Master ACLKR output wave format.
1828 * 0 High periods is one 27MHz clock period (default).
1829 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1830 * times bigger number value need to be set up on the ACKI register. If
1831 * AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1.
1832 */
1833 #define TW5864_INDIR_AIN_0x0E4_MASCKMD BIT(6)
1834 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1835 #define TW5864_INDIR_AIN_0x0E4_PBINSWAP BIT(5)
1836 /*
1837 * ASYNR input signal delay.
1838 * 0 No delay
1839 * 1 Add one 27MHz period delay in ASYNR signal input
1840 */
1841 #define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4)
1842 /*
1843 * ASYNP input signal delay.
1844 * 0 no delay
1845 * 1 add one 27MHz period delay in ASYNP signal input
1846 */
1847 #define TW5864_INDIR_AIN_0x0E4_ASYNPDLY BIT(3)
1848 /*
1849 * ADATP input data delay by one ACLKP clock.
1850 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1851 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1852 * type 0T delay input interface.
1853 */
1854 #define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2)
1855 /*
1856 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1857 * 0 PCM input (Default)
1858 * 1 SB (Signed MSB bit in PCM data is inverted) input
1859 * 2 u-Law input
1860 * 3 A-Law input
1861 */
1862 #define TW5864_INDIR_AIN_0x0E4_INLAWMD 0x03
1864 /*
1865 * Enable state register updating and interrupt request of audio AIN5 detection
1866 * for each input
1867 */
1868 #define TW5864_INDIR_AIN_A5DETENA 0x0e5
1870 /* Some registers skipped */
1872 /*
1873 * [7:3]: DEV_ID The TW5864 product ID code is 01000
1874 * [2:0]: REV_ID The revision number is 0h
1875 */
1876 #define TW5864_INDIR_ID 0x0fe
1878 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)
1879 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)
1880 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)
1881 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)
1883 /* Some registers skipped */
1885 #define TW5864_INDIR_CROP_ETC 0x260
1886 /* Define controls in register TW5864_INDIR_CROP_ETC */
1887 /* Enable cropping from 720 to 704 */
1888 #define TW5864_INDIR_CROP_ETC_CROP_EN 0x4
1890 /*
1891 * Interrupt status register from the front-end. Write "1" to each bit to clear
1892 * the interrupt
1893 * 15:0 Motion detection interrupt for channel 0 ~ 15
1894 * 31:16 Night detection interrupt for channel 0 ~ 15
1895 * 47:32 Blind detection interrupt for channel 0 ~ 15
1896 * 63:48 No video interrupt for channel 0 ~ 15
1897 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1898 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1899 */
1900 /* 0x2d0~0x2d7: [63:0] bits */
1901 #define TW5864_INDIR_INTERRUPT1 0x2d0
1902 /* 0x2e0~0x2e3: [95:64] bits */
1903 #define TW5864_INDIR_INTERRUPT2 0x2e0
1905 /*
1906 * Interrupt mask register for interrupts in 0x2d0 ~ 0x2d7
1907 * 15:0 Motion detection interrupt for channel 0 ~ 15
1908 * 31:16 Night detection interrupt for channel 0 ~ 15
1909 * 47:32 Blind detection interrupt for channel 0 ~ 15
1910 * 63:48 No video interrupt for channel 0 ~ 15
1911 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1912 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1913 */
1914 /* 0x2d8~0x2df: [63:0] bits */
1915 #define TW5864_INDIR_INTERRUPT_MASK1 0x2d8
1916 /* 0x2e8~0x2eb: [95:64] bits */
1917 #define TW5864_INDIR_INTERRUPT_MASK2 0x2e8
1919 /* [11:0]: Interrupt summary register for interrupts & interrupt mask from in
1920 * 0x2d0 ~ 0x2d7 and 0x2d8 ~ 0x2df
1921 * bit 0: interrupt occurs in 0x2d0 & 0x2d8
1922 * bit 1: interrupt occurs in 0x2d1 & 0x2d9
1923 * bit 2: interrupt occurs in 0x2d2 & 0x2da
1924 * bit 3: interrupt occurs in 0x2d3 & 0x2db
1925 * bit 4: interrupt occurs in 0x2d4 & 0x2dc
1926 * bit 5: interrupt occurs in 0x2d5 & 0x2dd
1927 * bit 6: interrupt occurs in 0x2d6 & 0x2de
1928 * bit 7: interrupt occurs in 0x2d7 & 0x2df
1929 * bit 8: interrupt occurs in 0x2e0 & 0x2e8
1930 * bit 9: interrupt occurs in 0x2e1 & 0x2e9
1931 * bit 10: interrupt occurs in 0x2e2 & 0x2ea
1932 * bit 11: interrupt occurs in 0x2e3 & 0x2eb
1933 */
1934 #define TW5864_INDIR_INTERRUPT_SUMMARY 0x2f0
1936 /* Motion / Blind / Night Detection */
1937 /* valid value for channel is [0:15] */
1938 #define TW5864_INDIR_DETECTION_CTL0(channel) (0x300 + channel * 0x08)
1939 /* Define controls in register TW5864_INDIR_DETECTION_CTL0 */
1940 /*
1941 * Disable the motion and blind detection.
1942 * 0 Enable motion and blind detection (default)
1943 * 1 Disable motion and blind detection
1944 */
1945 #define TW5864_INDIR_DETECTION_CTL0_MD_DIS BIT(5)
1946 /*
1947 * Request to start motion detection on manual trigger mode
1948 * 0 None Operation (default)
1949 * 1 Request to start motion detection
1950 */
1951 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB BIT(3)
1952 /*
1953 * Select the trigger mode of motion detection
1954 * 0 Automatic trigger mode of motion detection (default)
1955 * 1 Manual trigger mode for motion detection
1956 */
1957 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2)
1958 /*
1959 * Define the threshold of cell for blind detection.
1960 * 0 Low threshold (More sensitive) (default)
1961 * : :
1962 * 3 High threshold (Less sensitive)
1963 */
1964 #define TW5864_INDIR_DETECTION_CTL0_BD_CELSENS 0x03
1966 #define TW5864_INDIR_DETECTION_CTL1(channel) (0x301 + channel * 0x08)
1967 /* Define controls in register TW5864_INDIR_DETECTION_CTL1 */
1968 /*
1969 * Control the temporal sensitivity of motion detector.
1970 * 0 More Sensitive (default)
1971 * : :
1972 * 15 Less Sensitive
1973 */
1974 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT 4
1975 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4)
1976 /*
1977 * Adjust the horizontal starting position for motion detection
1978 * 0 0 pixel (default)
1979 * : :
1980 * 15 15 pixels
1981 */
1982 #define TW5864_INDIR_DETECTION_CTL1_MD_PIXEL_OS 0x0f
1984 #define TW5864_INDIR_DETECTION_CTL2(channel) (0x302 + channel * 0x08)
1985 /* Define controls in register TW5864_INDIR_DETECTION_CTL2 */
1986 /*
1987 * Control the updating time of reference field for motion detection.
1988 * 0 Update reference field every field (default)
1989 * 1 Update reference field according to MD_SPEED
1990 */
1991 #define TW5864_INDIR_DETECTION_CTL2_MD_REFFLD BIT(7)
1992 /*
1993 * Select the field for motion detection.
1994 * 0 Detecting motion for only odd field (default)
1995 * 1 Detecting motion for only even field
1996 * 2 Detecting motion for any field
1997 * 3 Detecting motion for both odd and even field
1998 */
1999 #define TW5864_INDIR_DETECTION_CTL2_MD_FIELD_SHIFT 5
2000 #define TW5864_INDIR_DETECTION_CTL2_MD_FIELD (0x03 << 5)
2001 /*
2002 * Control the level sensitivity of motion detector.
2003 * 0 More sensitive (default)
2004 * : :
2005 * 15 Less sensitive
2006 */
2007 #define TW5864_INDIR_DETECTION_CTL2_MD_LVSENS 0x1f
2009 #define TW5864_INDIR_DETECTION_CTL3(channel) (0x303 + channel * 0x08)
2010 /* Define controls in register TW5864_INDIR_DETECTION_CTL3 */
2011 /*
2012 * Define the threshold of sub-cell number for motion detection.
2013 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2014 * 1 Motion is detected if 2 sub-cells have motion
2015 * 2 Motion is detected if 3 sub-cells have motion
2016 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2017 */
2018 #define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS_SHIFT 6
2019 #define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS (0x03 << 6)
2020 /*
2021 * Control the velocity of motion detector.
2022 * Large value is suitable for slow motion detection.
2023 * In MD_DUAL_EN = 1, MD_SPEED should be limited to 0 ~ 31.
2024 * 0 1 field intervals (default)
2025 * 1 2 field intervals
2026 * : :
2027 * 61 62 field intervals
2028 * 62 63 field intervals
2029 * 63 Not supported
2030 */
2031 #define TW5864_INDIR_DETECTION_CTL3_MD_SPEED 0x3f
2033 #define TW5864_INDIR_DETECTION_CTL4(channel) (0x304 + channel * 0x08)
2034 /* Define controls in register TW5864_INDIR_DETECTION_CTL4 */
2035 /*
2036 * Control the spatial sensitivity of motion detector.
2037 * 0 More Sensitive (default)
2038 * : :
2039 * 15 Less Sensitive
2040 */
2041 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT 4
2042 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4)
2043 /*
2044 * Define the threshold of level for blind detection.
2045 * 0 Low threshold (More sensitive) (default)
2046 * : :
2047 * 15 High threshold (Less sensitive)
2048 */
2049 #define TW5864_INDIR_DETECTION_CTL4_BD_LVSENS 0x0f
2051 #define TW5864_INDIR_DETECTION_CTL5(channel) (0x305 + channel * 0x08)
2052 /*
2053 * Define the threshold of temporal sensitivity for night detection.
2054 * 0 Low threshold (More sensitive) (default)
2055 * : :
2056 * 15 High threshold (Less sensitive)
2057 */
2058 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT 4
2059 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4)
2060 /*
2061 * Define the threshold of level for night detection.
2062 * 0 Low threshold (More sensitive) (default)
2063 * : :
2064 * 3 High threshold (Less sensitive)
2065 */
2066 #define TW5864_INDIR_DETECTION_CTL5_ND_LVSENS 0x0f
2068 /*
2069 * [11:0] The base address of the motion detection buffer. This address is in
2070 * unit of 64K bytes. The generated DDR address will be {MD_BASE_ADDR,
2071 * 16"h0000}. The default value should be 12"h000
2072 */
2073 #define TW5864_INDIR_MD_BASE_ADDR 0x380
2075 /*
2076 * This controls the channel of the motion detection result shown in register
2077 * 0x3a0 ~ 0x3b7. Before reading back motion result, always set this first.
2078 */
2079 #define TW5864_INDIR_RGR_MOTION_SEL 0x382
2081 /* [15:0] MD strobe has been performed at channel n (read only) */
2082 #define TW5864_INDIR_MD_STRB 0x386
2083 /* NO_VIDEO Detected from channel n (read only) */
2084 #define TW5864_INDIR_NOVID_DET 0x388
2085 /* Motion Detected from channel n (read only) */
2086 #define TW5864_INDIR_MD_DET 0x38a
2087 /* Blind Detected from channel n (read only) */
2088 #define TW5864_INDIR_BD_DET 0x38c
2089 /* Night Detected from channel n (read only) */
2090 #define TW5864_INDIR_ND_DET 0x38e
2092 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2093 #define TW5864_INDIR_MOTION_FLAG 0x3a0
2094 #define TW5864_INDIR_MOTION_FLAG_BYTE_COUNT 24
2096 /*
2097 * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2098 * for DI purpose
2099 */
2100 #define TW5864_INDIR_MD_DI_CNT 0x3b8
2101 /* The motion detection cell sensitivity for DI purpose */
2102 #define TW5864_INDIR_MD_DI_CELLSENS 0x3ba
2103 /* The motion detection threshold level for DI purpose */
2104 #define TW5864_INDIR_MD_DI_LVSENS 0x3bb
2106 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2107 #define TW5864_INDIR_MOTION_MASK 0x3e0
2108 #define TW5864_INDIR_MOTION_MASK_BYTE_COUNT 24
2110 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2111 #define TW5864_INDIR_MASK_CH_SEL 0x3fe
2113 /* Clock PLL / Analog IP Control */
2114 /* Some registers skipped */
2116 #define TW5864_INDIR_DDRA_DLL_DQS_SEL0 0xee6
2117 #define TW5864_INDIR_DDRA_DLL_DQS_SEL1 0xee7
2118 #define TW5864_INDIR_DDRA_DLL_CLK90_SEL 0xee8
2119 #define TW5864_INDIR_DDRA_DLL_TEST_SEL_AND_TAP_S 0xee9
2121 #define TW5864_INDIR_DDRB_DLL_DQS_SEL0 0xeeb
2122 #define TW5864_INDIR_DDRB_DLL_DQS_SEL1 0xeec
2123 #define TW5864_INDIR_DDRB_DLL_CLK90_SEL 0xeed
2124 #define TW5864_INDIR_DDRB_DLL_TEST_SEL_AND_TAP_S 0xeee
2126 #define TW5864_INDIR_RESET 0xef0
2127 #define TW5864_INDIR_RESET_VD BIT(7)
2128 #define TW5864_INDIR_RESET_DLL BIT(6)
2129 #define TW5864_INDIR_RESET_MUX_CORE BIT(5)
2131 #define TW5864_INDIR_PV_VD_CK_POL 0xefd
2132 #define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel)
2133 #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4)
2135 #define TW5864_INDIR_CLK0_SEL 0xefe
2136 #define TW5864_INDIR_CLK0_SEL_VD_SHIFT 0
2137 #define TW5864_INDIR_CLK0_SEL_VD_MASK 0x3
2138 #define TW5864_INDIR_CLK0_SEL_PV_SHIFT 2
2139 #define TW5864_INDIR_CLK0_SEL_PV_MASK (0x3 << 2)
2140 #define TW5864_INDIR_CLK0_SEL_PV2_SHIFT 4
2141 #define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4)