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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blobbb0a5887c9a9c3685ad6fabb03afb653086d6d82
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_reserved_mem.h>
26 #include <media/videobuf2-v4l2.h>
27 #include "s5p_mfc_common.h"
28 #include "s5p_mfc_ctrl.h"
29 #include "s5p_mfc_debug.h"
30 #include "s5p_mfc_dec.h"
31 #include "s5p_mfc_enc.h"
32 #include "s5p_mfc_intr.h"
33 #include "s5p_mfc_iommu.h"
34 #include "s5p_mfc_opr.h"
35 #include "s5p_mfc_cmd.h"
36 #include "s5p_mfc_pm.h"
37
38 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
39 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40
41 int mfc_debug_level;
42 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44
45 /* Helper functions for interrupt processing */
46
47 /* Remove from hw execution round robin */
48 void clear_work_bit(struct s5p_mfc_ctx *ctx)
49 {
50 struct s5p_mfc_dev *dev = ctx->dev;
51
52 spin_lock(&dev->condlock);
53 __clear_bit(ctx->num, &dev->ctx_work_bits);
54 spin_unlock(&dev->condlock);
55 }
56
57 /* Add to hw execution round robin */
58 void set_work_bit(struct s5p_mfc_ctx *ctx)
59 {
60 struct s5p_mfc_dev *dev = ctx->dev;
61
62 spin_lock(&dev->condlock);
63 __set_bit(ctx->num, &dev->ctx_work_bits);
64 spin_unlock(&dev->condlock);
65 }
66
67 /* Remove from hw execution round robin */
68 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
69 {
70 struct s5p_mfc_dev *dev = ctx->dev;
71 unsigned long flags;
72
73 spin_lock_irqsave(&dev->condlock, flags);
74 __clear_bit(ctx->num, &dev->ctx_work_bits);
75 spin_unlock_irqrestore(&dev->condlock, flags);
76 }
77
78 /* Add to hw execution round robin */
79 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
80 {
81 struct s5p_mfc_dev *dev = ctx->dev;
82 unsigned long flags;
83
84 spin_lock_irqsave(&dev->condlock, flags);
85 __set_bit(ctx->num, &dev->ctx_work_bits);
86 spin_unlock_irqrestore(&dev->condlock, flags);
87 }
88
89 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
90 {
91 unsigned long flags;
92 int ctx;
93
94 spin_lock_irqsave(&dev->condlock, flags);
95 ctx = dev->curr_ctx;
96 do {
97 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
98 if (ctx == dev->curr_ctx) {
99 if (!test_bit(ctx, &dev->ctx_work_bits))
100 ctx = -EAGAIN;
101 break;
102 }
103 } while (!test_bit(ctx, &dev->ctx_work_bits));
104 spin_unlock_irqrestore(&dev->condlock, flags);
105
106 return ctx;
107 }
108
109 /* Wake up context wait_queue */
110 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
111 unsigned int err)
112 {
113 ctx->int_cond = 1;
114 ctx->int_type = reason;
115 ctx->int_err = err;
116 wake_up(&ctx->queue);
117 }
118
119 /* Wake up device wait_queue */
120 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
121 unsigned int err)
122 {
123 dev->int_cond = 1;
124 dev->int_type = reason;
125 dev->int_err = err;
126 wake_up(&dev->queue);
127 }
128
129 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
130 {
131 struct s5p_mfc_buf *b;
132 int i;
133
134 while (!list_empty(lh)) {
135 b = list_entry(lh->next, struct s5p_mfc_buf, list);
136 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
137 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
138 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
139 list_del(&b->list);
140 }
141 }
142
143 static void s5p_mfc_watchdog(unsigned long arg)
144 {
145 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
146
147 if (test_bit(0, &dev->hw_lock))
148 atomic_inc(&dev->watchdog_cnt);
149 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
150 /* This means that hw is busy and no interrupts were
151 * generated by hw for the Nth time of running this
152 * watchdog timer. This usually means a serious hw
153 * error. Now it is time to kill all instances and
154 * reset the MFC. */
155 mfc_err("Time out during waiting for HW\n");
156 schedule_work(&dev->watchdog_work);
157 }
158 dev->watchdog_timer.expires = jiffies +
159 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
160 add_timer(&dev->watchdog_timer);
161 }
162
163 static void s5p_mfc_watchdog_worker(struct work_struct *work)
164 {
165 struct s5p_mfc_dev *dev;
166 struct s5p_mfc_ctx *ctx;
167 unsigned long flags;
168 int mutex_locked;
169 int i, ret;
170
171 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
172
173 mfc_err("Driver timeout error handling\n");
174 /* Lock the mutex that protects open and release.
175 * This is necessary as they may load and unload firmware. */
176 mutex_locked = mutex_trylock(&dev->mfc_mutex);
177 if (!mutex_locked)
178 mfc_err("Error: some instance may be closing/opening\n");
179 spin_lock_irqsave(&dev->irqlock, flags);
180
181 s5p_mfc_clock_off();
182
183 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
184 ctx = dev->ctx[i];
185 if (!ctx)
186 continue;
187 ctx->state = MFCINST_ERROR;
188 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
189 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
190 clear_work_bit(ctx);
191 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
192 }
193 clear_bit(0, &dev->hw_lock);
194 spin_unlock_irqrestore(&dev->irqlock, flags);
195
196 /* De-init MFC */
197 s5p_mfc_deinit_hw(dev);
198
199 /* Double check if there is at least one instance running.
200 * If no instance is in memory than no firmware should be present */
201 if (dev->num_inst > 0) {
202 ret = s5p_mfc_load_firmware(dev);
203 if (ret) {
204 mfc_err("Failed to reload FW\n");
205 goto unlock;
206 }
207 s5p_mfc_clock_on();
208 ret = s5p_mfc_init_hw(dev);
209 if (ret)
210 mfc_err("Failed to reinit FW\n");
211 }
212 unlock:
213 if (mutex_locked)
214 mutex_unlock(&dev->mfc_mutex);
215 }
216
217 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
218 {
219 struct s5p_mfc_buf *dst_buf;
220 struct s5p_mfc_dev *dev = ctx->dev;
221
222 ctx->state = MFCINST_FINISHED;
223 ctx->sequence++;
224 while (!list_empty(&ctx->dst_queue)) {
225 dst_buf = list_entry(ctx->dst_queue.next,
226 struct s5p_mfc_buf, list);
227 mfc_debug(2, "Cleaning up buffer: %d\n",
228 dst_buf->b->vb2_buf.index);
229 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
230 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
231 list_del(&dst_buf->list);
232 dst_buf->flags |= MFC_BUF_FLAG_EOS;
233 ctx->dst_queue_cnt--;
234 dst_buf->b->sequence = (ctx->sequence++);
235
236 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
237 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
238 dst_buf->b->field = V4L2_FIELD_NONE;
239 else
240 dst_buf->b->field = V4L2_FIELD_INTERLACED;
241 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
242
243 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
244 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
245 }
246 }
247
248 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
249 {
250 struct s5p_mfc_dev *dev = ctx->dev;
251 struct s5p_mfc_buf *dst_buf, *src_buf;
252 size_t dec_y_addr;
253 unsigned int frame_type;
254
255 /* Make sure we actually have a new frame before continuing. */
256 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
257 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
258 return;
259 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
260
261 /* Copy timestamp / timecode from decoded src to dst and set
262 appropriate flags. */
263 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
264 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
265 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
266 == dec_y_addr) {
267 dst_buf->b->timecode =
268 src_buf->b->timecode;
269 dst_buf->b->vb2_buf.timestamp =
270 src_buf->b->vb2_buf.timestamp;
271 dst_buf->b->flags &=
272 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
273 dst_buf->b->flags |=
274 src_buf->b->flags
275 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
276 switch (frame_type) {
277 case S5P_FIMV_DECODE_FRAME_I_FRAME:
278 dst_buf->b->flags |=
279 V4L2_BUF_FLAG_KEYFRAME;
280 break;
281 case S5P_FIMV_DECODE_FRAME_P_FRAME:
282 dst_buf->b->flags |=
283 V4L2_BUF_FLAG_PFRAME;
284 break;
285 case S5P_FIMV_DECODE_FRAME_B_FRAME:
286 dst_buf->b->flags |=
287 V4L2_BUF_FLAG_BFRAME;
288 break;
289 default:
290 /* Don't know how to handle
291 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
292 mfc_debug(2, "Unexpected frame type: %d\n",
293 frame_type);
294 }
295 break;
296 }
297 }
298 }
299
300 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
301 {
302 struct s5p_mfc_dev *dev = ctx->dev;
303 struct s5p_mfc_buf *dst_buf;
304 size_t dspl_y_addr;
305 unsigned int frame_type;
306
307 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
308 if (IS_MFCV6_PLUS(dev))
309 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
310 get_disp_frame_type, ctx);
311 else
312 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
313 get_dec_frame_type, dev);
314
315 /* If frame is same as previous then skip and do not dequeue */
316 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
317 if (!ctx->after_packed_pb)
318 ctx->sequence++;
319 ctx->after_packed_pb = 0;
320 return;
321 }
322 ctx->sequence++;
323 /* The MFC returns address of the buffer, now we have to
324 * check which videobuf does it correspond to */
325 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
326 /* Check if this is the buffer we're looking for */
327 if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0)
328 == dspl_y_addr) {
329 list_del(&dst_buf->list);
330 ctx->dst_queue_cnt--;
331 dst_buf->b->sequence = ctx->sequence;
332 if (s5p_mfc_hw_call(dev->mfc_ops,
333 get_pic_type_top, ctx) ==
334 s5p_mfc_hw_call(dev->mfc_ops,
335 get_pic_type_bot, ctx))
336 dst_buf->b->field = V4L2_FIELD_NONE;
337 else
338 dst_buf->b->field =
339 V4L2_FIELD_INTERLACED;
340 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
341 ctx->luma_size);
342 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
343 ctx->chroma_size);
344 clear_bit(dst_buf->b->vb2_buf.index,
345 &ctx->dec_dst_flag);
346
347 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
348 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
349
350 break;
351 }
352 }
353 }
354
355 /* Handle frame decoding interrupt */
356 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
357 unsigned int reason, unsigned int err)
358 {
359 struct s5p_mfc_dev *dev = ctx->dev;
360 unsigned int dst_frame_status;
361 unsigned int dec_frame_status;
362 struct s5p_mfc_buf *src_buf;
363 unsigned int res_change;
364
365 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
366 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
367 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
368 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
369 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
370 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
371 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
372 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
373 if (ctx->state == MFCINST_RES_CHANGE_INIT)
374 ctx->state = MFCINST_RES_CHANGE_FLUSH;
375 if (res_change == S5P_FIMV_RES_INCREASE ||
376 res_change == S5P_FIMV_RES_DECREASE) {
377 ctx->state = MFCINST_RES_CHANGE_INIT;
378 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
379 wake_up_ctx(ctx, reason, err);
380 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
381 s5p_mfc_clock_off();
382 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
383 return;
384 }
385 if (ctx->dpb_flush_flag)
386 ctx->dpb_flush_flag = 0;
387
388 /* All frames remaining in the buffer have been extracted */
389 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
390 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
391 static const struct v4l2_event ev_src_ch = {
392 .type = V4L2_EVENT_SOURCE_CHANGE,
393 .u.src_change.changes =
394 V4L2_EVENT_SRC_CH_RESOLUTION,
395 };
396
397 s5p_mfc_handle_frame_all_extracted(ctx);
398 ctx->state = MFCINST_RES_CHANGE_END;
399 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
400
401 goto leave_handle_frame;
402 } else {
403 s5p_mfc_handle_frame_all_extracted(ctx);
404 }
405 }
406
407 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
408 s5p_mfc_handle_frame_copy_time(ctx);
409
410 /* A frame has been decoded and is in the buffer */
411 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
412 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
413 s5p_mfc_handle_frame_new(ctx, err);
414 } else {
415 mfc_debug(2, "No frame decode\n");
416 }
417 /* Mark source buffer as complete */
418 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
419 && !list_empty(&ctx->src_queue)) {
420 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
421 list);
422 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
423 get_consumed_stream, dev);
424 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
425 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
426 ctx->consumed_stream + STUFF_BYTE <
427 src_buf->b->vb2_buf.planes[0].bytesused) {
428 /* Run MFC again on the same buffer */
429 mfc_debug(2, "Running again the same buffer\n");
430 ctx->after_packed_pb = 1;
431 } else {
432 mfc_debug(2, "MFC needs next buffer\n");
433 ctx->consumed_stream = 0;
434 if (src_buf->flags & MFC_BUF_FLAG_EOS)
435 ctx->state = MFCINST_FINISHING;
436 list_del(&src_buf->list);
437 ctx->src_queue_cnt--;
438 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
439 vb2_buffer_done(&src_buf->b->vb2_buf,
440 VB2_BUF_STATE_ERROR);
441 else
442 vb2_buffer_done(&src_buf->b->vb2_buf,
443 VB2_BUF_STATE_DONE);
444 }
445 }
446 leave_handle_frame:
447 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
448 || ctx->dst_queue_cnt < ctx->pb_count)
449 clear_work_bit(ctx);
450 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
451 wake_up_ctx(ctx, reason, err);
452 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
453 s5p_mfc_clock_off();
454 /* if suspending, wake up device and do not try_run again*/
455 if (test_bit(0, &dev->enter_suspend))
456 wake_up_dev(dev, reason, err);
457 else
458 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
459 }
460
461 /* Error handling for interrupt */
462 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
463 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
464 {
465 mfc_err("Interrupt Error: %08x\n", err);
466
467 if (ctx != NULL) {
468 /* Error recovery is dependent on the state of context */
469 switch (ctx->state) {
470 case MFCINST_RES_CHANGE_INIT:
471 case MFCINST_RES_CHANGE_FLUSH:
472 case MFCINST_RES_CHANGE_END:
473 case MFCINST_FINISHING:
474 case MFCINST_FINISHED:
475 case MFCINST_RUNNING:
476 /* It is highly probable that an error occurred
477 * while decoding a frame */
478 clear_work_bit(ctx);
479 ctx->state = MFCINST_ERROR;
480 /* Mark all dst buffers as having an error */
481 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
482 /* Mark all src buffers as having an error */
483 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
484 wake_up_ctx(ctx, reason, err);
485 break;
486 default:
487 clear_work_bit(ctx);
488 ctx->state = MFCINST_ERROR;
489 wake_up_ctx(ctx, reason, err);
490 break;
491 }
492 }
493 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
494 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
495 s5p_mfc_clock_off();
496 wake_up_dev(dev, reason, err);
497 }
498
499 /* Header parsing interrupt handling */
500 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
501 unsigned int reason, unsigned int err)
502 {
503 struct s5p_mfc_dev *dev;
504
505 if (ctx == NULL)
506 return;
507 dev = ctx->dev;
508 if (ctx->c_ops->post_seq_start) {
509 if (ctx->c_ops->post_seq_start(ctx))
510 mfc_err("post_seq_start() failed\n");
511 } else {
512 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
513 dev);
514 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
515 dev);
516
517 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
518
519 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
520 dev);
521 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
522 dev);
523 if (ctx->img_width == 0 || ctx->img_height == 0)
524 ctx->state = MFCINST_ERROR;
525 else
526 ctx->state = MFCINST_HEAD_PARSED;
527
528 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
529 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
530 !list_empty(&ctx->src_queue)) {
531 struct s5p_mfc_buf *src_buf;
532 src_buf = list_entry(ctx->src_queue.next,
533 struct s5p_mfc_buf, list);
534 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
535 dev) <
536 src_buf->b->vb2_buf.planes[0].bytesused)
537 ctx->head_processed = 0;
538 else
539 ctx->head_processed = 1;
540 } else {
541 ctx->head_processed = 1;
542 }
543 }
544 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
545 clear_work_bit(ctx);
546 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
547 s5p_mfc_clock_off();
548 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
549 wake_up_ctx(ctx, reason, err);
550 }
551
552 /* Header parsing interrupt handling */
553 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
554 unsigned int reason, unsigned int err)
555 {
556 struct s5p_mfc_buf *src_buf;
557 struct s5p_mfc_dev *dev;
558
559 if (ctx == NULL)
560 return;
561 dev = ctx->dev;
562 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
563 ctx->int_type = reason;
564 ctx->int_err = err;
565 ctx->int_cond = 1;
566 clear_work_bit(ctx);
567 if (err == 0) {
568 ctx->state = MFCINST_RUNNING;
569 if (!ctx->dpb_flush_flag && ctx->head_processed) {
570 if (!list_empty(&ctx->src_queue)) {
571 src_buf = list_entry(ctx->src_queue.next,
572 struct s5p_mfc_buf, list);
573 list_del(&src_buf->list);
574 ctx->src_queue_cnt--;
575 vb2_buffer_done(&src_buf->b->vb2_buf,
576 VB2_BUF_STATE_DONE);
577 }
578 } else {
579 ctx->dpb_flush_flag = 0;
580 }
581 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
582
583 s5p_mfc_clock_off();
584
585 wake_up(&ctx->queue);
586 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
587 } else {
588 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
589
590 s5p_mfc_clock_off();
591
592 wake_up(&ctx->queue);
593 }
594 }
595
596 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
597 {
598 struct s5p_mfc_dev *dev = ctx->dev;
599 struct s5p_mfc_buf *mb_entry;
600
601 mfc_debug(2, "Stream completed\n");
602
603 ctx->state = MFCINST_FINISHED;
604
605 if (!list_empty(&ctx->dst_queue)) {
606 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
607 list);
608 list_del(&mb_entry->list);
609 ctx->dst_queue_cnt--;
610 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
611 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
612 }
613
614 clear_work_bit(ctx);
615
616 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
617
618 s5p_mfc_clock_off();
619 wake_up(&ctx->queue);
620 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
621 }
622
623 /* Interrupt processing */
624 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
625 {
626 struct s5p_mfc_dev *dev = priv;
627 struct s5p_mfc_ctx *ctx;
628 unsigned int reason;
629 unsigned int err;
630
631 mfc_debug_enter();
632 /* Reset the timeout watchdog */
633 atomic_set(&dev->watchdog_cnt, 0);
634 spin_lock(&dev->irqlock);
635 ctx = dev->ctx[dev->curr_ctx];
636 /* Get the reason of interrupt and the error code */
637 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
638 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
639 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
640 switch (reason) {
641 case S5P_MFC_R2H_CMD_ERR_RET:
642 /* An error has occurred */
643 if (ctx->state == MFCINST_RUNNING &&
644 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
645 dev->warn_start ||
646 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
647 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
648 err == S5P_FIMV_ERR_TIMEOUT))
649 s5p_mfc_handle_frame(ctx, reason, err);
650 else
651 s5p_mfc_handle_error(dev, ctx, reason, err);
652 clear_bit(0, &dev->enter_suspend);
653 break;
654
655 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
656 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
657 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
658 if (ctx->c_ops->post_frame_start) {
659 if (ctx->c_ops->post_frame_start(ctx))
660 mfc_err("post_frame_start() failed\n");
661
662 if (ctx->state == MFCINST_FINISHING &&
663 list_empty(&ctx->ref_queue)) {
664 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
665 s5p_mfc_handle_stream_complete(ctx);
666 break;
667 }
668 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
669 wake_up_ctx(ctx, reason, err);
670 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
671 s5p_mfc_clock_off();
672 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
673 } else {
674 s5p_mfc_handle_frame(ctx, reason, err);
675 }
676 break;
677
678 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
679 s5p_mfc_handle_seq_done(ctx, reason, err);
680 break;
681
682 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
683 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
684 ctx->state = MFCINST_GOT_INST;
685 clear_work_bit(ctx);
686 wake_up(&ctx->queue);
687 goto irq_cleanup_hw;
688
689 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
690 clear_work_bit(ctx);
691 ctx->inst_no = MFC_NO_INSTANCE_SET;
692 ctx->state = MFCINST_FREE;
693 wake_up(&ctx->queue);
694 goto irq_cleanup_hw;
695
696 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
697 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
698 case S5P_MFC_R2H_CMD_SLEEP_RET:
699 case S5P_MFC_R2H_CMD_WAKEUP_RET:
700 if (ctx)
701 clear_work_bit(ctx);
702 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
703 wake_up_dev(dev, reason, err);
704 clear_bit(0, &dev->hw_lock);
705 clear_bit(0, &dev->enter_suspend);
706 break;
707
708 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
709 s5p_mfc_handle_init_buffers(ctx, reason, err);
710 break;
711
712 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
713 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
714 ctx->int_type = reason;
715 ctx->int_err = err;
716 s5p_mfc_handle_stream_complete(ctx);
717 break;
718
719 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
720 clear_work_bit(ctx);
721 ctx->state = MFCINST_RUNNING;
722 wake_up(&ctx->queue);
723 goto irq_cleanup_hw;
724
725 default:
726 mfc_debug(2, "Unknown int reason\n");
727 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
728 }
729 spin_unlock(&dev->irqlock);
730 mfc_debug_leave();
731 return IRQ_HANDLED;
732 irq_cleanup_hw:
733 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
734 ctx->int_type = reason;
735 ctx->int_err = err;
736 ctx->int_cond = 1;
737 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
738 mfc_err("Failed to unlock hw\n");
739
740 s5p_mfc_clock_off();
741
742 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
743 spin_unlock(&dev->irqlock);
744 mfc_debug(2, "Exit via irq_cleanup_hw\n");
745 return IRQ_HANDLED;
746 }
747
748 /* Open an MFC node */
749 static int s5p_mfc_open(struct file *file)
750 {
751 struct video_device *vdev = video_devdata(file);
752 struct s5p_mfc_dev *dev = video_drvdata(file);
753 struct s5p_mfc_ctx *ctx = NULL;
754 struct vb2_queue *q;
755 int ret = 0;
756
757 mfc_debug_enter();
758 if (mutex_lock_interruptible(&dev->mfc_mutex))
759 return -ERESTARTSYS;
760 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
761 /* Allocate memory for context */
762 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
763 if (!ctx) {
764 ret = -ENOMEM;
765 goto err_alloc;
766 }
767 v4l2_fh_init(&ctx->fh, vdev);
768 file->private_data = &ctx->fh;
769 v4l2_fh_add(&ctx->fh);
770 ctx->dev = dev;
771 INIT_LIST_HEAD(&ctx->src_queue);
772 INIT_LIST_HEAD(&ctx->dst_queue);
773 ctx->src_queue_cnt = 0;
774 ctx->dst_queue_cnt = 0;
775 /* Get context number */
776 ctx->num = 0;
777 while (dev->ctx[ctx->num]) {
778 ctx->num++;
779 if (ctx->num >= MFC_NUM_CONTEXTS) {
780 mfc_debug(2, "Too many open contexts\n");
781 ret = -EBUSY;
782 goto err_no_ctx;
783 }
784 }
785 /* Mark context as idle */
786 clear_work_bit_irqsave(ctx);
787 dev->ctx[ctx->num] = ctx;
788 if (vdev == dev->vfd_dec) {
789 ctx->type = MFCINST_DECODER;
790 ctx->c_ops = get_dec_codec_ops();
791 s5p_mfc_dec_init(ctx);
792 /* Setup ctrl handler */
793 ret = s5p_mfc_dec_ctrls_setup(ctx);
794 if (ret) {
795 mfc_err("Failed to setup mfc controls\n");
796 goto err_ctrls_setup;
797 }
798 } else if (vdev == dev->vfd_enc) {
799 ctx->type = MFCINST_ENCODER;
800 ctx->c_ops = get_enc_codec_ops();
801 /* only for encoder */
802 INIT_LIST_HEAD(&ctx->ref_queue);
803 ctx->ref_queue_cnt = 0;
804 s5p_mfc_enc_init(ctx);
805 /* Setup ctrl handler */
806 ret = s5p_mfc_enc_ctrls_setup(ctx);
807 if (ret) {
808 mfc_err("Failed to setup mfc controls\n");
809 goto err_ctrls_setup;
810 }
811 } else {
812 ret = -ENOENT;
813 goto err_bad_node;
814 }
815 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
816 ctx->inst_no = MFC_NO_INSTANCE_SET;
817 /* Load firmware if this is the first instance */
818 if (dev->num_inst == 1) {
819 dev->watchdog_timer.expires = jiffies +
820 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
821 add_timer(&dev->watchdog_timer);
822 ret = s5p_mfc_power_on();
823 if (ret < 0) {
824 mfc_err("power on failed\n");
825 goto err_pwr_enable;
826 }
827 s5p_mfc_clock_on();
828 ret = s5p_mfc_load_firmware(dev);
829 if (ret) {
830 s5p_mfc_clock_off();
831 goto err_load_fw;
832 }
833 /* Init the FW */
834 ret = s5p_mfc_init_hw(dev);
835 s5p_mfc_clock_off();
836 if (ret)
837 goto err_init_hw;
838 }
839 /* Init videobuf2 queue for CAPTURE */
840 q = &ctx->vq_dst;
841 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
842 q->drv_priv = &ctx->fh;
843 q->lock = &dev->mfc_mutex;
844 if (vdev == dev->vfd_dec) {
845 q->io_modes = VB2_MMAP;
846 q->ops = get_dec_queue_ops();
847 } else if (vdev == dev->vfd_enc) {
848 q->io_modes = VB2_MMAP | VB2_USERPTR;
849 q->ops = get_enc_queue_ops();
850 } else {
851 ret = -ENOENT;
852 goto err_queue_init;
853 }
854 /*
855 * We'll do mostly sequential access, so sacrifice TLB efficiency for
856 * faster allocation.
857 */
858 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
859 q->mem_ops = &vb2_dma_contig_memops;
860 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
861 ret = vb2_queue_init(q);
862 if (ret) {
863 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
864 goto err_queue_init;
865 }
866 /* Init videobuf2 queue for OUTPUT */
867 q = &ctx->vq_src;
868 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
869 q->io_modes = VB2_MMAP;
870 q->drv_priv = &ctx->fh;
871 q->lock = &dev->mfc_mutex;
872 if (vdev == dev->vfd_dec) {
873 q->io_modes = VB2_MMAP;
874 q->ops = get_dec_queue_ops();
875 } else if (vdev == dev->vfd_enc) {
876 q->io_modes = VB2_MMAP | VB2_USERPTR;
877 q->ops = get_enc_queue_ops();
878 } else {
879 ret = -ENOENT;
880 goto err_queue_init;
881 }
882 /* One way to indicate end-of-stream for MFC is to set the
883 * bytesused == 0. However by default videobuf2 handles bytesused
884 * equal to 0 as a special case and changes its value to the size
885 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
886 * will keep the value of bytesused intact.
887 */
888 q->allow_zero_bytesused = 1;
889
890 /*
891 * We'll do mostly sequential access, so sacrifice TLB efficiency for
892 * faster allocation.
893 */
894 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
895 q->mem_ops = &vb2_dma_contig_memops;
896 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
897 ret = vb2_queue_init(q);
898 if (ret) {
899 mfc_err("Failed to initialize videobuf2 queue(output)\n");
900 goto err_queue_init;
901 }
902 init_waitqueue_head(&ctx->queue);
903 mutex_unlock(&dev->mfc_mutex);
904 mfc_debug_leave();
905 return ret;
906 /* Deinit when failure occurred */
907 err_queue_init:
908 if (dev->num_inst == 1)
909 s5p_mfc_deinit_hw(dev);
910 err_init_hw:
911 err_load_fw:
912 err_pwr_enable:
913 if (dev->num_inst == 1) {
914 if (s5p_mfc_power_off() < 0)
915 mfc_err("power off failed\n");
916 del_timer_sync(&dev->watchdog_timer);
917 }
918 err_ctrls_setup:
919 s5p_mfc_dec_ctrls_delete(ctx);
920 err_bad_node:
921 dev->ctx[ctx->num] = NULL;
922 err_no_ctx:
923 v4l2_fh_del(&ctx->fh);
924 v4l2_fh_exit(&ctx->fh);
925 kfree(ctx);
926 err_alloc:
927 dev->num_inst--;
928 mutex_unlock(&dev->mfc_mutex);
929 mfc_debug_leave();
930 return ret;
931 }
932
933 /* Release MFC context */
934 static int s5p_mfc_release(struct file *file)
935 {
936 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
937 struct s5p_mfc_dev *dev = ctx->dev;
938
939 /* if dev is null, do cleanup that doesn't need dev */
940 mfc_debug_enter();
941 if (dev)
942 mutex_lock(&dev->mfc_mutex);
943 vb2_queue_release(&ctx->vq_src);
944 vb2_queue_release(&ctx->vq_dst);
945 if (dev) {
946 s5p_mfc_clock_on();
947
948 /* Mark context as idle */
949 clear_work_bit_irqsave(ctx);
950 /*
951 * If instance was initialised and not yet freed,
952 * return instance and free resources
953 */
954 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
955 mfc_debug(2, "Has to free instance\n");
956 s5p_mfc_close_mfc_inst(dev, ctx);
957 }
958 /* hardware locking scheme */
959 if (dev->curr_ctx == ctx->num)
960 clear_bit(0, &dev->hw_lock);
961 dev->num_inst--;
962 if (dev->num_inst == 0) {
963 mfc_debug(2, "Last instance\n");
964 s5p_mfc_deinit_hw(dev);
965 del_timer_sync(&dev->watchdog_timer);
966 s5p_mfc_clock_off();
967 if (s5p_mfc_power_off() < 0)
968 mfc_err("Power off failed\n");
969 } else {
970 mfc_debug(2, "Shutting down clock\n");
971 s5p_mfc_clock_off();
972 }
973 }
974 if (dev)
975 dev->ctx[ctx->num] = NULL;
976 s5p_mfc_dec_ctrls_delete(ctx);
977 v4l2_fh_del(&ctx->fh);
978 /* vdev is gone if dev is null */
979 if (dev)
980 v4l2_fh_exit(&ctx->fh);
981 kfree(ctx);
982 mfc_debug_leave();
983 if (dev)
984 mutex_unlock(&dev->mfc_mutex);
985
986 return 0;
987 }
988
989 /* Poll */
990 static unsigned int s5p_mfc_poll(struct file *file,
991 struct poll_table_struct *wait)
992 {
993 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
994 struct s5p_mfc_dev *dev = ctx->dev;
995 struct vb2_queue *src_q, *dst_q;
996 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
997 unsigned int rc = 0;
998 unsigned long flags;
999
1000 mutex_lock(&dev->mfc_mutex);
1001 src_q = &ctx->vq_src;
1002 dst_q = &ctx->vq_dst;
1003 /*
1004 * There has to be at least one buffer queued on each queued_list, which
1005 * means either in driver already or waiting for driver to claim it
1006 * and start processing.
1007 */
1008 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1009 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1010 rc = POLLERR;
1011 goto end;
1012 }
1013 mutex_unlock(&dev->mfc_mutex);
1014 poll_wait(file, &ctx->fh.wait, wait);
1015 poll_wait(file, &src_q->done_wq, wait);
1016 poll_wait(file, &dst_q->done_wq, wait);
1017 mutex_lock(&dev->mfc_mutex);
1018 if (v4l2_event_pending(&ctx->fh))
1019 rc |= POLLPRI;
1020 spin_lock_irqsave(&src_q->done_lock, flags);
1021 if (!list_empty(&src_q->done_list))
1022 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1023 done_entry);
1024 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1025 || src_vb->state == VB2_BUF_STATE_ERROR))
1026 rc |= POLLOUT | POLLWRNORM;
1027 spin_unlock_irqrestore(&src_q->done_lock, flags);
1028 spin_lock_irqsave(&dst_q->done_lock, flags);
1029 if (!list_empty(&dst_q->done_list))
1030 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1031 done_entry);
1032 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1033 || dst_vb->state == VB2_BUF_STATE_ERROR))
1034 rc |= POLLIN | POLLRDNORM;
1035 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1036 end:
1037 mutex_unlock(&dev->mfc_mutex);
1038 return rc;
1039 }
1040
1041 /* Mmap */
1042 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1043 {
1044 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1045 struct s5p_mfc_dev *dev = ctx->dev;
1046 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1047 int ret;
1048
1049 if (mutex_lock_interruptible(&dev->mfc_mutex))
1050 return -ERESTARTSYS;
1051 if (offset < DST_QUEUE_OFF_BASE) {
1052 mfc_debug(2, "mmaping source\n");
1053 ret = vb2_mmap(&ctx->vq_src, vma);
1054 } else { /* capture */
1055 mfc_debug(2, "mmaping destination\n");
1056 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1057 ret = vb2_mmap(&ctx->vq_dst, vma);
1058 }
1059 mutex_unlock(&dev->mfc_mutex);
1060 return ret;
1061 }
1062
1063 /* v4l2 ops */
1064 static const struct v4l2_file_operations s5p_mfc_fops = {
1065 .owner = THIS_MODULE,
1066 .open = s5p_mfc_open,
1067 .release = s5p_mfc_release,
1068 .poll = s5p_mfc_poll,
1069 .unlocked_ioctl = video_ioctl2,
1070 .mmap = s5p_mfc_mmap,
1071 };
1072
1073 /* DMA memory related helper functions */
1074 static void s5p_mfc_memdev_release(struct device *dev)
1075 {
1076 of_reserved_mem_device_release(dev);
1077 }
1078
1079 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1080 const char *name, unsigned int idx)
1081 {
1082 struct device *child;
1083 int ret;
1084
1085 child = devm_kzalloc(dev, sizeof(struct device), GFP_KERNEL);
1086 if (!child)
1087 return NULL;
1088
1089 device_initialize(child);
1090 dev_set_name(child, "%s:%s", dev_name(dev), name);
1091 child->parent = dev;
1092 child->bus = dev->bus;
1093 child->coherent_dma_mask = dev->coherent_dma_mask;
1094 child->dma_mask = dev->dma_mask;
1095 child->release = s5p_mfc_memdev_release;
1096
1097 if (device_add(child) == 0) {
1098 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1099 idx);
1100 if (ret == 0)
1101 return child;
1102 device_del(child);
1103 }
1104
1105 put_device(child);
1106 return NULL;
1107 }
1108
1109 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1110 {
1111 struct device *dev = &mfc_dev->plat_dev->dev;
1112
1113 /*
1114 * When IOMMU is available, we cannot use the default configuration,
1115 * because of MFC firmware requirements: address space limited to
1116 * 256M and non-zero default start address.
1117 * This is still simplified, not optimal configuration, but for now
1118 * IOMMU core doesn't allow to configure device's IOMMUs channel
1119 * separately.
1120 */
1121 if (exynos_is_iommu_available(dev)) {
1122 int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE,
1123 S5P_MFC_IOMMU_DMA_SIZE);
1124 if (ret == 0)
1125 mfc_dev->mem_dev_l = mfc_dev->mem_dev_r = dev;
1126 return ret;
1127 }
1128
1129 /*
1130 * Create and initialize virtual devices for accessing
1131 * reserved memory regions.
1132 */
1133 mfc_dev->mem_dev_l = s5p_mfc_alloc_memdev(dev, "left",
1134 MFC_BANK1_ALLOC_CTX);
1135 if (!mfc_dev->mem_dev_l)
1136 return -ENODEV;
1137 mfc_dev->mem_dev_r = s5p_mfc_alloc_memdev(dev, "right",
1138 MFC_BANK2_ALLOC_CTX);
1139 if (!mfc_dev->mem_dev_r) {
1140 device_unregister(mfc_dev->mem_dev_l);
1141 return -ENODEV;
1142 }
1143
1144 return 0;
1145 }
1146
1147 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1148 {
1149 struct device *dev = &mfc_dev->plat_dev->dev;
1150
1151 if (exynos_is_iommu_available(dev)) {
1152 exynos_unconfigure_iommu(dev);
1153 return;
1154 }
1155
1156 device_unregister(mfc_dev->mem_dev_l);
1157 device_unregister(mfc_dev->mem_dev_r);
1158 }
1159
1160 static void *mfc_get_drv_data(struct platform_device *pdev);
1161
1162 /* MFC probe function */
1163 static int s5p_mfc_probe(struct platform_device *pdev)
1164 {
1165 struct s5p_mfc_dev *dev;
1166 struct video_device *vfd;
1167 struct resource *res;
1168 int ret;
1169
1170 pr_debug("%s++\n", __func__);
1171 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1172 if (!dev) {
1173 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1174 return -ENOMEM;
1175 }
1176
1177 spin_lock_init(&dev->irqlock);
1178 spin_lock_init(&dev->condlock);
1179 dev->plat_dev = pdev;
1180 if (!dev->plat_dev) {
1181 dev_err(&pdev->dev, "No platform data specified\n");
1182 return -ENODEV;
1183 }
1184
1185 dev->variant = mfc_get_drv_data(pdev);
1186
1187 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1189 if (IS_ERR(dev->regs_base))
1190 return PTR_ERR(dev->regs_base);
1191
1192 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1193 if (res == NULL) {
1194 dev_err(&pdev->dev, "failed to get irq resource\n");
1195 return -ENOENT;
1196 }
1197 dev->irq = res->start;
1198 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1199 0, pdev->name, dev);
1200 if (ret) {
1201 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1202 return ret;
1203 }
1204
1205 ret = s5p_mfc_configure_dma_memory(dev);
1206 if (ret < 0) {
1207 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1208 return ret;
1209 }
1210
1211 ret = s5p_mfc_init_pm(dev);
1212 if (ret < 0) {
1213 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1214 goto err_dma;
1215 }
1216
1217 vb2_dma_contig_set_max_seg_size(dev->mem_dev_l, DMA_BIT_MASK(32));
1218 vb2_dma_contig_set_max_seg_size(dev->mem_dev_r, DMA_BIT_MASK(32));
1219
1220 mutex_init(&dev->mfc_mutex);
1221
1222 ret = s5p_mfc_alloc_firmware(dev);
1223 if (ret)
1224 goto err_res;
1225
1226 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1227 if (ret)
1228 goto err_v4l2_dev_reg;
1229 init_waitqueue_head(&dev->queue);
1230
1231 /* decoder */
1232 vfd = video_device_alloc();
1233 if (!vfd) {
1234 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1235 ret = -ENOMEM;
1236 goto err_dec_alloc;
1237 }
1238 vfd->fops = &s5p_mfc_fops;
1239 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1240 vfd->release = video_device_release;
1241 vfd->lock = &dev->mfc_mutex;
1242 vfd->v4l2_dev = &dev->v4l2_dev;
1243 vfd->vfl_dir = VFL_DIR_M2M;
1244 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1245 dev->vfd_dec = vfd;
1246 video_set_drvdata(vfd, dev);
1247
1248 /* encoder */
1249 vfd = video_device_alloc();
1250 if (!vfd) {
1251 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1252 ret = -ENOMEM;
1253 goto err_enc_alloc;
1254 }
1255 vfd->fops = &s5p_mfc_fops;
1256 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1257 vfd->release = video_device_release;
1258 vfd->lock = &dev->mfc_mutex;
1259 vfd->v4l2_dev = &dev->v4l2_dev;
1260 vfd->vfl_dir = VFL_DIR_M2M;
1261 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1262 dev->vfd_enc = vfd;
1263 video_set_drvdata(vfd, dev);
1264 platform_set_drvdata(pdev, dev);
1265
1266 dev->hw_lock = 0;
1267 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1268 atomic_set(&dev->watchdog_cnt, 0);
1269 init_timer(&dev->watchdog_timer);
1270 dev->watchdog_timer.data = (unsigned long)dev;
1271 dev->watchdog_timer.function = s5p_mfc_watchdog;
1272
1273 /* Initialize HW ops and commands based on MFC version */
1274 s5p_mfc_init_hw_ops(dev);
1275 s5p_mfc_init_hw_cmds(dev);
1276 s5p_mfc_init_regs(dev);
1277
1278 /* Register decoder and encoder */
1279 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1280 if (ret) {
1281 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1282 goto err_dec_reg;
1283 }
1284 v4l2_info(&dev->v4l2_dev,
1285 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1286
1287 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1288 if (ret) {
1289 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1290 goto err_enc_reg;
1291 }
1292 v4l2_info(&dev->v4l2_dev,
1293 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1294
1295 pr_debug("%s--\n", __func__);
1296 return 0;
1297
1298 /* Deinit MFC if probe had failed */
1299 err_enc_reg:
1300 video_unregister_device(dev->vfd_dec);
1301 err_dec_reg:
1302 video_device_release(dev->vfd_enc);
1303 err_enc_alloc:
1304 video_device_release(dev->vfd_dec);
1305 err_dec_alloc:
1306 v4l2_device_unregister(&dev->v4l2_dev);
1307 err_v4l2_dev_reg:
1308 s5p_mfc_release_firmware(dev);
1309 err_res:
1310 s5p_mfc_final_pm(dev);
1311 err_dma:
1312 s5p_mfc_unconfigure_dma_memory(dev);
1313
1314 pr_debug("%s-- with error\n", __func__);
1315 return ret;
1316
1317 }
1318
1319 /* Remove the driver */
1320 static int s5p_mfc_remove(struct platform_device *pdev)
1321 {
1322 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1323 struct s5p_mfc_ctx *ctx;
1324 int i;
1325
1326 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1327
1328 /*
1329 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1330 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1331 * after s5p_mfc_remove() is run during unbind.
1332 */
1333 mutex_lock(&dev->mfc_mutex);
1334 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1335 ctx = dev->ctx[i];
1336 if (!ctx)
1337 continue;
1338 /* clear ctx->dev */
1339 ctx->dev = NULL;
1340 }
1341 mutex_unlock(&dev->mfc_mutex);
1342
1343 del_timer_sync(&dev->watchdog_timer);
1344 flush_work(&dev->watchdog_work);
1345
1346 video_unregister_device(dev->vfd_enc);
1347 video_unregister_device(dev->vfd_dec);
1348 video_device_release(dev->vfd_enc);
1349 video_device_release(dev->vfd_dec);
1350 v4l2_device_unregister(&dev->v4l2_dev);
1351 s5p_mfc_release_firmware(dev);
1352 s5p_mfc_unconfigure_dma_memory(dev);
1353 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_l);
1354 vb2_dma_contig_clear_max_seg_size(dev->mem_dev_r);
1355
1356 s5p_mfc_final_pm(dev);
1357 return 0;
1358 }
1359
1360 #ifdef CONFIG_PM_SLEEP
1361
1362 static int s5p_mfc_suspend(struct device *dev)
1363 {
1364 struct platform_device *pdev = to_platform_device(dev);
1365 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1366 int ret;
1367
1368 if (m_dev->num_inst == 0)
1369 return 0;
1370
1371 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1372 mfc_err("Error: going to suspend for a second time\n");
1373 return -EIO;
1374 }
1375
1376 /* Check if we're processing then wait if it necessary. */
1377 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1378 /* Try and lock the HW */
1379 /* Wait on the interrupt waitqueue */
1380 ret = wait_event_interruptible_timeout(m_dev->queue,
1381 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1382 if (ret == 0) {
1383 mfc_err("Waiting for hardware to finish timed out\n");
1384 clear_bit(0, &m_dev->enter_suspend);
1385 return -EIO;
1386 }
1387 }
1388
1389 ret = s5p_mfc_sleep(m_dev);
1390 if (ret) {
1391 clear_bit(0, &m_dev->enter_suspend);
1392 clear_bit(0, &m_dev->hw_lock);
1393 }
1394 return ret;
1395 }
1396
1397 static int s5p_mfc_resume(struct device *dev)
1398 {
1399 struct platform_device *pdev = to_platform_device(dev);
1400 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1401
1402 if (m_dev->num_inst == 0)
1403 return 0;
1404 return s5p_mfc_wakeup(m_dev);
1405 }
1406 #endif
1407
1408 /* Power management */
1409 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1410 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1411 };
1412
1413 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1414 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1415 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1416 .dsc = DESC_BUF_SIZE,
1417 .shm = SHARED_BUF_SIZE,
1418 };
1419
1420 static struct s5p_mfc_buf_size buf_size_v5 = {
1421 .fw = MAX_FW_SIZE,
1422 .cpb = MAX_CPB_SIZE,
1423 .priv = &mfc_buf_size_v5,
1424 };
1425
1426 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1427 .base = MFC_BASE_ALIGN_ORDER,
1428 };
1429
1430 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1431 .version = MFC_VERSION,
1432 .version_bit = MFC_V5_BIT,
1433 .port_num = MFC_NUM_PORTS,
1434 .buf_size = &buf_size_v5,
1435 .buf_align = &mfc_buf_align_v5,
1436 .fw_name[0] = "s5p-mfc.fw",
1437 .clk_names = {"mfc", "sclk_mfc"},
1438 .num_clocks = 2,
1439 .use_clock_gating = true,
1440 };
1441
1442 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1443 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1444 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1445 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1446 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1447 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1448 };
1449
1450 static struct s5p_mfc_buf_size buf_size_v6 = {
1451 .fw = MAX_FW_SIZE_V6,
1452 .cpb = MAX_CPB_SIZE_V6,
1453 .priv = &mfc_buf_size_v6,
1454 };
1455
1456 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1457 .base = 0,
1458 };
1459
1460 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1461 .version = MFC_VERSION_V6,
1462 .version_bit = MFC_V6_BIT,
1463 .port_num = MFC_NUM_PORTS_V6,
1464 .buf_size = &buf_size_v6,
1465 .buf_align = &mfc_buf_align_v6,
1466 .fw_name[0] = "s5p-mfc-v6.fw",
1467 /*
1468 * v6-v2 firmware contains bug fixes and interface change
1469 * for init buffer command
1470 */
1471 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1472 .clk_names = {"mfc"},
1473 .num_clocks = 1,
1474 };
1475
1476 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1477 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1478 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1479 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1480 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1481 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1482 };
1483
1484 static struct s5p_mfc_buf_size buf_size_v7 = {
1485 .fw = MAX_FW_SIZE_V7,
1486 .cpb = MAX_CPB_SIZE_V7,
1487 .priv = &mfc_buf_size_v7,
1488 };
1489
1490 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1491 .base = 0,
1492 };
1493
1494 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1495 .version = MFC_VERSION_V7,
1496 .version_bit = MFC_V7_BIT,
1497 .port_num = MFC_NUM_PORTS_V7,
1498 .buf_size = &buf_size_v7,
1499 .buf_align = &mfc_buf_align_v7,
1500 .fw_name[0] = "s5p-mfc-v7.fw",
1501 .clk_names = {"mfc", "sclk_mfc"},
1502 .num_clocks = 2,
1503 };
1504
1505 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1506 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1507 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1508 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1509 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1510 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1511 };
1512
1513 static struct s5p_mfc_buf_size buf_size_v8 = {
1514 .fw = MAX_FW_SIZE_V8,
1515 .cpb = MAX_CPB_SIZE_V8,
1516 .priv = &mfc_buf_size_v8,
1517 };
1518
1519 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1520 .base = 0,
1521 };
1522
1523 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1524 .version = MFC_VERSION_V8,
1525 .version_bit = MFC_V8_BIT,
1526 .port_num = MFC_NUM_PORTS_V8,
1527 .buf_size = &buf_size_v8,
1528 .buf_align = &mfc_buf_align_v8,
1529 .fw_name[0] = "s5p-mfc-v8.fw",
1530 .clk_names = {"mfc"},
1531 .num_clocks = 1,
1532 };
1533
1534 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1535 .version = MFC_VERSION_V8,
1536 .version_bit = MFC_V8_BIT,
1537 .port_num = MFC_NUM_PORTS_V8,
1538 .buf_size = &buf_size_v8,
1539 .buf_align = &mfc_buf_align_v8,
1540 .fw_name[0] = "s5p-mfc-v8.fw",
1541 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1542 .num_clocks = 3,
1543 };
1544
1545 static const struct of_device_id exynos_mfc_match[] = {
1546 {
1547 .compatible = "samsung,mfc-v5",
1548 .data = &mfc_drvdata_v5,
1549 }, {
1550 .compatible = "samsung,mfc-v6",
1551 .data = &mfc_drvdata_v6,
1552 }, {
1553 .compatible = "samsung,mfc-v7",
1554 .data = &mfc_drvdata_v7,
1555 }, {
1556 .compatible = "samsung,mfc-v8",
1557 .data = &mfc_drvdata_v8,
1558 }, {
1559 .compatible = "samsung,exynos5433-mfc",
1560 .data = &mfc_drvdata_v8_5433,
1561 },
1562 {},
1563 };
1564 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1565
1566 static void *mfc_get_drv_data(struct platform_device *pdev)
1567 {
1568 struct s5p_mfc_variant *driver_data = NULL;
1569 const struct of_device_id *match;
1570
1571 match = of_match_node(exynos_mfc_match, pdev->dev.of_node);
1572 if (match)
1573 driver_data = (struct s5p_mfc_variant *)match->data;
1574
1575 return driver_data;
1576 }
1577
1578 static struct platform_driver s5p_mfc_driver = {
1579 .probe = s5p_mfc_probe,
1580 .remove = s5p_mfc_remove,
1581 .driver = {
1582 .name = S5P_MFC_NAME,
1583 .pm = &s5p_mfc_pm_ops,
1584 .of_match_table = exynos_mfc_match,
1585 },
1586 };
1587
1588 module_platform_driver(s5p_mfc_driver);
1589
1590 MODULE_LICENSE("GPL");
1591 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1592 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1593
Linux with added FPC-III support