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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / platform / ti-vpe / cal.c
blob7a058b6e03d0ff2f6cdc6699912d3809c8824309
1 /*
2 * TI CAL camera interface driver
3 *
4 * Copyright (c) 2015 Texas Instruments Inc.
5 * Benoit Parrot, <bparrot@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation
10 */
11
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioctl.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/videodev2.h>
21 #include <linux/of_device.h>
22 #include <linux/of_graph.h>
23
24 #include <media/v4l2-of.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-common.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-fh.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-common.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include "cal_regs.h"
38
39 #define CAL_MODULE_NAME "cal"
40
41 #define MAX_WIDTH 1920
42 #define MAX_HEIGHT 1200
43
44 #define CAL_VERSION "0.1.0"
45
46 MODULE_DESCRIPTION("TI CAL driver");
47 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
48 MODULE_LICENSE("GPL v2");
49 MODULE_VERSION(CAL_VERSION);
50
51 static unsigned video_nr = -1;
52 module_param(video_nr, uint, 0644);
53 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
54
55 static unsigned debug;
56 module_param(debug, uint, 0644);
57 MODULE_PARM_DESC(debug, "activates debug info");
58
59 /* timeperframe: min/max and default */
60 static const struct v4l2_fract
61 tpf_default = {.numerator = 1001, .denominator = 30000};
62
63 #define cal_dbg(level, caldev, fmt, arg...) \
64 v4l2_dbg(level, debug, &caldev->v4l2_dev, fmt, ##arg)
65 #define cal_info(caldev, fmt, arg...) \
66 v4l2_info(&caldev->v4l2_dev, fmt, ##arg)
67 #define cal_err(caldev, fmt, arg...) \
68 v4l2_err(&caldev->v4l2_dev, fmt, ##arg)
69
70 #define ctx_dbg(level, ctx, fmt, arg...) \
71 v4l2_dbg(level, debug, &ctx->v4l2_dev, fmt, ##arg)
72 #define ctx_info(ctx, fmt, arg...) \
73 v4l2_info(&ctx->v4l2_dev, fmt, ##arg)
74 #define ctx_err(ctx, fmt, arg...) \
75 v4l2_err(&ctx->v4l2_dev, fmt, ##arg)
76
77 #define CAL_NUM_INPUT 1
78 #define CAL_NUM_CONTEXT 2
79
80 #define bytes_per_line(pixel, bpp) (ALIGN(pixel * bpp, 16))
81
82 #define reg_read(dev, offset) ioread32(dev->base + offset)
83 #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset)
84
85 #define reg_read_field(dev, offset, mask) get_field(reg_read(dev, offset), \
86 mask)
87 #define reg_write_field(dev, offset, field, mask) { \
88 u32 val = reg_read(dev, offset); \
89 set_field(&val, field, mask); \
90 reg_write(dev, offset, val); }
91
92 /* ------------------------------------------------------------------
93 * Basic structures
94 * ------------------------------------------------------------------
95 */
96
97 struct cal_fmt {
98 u32 fourcc;
99 u32 code;
100 u8 depth;
101 };
102
103 static struct cal_fmt cal_formats[] = {
104 {
105 .fourcc = V4L2_PIX_FMT_YUYV,
106 .code = MEDIA_BUS_FMT_YUYV8_2X8,
107 .depth = 16,
108 }, {
109 .fourcc = V4L2_PIX_FMT_UYVY,
110 .code = MEDIA_BUS_FMT_UYVY8_2X8,
111 .depth = 16,
112 }, {
113 .fourcc = V4L2_PIX_FMT_YVYU,
114 .code = MEDIA_BUS_FMT_YVYU8_2X8,
115 .depth = 16,
116 }, {
117 .fourcc = V4L2_PIX_FMT_VYUY,
118 .code = MEDIA_BUS_FMT_VYUY8_2X8,
119 .depth = 16,
120 }, {
121 .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
122 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
123 .depth = 16,
124 }, {
125 .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
126 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
127 .depth = 16,
128 }, {
129 .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
130 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
131 .depth = 16,
132 }, {
133 .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
134 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
135 .depth = 16,
136 }, {
137 .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
138 .code = MEDIA_BUS_FMT_RGB888_2X12_LE,
139 .depth = 24,
140 }, {
141 .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
142 .code = MEDIA_BUS_FMT_RGB888_2X12_BE,
143 .depth = 24,
144 }, {
145 .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
146 .code = MEDIA_BUS_FMT_ARGB8888_1X32,
147 .depth = 32,
148 }, {
149 .fourcc = V4L2_PIX_FMT_SBGGR8,
150 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
151 .depth = 8,
152 }, {
153 .fourcc = V4L2_PIX_FMT_SGBRG8,
154 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
155 .depth = 8,
156 }, {
157 .fourcc = V4L2_PIX_FMT_SGRBG8,
158 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
159 .depth = 8,
160 }, {
161 .fourcc = V4L2_PIX_FMT_SRGGB8,
162 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
163 .depth = 8,
164 }, {
165 .fourcc = V4L2_PIX_FMT_SBGGR10,
166 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
167 .depth = 16,
168 }, {
169 .fourcc = V4L2_PIX_FMT_SGBRG10,
170 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
171 .depth = 16,
172 }, {
173 .fourcc = V4L2_PIX_FMT_SGRBG10,
174 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
175 .depth = 16,
176 }, {
177 .fourcc = V4L2_PIX_FMT_SRGGB10,
178 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
179 .depth = 16,
180 }, {
181 .fourcc = V4L2_PIX_FMT_SBGGR12,
182 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
183 .depth = 16,
184 }, {
185 .fourcc = V4L2_PIX_FMT_SGBRG12,
186 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
187 .depth = 16,
188 }, {
189 .fourcc = V4L2_PIX_FMT_SGRBG12,
190 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
191 .depth = 16,
192 }, {
193 .fourcc = V4L2_PIX_FMT_SRGGB12,
194 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
195 .depth = 16,
196 },
197 };
198
199 /* Print Four-character-code (FOURCC) */
200 static char *fourcc_to_str(u32 fmt)
201 {
202 static char code[5];
203
204 code[0] = (unsigned char)(fmt & 0xff);
205 code[1] = (unsigned char)((fmt >> 8) & 0xff);
206 code[2] = (unsigned char)((fmt >> 16) & 0xff);
207 code[3] = (unsigned char)((fmt >> 24) & 0xff);
208 code[4] = '\0';
209
210 return code;
211 }
212
213 /* buffer for one video frame */
214 struct cal_buffer {
215 /* common v4l buffer stuff -- must be first */
216 struct vb2_v4l2_buffer vb;
217 struct list_head list;
218 const struct cal_fmt *fmt;
219 };
220
221 struct cal_dmaqueue {
222 struct list_head active;
223
224 /* Counters to control fps rate */
225 int frame;
226 int ini_jiffies;
227 };
228
229 struct cm_data {
230 void __iomem *base;
231 struct resource *res;
232
233 unsigned int camerrx_control;
234
235 struct platform_device *pdev;
236 };
237
238 struct cc_data {
239 void __iomem *base;
240 struct resource *res;
241
242 struct platform_device *pdev;
243 };
244
245 /*
246 * there is one cal_dev structure in the driver, it is shared by
247 * all instances.
248 */
249 struct cal_dev {
250 int irq;
251 void __iomem *base;
252 struct resource *res;
253 struct platform_device *pdev;
254 struct v4l2_device v4l2_dev;
255
256 /* Control Module handle */
257 struct cm_data *cm;
258 /* Camera Core Module handle */
259 struct cc_data *cc[CAL_NUM_CSI2_PORTS];
260
261 struct cal_ctx *ctx[CAL_NUM_CONTEXT];
262 };
263
264 /*
265 * There is one cal_ctx structure for each camera core context.
266 */
267 struct cal_ctx {
268 struct v4l2_device v4l2_dev;
269 struct v4l2_ctrl_handler ctrl_handler;
270 struct video_device vdev;
271 struct v4l2_async_notifier notifier;
272 struct v4l2_subdev *sensor;
273 struct v4l2_of_endpoint endpoint;
274
275 struct v4l2_async_subdev asd;
276 struct v4l2_async_subdev *asd_list[1];
277
278 struct v4l2_fh fh;
279 struct cal_dev *dev;
280 struct cc_data *cc;
281
282 /* v4l2_ioctl mutex */
283 struct mutex mutex;
284 /* v4l2 buffers lock */
285 spinlock_t slock;
286
287 /* Several counters */
288 unsigned long jiffies;
289
290 struct cal_dmaqueue vidq;
291
292 /* Input Number */
293 int input;
294
295 /* video capture */
296 const struct cal_fmt *fmt;
297 /* Used to store current pixel format */
298 struct v4l2_format v_fmt;
299 /* Used to store current mbus frame format */
300 struct v4l2_mbus_framefmt m_fmt;
301
302 /* Current subdev enumerated format */
303 struct cal_fmt *active_fmt[ARRAY_SIZE(cal_formats)];
304 int num_active_fmt;
305
306 struct v4l2_fract timeperframe;
307 unsigned int sequence;
308 unsigned int external_rate;
309 struct vb2_queue vb_vidq;
310 unsigned int seq_count;
311 unsigned int csi2_port;
312 unsigned int virtual_channel;
313
314 /* Pointer pointing to current v4l2_buffer */
315 struct cal_buffer *cur_frm;
316 /* Pointer pointing to next v4l2_buffer */
317 struct cal_buffer *next_frm;
318 };
319
320 static const struct cal_fmt *find_format_by_pix(struct cal_ctx *ctx,
321 u32 pixelformat)
322 {
323 const struct cal_fmt *fmt;
324 unsigned int k;
325
326 for (k = 0; k < ctx->num_active_fmt; k++) {
327 fmt = ctx->active_fmt[k];
328 if (fmt->fourcc == pixelformat)
329 return fmt;
330 }
331
332 return NULL;
333 }
334
335 static const struct cal_fmt *find_format_by_code(struct cal_ctx *ctx,
336 u32 code)
337 {
338 const struct cal_fmt *fmt;
339 unsigned int k;
340
341 for (k = 0; k < ctx->num_active_fmt; k++) {
342 fmt = ctx->active_fmt[k];
343 if (fmt->code == code)
344 return fmt;
345 }
346
347 return NULL;
348 }
349
350 static inline struct cal_ctx *notifier_to_ctx(struct v4l2_async_notifier *n)
351 {
352 return container_of(n, struct cal_ctx, notifier);
353 }
354
355 static inline int get_field(u32 value, u32 mask)
356 {
357 return (value & mask) >> __ffs(mask);
358 }
359
360 static inline void set_field(u32 *valp, u32 field, u32 mask)
361 {
362 u32 val = *valp;
363
364 val &= ~mask;
365 val |= (field << __ffs(mask)) & mask;
366 *valp = val;
367 }
368
369 /*
370 * Control Module block access
371 */
372 static struct cm_data *cm_create(struct cal_dev *dev)
373 {
374 struct platform_device *pdev = dev->pdev;
375 struct cm_data *cm;
376
377 cm = devm_kzalloc(&pdev->dev, sizeof(*cm), GFP_KERNEL);
378 if (!cm)
379 return ERR_PTR(-ENOMEM);
380
381 cm->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
382 "camerrx_control");
383 cm->base = devm_ioremap_resource(&pdev->dev, cm->res);
384 if (IS_ERR(cm->base)) {
385 cal_err(dev, "failed to ioremap\n");
386 return ERR_CAST(cm->base);
387 }
388
389 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
390 cm->res->name, &cm->res->start, &cm->res->end);
391
392 return cm;
393 }
394
395 static void camerarx_phy_enable(struct cal_ctx *ctx)
396 {
397 u32 val;
398
399 if (!ctx->dev->cm->base) {
400 ctx_err(ctx, "cm not mapped\n");
401 return;
402 }
403
404 val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
405 if (ctx->csi2_port == 1) {
406 set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
407 set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK);
408 /* enable all lanes by default */
409 set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK);
410 set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK);
411 } else if (ctx->csi2_port == 2) {
412 set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
413 set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK);
414 /* enable all lanes by default */
415 set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK);
416 set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK);
417 }
418 reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
419 }
420
421 static void camerarx_phy_disable(struct cal_ctx *ctx)
422 {
423 u32 val;
424
425 if (!ctx->dev->cm->base) {
426 ctx_err(ctx, "cm not mapped\n");
427 return;
428 }
429
430 val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
431 if (ctx->csi2_port == 1)
432 set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
433 else if (ctx->csi2_port == 2)
434 set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
435 reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
436 }
437
438 /*
439 * Camera Instance access block
440 */
441 static struct cc_data *cc_create(struct cal_dev *dev, unsigned int core)
442 {
443 struct platform_device *pdev = dev->pdev;
444 struct cc_data *cc;
445
446 cc = devm_kzalloc(&pdev->dev, sizeof(*cc), GFP_KERNEL);
447 if (!cc)
448 return ERR_PTR(-ENOMEM);
449
450 cc->res = platform_get_resource_byname(pdev,
451 IORESOURCE_MEM,
452 (core == 0) ?
453 "cal_rx_core0" :
454 "cal_rx_core1");
455 cc->base = devm_ioremap_resource(&pdev->dev, cc->res);
456 if (IS_ERR(cc->base)) {
457 cal_err(dev, "failed to ioremap\n");
458 return ERR_CAST(cc->base);
459 }
460
461 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
462 cc->res->name, &cc->res->start, &cc->res->end);
463
464 return cc;
465 }
466
467 /*
468 * Get Revision and HW info
469 */
470 static void cal_get_hwinfo(struct cal_dev *dev)
471 {
472 u32 revision = 0;
473 u32 hwinfo = 0;
474
475 revision = reg_read(dev, CAL_HL_REVISION);
476 cal_dbg(3, dev, "CAL_HL_REVISION = 0x%08x (expecting 0x40000200)\n",
477 revision);
478
479 hwinfo = reg_read(dev, CAL_HL_HWINFO);
480 cal_dbg(3, dev, "CAL_HL_HWINFO = 0x%08x (expecting 0xA3C90469)\n",
481 hwinfo);
482 }
483
484 static inline int cal_runtime_get(struct cal_dev *dev)
485 {
486 return pm_runtime_get_sync(&dev->pdev->dev);
487 }
488
489 static inline void cal_runtime_put(struct cal_dev *dev)
490 {
491 pm_runtime_put_sync(&dev->pdev->dev);
492 }
493
494 static void cal_quickdump_regs(struct cal_dev *dev)
495 {
496 cal_info(dev, "CAL Registers @ 0x%pa:\n", &dev->res->start);
497 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
498 (__force const void *)dev->base,
499 resource_size(dev->res), false);
500
501 if (dev->ctx[0]) {
502 cal_info(dev, "CSI2 Core 0 Registers @ %pa:\n",
503 &dev->ctx[0]->cc->res->start);
504 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
505 (__force const void *)dev->ctx[0]->cc->base,
506 resource_size(dev->ctx[0]->cc->res),
507 false);
508 }
509
510 if (dev->ctx[1]) {
511 cal_info(dev, "CSI2 Core 1 Registers @ %pa:\n",
512 &dev->ctx[1]->cc->res->start);
513 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
514 (__force const void *)dev->ctx[1]->cc->base,
515 resource_size(dev->ctx[1]->cc->res),
516 false);
517 }
518
519 cal_info(dev, "CAMERRX_Control Registers @ %pa:\n",
520 &dev->cm->res->start);
521 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
522 (__force const void *)dev->cm->base,
523 resource_size(dev->cm->res), false);
524 }
525
526 /*
527 * Enable the expected IRQ sources
528 */
529 static void enable_irqs(struct cal_ctx *ctx)
530 {
531 /* Enable IRQ_WDMA_END 0/1 */
532 reg_write_field(ctx->dev,
533 CAL_HL_IRQENABLE_SET(2),
534 CAL_HL_IRQ_ENABLE,
535 CAL_HL_IRQ_MASK(ctx->csi2_port));
536 /* Enable IRQ_WDMA_START 0/1 */
537 reg_write_field(ctx->dev,
538 CAL_HL_IRQENABLE_SET(3),
539 CAL_HL_IRQ_ENABLE,
540 CAL_HL_IRQ_MASK(ctx->csi2_port));
541 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
542 reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000);
543 }
544
545 static void disable_irqs(struct cal_ctx *ctx)
546 {
547 /* Disable IRQ_WDMA_END 0/1 */
548 reg_write_field(ctx->dev,
549 CAL_HL_IRQENABLE_CLR(2),
550 CAL_HL_IRQ_CLEAR,
551 CAL_HL_IRQ_MASK(ctx->csi2_port));
552 /* Disable IRQ_WDMA_START 0/1 */
553 reg_write_field(ctx->dev,
554 CAL_HL_IRQENABLE_CLR(3),
555 CAL_HL_IRQ_CLEAR,
556 CAL_HL_IRQ_MASK(ctx->csi2_port));
557 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
558 reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0);
559 }
560
561 static void csi2_init(struct cal_ctx *ctx)
562 {
563 int i;
564 u32 val;
565
566 val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port));
567 set_field(&val, CAL_GEN_ENABLE,
568 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
569 set_field(&val, CAL_GEN_ENABLE,
570 CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
571 set_field(&val, CAL_GEN_DISABLE,
572 CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
573 set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
574 reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val);
575 ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x\n", ctx->csi2_port,
576 reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)));
577
578 val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port));
579 set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
580 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
581 set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON,
582 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
583 reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val);
584 for (i = 0; i < 10; i++) {
585 if (reg_read_field(ctx->dev,
586 CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
587 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
588 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON)
589 break;
590 usleep_range(1000, 1100);
591 }
592 ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n", ctx->csi2_port,
593 reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
594
595 val = reg_read(ctx->dev, CAL_CTRL);
596 set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK);
597 set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK);
598 set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
599 CAL_CTRL_POSTED_WRITES_MASK);
600 set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK);
601 set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK);
602 reg_write(ctx->dev, CAL_CTRL, val);
603 ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->dev, CAL_CTRL));
604 }
605
606 static void csi2_lane_config(struct cal_ctx *ctx)
607 {
608 u32 val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port));
609 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
610 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
611 struct v4l2_of_bus_mipi_csi2 *mipi_csi2 = &ctx->endpoint.bus.mipi_csi2;
612 int lane;
613
614 set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
615 set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
616 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
617 /*
618 * Every lane are one nibble apart starting with the
619 * clock followed by the data lanes so shift masks by 4.
620 */
621 lane_mask <<= 4;
622 polarity_mask <<= 4;
623 set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
624 set_field(&val, mipi_csi2->lane_polarities[lane + 1],
625 polarity_mask);
626 }
627
628 reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val);
629 ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
630 ctx->csi2_port, val);
631 }
632
633 static void csi2_ppi_enable(struct cal_ctx *ctx)
634 {
635 reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
636 CAL_GEN_ENABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
637 }
638
639 static void csi2_ppi_disable(struct cal_ctx *ctx)
640 {
641 reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
642 CAL_GEN_DISABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
643 }
644
645 static void csi2_ctx_config(struct cal_ctx *ctx)
646 {
647 u32 val;
648
649 val = reg_read(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port));
650 set_field(&val, ctx->csi2_port, CAL_CSI2_CTX_CPORT_MASK);
651 /*
652 * DT type: MIPI CSI-2 Specs
653 * 0x1: All - DT filter is disabled
654 * 0x24: RGB888 1 pixel = 3 bytes
655 * 0x2B: RAW10 4 pixels = 5 bytes
656 * 0x2A: RAW8 1 pixel = 1 byte
657 * 0x1E: YUV422 2 pixels = 4 bytes
658 */
659 set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK);
660 /* Virtual Channel from the CSI2 sensor usually 0! */
661 set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK);
662 /* NUM_LINES_PER_FRAME => 0 means auto detect */
663 set_field(&val, 0, CAL_CSI2_CTX_LINES_MASK);
664 set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
665 set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
666 CAL_CSI2_CTX_PACK_MODE_MASK);
667 reg_write(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port), val);
668 ctx_dbg(3, ctx, "CAL_CSI2_CTX0(%d) = 0x%08x\n", ctx->csi2_port,
669 reg_read(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port)));
670 }
671
672 static void pix_proc_config(struct cal_ctx *ctx)
673 {
674 u32 val;
675
676 val = reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port));
677 set_field(&val, CAL_PIX_PROC_EXTRACT_B8, CAL_PIX_PROC_EXTRACT_MASK);
678 set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
679 set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
680 set_field(&val, CAL_PIX_PROC_PACK_B8, CAL_PIX_PROC_PACK_MASK);
681 set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK);
682 set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK);
683 reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val);
684 ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->csi2_port,
685 reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port)));
686 }
687
688 static void cal_wr_dma_config(struct cal_ctx *ctx,
689 unsigned int width)
690 {
691 u32 val;
692
693 val = reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port));
694 set_field(&val, ctx->csi2_port, CAL_WR_DMA_CTRL_CPORT_MASK);
695 set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
696 CAL_WR_DMA_CTRL_DTAG_MASK);
697 set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
698 CAL_WR_DMA_CTRL_MODE_MASK);
699 set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
700 CAL_WR_DMA_CTRL_PATTERN_MASK);
701 set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK);
702 reg_write(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port), val);
703 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->csi2_port,
704 reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port)));
705
706 /*
707 * width/16 not sure but giving it a whirl.
708 * zero does not work right
709 */
710 reg_write_field(ctx->dev,
711 CAL_WR_DMA_OFST(ctx->csi2_port),
712 (width / 16),
713 CAL_WR_DMA_OFST_MASK);
714 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->csi2_port,
715 reg_read(ctx->dev, CAL_WR_DMA_OFST(ctx->csi2_port)));
716
717 val = reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port));
718 /* 64 bit word means no skipping */
719 set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
720 /*
721 * (width*8)/64 this should be size of an entire line
722 * in 64bit word but 0 means all data until the end
723 * is detected automagically
724 */
725 set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK);
726 reg_write(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port), val);
727 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->csi2_port,
728 reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port)));
729 }
730
731 static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
732 {
733 reg_write(ctx->dev, CAL_WR_DMA_ADDR(ctx->csi2_port), dmaaddr);
734 }
735
736 /*
737 * TCLK values are OK at their reset values
738 */
739 #define TCLK_TERM 0
740 #define TCLK_MISS 1
741 #define TCLK_SETTLE 14
742 #define THS_SETTLE 15
743
744 static void csi2_phy_config(struct cal_ctx *ctx)
745 {
746 unsigned int reg0, reg1;
747 unsigned int ths_term, ths_settle;
748 unsigned int ddrclkperiod_us;
749
750 /*
751 * THS_TERM: Programmed value = floor(20 ns/DDRClk period) - 2.
752 */
753 ddrclkperiod_us = ctx->external_rate / 2000000;
754 ddrclkperiod_us = 1000000 / ddrclkperiod_us;
755 ctx_dbg(1, ctx, "ddrclkperiod_us: %d\n", ddrclkperiod_us);
756
757 ths_term = 20000 / ddrclkperiod_us;
758 ths_term = (ths_term >= 2) ? ths_term - 2 : ths_term;
759 ctx_dbg(1, ctx, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
760
761 /*
762 * THS_SETTLE: Programmed value = floor(176.3 ns/CtrlClk period) - 1.
763 * Since CtrlClk is fixed at 96Mhz then we get
764 * ths_settle = floor(176.3 / 10.416) - 1 = 15
765 * If we ever switch to a dynamic clock then this code might be useful
766 *
767 * unsigned int ctrlclkperiod_us;
768 * ctrlclkperiod_us = 96000000 / 1000000;
769 * ctrlclkperiod_us = 1000000 / ctrlclkperiod_us;
770 * ctx_dbg(1, ctx, "ctrlclkperiod_us: %d\n", ctrlclkperiod_us);
771
772 * ths_settle = 176300 / ctrlclkperiod_us;
773 * ths_settle = (ths_settle > 1) ? ths_settle - 1 : ths_settle;
774 */
775
776 ths_settle = THS_SETTLE;
777 ctx_dbg(1, ctx, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
778
779 reg0 = reg_read(ctx->cc, CAL_CSI2_PHY_REG0);
780 set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
781 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
782 set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
783 set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
784
785 ctx_dbg(1, ctx, "CSI2_%d_REG0 = 0x%08x\n", (ctx->csi2_port - 1), reg0);
786 reg_write(ctx->cc, CAL_CSI2_PHY_REG0, reg0);
787
788 reg1 = reg_read(ctx->cc, CAL_CSI2_PHY_REG1);
789 set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
790 set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
791 set_field(&reg1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
792 set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
793
794 ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x\n", (ctx->csi2_port - 1), reg1);
795 reg_write(ctx->cc, CAL_CSI2_PHY_REG1, reg1);
796 }
797
798 static int cal_get_external_info(struct cal_ctx *ctx)
799 {
800 struct v4l2_ctrl *ctrl;
801
802 if (!ctx->sensor)
803 return -ENODEV;
804
805 ctrl = v4l2_ctrl_find(ctx->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
806 if (!ctrl) {
807 ctx_err(ctx, "no pixel rate control in subdev: %s\n",
808 ctx->sensor->name);
809 return -EPIPE;
810 }
811
812 ctx->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
813 ctx_dbg(3, ctx, "sensor Pixel Rate: %d\n", ctx->external_rate);
814
815 return 0;
816 }
817
818 static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
819 {
820 struct cal_dmaqueue *dma_q = &ctx->vidq;
821 struct cal_buffer *buf;
822 unsigned long addr;
823
824 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
825 ctx->next_frm = buf;
826 list_del(&buf->list);
827
828 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
829 cal_wr_dma_addr(ctx, addr);
830 }
831
832 static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
833 {
834 ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
835 ctx->cur_frm->vb.field = ctx->m_fmt.field;
836 ctx->cur_frm->vb.sequence = ctx->sequence++;
837
838 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
839 ctx->cur_frm = ctx->next_frm;
840 }
841
842 #define isvcirqset(irq, vc, ff) (irq & \
843 (CAL_CSI2_VC_IRQENABLE_ ##ff ##_IRQ_##vc ##_MASK))
844
845 #define isportirqset(irq, port) (irq & CAL_HL_IRQ_MASK(port))
846
847 static irqreturn_t cal_irq(int irq_cal, void *data)
848 {
849 struct cal_dev *dev = (struct cal_dev *)data;
850 struct cal_ctx *ctx;
851 struct cal_dmaqueue *dma_q;
852 u32 irqst2, irqst3;
853
854 /* Check which DMA just finished */
855 irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2));
856 if (irqst2) {
857 /* Clear Interrupt status */
858 reg_write(dev, CAL_HL_IRQSTATUS(2), irqst2);
859
860 /* Need to check both port */
861 if (isportirqset(irqst2, 1)) {
862 ctx = dev->ctx[0];
863
864 if (ctx->cur_frm != ctx->next_frm)
865 cal_process_buffer_complete(ctx);
866 }
867
868 if (isportirqset(irqst2, 2)) {
869 ctx = dev->ctx[1];
870
871 if (ctx->cur_frm != ctx->next_frm)
872 cal_process_buffer_complete(ctx);
873 }
874 }
875
876 /* Check which DMA just started */
877 irqst3 = reg_read(dev, CAL_HL_IRQSTATUS(3));
878 if (irqst3) {
879 /* Clear Interrupt status */
880 reg_write(dev, CAL_HL_IRQSTATUS(3), irqst3);
881
882 /* Need to check both port */
883 if (isportirqset(irqst3, 1)) {
884 ctx = dev->ctx[0];
885 dma_q = &ctx->vidq;
886
887 spin_lock(&ctx->slock);
888 if (!list_empty(&dma_q->active) &&
889 ctx->cur_frm == ctx->next_frm)
890 cal_schedule_next_buffer(ctx);
891 spin_unlock(&ctx->slock);
892 }
893
894 if (isportirqset(irqst3, 2)) {
895 ctx = dev->ctx[1];
896 dma_q = &ctx->vidq;
897
898 spin_lock(&ctx->slock);
899 if (!list_empty(&dma_q->active) &&
900 ctx->cur_frm == ctx->next_frm)
901 cal_schedule_next_buffer(ctx);
902 spin_unlock(&ctx->slock);
903 }
904 }
905
906 return IRQ_HANDLED;
907 }
908
909 /*
910 * video ioctls
911 */
912 static int cal_querycap(struct file *file, void *priv,
913 struct v4l2_capability *cap)
914 {
915 struct cal_ctx *ctx = video_drvdata(file);
916
917 strlcpy(cap->driver, CAL_MODULE_NAME, sizeof(cap->driver));
918 strlcpy(cap->card, CAL_MODULE_NAME, sizeof(cap->card));
919
920 snprintf(cap->bus_info, sizeof(cap->bus_info),
921 "platform:%s", ctx->v4l2_dev.name);
922 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
923 V4L2_CAP_READWRITE;
924 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
925 return 0;
926 }
927
928 static int cal_enum_fmt_vid_cap(struct file *file, void *priv,
929 struct v4l2_fmtdesc *f)
930 {
931 struct cal_ctx *ctx = video_drvdata(file);
932 const struct cal_fmt *fmt = NULL;
933
934 if (f->index >= ctx->num_active_fmt)
935 return -EINVAL;
936
937 fmt = ctx->active_fmt[f->index];
938
939 f->pixelformat = fmt->fourcc;
940 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
941 return 0;
942 }
943
944 static int __subdev_get_format(struct cal_ctx *ctx,
945 struct v4l2_mbus_framefmt *fmt)
946 {
947 struct v4l2_subdev_format sd_fmt;
948 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
949 int ret;
950
951 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
952 sd_fmt.pad = 0;
953
954 ret = v4l2_subdev_call(ctx->sensor, pad, get_fmt, NULL, &sd_fmt);
955 if (ret)
956 return ret;
957
958 *fmt = *mbus_fmt;
959
960 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
961 fmt->width, fmt->height, fmt->code);
962
963 return 0;
964 }
965
966 static int __subdev_set_format(struct cal_ctx *ctx,
967 struct v4l2_mbus_framefmt *fmt)
968 {
969 struct v4l2_subdev_format sd_fmt;
970 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
971 int ret;
972
973 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
974 sd_fmt.pad = 0;
975 *mbus_fmt = *fmt;
976
977 ret = v4l2_subdev_call(ctx->sensor, pad, set_fmt, NULL, &sd_fmt);
978 if (ret)
979 return ret;
980
981 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
982 fmt->width, fmt->height, fmt->code);
983
984 return 0;
985 }
986
987 static int cal_calc_format_size(struct cal_ctx *ctx,
988 const struct cal_fmt *fmt,
989 struct v4l2_format *f)
990 {
991 if (!fmt) {
992 ctx_dbg(3, ctx, "No cal_fmt provided!\n");
993 return -EINVAL;
994 }
995
996 v4l_bound_align_image(&f->fmt.pix.width, 48, MAX_WIDTH, 2,
997 &f->fmt.pix.height, 32, MAX_HEIGHT, 0, 0);
998 f->fmt.pix.bytesperline = bytes_per_line(f->fmt.pix.width,
999 fmt->depth >> 3);
1000 f->fmt.pix.sizeimage = f->fmt.pix.height *
1001 f->fmt.pix.bytesperline;
1002
1003 ctx_dbg(3, ctx, "%s: fourcc: %s size: %dx%d bpl:%d img_size:%d\n",
1004 __func__, fourcc_to_str(f->fmt.pix.pixelformat),
1005 f->fmt.pix.width, f->fmt.pix.height,
1006 f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
1007
1008 return 0;
1009 }
1010
1011 static int cal_g_fmt_vid_cap(struct file *file, void *priv,
1012 struct v4l2_format *f)
1013 {
1014 struct cal_ctx *ctx = video_drvdata(file);
1015
1016 *f = ctx->v_fmt;
1017
1018 return 0;
1019 }
1020
1021 static int cal_try_fmt_vid_cap(struct file *file, void *priv,
1022 struct v4l2_format *f)
1023 {
1024 struct cal_ctx *ctx = video_drvdata(file);
1025 const struct cal_fmt *fmt;
1026 struct v4l2_subdev_frame_size_enum fse;
1027 int ret, found;
1028
1029 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1030 if (!fmt) {
1031 ctx_dbg(3, ctx, "Fourcc format (0x%08x) not found.\n",
1032 f->fmt.pix.pixelformat);
1033
1034 /* Just get the first one enumerated */
1035 fmt = ctx->active_fmt[0];
1036 f->fmt.pix.pixelformat = fmt->fourcc;
1037 }
1038
1039 f->fmt.pix.field = ctx->v_fmt.fmt.pix.field;
1040
1041 /* check for/find a valid width/height */
1042 ret = 0;
1043 found = false;
1044 fse.pad = 0;
1045 fse.code = fmt->code;
1046 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1047 for (fse.index = 0; ; fse.index++) {
1048 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_size,
1049 NULL, &fse);
1050 if (ret)
1051 break;
1052
1053 if ((f->fmt.pix.width == fse.max_width) &&
1054 (f->fmt.pix.height == fse.max_height)) {
1055 found = true;
1056 break;
1057 } else if ((f->fmt.pix.width >= fse.min_width) &&
1058 (f->fmt.pix.width <= fse.max_width) &&
1059 (f->fmt.pix.height >= fse.min_height) &&
1060 (f->fmt.pix.height <= fse.max_height)) {
1061 found = true;
1062 break;
1063 }
1064 }
1065
1066 if (!found) {
1067 /* use existing values as default */
1068 f->fmt.pix.width = ctx->v_fmt.fmt.pix.width;
1069 f->fmt.pix.height = ctx->v_fmt.fmt.pix.height;
1070 }
1071
1072 /*
1073 * Use current colorspace for now, it will get
1074 * updated properly during s_fmt
1075 */
1076 f->fmt.pix.colorspace = ctx->v_fmt.fmt.pix.colorspace;
1077 return cal_calc_format_size(ctx, fmt, f);
1078 }
1079
1080 static int cal_s_fmt_vid_cap(struct file *file, void *priv,
1081 struct v4l2_format *f)
1082 {
1083 struct cal_ctx *ctx = video_drvdata(file);
1084 struct vb2_queue *q = &ctx->vb_vidq;
1085 const struct cal_fmt *fmt;
1086 struct v4l2_mbus_framefmt mbus_fmt;
1087 int ret;
1088
1089 if (vb2_is_busy(q)) {
1090 ctx_dbg(3, ctx, "%s device busy\n", __func__);
1091 return -EBUSY;
1092 }
1093
1094 ret = cal_try_fmt_vid_cap(file, priv, f);
1095 if (ret < 0)
1096 return ret;
1097
1098 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1099
1100 v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
1101
1102 ret = __subdev_set_format(ctx, &mbus_fmt);
1103 if (ret)
1104 return ret;
1105
1106 /* Just double check nothing has gone wrong */
1107 if (mbus_fmt.code != fmt->code) {
1108 ctx_dbg(3, ctx,
1109 "%s subdev changed format on us, this should not happen\n",
1110 __func__);
1111 return -EINVAL;
1112 }
1113
1114 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
1115 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1116 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1117 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
1118 ctx->fmt = fmt;
1119 ctx->m_fmt = mbus_fmt;
1120 *f = ctx->v_fmt;
1121
1122 return 0;
1123 }
1124
1125 static int cal_enum_framesizes(struct file *file, void *fh,
1126 struct v4l2_frmsizeenum *fsize)
1127 {
1128 struct cal_ctx *ctx = video_drvdata(file);
1129 const struct cal_fmt *fmt;
1130 struct v4l2_subdev_frame_size_enum fse;
1131 int ret;
1132
1133 /* check for valid format */
1134 fmt = find_format_by_pix(ctx, fsize->pixel_format);
1135 if (!fmt) {
1136 ctx_dbg(3, ctx, "Invalid pixel code: %x\n",
1137 fsize->pixel_format);
1138 return -EINVAL;
1139 }
1140
1141 fse.index = fsize->index;
1142 fse.pad = 0;
1143 fse.code = fmt->code;
1144
1145 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_size, NULL, &fse);
1146 if (ret)
1147 return ret;
1148
1149 ctx_dbg(1, ctx, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
1150 __func__, fse.index, fse.code, fse.min_width, fse.max_width,
1151 fse.min_height, fse.max_height);
1152
1153 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1154 fsize->discrete.width = fse.max_width;
1155 fsize->discrete.height = fse.max_height;
1156
1157 return 0;
1158 }
1159
1160 static int cal_enum_input(struct file *file, void *priv,
1161 struct v4l2_input *inp)
1162 {
1163 if (inp->index >= CAL_NUM_INPUT)
1164 return -EINVAL;
1165
1166 inp->type = V4L2_INPUT_TYPE_CAMERA;
1167 sprintf(inp->name, "Camera %u", inp->index);
1168 return 0;
1169 }
1170
1171 static int cal_g_input(struct file *file, void *priv, unsigned int *i)
1172 {
1173 struct cal_ctx *ctx = video_drvdata(file);
1174
1175 *i = ctx->input;
1176 return 0;
1177 }
1178
1179 static int cal_s_input(struct file *file, void *priv, unsigned int i)
1180 {
1181 struct cal_ctx *ctx = video_drvdata(file);
1182
1183 if (i >= CAL_NUM_INPUT)
1184 return -EINVAL;
1185
1186 ctx->input = i;
1187 return 0;
1188 }
1189
1190 /* timeperframe is arbitrary and continuous */
1191 static int cal_enum_frameintervals(struct file *file, void *priv,
1192 struct v4l2_frmivalenum *fival)
1193 {
1194 struct cal_ctx *ctx = video_drvdata(file);
1195 const struct cal_fmt *fmt;
1196 struct v4l2_subdev_frame_interval_enum fie = {
1197 .index = fival->index,
1198 .width = fival->width,
1199 .height = fival->height,
1200 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1201 };
1202 int ret;
1203
1204 fmt = find_format_by_pix(ctx, fival->pixel_format);
1205 if (!fmt)
1206 return -EINVAL;
1207
1208 fie.code = fmt->code;
1209 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_interval,
1210 NULL, &fie);
1211 if (ret)
1212 return ret;
1213 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1214 fival->discrete = fie.interval;
1215
1216 return 0;
1217 }
1218
1219 /*
1220 * Videobuf operations
1221 */
1222 static int cal_queue_setup(struct vb2_queue *vq,
1223 unsigned int *nbuffers, unsigned int *nplanes,
1224 unsigned int sizes[], struct device *alloc_devs[])
1225 {
1226 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1227 unsigned size = ctx->v_fmt.fmt.pix.sizeimage;
1228
1229 if (vq->num_buffers + *nbuffers < 3)
1230 *nbuffers = 3 - vq->num_buffers;
1231
1232 if (*nplanes) {
1233 if (sizes[0] < size)
1234 return -EINVAL;
1235 size = sizes[0];
1236 }
1237
1238 *nplanes = 1;
1239 sizes[0] = size;
1240
1241 ctx_dbg(3, ctx, "nbuffers=%d, size=%d\n", *nbuffers, sizes[0]);
1242
1243 return 0;
1244 }
1245
1246 static int cal_buffer_prepare(struct vb2_buffer *vb)
1247 {
1248 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1249 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1250 vb.vb2_buf);
1251 unsigned long size;
1252
1253 if (WARN_ON(!ctx->fmt))
1254 return -EINVAL;
1255
1256 size = ctx->v_fmt.fmt.pix.sizeimage;
1257 if (vb2_plane_size(vb, 0) < size) {
1258 ctx_err(ctx,
1259 "data will not fit into plane (%lu < %lu)\n",
1260 vb2_plane_size(vb, 0), size);
1261 return -EINVAL;
1262 }
1263
1264 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1265 return 0;
1266 }
1267
1268 static void cal_buffer_queue(struct vb2_buffer *vb)
1269 {
1270 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1271 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1272 vb.vb2_buf);
1273 struct cal_dmaqueue *vidq = &ctx->vidq;
1274 unsigned long flags = 0;
1275
1276 /* recheck locking */
1277 spin_lock_irqsave(&ctx->slock, flags);
1278 list_add_tail(&buf->list, &vidq->active);
1279 spin_unlock_irqrestore(&ctx->slock, flags);
1280 }
1281
1282 static int cal_start_streaming(struct vb2_queue *vq, unsigned int count)
1283 {
1284 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1285 struct cal_dmaqueue *dma_q = &ctx->vidq;
1286 struct cal_buffer *buf, *tmp;
1287 unsigned long addr = 0;
1288 unsigned long flags;
1289 int ret;
1290
1291 spin_lock_irqsave(&ctx->slock, flags);
1292 if (list_empty(&dma_q->active)) {
1293 spin_unlock_irqrestore(&ctx->slock, flags);
1294 ctx_dbg(3, ctx, "buffer queue is empty\n");
1295 return -EIO;
1296 }
1297
1298 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
1299 ctx->cur_frm = buf;
1300 ctx->next_frm = buf;
1301 list_del(&buf->list);
1302 spin_unlock_irqrestore(&ctx->slock, flags);
1303
1304 addr = vb2_dma_contig_plane_dma_addr(&ctx->cur_frm->vb.vb2_buf, 0);
1305 ctx->sequence = 0;
1306
1307 ret = cal_get_external_info(ctx);
1308 if (ret < 0)
1309 goto err;
1310
1311 cal_runtime_get(ctx->dev);
1312
1313 enable_irqs(ctx);
1314 camerarx_phy_enable(ctx);
1315 csi2_init(ctx);
1316 csi2_phy_config(ctx);
1317 csi2_lane_config(ctx);
1318 csi2_ctx_config(ctx);
1319 pix_proc_config(ctx);
1320 cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline);
1321 cal_wr_dma_addr(ctx, addr);
1322 csi2_ppi_enable(ctx);
1323
1324 ret = v4l2_subdev_call(ctx->sensor, video, s_stream, 1);
1325 if (ret) {
1326 ctx_err(ctx, "stream on failed in subdev\n");
1327 cal_runtime_put(ctx->dev);
1328 goto err;
1329 }
1330
1331 if (debug >= 4)
1332 cal_quickdump_regs(ctx->dev);
1333
1334 return 0;
1335
1336 err:
1337 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1338 list_del(&buf->list);
1339 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1340 }
1341 return ret;
1342 }
1343
1344 static void cal_stop_streaming(struct vb2_queue *vq)
1345 {
1346 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1347 struct cal_dmaqueue *dma_q = &ctx->vidq;
1348 struct cal_buffer *buf, *tmp;
1349 unsigned long flags;
1350
1351 if (v4l2_subdev_call(ctx->sensor, video, s_stream, 0))
1352 ctx_err(ctx, "stream off failed in subdev\n");
1353
1354 csi2_ppi_disable(ctx);
1355 disable_irqs(ctx);
1356
1357 /* Release all active buffers */
1358 spin_lock_irqsave(&ctx->slock, flags);
1359 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1360 list_del(&buf->list);
1361 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1362 }
1363
1364 if (ctx->cur_frm == ctx->next_frm) {
1365 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1366 } else {
1367 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1368 vb2_buffer_done(&ctx->next_frm->vb.vb2_buf,
1369 VB2_BUF_STATE_ERROR);
1370 }
1371 ctx->cur_frm = NULL;
1372 ctx->next_frm = NULL;
1373 spin_unlock_irqrestore(&ctx->slock, flags);
1374
1375 cal_runtime_put(ctx->dev);
1376 }
1377
1378 static const struct vb2_ops cal_video_qops = {
1379 .queue_setup = cal_queue_setup,
1380 .buf_prepare = cal_buffer_prepare,
1381 .buf_queue = cal_buffer_queue,
1382 .start_streaming = cal_start_streaming,
1383 .stop_streaming = cal_stop_streaming,
1384 .wait_prepare = vb2_ops_wait_prepare,
1385 .wait_finish = vb2_ops_wait_finish,
1386 };
1387
1388 static const struct v4l2_file_operations cal_fops = {
1389 .owner = THIS_MODULE,
1390 .open = v4l2_fh_open,
1391 .release = vb2_fop_release,
1392 .read = vb2_fop_read,
1393 .poll = vb2_fop_poll,
1394 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
1395 .mmap = vb2_fop_mmap,
1396 };
1397
1398 static const struct v4l2_ioctl_ops cal_ioctl_ops = {
1399 .vidioc_querycap = cal_querycap,
1400 .vidioc_enum_fmt_vid_cap = cal_enum_fmt_vid_cap,
1401 .vidioc_g_fmt_vid_cap = cal_g_fmt_vid_cap,
1402 .vidioc_try_fmt_vid_cap = cal_try_fmt_vid_cap,
1403 .vidioc_s_fmt_vid_cap = cal_s_fmt_vid_cap,
1404 .vidioc_enum_framesizes = cal_enum_framesizes,
1405 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1406 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1407 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1408 .vidioc_querybuf = vb2_ioctl_querybuf,
1409 .vidioc_qbuf = vb2_ioctl_qbuf,
1410 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1411 .vidioc_enum_input = cal_enum_input,
1412 .vidioc_g_input = cal_g_input,
1413 .vidioc_s_input = cal_s_input,
1414 .vidioc_enum_frameintervals = cal_enum_frameintervals,
1415 .vidioc_streamon = vb2_ioctl_streamon,
1416 .vidioc_streamoff = vb2_ioctl_streamoff,
1417 .vidioc_log_status = v4l2_ctrl_log_status,
1418 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1419 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1420 };
1421
1422 static struct video_device cal_videodev = {
1423 .name = CAL_MODULE_NAME,
1424 .fops = &cal_fops,
1425 .ioctl_ops = &cal_ioctl_ops,
1426 .minor = -1,
1427 .release = video_device_release_empty,
1428 };
1429
1430 /* -----------------------------------------------------------------
1431 * Initialization and module stuff
1432 * ------------------------------------------------------------------
1433 */
1434 static int cal_complete_ctx(struct cal_ctx *ctx);
1435
1436 static int cal_async_bound(struct v4l2_async_notifier *notifier,
1437 struct v4l2_subdev *subdev,
1438 struct v4l2_async_subdev *asd)
1439 {
1440 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1441 struct v4l2_subdev_mbus_code_enum mbus_code;
1442 int ret = 0;
1443 int i, j, k;
1444
1445 if (ctx->sensor) {
1446 ctx_info(ctx, "Rejecting subdev %s (Already set!!)",
1447 subdev->name);
1448 return 0;
1449 }
1450
1451 ctx->sensor = subdev;
1452 ctx_dbg(1, ctx, "Using sensor %s for capture\n", subdev->name);
1453
1454 /* Enumerate sub device formats and enable all matching local formats */
1455 ctx->num_active_fmt = 0;
1456 for (j = 0, i = 0; ret != -EINVAL; ++j) {
1457 struct cal_fmt *fmt;
1458
1459 memset(&mbus_code, 0, sizeof(mbus_code));
1460 mbus_code.index = j;
1461 ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
1462 NULL, &mbus_code);
1463 if (ret)
1464 continue;
1465
1466 ctx_dbg(2, ctx,
1467 "subdev %s: code: %04x idx: %d\n",
1468 subdev->name, mbus_code.code, j);
1469
1470 for (k = 0; k < ARRAY_SIZE(cal_formats); k++) {
1471 fmt = &cal_formats[k];
1472
1473 if (mbus_code.code == fmt->code) {
1474 ctx->active_fmt[i] = fmt;
1475 ctx_dbg(2, ctx,
1476 "matched fourcc: %s: code: %04x idx: %d\n",
1477 fourcc_to_str(fmt->fourcc),
1478 fmt->code, i);
1479 ctx->num_active_fmt = ++i;
1480 }
1481 }
1482 }
1483
1484 if (i == 0) {
1485 ctx_err(ctx, "No suitable format reported by subdev %s\n",
1486 subdev->name);
1487 return -EINVAL;
1488 }
1489
1490 cal_complete_ctx(ctx);
1491
1492 return 0;
1493 }
1494
1495 static int cal_async_complete(struct v4l2_async_notifier *notifier)
1496 {
1497 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1498 const struct cal_fmt *fmt;
1499 struct v4l2_mbus_framefmt mbus_fmt;
1500 int ret;
1501
1502 ret = __subdev_get_format(ctx, &mbus_fmt);
1503 if (ret)
1504 return ret;
1505
1506 fmt = find_format_by_code(ctx, mbus_fmt.code);
1507 if (!fmt) {
1508 ctx_dbg(3, ctx, "mbus code format (0x%08x) not found.\n",
1509 mbus_fmt.code);
1510 return -EINVAL;
1511 }
1512
1513 /* Save current subdev format */
1514 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
1515 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1516 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1517 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
1518 ctx->fmt = fmt;
1519 ctx->m_fmt = mbus_fmt;
1520
1521 return 0;
1522 }
1523
1524 static int cal_complete_ctx(struct cal_ctx *ctx)
1525 {
1526 struct video_device *vfd;
1527 struct vb2_queue *q;
1528 int ret;
1529
1530 ctx->timeperframe = tpf_default;
1531 ctx->external_rate = 192000000;
1532
1533 /* initialize locks */
1534 spin_lock_init(&ctx->slock);
1535 mutex_init(&ctx->mutex);
1536
1537 /* initialize queue */
1538 q = &ctx->vb_vidq;
1539 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1540 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1541 q->drv_priv = ctx;
1542 q->buf_struct_size = sizeof(struct cal_buffer);
1543 q->ops = &cal_video_qops;
1544 q->mem_ops = &vb2_dma_contig_memops;
1545 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1546 q->lock = &ctx->mutex;
1547 q->min_buffers_needed = 3;
1548 q->dev = ctx->v4l2_dev.dev;
1549
1550 ret = vb2_queue_init(q);
1551 if (ret)
1552 return ret;
1553
1554 /* init video dma queues */
1555 INIT_LIST_HEAD(&ctx->vidq.active);
1556
1557 vfd = &ctx->vdev;
1558 *vfd = cal_videodev;
1559 vfd->v4l2_dev = &ctx->v4l2_dev;
1560 vfd->queue = q;
1561
1562 /*
1563 * Provide a mutex to v4l2 core. It will be used to protect
1564 * all fops and v4l2 ioctls.
1565 */
1566 vfd->lock = &ctx->mutex;
1567 video_set_drvdata(vfd, ctx);
1568
1569 ret = video_register_device(vfd, VFL_TYPE_GRABBER, video_nr);
1570 if (ret < 0)
1571 return ret;
1572
1573 v4l2_info(&ctx->v4l2_dev, "V4L2 device registered as %s\n",
1574 video_device_node_name(vfd));
1575
1576 return 0;
1577 }
1578
1579 static struct device_node *
1580 of_get_next_port(const struct device_node *parent,
1581 struct device_node *prev)
1582 {
1583 struct device_node *port = NULL;
1584
1585 if (!parent)
1586 return NULL;
1587
1588 if (!prev) {
1589 struct device_node *ports;
1590 /*
1591 * It's the first call, we have to find a port subnode
1592 * within this node or within an optional 'ports' node.
1593 */
1594 ports = of_get_child_by_name(parent, "ports");
1595 if (ports)
1596 parent = ports;
1597
1598 port = of_get_child_by_name(parent, "port");
1599
1600 /* release the 'ports' node */
1601 of_node_put(ports);
1602 } else {
1603 struct device_node *ports;
1604
1605 ports = of_get_parent(prev);
1606 if (!ports)
1607 return NULL;
1608
1609 do {
1610 port = of_get_next_child(ports, prev);
1611 if (!port) {
1612 of_node_put(ports);
1613 return NULL;
1614 }
1615 prev = port;
1616 } while (of_node_cmp(port->name, "port") != 0);
1617 }
1618
1619 return port;
1620 }
1621
1622 static struct device_node *
1623 of_get_next_endpoint(const struct device_node *parent,
1624 struct device_node *prev)
1625 {
1626 struct device_node *ep = NULL;
1627
1628 if (!parent)
1629 return NULL;
1630
1631 do {
1632 ep = of_get_next_child(parent, prev);
1633 if (!ep)
1634 return NULL;
1635 prev = ep;
1636 } while (of_node_cmp(ep->name, "endpoint") != 0);
1637
1638 return ep;
1639 }
1640
1641 static int of_cal_create_instance(struct cal_ctx *ctx, int inst)
1642 {
1643 struct platform_device *pdev = ctx->dev->pdev;
1644 struct device_node *ep_node, *port, *remote_ep,
1645 *sensor_node, *parent;
1646 struct v4l2_of_endpoint *endpoint;
1647 struct v4l2_async_subdev *asd;
1648 u32 regval = 0;
1649 int ret, index, found_port = 0, lane;
1650
1651 parent = pdev->dev.of_node;
1652
1653 asd = &ctx->asd;
1654 endpoint = &ctx->endpoint;
1655
1656 ep_node = NULL;
1657 port = NULL;
1658 remote_ep = NULL;
1659 sensor_node = NULL;
1660 ret = -EINVAL;
1661
1662 ctx_dbg(3, ctx, "Scanning Port node for csi2 port: %d\n", inst);
1663 for (index = 0; index < CAL_NUM_CSI2_PORTS; index++) {
1664 port = of_get_next_port(parent, port);
1665 if (!port) {
1666 ctx_dbg(1, ctx, "No port node found for csi2 port:%d\n",
1667 index);
1668 goto cleanup_exit;
1669 }
1670
1671 /* Match the slice number with <REG> */
1672 of_property_read_u32(port, "reg", &regval);
1673 ctx_dbg(3, ctx, "port:%d inst:%d <reg>:%d\n",
1674 index, inst, regval);
1675 if ((regval == inst) && (index == inst)) {
1676 found_port = 1;
1677 break;
1678 }
1679 }
1680
1681 if (!found_port) {
1682 ctx_dbg(1, ctx, "No port node matches csi2 port:%d\n",
1683 inst);
1684 goto cleanup_exit;
1685 }
1686
1687 ctx_dbg(3, ctx, "Scanning sub-device for csi2 port: %d\n",
1688 inst);
1689
1690 ep_node = of_get_next_endpoint(port, ep_node);
1691 if (!ep_node) {
1692 ctx_dbg(3, ctx, "can't get next endpoint\n");
1693 goto cleanup_exit;
1694 }
1695
1696 sensor_node = of_graph_get_remote_port_parent(ep_node);
1697 if (!sensor_node) {
1698 ctx_dbg(3, ctx, "can't get remote parent\n");
1699 goto cleanup_exit;
1700 }
1701 asd->match_type = V4L2_ASYNC_MATCH_OF;
1702 asd->match.of.node = sensor_node;
1703
1704 remote_ep = of_parse_phandle(ep_node, "remote-endpoint", 0);
1705 if (!remote_ep) {
1706 ctx_dbg(3, ctx, "can't get remote-endpoint\n");
1707 goto cleanup_exit;
1708 }
1709 v4l2_of_parse_endpoint(remote_ep, endpoint);
1710
1711 if (endpoint->bus_type != V4L2_MBUS_CSI2) {
1712 ctx_err(ctx, "Port:%d sub-device %s is not a CSI2 device\n",
1713 inst, sensor_node->name);
1714 goto cleanup_exit;
1715 }
1716
1717 /* Store Virtual Channel number */
1718 ctx->virtual_channel = endpoint->base.id;
1719
1720 ctx_dbg(3, ctx, "Port:%d v4l2-endpoint: CSI2\n", inst);
1721 ctx_dbg(3, ctx, "Virtual Channel=%d\n", ctx->virtual_channel);
1722 ctx_dbg(3, ctx, "flags=0x%08x\n", endpoint->bus.mipi_csi2.flags);
1723 ctx_dbg(3, ctx, "clock_lane=%d\n", endpoint->bus.mipi_csi2.clock_lane);
1724 ctx_dbg(3, ctx, "num_data_lanes=%d\n",
1725 endpoint->bus.mipi_csi2.num_data_lanes);
1726 ctx_dbg(3, ctx, "data_lanes= <\n");
1727 for (lane = 0; lane < endpoint->bus.mipi_csi2.num_data_lanes; lane++)
1728 ctx_dbg(3, ctx, "\t%d\n",
1729 endpoint->bus.mipi_csi2.data_lanes[lane]);
1730 ctx_dbg(3, ctx, "\t>\n");
1731
1732 ctx_dbg(1, ctx, "Port: %d found sub-device %s\n",
1733 inst, sensor_node->name);
1734
1735 ctx->asd_list[0] = asd;
1736 ctx->notifier.subdevs = ctx->asd_list;
1737 ctx->notifier.num_subdevs = 1;
1738 ctx->notifier.bound = cal_async_bound;
1739 ctx->notifier.complete = cal_async_complete;
1740 ret = v4l2_async_notifier_register(&ctx->v4l2_dev,
1741 &ctx->notifier);
1742 if (ret) {
1743 ctx_err(ctx, "Error registering async notifier\n");
1744 ret = -EINVAL;
1745 }
1746
1747 cleanup_exit:
1748 if (remote_ep)
1749 of_node_put(remote_ep);
1750 if (sensor_node)
1751 of_node_put(sensor_node);
1752 if (ep_node)
1753 of_node_put(ep_node);
1754 if (port)
1755 of_node_put(port);
1756
1757 return ret;
1758 }
1759
1760 static struct cal_ctx *cal_create_instance(struct cal_dev *dev, int inst)
1761 {
1762 struct cal_ctx *ctx;
1763 struct v4l2_ctrl_handler *hdl;
1764 int ret;
1765
1766 ctx = devm_kzalloc(&dev->pdev->dev, sizeof(*ctx), GFP_KERNEL);
1767 if (!ctx)
1768 return NULL;
1769
1770 /* save the cal_dev * for future ref */
1771 ctx->dev = dev;
1772
1773 snprintf(ctx->v4l2_dev.name, sizeof(ctx->v4l2_dev.name),
1774 "%s-%03d", CAL_MODULE_NAME, inst);
1775 ret = v4l2_device_register(&dev->pdev->dev, &ctx->v4l2_dev);
1776 if (ret)
1777 goto err_exit;
1778
1779 hdl = &ctx->ctrl_handler;
1780 ret = v4l2_ctrl_handler_init(hdl, 11);
1781 if (ret) {
1782 ctx_err(ctx, "Failed to init ctrl handler\n");
1783 goto unreg_dev;
1784 }
1785 ctx->v4l2_dev.ctrl_handler = hdl;
1786
1787 /* Make sure Camera Core H/W register area is available */
1788 ctx->cc = dev->cc[inst];
1789
1790 /* Store the instance id */
1791 ctx->csi2_port = inst + 1;
1792
1793 ret = of_cal_create_instance(ctx, inst);
1794 if (ret) {
1795 ret = -EINVAL;
1796 goto free_hdl;
1797 }
1798 return ctx;
1799
1800 free_hdl:
1801 v4l2_ctrl_handler_free(hdl);
1802 unreg_dev:
1803 v4l2_device_unregister(&ctx->v4l2_dev);
1804 err_exit:
1805 return NULL;
1806 }
1807
1808 static int cal_probe(struct platform_device *pdev)
1809 {
1810 struct cal_dev *dev;
1811 int ret;
1812 int irq;
1813
1814 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1815 if (!dev)
1816 return -ENOMEM;
1817
1818 /* set pseudo v4l2 device name so we can use v4l2_printk */
1819 strlcpy(dev->v4l2_dev.name, CAL_MODULE_NAME,
1820 sizeof(dev->v4l2_dev.name));
1821
1822 /* save pdev pointer */
1823 dev->pdev = pdev;
1824
1825 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1826 "cal_top");
1827 dev->base = devm_ioremap_resource(&pdev->dev, dev->res);
1828 if (IS_ERR(dev->base))
1829 return PTR_ERR(dev->base);
1830
1831 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
1832 dev->res->name, &dev->res->start, &dev->res->end);
1833
1834 irq = platform_get_irq(pdev, 0);
1835 cal_dbg(1, dev, "got irq# %d\n", irq);
1836 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
1837 dev);
1838 if (ret)
1839 return ret;
1840
1841 platform_set_drvdata(pdev, dev);
1842
1843 dev->cm = cm_create(dev);
1844 if (IS_ERR(dev->cm))
1845 return PTR_ERR(dev->cm);
1846
1847 dev->cc[0] = cc_create(dev, 0);
1848 if (IS_ERR(dev->cc[0]))
1849 return PTR_ERR(dev->cc[0]);
1850
1851 dev->cc[1] = cc_create(dev, 1);
1852 if (IS_ERR(dev->cc[1]))
1853 return PTR_ERR(dev->cc[1]);
1854
1855 dev->ctx[0] = NULL;
1856 dev->ctx[1] = NULL;
1857
1858 dev->ctx[0] = cal_create_instance(dev, 0);
1859 dev->ctx[1] = cal_create_instance(dev, 1);
1860 if (!dev->ctx[0] && !dev->ctx[1]) {
1861 cal_err(dev, "Neither port is configured, no point in staying up\n");
1862 return -ENODEV;
1863 }
1864
1865 pm_runtime_enable(&pdev->dev);
1866
1867 ret = cal_runtime_get(dev);
1868 if (ret)
1869 goto runtime_disable;
1870
1871 /* Just check we can actually access the module */
1872 cal_get_hwinfo(dev);
1873
1874 cal_runtime_put(dev);
1875
1876 return 0;
1877
1878 runtime_disable:
1879 pm_runtime_disable(&pdev->dev);
1880 return ret;
1881 }
1882
1883 static int cal_remove(struct platform_device *pdev)
1884 {
1885 struct cal_dev *dev =
1886 (struct cal_dev *)platform_get_drvdata(pdev);
1887 struct cal_ctx *ctx;
1888 int i;
1889
1890 cal_dbg(1, dev, "Removing %s\n", CAL_MODULE_NAME);
1891
1892 cal_runtime_get(dev);
1893
1894 for (i = 0; i < CAL_NUM_CONTEXT; i++) {
1895 ctx = dev->ctx[i];
1896 if (ctx) {
1897 ctx_dbg(1, ctx, "unregistering %s\n",
1898 video_device_node_name(&ctx->vdev));
1899 camerarx_phy_disable(ctx);
1900 v4l2_async_notifier_unregister(&ctx->notifier);
1901 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1902 v4l2_device_unregister(&ctx->v4l2_dev);
1903 video_unregister_device(&ctx->vdev);
1904 }
1905 }
1906
1907 cal_runtime_put(dev);
1908 pm_runtime_disable(&pdev->dev);
1909
1910 return 0;
1911 }
1912
1913 #if defined(CONFIG_OF)
1914 static const struct of_device_id cal_of_match[] = {
1915 { .compatible = "ti,dra72-cal", },
1916 {},
1917 };
1918 MODULE_DEVICE_TABLE(of, cal_of_match);
1919 #endif
1920
1921 static struct platform_driver cal_pdrv = {
1922 .probe = cal_probe,
1923 .remove = cal_remove,
1924 .driver = {
1925 .name = CAL_MODULE_NAME,
1926 .of_match_table = of_match_ptr(cal_of_match),
1927 },
1928 };
1929
1930 module_platform_driver(cal_pdrv);
Linux with added FPC-III support