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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / media / rc / nuvoton-cir.c
blob4b78c891eb7794935390b7bd60aacb4fb6a0886c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline struct device *nvt_get_dev(const struct nvt_dev *nvt)
52 {
53 return nvt->rdev->dev.parent;
54 }
55
56 static inline bool is_w83667hg(struct nvt_dev *nvt)
57 {
58 return nvt->chip_ver == NVT_W83667HG;
59 }
60
61 /* write val to config reg */
62 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
63 {
64 outb(reg, nvt->cr_efir);
65 outb(val, nvt->cr_efdr);
66 }
67
68 /* read val from config reg */
69 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
70 {
71 outb(reg, nvt->cr_efir);
72 return inb(nvt->cr_efdr);
73 }
74
75 /* update config register bit without changing other bits */
76 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
77 {
78 u8 tmp = nvt_cr_read(nvt, reg) | val;
79 nvt_cr_write(nvt, tmp, reg);
80 }
81
82 /* clear config register bit without changing other bits */
83 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
84 {
85 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
86 nvt_cr_write(nvt, tmp, reg);
87 }
88
89 /* enter extended function mode */
90 static inline int nvt_efm_enable(struct nvt_dev *nvt)
91 {
92 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
93 return -EBUSY;
94
95 /* Enabling Extended Function Mode explicitly requires writing 2x */
96 outb(EFER_EFM_ENABLE, nvt->cr_efir);
97 outb(EFER_EFM_ENABLE, nvt->cr_efir);
98
99 return 0;
100 }
101
102 /* exit extended function mode */
103 static inline void nvt_efm_disable(struct nvt_dev *nvt)
104 {
105 outb(EFER_EFM_DISABLE, nvt->cr_efir);
106
107 release_region(nvt->cr_efir, 2);
108 }
109
110 /*
111 * When you want to address a specific logical device, write its logical
112 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
113 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
114 */
115 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
116 {
117 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
118 }
119
120 /* select and enable logical device with setting EFM mode*/
121 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
122 {
123 nvt_efm_enable(nvt);
124 nvt_select_logical_dev(nvt, ldev);
125 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
126 nvt_efm_disable(nvt);
127 }
128
129 /* select and disable logical device with setting EFM mode*/
130 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
131 {
132 nvt_efm_enable(nvt);
133 nvt_select_logical_dev(nvt, ldev);
134 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
135 nvt_efm_disable(nvt);
136 }
137
138 /* write val to cir config register */
139 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
140 {
141 outb(val, nvt->cir_addr + offset);
142 }
143
144 /* read val from cir config register */
145 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
146 {
147 return inb(nvt->cir_addr + offset);
148 }
149
150 /* write val to cir wake register */
151 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
152 u8 val, u8 offset)
153 {
154 outb(val, nvt->cir_wake_addr + offset);
155 }
156
157 /* read val from cir wake config register */
158 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
159 {
160 return inb(nvt->cir_wake_addr + offset);
161 }
162
163 /* don't override io address if one is set already */
164 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
165 {
166 unsigned long old_addr;
167
168 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
169 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
170
171 if (old_addr)
172 *ioaddr = old_addr;
173 else {
174 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
175 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
176 }
177 }
178
179 static ssize_t wakeup_data_show(struct device *dev,
180 struct device_attribute *attr,
181 char *buf)
182 {
183 struct rc_dev *rc_dev = to_rc_dev(dev);
184 struct nvt_dev *nvt = rc_dev->priv;
185 int fifo_len, duration;
186 unsigned long flags;
187 ssize_t buf_len = 0;
188 int i;
189
190 spin_lock_irqsave(&nvt->lock, flags);
191
192 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
193 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
194
195 /* go to first element to be read */
196 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
198
199 for (i = 0; i < fifo_len; i++) {
200 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
201 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
202 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
203 "%d ", duration);
204 }
205 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
206
207 spin_unlock_irqrestore(&nvt->lock, flags);
208
209 return buf_len;
210 }
211
212 static ssize_t wakeup_data_store(struct device *dev,
213 struct device_attribute *attr,
214 const char *buf, size_t len)
215 {
216 struct rc_dev *rc_dev = to_rc_dev(dev);
217 struct nvt_dev *nvt = rc_dev->priv;
218 unsigned long flags;
219 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
220 char **argv;
221 int i, count;
222 unsigned int val;
223 ssize_t ret;
224
225 argv = argv_split(GFP_KERNEL, buf, &count);
226 if (!argv)
227 return -ENOMEM;
228 if (!count || count > WAKEUP_MAX_SIZE) {
229 ret = -EINVAL;
230 goto out;
231 }
232
233 for (i = 0; i < count; i++) {
234 ret = kstrtouint(argv[i], 10, &val);
235 if (ret)
236 goto out;
237 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
238 if (!val || val > 0x7f) {
239 ret = -EINVAL;
240 goto out;
241 }
242 wake_buf[i] = val;
243 /* sequence must start with a pulse */
244 if (i % 2 == 0)
245 wake_buf[i] |= BUF_PULSE_BIT;
246 }
247
248 /* hardcode the tolerance to 10% */
249 tolerance = DIV_ROUND_UP(count, 10);
250
251 spin_lock_irqsave(&nvt->lock, flags);
252
253 nvt_clear_cir_wake_fifo(nvt);
254 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
255 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
256
257 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
258
259 /* enable writes to wake fifo */
260 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
261 CIR_WAKE_IRCON);
262
263 for (i = 0; i < count; i++)
264 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
265
266 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
267
268 spin_unlock_irqrestore(&nvt->lock, flags);
269
270 ret = len;
271 out:
272 argv_free(argv);
273 return ret;
274 }
275 static DEVICE_ATTR_RW(wakeup_data);
276
277 /* dump current cir register contents */
278 static void cir_dump_regs(struct nvt_dev *nvt)
279 {
280 nvt_efm_enable(nvt);
281 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
282
283 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
284 pr_info(" * CR CIR ACTIVE : 0x%x\n",
285 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
286 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
287 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
288 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
289 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
290 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
291
292 nvt_efm_disable(nvt);
293
294 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
295 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
296 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
297 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
298 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
299 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
300 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
301 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
302 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
303 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
304 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
305 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
306 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
307 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
308 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
309 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
310 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
311 }
312
313 /* dump current cir wake register contents */
314 static void cir_wake_dump_regs(struct nvt_dev *nvt)
315 {
316 u8 i, fifo_len;
317
318 nvt_efm_enable(nvt);
319 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
320
321 pr_info("%s: Dump CIR WAKE logical device registers:\n",
322 NVT_DRIVER_NAME);
323 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
324 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
325 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
326 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
327 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
328 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
329 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
330
331 nvt_efm_disable(nvt);
332
333 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
334 pr_info(" * IRCON: 0x%x\n",
335 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
336 pr_info(" * IRSTS: 0x%x\n",
337 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
338 pr_info(" * IREN: 0x%x\n",
339 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
340 pr_info(" * FIFO CMP DEEP: 0x%x\n",
341 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
342 pr_info(" * FIFO CMP TOL: 0x%x\n",
343 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
344 pr_info(" * FIFO COUNT: 0x%x\n",
345 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
346 pr_info(" * SLCH: 0x%x\n",
347 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
348 pr_info(" * SLCL: 0x%x\n",
349 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
350 pr_info(" * FIFOCON: 0x%x\n",
351 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
352 pr_info(" * SRXFSTS: 0x%x\n",
353 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
354 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
355 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
356 pr_info(" * WR FIFO DATA: 0x%x\n",
357 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
358 pr_info(" * RD FIFO ONLY: 0x%x\n",
359 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
360 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
361 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
362 pr_info(" * FIFO IGNORE: 0x%x\n",
363 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
364 pr_info(" * IRFSM: 0x%x\n",
365 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
366
367 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
368 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
369 pr_info("* Contents =");
370 for (i = 0; i < fifo_len; i++)
371 pr_cont(" %02x",
372 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
373 pr_cont("\n");
374 }
375
376 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
377 {
378 int i;
379
380 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
381 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
382 nvt->chip_ver = nvt_chips[i].chip_ver;
383 return nvt_chips[i].name;
384 }
385
386 return NULL;
387 }
388
389
390 /* detect hardware features */
391 static int nvt_hw_detect(struct nvt_dev *nvt)
392 {
393 struct device *dev = nvt_get_dev(nvt);
394 const char *chip_name;
395 int chip_id;
396
397 nvt_efm_enable(nvt);
398
399 /* Check if we're wired for the alternate EFER setup */
400 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
401 if (nvt->chip_major == 0xff) {
402 nvt_efm_disable(nvt);
403 nvt->cr_efir = CR_EFIR2;
404 nvt->cr_efdr = CR_EFDR2;
405 nvt_efm_enable(nvt);
406 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
407 }
408 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
409
410 nvt_efm_disable(nvt);
411
412 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
413 if (chip_id == NVT_INVALID) {
414 dev_err(dev, "No device found on either EFM port\n");
415 return -ENODEV;
416 }
417
418 chip_name = nvt_find_chip(nvt, chip_id);
419
420 /* warn, but still let the driver load, if we don't know this chip */
421 if (!chip_name)
422 dev_warn(dev,
423 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
424 nvt->chip_major, nvt->chip_minor);
425 else
426 dev_info(dev, "found %s or compatible: chip id: 0x%02x 0x%02x",
427 chip_name, nvt->chip_major, nvt->chip_minor);
428
429 return 0;
430 }
431
432 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
433 {
434 u8 val, psreg, psmask, psval;
435
436 if (is_w83667hg(nvt)) {
437 psreg = CR_MULTIFUNC_PIN_SEL;
438 psmask = MULTIFUNC_PIN_SEL_MASK;
439 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
440 } else {
441 psreg = CR_OUTPUT_PIN_SEL;
442 psmask = OUTPUT_PIN_SEL_MASK;
443 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
444 }
445
446 /* output pin selection: enable CIR, with WB sensor enabled */
447 val = nvt_cr_read(nvt, psreg);
448 val &= psmask;
449 val |= psval;
450 nvt_cr_write(nvt, val, psreg);
451
452 /* Select CIR logical device */
453 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
454
455 nvt_set_ioaddr(nvt, &nvt->cir_addr);
456
457 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
458
459 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
460 nvt->cir_addr, nvt->cir_irq);
461 }
462
463 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
464 {
465 /* Select ACPI logical device and anable it */
466 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
467 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
468
469 /* Enable CIR Wake via PSOUT# (Pin60) */
470 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
471
472 /* enable pme interrupt of cir wakeup event */
473 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
474
475 /* Select CIR Wake logical device */
476 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
477
478 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
479
480 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
481 nvt->cir_wake_addr);
482 }
483
484 /* clear out the hardware's cir rx fifo */
485 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
486 {
487 u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
488 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
489 }
490
491 /* clear out the hardware's cir wake rx fifo */
492 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
493 {
494 u8 val, config;
495
496 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
497
498 /* clearing wake fifo works in learning mode only */
499 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
500 CIR_WAKE_IRCON);
501
502 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
503 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
504 CIR_WAKE_FIFOCON);
505
506 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
507 }
508
509 /* clear out the hardware's cir tx fifo */
510 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
511 {
512 u8 val;
513
514 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
515 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
516 }
517
518 /* enable RX Trigger Level Reach and Packet End interrupts */
519 static void nvt_set_cir_iren(struct nvt_dev *nvt)
520 {
521 u8 iren;
522
523 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
524 nvt_cir_reg_write(nvt, iren, CIR_IREN);
525 }
526
527 static void nvt_cir_regs_init(struct nvt_dev *nvt)
528 {
529 /* set sample limit count (PE interrupt raised when reached) */
530 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
531 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
532
533 /* set fifo irq trigger levels */
534 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
535 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
536
537 /*
538 * Enable TX and RX, specify carrier on = low, off = high, and set
539 * sample period (currently 50us)
540 */
541 nvt_cir_reg_write(nvt,
542 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
543 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
544 CIR_IRCON);
545
546 /* clear hardware rx and tx fifos */
547 nvt_clear_cir_fifo(nvt);
548 nvt_clear_tx_fifo(nvt);
549
550 /* clear any and all stray interrupts */
551 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
552
553 /* and finally, enable interrupts */
554 nvt_set_cir_iren(nvt);
555
556 /* enable the CIR logical device */
557 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
558 }
559
560 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
561 {
562 /*
563 * Disable RX, set specific carrier on = low, off = high,
564 * and sample period (currently 50us)
565 */
566 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
567 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
568 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
569 CIR_WAKE_IRCON);
570
571 /* clear any and all stray interrupts */
572 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
573
574 /* enable the CIR WAKE logical device */
575 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
576 }
577
578 static void nvt_enable_wake(struct nvt_dev *nvt)
579 {
580 unsigned long flags;
581
582 nvt_efm_enable(nvt);
583
584 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
585 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
586 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
587
588 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
589 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
590
591 nvt_efm_disable(nvt);
592
593 spin_lock_irqsave(&nvt->lock, flags);
594
595 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
596 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
597 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
598 CIR_WAKE_IRCON);
599 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
600 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
601
602 spin_unlock_irqrestore(&nvt->lock, flags);
603 }
604
605 #if 0 /* Currently unused */
606 /* rx carrier detect only works in learning mode, must be called w/lock */
607 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
608 {
609 u32 count, carrier, duration = 0;
610 int i;
611
612 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
613 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
614
615 for (i = 0; i < nvt->pkts; i++) {
616 if (nvt->buf[i] & BUF_PULSE_BIT)
617 duration += nvt->buf[i] & BUF_LEN_MASK;
618 }
619
620 duration *= SAMPLE_PERIOD;
621
622 if (!count || !duration) {
623 dev_notice(nvt_get_dev(nvt),
624 "Unable to determine carrier! (c:%u, d:%u)",
625 count, duration);
626 return 0;
627 }
628
629 carrier = MS_TO_NS(count) / duration;
630
631 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
632 nvt_dbg("WTF? Carrier frequency out of range!");
633
634 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
635 carrier, count, duration);
636
637 return carrier;
638 }
639 #endif
640 /*
641 * set carrier frequency
642 *
643 * set carrier on 2 registers: CP & CC
644 * always set CP as 0x81
645 * set CC by SPEC, CC = 3MHz/carrier - 1
646 */
647 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
648 {
649 struct nvt_dev *nvt = dev->priv;
650 u16 val;
651
652 if (carrier == 0)
653 return -EINVAL;
654
655 nvt_cir_reg_write(nvt, 1, CIR_CP);
656 val = 3000000 / (carrier) - 1;
657 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
658
659 nvt_dbg("cp: 0x%x cc: 0x%x\n",
660 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
661
662 return 0;
663 }
664
665 /*
666 * nvt_tx_ir
667 *
668 * 1) clean TX fifo first (handled by AP)
669 * 2) copy data from user space
670 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
671 * 4) send 9 packets to TX FIFO to open TTR
672 * in interrupt_handler:
673 * 5) send all data out
674 * go back to write():
675 * 6) disable TX interrupts, re-enable RX interupts
676 *
677 * The key problem of this function is user space data may larger than
678 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
679 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
680 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
681 * set TXFCONT as 0xff, until buf_count less than 0xff.
682 */
683 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
684 {
685 struct nvt_dev *nvt = dev->priv;
686 unsigned long flags;
687 unsigned int i;
688 u8 iren;
689 int ret;
690
691 spin_lock_irqsave(&nvt->lock, flags);
692
693 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
694 nvt->tx.buf_count = (ret * sizeof(unsigned));
695
696 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
697
698 nvt->tx.cur_buf_num = 0;
699
700 /* save currently enabled interrupts */
701 iren = nvt_cir_reg_read(nvt, CIR_IREN);
702
703 /* now disable all interrupts, save TFU & TTR */
704 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
705
706 nvt->tx.tx_state = ST_TX_REPLY;
707
708 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
709 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
710
711 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
712 for (i = 0; i < 9; i++)
713 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
714
715 spin_unlock_irqrestore(&nvt->lock, flags);
716
717 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
718
719 spin_lock_irqsave(&nvt->lock, flags);
720 nvt->tx.tx_state = ST_TX_NONE;
721 spin_unlock_irqrestore(&nvt->lock, flags);
722
723 /* restore enabled interrupts to prior state */
724 nvt_cir_reg_write(nvt, iren, CIR_IREN);
725
726 return ret;
727 }
728
729 /* dump contents of the last rx buffer we got from the hw rx fifo */
730 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
731 {
732 int i;
733
734 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
735 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
736 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
737 printk(KERN_CONT "\n");
738 }
739
740 /*
741 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
742 * trigger decode when appropriate.
743 *
744 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
745 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
746 * (default 50us) intervals for that pulse/space. A discrete signal is
747 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
748 * to signal more IR coming (repeats) or end of IR, respectively. We store
749 * sample data in the raw event kfifo until we see 0x7<something> (except f)
750 * or 0x80, at which time, we trigger a decode operation.
751 */
752 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
753 {
754 DEFINE_IR_RAW_EVENT(rawir);
755 u8 sample;
756 int i;
757
758 nvt_dbg_verbose("%s firing", __func__);
759
760 if (debug)
761 nvt_dump_rx_buf(nvt);
762
763 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
764
765 for (i = 0; i < nvt->pkts; i++) {
766 sample = nvt->buf[i];
767
768 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
769 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
770 * SAMPLE_PERIOD);
771
772 nvt_dbg("Storing %s with duration %d",
773 rawir.pulse ? "pulse" : "space", rawir.duration);
774
775 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
776 }
777
778 nvt->pkts = 0;
779
780 nvt_dbg("Calling ir_raw_event_handle\n");
781 ir_raw_event_handle(nvt->rdev);
782
783 nvt_dbg_verbose("%s done", __func__);
784 }
785
786 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
787 {
788 dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!");
789
790 nvt->pkts = 0;
791 nvt_clear_cir_fifo(nvt);
792 ir_raw_event_reset(nvt->rdev);
793 }
794
795 /* copy data from hardware rx fifo into driver buffer */
796 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
797 {
798 u8 fifocount;
799 int i;
800
801 /* Get count of how many bytes to read from RX FIFO */
802 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
803
804 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
805
806 /* Read fifocount bytes from CIR Sample RX FIFO register */
807 for (i = 0; i < fifocount; i++)
808 nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
809
810 nvt->pkts = fifocount;
811 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
812
813 nvt_process_rx_ir_data(nvt);
814 }
815
816 static void nvt_cir_log_irqs(u8 status, u8 iren)
817 {
818 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
819 status, iren,
820 status & CIR_IRSTS_RDR ? " RDR" : "",
821 status & CIR_IRSTS_RTR ? " RTR" : "",
822 status & CIR_IRSTS_PE ? " PE" : "",
823 status & CIR_IRSTS_RFO ? " RFO" : "",
824 status & CIR_IRSTS_TE ? " TE" : "",
825 status & CIR_IRSTS_TTR ? " TTR" : "",
826 status & CIR_IRSTS_TFU ? " TFU" : "",
827 status & CIR_IRSTS_GH ? " GH" : "",
828 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
829 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
830 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
831 }
832
833 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
834 {
835 return nvt->tx.tx_state == ST_TX_NONE;
836 }
837
838 /* interrupt service routine for incoming and outgoing CIR data */
839 static irqreturn_t nvt_cir_isr(int irq, void *data)
840 {
841 struct nvt_dev *nvt = data;
842 u8 status, iren;
843
844 nvt_dbg_verbose("%s firing", __func__);
845
846 spin_lock(&nvt->lock);
847
848 /*
849 * Get IR Status register contents. Write 1 to ack/clear
850 *
851 * bit: reg name - description
852 * 7: CIR_IRSTS_RDR - RX Data Ready
853 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
854 * 5: CIR_IRSTS_PE - Packet End
855 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
856 * 3: CIR_IRSTS_TE - TX FIFO Empty
857 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
858 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
859 * 0: CIR_IRSTS_GH - Min Length Detected
860 */
861 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
862 iren = nvt_cir_reg_read(nvt, CIR_IREN);
863
864 /* At least NCT6779D creates a spurious interrupt when the
865 * logical device is being disabled.
866 */
867 if (status == 0xff && iren == 0xff) {
868 spin_unlock(&nvt->lock);
869 nvt_dbg_verbose("Spurious interrupt detected");
870 return IRQ_HANDLED;
871 }
872
873 /* IRQ may be shared with CIR WAKE, therefore check for each
874 * status bit whether the related interrupt source is enabled
875 */
876 if (!(status & iren)) {
877 spin_unlock(&nvt->lock);
878 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
879 return IRQ_NONE;
880 }
881
882 /* ack/clear all irq flags we've got */
883 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
884 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
885
886 nvt_cir_log_irqs(status, iren);
887
888 if (status & CIR_IRSTS_RFO)
889 nvt_handle_rx_fifo_overrun(nvt);
890
891 else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE)) {
892 /* We only do rx if not tx'ing */
893 if (nvt_cir_tx_inactive(nvt))
894 nvt_get_rx_ir_data(nvt);
895 }
896
897 if (status & CIR_IRSTS_TE)
898 nvt_clear_tx_fifo(nvt);
899
900 if (status & CIR_IRSTS_TTR) {
901 unsigned int pos, count;
902 u8 tmp;
903
904 pos = nvt->tx.cur_buf_num;
905 count = nvt->tx.buf_count;
906
907 /* Write data into the hardware tx fifo while pos < count */
908 if (pos < count) {
909 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
910 nvt->tx.cur_buf_num++;
911 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
912 } else {
913 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
914 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
915 }
916 }
917
918 if (status & CIR_IRSTS_TFU) {
919 if (nvt->tx.tx_state == ST_TX_REPLY) {
920 nvt->tx.tx_state = ST_TX_REQUEST;
921 wake_up(&nvt->tx.queue);
922 }
923 }
924
925 spin_unlock(&nvt->lock);
926
927 nvt_dbg_verbose("%s done", __func__);
928 return IRQ_HANDLED;
929 }
930
931 static void nvt_disable_cir(struct nvt_dev *nvt)
932 {
933 unsigned long flags;
934
935 spin_lock_irqsave(&nvt->lock, flags);
936
937 /* disable CIR interrupts */
938 nvt_cir_reg_write(nvt, 0, CIR_IREN);
939
940 /* clear any and all pending interrupts */
941 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
942
943 /* clear all function enable flags */
944 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
945
946 /* clear hardware rx and tx fifos */
947 nvt_clear_cir_fifo(nvt);
948 nvt_clear_tx_fifo(nvt);
949
950 spin_unlock_irqrestore(&nvt->lock, flags);
951
952 /* disable the CIR logical device */
953 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
954 }
955
956 static int nvt_open(struct rc_dev *dev)
957 {
958 struct nvt_dev *nvt = dev->priv;
959 unsigned long flags;
960
961 spin_lock_irqsave(&nvt->lock, flags);
962
963 /* set function enable flags */
964 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
965 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
966 CIR_IRCON);
967
968 /* clear all pending interrupts */
969 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
970
971 /* enable interrupts */
972 nvt_set_cir_iren(nvt);
973
974 spin_unlock_irqrestore(&nvt->lock, flags);
975
976 /* enable the CIR logical device */
977 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
978
979 return 0;
980 }
981
982 static void nvt_close(struct rc_dev *dev)
983 {
984 struct nvt_dev *nvt = dev->priv;
985
986 nvt_disable_cir(nvt);
987 }
988
989 /* Allocate memory, probe hardware, and initialize everything */
990 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
991 {
992 struct nvt_dev *nvt;
993 struct rc_dev *rdev;
994 int ret;
995
996 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
997 if (!nvt)
998 return -ENOMEM;
999
1000 /* input device for IR remote (and tx) */
1001 nvt->rdev = devm_rc_allocate_device(&pdev->dev);
1002 if (!nvt->rdev)
1003 return -ENOMEM;
1004 rdev = nvt->rdev;
1005
1006 /* activate pnp device */
1007 ret = pnp_activate_dev(pdev);
1008 if (ret) {
1009 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1010 return ret;
1011 }
1012
1013 /* validate pnp resources */
1014 if (!pnp_port_valid(pdev, 0) ||
1015 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1016 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1017 return -EINVAL;
1018 }
1019
1020 if (!pnp_irq_valid(pdev, 0)) {
1021 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1022 return -EINVAL;
1023 }
1024
1025 if (!pnp_port_valid(pdev, 1) ||
1026 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1027 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1028 return -EINVAL;
1029 }
1030
1031 nvt->cir_addr = pnp_port_start(pdev, 0);
1032 nvt->cir_irq = pnp_irq(pdev, 0);
1033
1034 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1035
1036 nvt->cr_efir = CR_EFIR;
1037 nvt->cr_efdr = CR_EFDR;
1038
1039 spin_lock_init(&nvt->lock);
1040
1041 pnp_set_drvdata(pdev, nvt);
1042
1043 init_waitqueue_head(&nvt->tx.queue);
1044
1045 ret = nvt_hw_detect(nvt);
1046 if (ret)
1047 return ret;
1048
1049 /* Initialize CIR & CIR Wake Logical Devices */
1050 nvt_efm_enable(nvt);
1051 nvt_cir_ldev_init(nvt);
1052 nvt_cir_wake_ldev_init(nvt);
1053 nvt_efm_disable(nvt);
1054
1055 /*
1056 * Initialize CIR & CIR Wake Config Registers
1057 * and enable logical devices
1058 */
1059 nvt_cir_regs_init(nvt);
1060 nvt_cir_wake_regs_init(nvt);
1061
1062 /* Set up the rc device */
1063 rdev->priv = nvt;
1064 rdev->driver_type = RC_DRIVER_IR_RAW;
1065 rdev->allowed_protocols = RC_BIT_ALL;
1066 rdev->open = nvt_open;
1067 rdev->close = nvt_close;
1068 rdev->tx_ir = nvt_tx_ir;
1069 rdev->s_tx_carrier = nvt_set_tx_carrier;
1070 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1071 rdev->input_phys = "nuvoton/cir0";
1072 rdev->input_id.bustype = BUS_HOST;
1073 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1074 rdev->input_id.product = nvt->chip_major;
1075 rdev->input_id.version = nvt->chip_minor;
1076 rdev->driver_name = NVT_DRIVER_NAME;
1077 rdev->map_name = RC_MAP_RC6_MCE;
1078 rdev->timeout = MS_TO_NS(100);
1079 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1080 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1081 #if 0
1082 rdev->min_timeout = XYZ;
1083 rdev->max_timeout = XYZ;
1084 /* tx bits */
1085 rdev->tx_resolution = XYZ;
1086 #endif
1087 ret = devm_rc_register_device(&pdev->dev, rdev);
1088 if (ret)
1089 return ret;
1090
1091 /* now claim resources */
1092 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1093 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1094 return -EBUSY;
1095
1096 ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1097 IRQF_SHARED, NVT_DRIVER_NAME, nvt);
1098 if (ret)
1099 return ret;
1100
1101 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1102 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1103 return -EBUSY;
1104
1105 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1106 if (ret)
1107 return ret;
1108
1109 device_init_wakeup(&pdev->dev, true);
1110
1111 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1112 if (debug) {
1113 cir_dump_regs(nvt);
1114 cir_wake_dump_regs(nvt);
1115 }
1116
1117 return 0;
1118 }
1119
1120 static void nvt_remove(struct pnp_dev *pdev)
1121 {
1122 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1123
1124 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1125
1126 nvt_disable_cir(nvt);
1127
1128 /* enable CIR Wake (for IR power-on) */
1129 nvt_enable_wake(nvt);
1130 }
1131
1132 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1133 {
1134 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1135 unsigned long flags;
1136
1137 nvt_dbg("%s called", __func__);
1138
1139 spin_lock_irqsave(&nvt->lock, flags);
1140
1141 nvt->tx.tx_state = ST_TX_NONE;
1142
1143 /* disable all CIR interrupts */
1144 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1145
1146 spin_unlock_irqrestore(&nvt->lock, flags);
1147
1148 /* disable cir logical dev */
1149 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1150
1151 /* make sure wake is enabled */
1152 nvt_enable_wake(nvt);
1153
1154 return 0;
1155 }
1156
1157 static int nvt_resume(struct pnp_dev *pdev)
1158 {
1159 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1160
1161 nvt_dbg("%s called", __func__);
1162
1163 nvt_cir_regs_init(nvt);
1164 nvt_cir_wake_regs_init(nvt);
1165
1166 return 0;
1167 }
1168
1169 static void nvt_shutdown(struct pnp_dev *pdev)
1170 {
1171 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1172
1173 nvt_enable_wake(nvt);
1174 }
1175
1176 static const struct pnp_device_id nvt_ids[] = {
1177 { "WEC0530", 0 }, /* CIR */
1178 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1179 { "", 0 },
1180 };
1181
1182 static struct pnp_driver nvt_driver = {
1183 .name = NVT_DRIVER_NAME,
1184 .id_table = nvt_ids,
1185 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1186 .probe = nvt_probe,
1187 .remove = nvt_remove,
1188 .suspend = nvt_suspend,
1189 .resume = nvt_resume,
1190 .shutdown = nvt_shutdown,
1191 };
1192
1193 module_param(debug, int, S_IRUGO | S_IWUSR);
1194 MODULE_PARM_DESC(debug, "Enable debugging output");
1195
1196 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1197 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1198
1199 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1200 MODULE_LICENSE("GPL");
1201
1202 module_pnp_driver(nvt_driver);
Linux with added FPC-III support