drivers/media/rc/sunxi-cir.c

   1 /*
   2  * Driver for Allwinner sunXi IR controller
   3  *
   4  * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
   5  * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
   6  *
   7  * Based on sun5i-ir.c:
   8  * Copyright (C) 2007-2012 Daniel Wang
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/reset.h>
  27 #include <media/rc-core.h>
  28
  29 #define SUNXI_IR_DEV "sunxi-ir"
  30
  31 /* Registers */
  32 /* IR Control */
  33 #define SUNXI_IR_CTL_REG      0x00
  34 /* Global Enable */
  35 #define REG_CTL_GEN                     BIT(0)
  36 /* RX block enable */
  37 #define REG_CTL_RXEN                    BIT(1)
  38 /* CIR mode */
  39 #define REG_CTL_MD                      (BIT(4) | BIT(5))
  40
  41 /* Rx Config */
  42 #define SUNXI_IR_RXCTL_REG    0x10
  43 /* Pulse Polarity Invert flag */
  44 #define REG_RXCTL_RPPI                  BIT(2)
  45
  46 /* Rx Data */
  47 #define SUNXI_IR_RXFIFO_REG   0x20
  48
  49 /* Rx Interrupt Enable */
  50 #define SUNXI_IR_RXINT_REG    0x2C
  51 /* Rx FIFO Overflow */
  52 #define REG_RXINT_ROI_EN                BIT(0)
  53 /* Rx Packet End */
  54 #define REG_RXINT_RPEI_EN               BIT(1)
  55 /* Rx FIFO Data Available */
  56 #define REG_RXINT_RAI_EN                BIT(4)
  57
  58 /* Rx FIFO available byte level */
  59 #define REG_RXINT_RAL(val)    ((val) << 8)
  60
  61 /* Rx Interrupt Status */
  62 #define SUNXI_IR_RXSTA_REG    0x30
  63 /* RX FIFO Get Available Counter */
  64 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
  65 /* Clear all interrupt status value */
  66 #define REG_RXSTA_CLEARALL    0xff
  67
  68 /* IR Sample Config */
  69 #define SUNXI_IR_CIR_REG      0x34
  70 /* CIR_REG register noise threshold */
  71 #define REG_CIR_NTHR(val)    (((val) << 2) & (GENMASK(7, 2)))
  72 /* CIR_REG register idle threshold */
  73 #define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))
  74
  75 /* Required frequency for IR0 or IR1 clock in CIR mode */
  76 #define SUNXI_IR_BASE_CLK     8000000
  77 /* Frequency after IR internal divider  */
  78 #define SUNXI_IR_CLK          (SUNXI_IR_BASE_CLK / 64)
  79 /* Sample period in ns */
  80 #define SUNXI_IR_SAMPLE       (1000000000ul / SUNXI_IR_CLK)
  81 /* Noise threshold in samples  */
  82 #define SUNXI_IR_RXNOISE      1
  83 /* Idle Threshold in samples */
  84 #define SUNXI_IR_RXIDLE       20
  85 /* Time after which device stops sending data in ms */
  86 #define SUNXI_IR_TIMEOUT      120
  87
  88 struct sunxi_ir {
  89         spinlock_t      ir_lock;
  90         struct rc_dev   *rc;
  91         void __iomem    *base;
  92         int             irq;
  93         int             fifo_size;
  94         struct clk      *clk;
  95         struct clk      *apb_clk;
  96         struct reset_control *rst;
  97         const char      *map_name;
  98 };
  99
 100 static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
 101 {
 102         unsigned long status;
 103         unsigned char dt;
 104         unsigned int cnt, rc;
 105         struct sunxi_ir *ir = dev_id;
 106         DEFINE_IR_RAW_EVENT(rawir);
 107
 108         spin_lock(&ir->ir_lock);
 109
 110         status = readl(ir->base + SUNXI_IR_RXSTA_REG);
 111
 112         /* clean all pending statuses */
 113         writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 114
 115         if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
 116                 /* How many messages in fifo */
 117                 rc  = REG_RXSTA_GET_AC(status);
 118                 /* Sanity check */
 119                 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
 120                 /* If we have data */
 121                 for (cnt = 0; cnt < rc; cnt++) {
 122                         /* for each bit in fifo */
 123                         dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
 124                         rawir.pulse = (dt & 0x80) != 0;
 125                         rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
 126                         ir_raw_event_store_with_filter(ir->rc, &rawir);
 127                 }
 128         }
 129
 130         if (status & REG_RXINT_ROI_EN) {
 131                 ir_raw_event_reset(ir->rc);
 132         } else if (status & REG_RXINT_RPEI_EN) {
 133                 ir_raw_event_set_idle(ir->rc, true);
 134                 ir_raw_event_handle(ir->rc);
 135         }
 136
 137         spin_unlock(&ir->ir_lock);
 138
 139         return IRQ_HANDLED;
 140 }
 141
 142 static int sunxi_ir_probe(struct platform_device *pdev)
 143 {
 144         int ret = 0;
 145         unsigned long tmp = 0;
 146
 147         struct device *dev = &pdev->dev;
 148         struct device_node *dn = dev->of_node;
 149         struct resource *res;
 150         struct sunxi_ir *ir;
 151
 152         ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
 153         if (!ir)
 154                 return -ENOMEM;
 155
 156         spin_lock_init(&ir->ir_lock);
 157
 158         if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
 159                 ir->fifo_size = 64;
 160         else
 161                 ir->fifo_size = 16;
 162
 163         /* Clock */
 164         ir->apb_clk = devm_clk_get(dev, "apb");
 165         if (IS_ERR(ir->apb_clk)) {
 166                 dev_err(dev, "failed to get a apb clock.\n");
 167                 return PTR_ERR(ir->apb_clk);
 168         }
 169         ir->clk = devm_clk_get(dev, "ir");
 170         if (IS_ERR(ir->clk)) {
 171                 dev_err(dev, "failed to get a ir clock.\n");
 172                 return PTR_ERR(ir->clk);
 173         }
 174
 175         /* Reset (optional) */
 176         ir->rst = devm_reset_control_get_optional(dev, NULL);
 177         if (IS_ERR(ir->rst)) {
 178                 ret = PTR_ERR(ir->rst);
 179                 if (ret == -EPROBE_DEFER)
 180                         return ret;
 181                 ir->rst = NULL;
 182         } else {
 183                 ret = reset_control_deassert(ir->rst);
 184                 if (ret)
 185                         return ret;
 186         }
 187
 188         ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
 189         if (ret) {
 190                 dev_err(dev, "set ir base clock failed!\n");
 191                 goto exit_reset_assert;
 192         }
 193
 194         if (clk_prepare_enable(ir->apb_clk)) {
 195                 dev_err(dev, "try to enable apb_ir_clk failed\n");
 196                 ret = -EINVAL;
 197                 goto exit_reset_assert;
 198         }
 199
 200         if (clk_prepare_enable(ir->clk)) {
 201                 dev_err(dev, "try to enable ir_clk failed\n");
 202                 ret = -EINVAL;
 203                 goto exit_clkdisable_apb_clk;
 204         }
 205
 206         /* IO */
 207         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 208         ir->base = devm_ioremap_resource(dev, res);
 209         if (IS_ERR(ir->base)) {
 210                 dev_err(dev, "failed to map registers\n");
 211                 ret = PTR_ERR(ir->base);
 212                 goto exit_clkdisable_clk;
 213         }
 214
 215         ir->rc = rc_allocate_device();
 216         if (!ir->rc) {
 217                 dev_err(dev, "failed to allocate device\n");
 218                 ret = -ENOMEM;
 219                 goto exit_clkdisable_clk;
 220         }
 221
 222         ir->rc->priv = ir;
 223         ir->rc->input_name = SUNXI_IR_DEV;
 224         ir->rc->input_phys = "sunxi-ir/input0";
 225         ir->rc->input_id.bustype = BUS_HOST;
 226         ir->rc->input_id.vendor = 0x0001;
 227         ir->rc->input_id.product = 0x0001;
 228         ir->rc->input_id.version = 0x0100;
 229         ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
 230         ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
 231         ir->rc->dev.parent = dev;
 232         ir->rc->driver_type = RC_DRIVER_IR_RAW;
 233         ir->rc->allowed_protocols = RC_BIT_ALL;
 234         ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
 235         ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
 236         ir->rc->driver_name = SUNXI_IR_DEV;
 237
 238         ret = rc_register_device(ir->rc);
 239         if (ret) {
 240                 dev_err(dev, "failed to register rc device\n");
 241                 goto exit_free_dev;
 242         }
 243
 244         platform_set_drvdata(pdev, ir);
 245
 246         /* IRQ */
 247         ir->irq = platform_get_irq(pdev, 0);
 248         if (ir->irq < 0) {
 249                 dev_err(dev, "no irq resource\n");
 250                 ret = ir->irq;
 251                 goto exit_free_dev;
 252         }
 253
 254         ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
 255         if (ret) {
 256                 dev_err(dev, "failed request irq\n");
 257                 goto exit_free_dev;
 258         }
 259
 260         /* Enable CIR Mode */
 261         writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
 262
 263         /* Set noise threshold and idle threshold */
 264         writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
 265                ir->base + SUNXI_IR_CIR_REG);
 266
 267         /* Invert Input Signal */
 268         writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
 269
 270         /* Clear All Rx Interrupt Status */
 271         writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 272
 273         /*
 274          * Enable IRQ on overflow, packet end, FIFO available with trigger
 275          * level
 276          */
 277         writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
 278                REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
 279                ir->base + SUNXI_IR_RXINT_REG);
 280
 281         /* Enable IR Module */
 282         tmp = readl(ir->base + SUNXI_IR_CTL_REG);
 283         writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
 284
 285         dev_info(dev, "initialized sunXi IR driver\n");
 286         return 0;
 287
 288 exit_free_dev:
 289         rc_free_device(ir->rc);
 290 exit_clkdisable_clk:
 291         clk_disable_unprepare(ir->clk);
 292 exit_clkdisable_apb_clk:
 293         clk_disable_unprepare(ir->apb_clk);
 294 exit_reset_assert:
 295         if (ir->rst)
 296                 reset_control_assert(ir->rst);
 297
 298         return ret;
 299 }
 300
 301 static int sunxi_ir_remove(struct platform_device *pdev)
 302 {
 303         unsigned long flags;
 304         struct sunxi_ir *ir = platform_get_drvdata(pdev);
 305
 306         clk_disable_unprepare(ir->clk);
 307         clk_disable_unprepare(ir->apb_clk);
 308         if (ir->rst)
 309                 reset_control_assert(ir->rst);
 310
 311         spin_lock_irqsave(&ir->ir_lock, flags);
 312         /* disable IR IRQ */
 313         writel(0, ir->base + SUNXI_IR_RXINT_REG);
 314         /* clear All Rx Interrupt Status */
 315         writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
 316         /* disable IR */
 317         writel(0, ir->base + SUNXI_IR_CTL_REG);
 318         spin_unlock_irqrestore(&ir->ir_lock, flags);
 319
 320         rc_unregister_device(ir->rc);
 321         return 0;
 322 }
 323
 324 static const struct of_device_id sunxi_ir_match[] = {
 325         { .compatible = "allwinner,sun4i-a10-ir", },
 326         { .compatible = "allwinner,sun5i-a13-ir", },
 327         {},
 328 };
 329 MODULE_DEVICE_TABLE(of, sunxi_ir_match);
 330
 331 static struct platform_driver sunxi_ir_driver = {
 332         .probe          = sunxi_ir_probe,
 333         .remove         = sunxi_ir_remove,
 334         .driver = {
 335                 .name = SUNXI_IR_DEV,
 336                 .of_match_table = sunxi_ir_match,
 337         },
 338 };
 339
 340 module_platform_driver(sunxi_ir_driver);
 341
 342 MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
 343 MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
 344 MODULE_LICENSE("GPL");