2 * Fitipower FC0012 tuner driver
4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "fc0012-priv.h"
24 static int fc0012_writereg(struct fc0012_priv
*priv
, u8 reg
, u8 val
)
26 u8 buf
[2] = {reg
, val
};
27 struct i2c_msg msg
= {
28 .addr
= priv
->cfg
->i2c_address
, .flags
= 0, .buf
= buf
, .len
= 2
31 if (i2c_transfer(priv
->i2c
, &msg
, 1) != 1) {
32 dev_err(&priv
->i2c
->dev
,
33 "%s: I2C write reg failed, reg: %02x, val: %02x\n",
34 KBUILD_MODNAME
, reg
, val
);
40 static int fc0012_readreg(struct fc0012_priv
*priv
, u8 reg
, u8
*val
)
42 struct i2c_msg msg
[2] = {
43 { .addr
= priv
->cfg
->i2c_address
, .flags
= 0,
44 .buf
= ®
, .len
= 1 },
45 { .addr
= priv
->cfg
->i2c_address
, .flags
= I2C_M_RD
,
46 .buf
= val
, .len
= 1 },
49 if (i2c_transfer(priv
->i2c
, msg
, 2) != 2) {
50 dev_err(&priv
->i2c
->dev
,
51 "%s: I2C read reg failed, reg: %02x\n",
58 static void fc0012_release(struct dvb_frontend
*fe
)
60 kfree(fe
->tuner_priv
);
61 fe
->tuner_priv
= NULL
;
64 static int fc0012_init(struct dvb_frontend
*fe
)
66 struct fc0012_priv
*priv
= fe
->tuner_priv
;
68 unsigned char reg
[] = {
69 0x00, /* dummy reg. 0 */
74 0x0f, /* reg. 0x05: may also be 0x0a */
75 0x00, /* reg. 0x06: divider 2, VCO slow */
76 0x00, /* reg. 0x07: may also be 0x0f */
77 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
79 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
80 0xb8, /* reg. 0x0a: Disable LO Test Buffer */
81 0x82, /* reg. 0x0b: Output Clock is same as clock frequency,
83 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
84 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */
87 0x00, /* reg. 0x10: may also be 0x0d */
89 0x1f, /* reg. 0x12: Set to maximum gain */
90 0x08, /* reg. 0x13: Set to Middle Gain: 0x08,
91 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */
93 0x04, /* reg. 0x15: Enable LNA COMPS */
96 switch (priv
->cfg
->xtal_freq
) {
98 case FC_XTAL_28_8_MHZ
:
106 if (priv
->cfg
->dual_master
)
109 if (priv
->cfg
->loop_through
)
112 if (fe
->ops
.i2c_gate_ctrl
)
113 fe
->ops
.i2c_gate_ctrl(fe
, 1); /* open I2C-gate */
115 for (i
= 1; i
< sizeof(reg
); i
++) {
116 ret
= fc0012_writereg(priv
, i
, reg
[i
]);
121 if (fe
->ops
.i2c_gate_ctrl
)
122 fe
->ops
.i2c_gate_ctrl(fe
, 0); /* close I2C-gate */
125 dev_err(&priv
->i2c
->dev
, "%s: fc0012_writereg failed: %d\n",
126 KBUILD_MODNAME
, ret
);
131 static int fc0012_set_params(struct dvb_frontend
*fe
)
133 struct fc0012_priv
*priv
= fe
->tuner_priv
;
135 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
136 u32 freq
= p
->frequency
/ 1000;
137 u32 delsys
= p
->delivery_system
;
138 unsigned char reg
[7], am
, pm
, multi
, tmp
;
140 unsigned short xtal_freq_khz_2
, xin
, xdiv
;
141 bool vco_select
= false;
144 ret
= fe
->callback(priv
->i2c
, DVB_FRONTEND_COMPONENT_TUNER
,
145 FC_FE_CALLBACK_VHF_ENABLE
, (freq
> 300000 ? 0 : 1));
150 switch (priv
->cfg
->xtal_freq
) {
152 xtal_freq_khz_2
= 27000 / 2;
155 xtal_freq_khz_2
= 36000 / 2;
157 case FC_XTAL_28_8_MHZ
:
159 xtal_freq_khz_2
= 28800 / 2;
163 /* select frequency divider and the frequency of VCO */
164 if (freq
< 37084) { /* freq * 96 < 3560000 */
168 } else if (freq
< 55625) { /* freq * 64 < 3560000 */
172 } else if (freq
< 74167) { /* freq * 48 < 3560000 */
176 } else if (freq
< 111250) { /* freq * 32 < 3560000 */
180 } else if (freq
< 148334) { /* freq * 24 < 3560000 */
184 } else if (freq
< 222500) { /* freq * 16 < 3560000 */
188 } else if (freq
< 296667) { /* freq * 12 < 3560000 */
192 } else if (freq
< 445000) { /* freq * 8 < 3560000 */
196 } else if (freq
< 593334) { /* freq * 6 < 3560000 */
206 f_vco
= freq
* multi
;
208 if (f_vco
>= 3060000) {
214 /* From divided value (XDIV) determined the FA and FP value */
215 xdiv
= (unsigned short)(f_vco
/ xtal_freq_khz_2
);
216 if ((f_vco
- xdiv
* xtal_freq_khz_2
) >= (xtal_freq_khz_2
/ 2))
219 pm
= (unsigned char)(xdiv
/ 8);
220 am
= (unsigned char)(xdiv
- (8 * pm
));
230 /* fix for frequency less than 45 MHz */
238 /* From VCO frequency determines the XIN ( fractional part of Delta
239 Sigma PLL) and divided value (XDIV) */
240 xin
= (unsigned short)(f_vco
- (f_vco
/ xtal_freq_khz_2
) * xtal_freq_khz_2
);
241 xin
= (xin
<< 15) / xtal_freq_khz_2
;
245 reg
[3] = xin
>> 8; /* xin with 9 bit resolution */
248 if (delsys
== SYS_DVBT
) {
249 reg
[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
250 switch (p
->bandwidth_hz
) {
262 dev_err(&priv
->i2c
->dev
, "%s: modulation type not supported!\n",
267 /* modified for Realtek demod */
270 if (fe
->ops
.i2c_gate_ctrl
)
271 fe
->ops
.i2c_gate_ctrl(fe
, 1); /* open I2C-gate */
273 for (i
= 1; i
<= 6; i
++) {
274 ret
= fc0012_writereg(priv
, i
, reg
[i
]);
279 /* VCO Calibration */
280 ret
= fc0012_writereg(priv
, 0x0e, 0x80);
282 ret
= fc0012_writereg(priv
, 0x0e, 0x00);
284 /* VCO Re-Calibration if needed */
286 ret
= fc0012_writereg(priv
, 0x0e, 0x00);
290 ret
= fc0012_readreg(priv
, 0x0e, &tmp
);
301 ret
= fc0012_writereg(priv
, 0x06, reg
[6]);
303 ret
= fc0012_writereg(priv
, 0x0e, 0x80);
305 ret
= fc0012_writereg(priv
, 0x0e, 0x00);
310 ret
= fc0012_writereg(priv
, 0x06, reg
[6]);
312 ret
= fc0012_writereg(priv
, 0x0e, 0x80);
314 ret
= fc0012_writereg(priv
, 0x0e, 0x00);
318 priv
->frequency
= p
->frequency
;
319 priv
->bandwidth
= p
->bandwidth_hz
;
322 if (fe
->ops
.i2c_gate_ctrl
)
323 fe
->ops
.i2c_gate_ctrl(fe
, 0); /* close I2C-gate */
325 dev_warn(&priv
->i2c
->dev
, "%s: %s failed: %d\n",
326 KBUILD_MODNAME
, __func__
, ret
);
330 static int fc0012_get_frequency(struct dvb_frontend
*fe
, u32
*frequency
)
332 struct fc0012_priv
*priv
= fe
->tuner_priv
;
333 *frequency
= priv
->frequency
;
337 static int fc0012_get_if_frequency(struct dvb_frontend
*fe
, u32
*frequency
)
339 *frequency
= 0; /* Zero-IF */
343 static int fc0012_get_bandwidth(struct dvb_frontend
*fe
, u32
*bandwidth
)
345 struct fc0012_priv
*priv
= fe
->tuner_priv
;
346 *bandwidth
= priv
->bandwidth
;
350 #define INPUT_ADC_LEVEL -8
352 static int fc0012_get_rf_strength(struct dvb_frontend
*fe
, u16
*strength
)
354 struct fc0012_priv
*priv
= fe
->tuner_priv
;
357 int int_temp
, lna_gain
, int_lna
, tot_agc_gain
, power
;
358 const int fc0012_lna_gain_table
[] = {
370 if (fe
->ops
.i2c_gate_ctrl
)
371 fe
->ops
.i2c_gate_ctrl(fe
, 1); /* open I2C-gate */
373 ret
= fc0012_writereg(priv
, 0x12, 0x00);
377 ret
= fc0012_readreg(priv
, 0x12, &tmp
);
382 ret
= fc0012_readreg(priv
, 0x13, &tmp
);
385 lna_gain
= tmp
& 0x1f;
387 if (fe
->ops
.i2c_gate_ctrl
)
388 fe
->ops
.i2c_gate_ctrl(fe
, 0); /* close I2C-gate */
390 if (lna_gain
< ARRAY_SIZE(fc0012_lna_gain_table
)) {
391 int_lna
= fc0012_lna_gain_table
[lna_gain
];
392 tot_agc_gain
= (abs((int_temp
>> 5) - 7) - 2 +
393 (int_temp
& 0x1f)) * 2;
394 power
= INPUT_ADC_LEVEL
- tot_agc_gain
- int_lna
/ 10;
397 *strength
= 255; /* 100% */
398 else if (power
< -95)
401 *strength
= (power
+ 95) * 255 / 140;
403 *strength
|= *strength
<< 8;
411 if (fe
->ops
.i2c_gate_ctrl
)
412 fe
->ops
.i2c_gate_ctrl(fe
, 0); /* close I2C-gate */
415 dev_warn(&priv
->i2c
->dev
, "%s: %s failed: %d\n",
416 KBUILD_MODNAME
, __func__
, ret
);
420 static const struct dvb_tuner_ops fc0012_tuner_ops
= {
422 .name
= "Fitipower FC0012",
424 .frequency_min
= 37000000, /* estimate */
425 .frequency_max
= 862000000, /* estimate */
429 .release
= fc0012_release
,
433 .set_params
= fc0012_set_params
,
435 .get_frequency
= fc0012_get_frequency
,
436 .get_if_frequency
= fc0012_get_if_frequency
,
437 .get_bandwidth
= fc0012_get_bandwidth
,
439 .get_rf_strength
= fc0012_get_rf_strength
,
442 struct dvb_frontend
*fc0012_attach(struct dvb_frontend
*fe
,
443 struct i2c_adapter
*i2c
, const struct fc0012_config
*cfg
)
445 struct fc0012_priv
*priv
;
449 if (fe
->ops
.i2c_gate_ctrl
)
450 fe
->ops
.i2c_gate_ctrl(fe
, 1);
452 priv
= kzalloc(sizeof(struct fc0012_priv
), GFP_KERNEL
);
455 dev_err(&i2c
->dev
, "%s: kzalloc() failed\n", KBUILD_MODNAME
);
462 /* check if the tuner is there */
463 ret
= fc0012_readreg(priv
, 0x00, &chip_id
);
467 dev_dbg(&i2c
->dev
, "%s: chip_id=%02x\n", __func__
, chip_id
);
477 dev_info(&i2c
->dev
, "%s: Fitipower FC0012 successfully identified\n",
480 if (priv
->cfg
->loop_through
) {
481 ret
= fc0012_writereg(priv
, 0x09, 0x6f);
487 * TODO: Clock out en or div?
488 * For dual tuner configuration clearing bit [0] is required.
490 if (priv
->cfg
->clock_out
) {
491 ret
= fc0012_writereg(priv
, 0x0b, 0x82);
496 fe
->tuner_priv
= priv
;
497 memcpy(&fe
->ops
.tuner_ops
, &fc0012_tuner_ops
,
498 sizeof(struct dvb_tuner_ops
));
501 if (fe
->ops
.i2c_gate_ctrl
)
502 fe
->ops
.i2c_gate_ctrl(fe
, 0);
505 dev_dbg(&i2c
->dev
, "%s: failed: %d\n", __func__
, ret
);
512 EXPORT_SYMBOL(fc0012_attach
);
514 MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver");
515 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
516 MODULE_LICENSE("GPL");
517 MODULE_VERSION("0.6");