drivers/media/tuners/fc0013.c

   1 /*
   2  * Fitipower FC0013 tuner driver
   3  *
   4  * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
   5  * partially based on driver code from Fitipower
   6  * Copyright (C) 2010 Fitipower Integrated Technology Inc
   7  *
   8  *    This program is free software; you can redistribute it and/or modify
   9  *    it under the terms of the GNU General Public License as published by
  10  *    the Free Software Foundation; either version 2 of the License, or
  11  *    (at your option) any later version.
  12  *
  13  *    This program is distributed in the hope that it will be useful,
  14  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *    GNU General Public License for more details.
  17  *
  18  *    You should have received a copy of the GNU General Public License
  19  *    along with this program; if not, write to the Free Software
  20  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include "fc0013.h"
  25 #include "fc0013-priv.h"
  26
  27 static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val)
  28 {
  29         u8 buf[2] = {reg, val};
  30         struct i2c_msg msg = {
  31                 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2
  32         };
  33
  34         if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
  35                 err("I2C write reg failed, reg: %02x, val: %02x", reg, val);
  36                 return -EREMOTEIO;
  37         }
  38         return 0;
  39 }
  40
  41 static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val)
  42 {
  43         struct i2c_msg msg[2] = {
  44                 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 },
  45                 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 },
  46         };
  47
  48         if (i2c_transfer(priv->i2c, msg, 2) != 2) {
  49                 err("I2C read reg failed, reg: %02x", reg);
  50                 return -EREMOTEIO;
  51         }
  52         return 0;
  53 }
  54
  55 static void fc0013_release(struct dvb_frontend *fe)
  56 {
  57         kfree(fe->tuner_priv);
  58         fe->tuner_priv = NULL;
  59 }
  60
  61 static int fc0013_init(struct dvb_frontend *fe)
  62 {
  63         struct fc0013_priv *priv = fe->tuner_priv;
  64         int i, ret = 0;
  65         unsigned char reg[] = {
  66                 0x00,   /* reg. 0x00: dummy */
  67                 0x09,   /* reg. 0x01 */
  68                 0x16,   /* reg. 0x02 */
  69                 0x00,   /* reg. 0x03 */
  70                 0x00,   /* reg. 0x04 */
  71                 0x17,   /* reg. 0x05 */
  72                 0x02,   /* reg. 0x06 */
  73                 0x0a,   /* reg. 0x07: CHECK */
  74                 0xff,   /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
  75                            Loop Bw 1/8 */
  76                 0x6f,   /* reg. 0x09: enable LoopThrough */
  77                 0xb8,   /* reg. 0x0a: Disable LO Test Buffer */
  78                 0x82,   /* reg. 0x0b: CHECK */
  79                 0xfc,   /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
  80                 0x01,   /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */
  81                 0x00,   /* reg. 0x0e */
  82                 0x00,   /* reg. 0x0f */
  83                 0x00,   /* reg. 0x10 */
  84                 0x00,   /* reg. 0x11 */
  85                 0x00,   /* reg. 0x12 */
  86                 0x00,   /* reg. 0x13 */
  87                 0x50,   /* reg. 0x14: DVB-t High Gain, UHF.
  88                            Middle Gain: 0x48, Low Gain: 0x40 */
  89                 0x01,   /* reg. 0x15 */
  90         };
  91
  92         switch (priv->xtal_freq) {
  93         case FC_XTAL_27_MHZ:
  94         case FC_XTAL_28_8_MHZ:
  95                 reg[0x07] |= 0x20;
  96                 break;
  97         case FC_XTAL_36_MHZ:
  98         default:
  99                 break;
 100         }
 101
 102         if (priv->dual_master)
 103                 reg[0x0c] |= 0x02;
 104
 105         if (fe->ops.i2c_gate_ctrl)
 106                 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
 107
 108         for (i = 1; i < sizeof(reg); i++) {
 109                 ret = fc0013_writereg(priv, i, reg[i]);
 110                 if (ret)
 111                         break;
 112         }
 113
 114         if (fe->ops.i2c_gate_ctrl)
 115                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 116
 117         if (ret)
 118                 err("fc0013_writereg failed: %d", ret);
 119
 120         return ret;
 121 }
 122
 123 static int fc0013_sleep(struct dvb_frontend *fe)
 124 {
 125         /* nothing to do here */
 126         return 0;
 127 }
 128
 129 int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
 130 {
 131         struct fc0013_priv *priv = fe->tuner_priv;
 132         int ret;
 133         u8 rc_cal;
 134         int val;
 135
 136         if (fe->ops.i2c_gate_ctrl)
 137                 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
 138
 139         /* push rc_cal value, get rc_cal value */
 140         ret = fc0013_writereg(priv, 0x10, 0x00);
 141         if (ret)
 142                 goto error_out;
 143
 144         /* get rc_cal value */
 145         ret = fc0013_readreg(priv, 0x10, &rc_cal);
 146         if (ret)
 147                 goto error_out;
 148
 149         rc_cal &= 0x0f;
 150
 151         val = (int)rc_cal + rc_val;
 152
 153         /* forcing rc_cal */
 154         ret = fc0013_writereg(priv, 0x0d, 0x11);
 155         if (ret)
 156                 goto error_out;
 157
 158         /* modify rc_cal value */
 159         if (val > 15)
 160                 ret = fc0013_writereg(priv, 0x10, 0x0f);
 161         else if (val < 0)
 162                 ret = fc0013_writereg(priv, 0x10, 0x00);
 163         else
 164                 ret = fc0013_writereg(priv, 0x10, (u8)val);
 165
 166 error_out:
 167         if (fe->ops.i2c_gate_ctrl)
 168                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 169
 170         return ret;
 171 }
 172 EXPORT_SYMBOL(fc0013_rc_cal_add);
 173
 174 int fc0013_rc_cal_reset(struct dvb_frontend *fe)
 175 {
 176         struct fc0013_priv *priv = fe->tuner_priv;
 177         int ret;
 178
 179         if (fe->ops.i2c_gate_ctrl)
 180                 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
 181
 182         ret = fc0013_writereg(priv, 0x0d, 0x01);
 183         if (!ret)
 184                 ret = fc0013_writereg(priv, 0x10, 0x00);
 185
 186         if (fe->ops.i2c_gate_ctrl)
 187                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 188
 189         return ret;
 190 }
 191 EXPORT_SYMBOL(fc0013_rc_cal_reset);
 192
 193 static int fc0013_set_vhf_track(struct fc0013_priv *priv, u32 freq)
 194 {
 195         int ret;
 196         u8 tmp;
 197
 198         ret = fc0013_readreg(priv, 0x1d, &tmp);
 199         if (ret)
 200                 goto error_out;
 201         tmp &= 0xe3;
 202         if (freq <= 177500) {           /* VHF Track: 7 */
 203                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
 204         } else if (freq <= 184500) {    /* VHF Track: 6 */
 205                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x18);
 206         } else if (freq <= 191500) {    /* VHF Track: 5 */
 207                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x14);
 208         } else if (freq <= 198500) {    /* VHF Track: 4 */
 209                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x10);
 210         } else if (freq <= 205500) {    /* VHF Track: 3 */
 211                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c);
 212         } else if (freq <= 219500) {    /* VHF Track: 2 */
 213                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x08);
 214         } else if (freq < 300000) {     /* VHF Track: 1 */
 215                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x04);
 216         } else {                        /* UHF and GPS */
 217                 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
 218         }
 219 error_out:
 220         return ret;
 221 }
 222
 223 static int fc0013_set_params(struct dvb_frontend *fe)
 224 {
 225         struct fc0013_priv *priv = fe->tuner_priv;
 226         int i, ret = 0;
 227         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 228         u32 freq = p->frequency / 1000;
 229         u32 delsys = p->delivery_system;
 230         unsigned char reg[7], am, pm, multi, tmp;
 231         unsigned long f_vco;
 232         unsigned short xtal_freq_khz_2, xin, xdiv;
 233         bool vco_select = false;
 234
 235         if (fe->callback) {
 236                 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
 237                         FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
 238                 if (ret)
 239                         goto exit;
 240         }
 241
 242         switch (priv->xtal_freq) {
 243         case FC_XTAL_27_MHZ:
 244                 xtal_freq_khz_2 = 27000 / 2;
 245                 break;
 246         case FC_XTAL_36_MHZ:
 247                 xtal_freq_khz_2 = 36000 / 2;
 248                 break;
 249         case FC_XTAL_28_8_MHZ:
 250         default:
 251                 xtal_freq_khz_2 = 28800 / 2;
 252                 break;
 253         }
 254
 255         if (fe->ops.i2c_gate_ctrl)
 256                 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
 257
 258         /* set VHF track */
 259         ret = fc0013_set_vhf_track(priv, freq);
 260         if (ret)
 261                 goto exit;
 262
 263         if (freq < 300000) {
 264                 /* enable VHF filter */
 265                 ret = fc0013_readreg(priv, 0x07, &tmp);
 266                 if (ret)
 267                         goto exit;
 268                 ret = fc0013_writereg(priv, 0x07, tmp | 0x10);
 269                 if (ret)
 270                         goto exit;
 271
 272                 /* disable UHF & disable GPS */
 273                 ret = fc0013_readreg(priv, 0x14, &tmp);
 274                 if (ret)
 275                         goto exit;
 276                 ret = fc0013_writereg(priv, 0x14, tmp & 0x1f);
 277                 if (ret)
 278                         goto exit;
 279         } else if (freq <= 862000) {
 280                 /* disable VHF filter */
 281                 ret = fc0013_readreg(priv, 0x07, &tmp);
 282                 if (ret)
 283                         goto exit;
 284                 ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
 285                 if (ret)
 286                         goto exit;
 287
 288                 /* enable UHF & disable GPS */
 289                 ret = fc0013_readreg(priv, 0x14, &tmp);
 290                 if (ret)
 291                         goto exit;
 292                 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40);
 293                 if (ret)
 294                         goto exit;
 295         } else {
 296                 /* disable VHF filter */
 297                 ret = fc0013_readreg(priv, 0x07, &tmp);
 298                 if (ret)
 299                         goto exit;
 300                 ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
 301                 if (ret)
 302                         goto exit;
 303
 304                 /* disable UHF & enable GPS */
 305                 ret = fc0013_readreg(priv, 0x14, &tmp);
 306                 if (ret)
 307                         goto exit;
 308                 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20);
 309                 if (ret)
 310                         goto exit;
 311         }
 312
 313         /* select frequency divider and the frequency of VCO */
 314         if (freq < 37084) {             /* freq * 96 < 3560000 */
 315                 multi = 96;
 316                 reg[5] = 0x82;
 317                 reg[6] = 0x00;
 318         } else if (freq < 55625) {      /* freq * 64 < 3560000 */
 319                 multi = 64;
 320                 reg[5] = 0x02;
 321                 reg[6] = 0x02;
 322         } else if (freq < 74167) {      /* freq * 48 < 3560000 */
 323                 multi = 48;
 324                 reg[5] = 0x42;
 325                 reg[6] = 0x00;
 326         } else if (freq < 111250) {     /* freq * 32 < 3560000 */
 327                 multi = 32;
 328                 reg[5] = 0x82;
 329                 reg[6] = 0x02;
 330         } else if (freq < 148334) {     /* freq * 24 < 3560000 */
 331                 multi = 24;
 332                 reg[5] = 0x22;
 333                 reg[6] = 0x00;
 334         } else if (freq < 222500) {     /* freq * 16 < 3560000 */
 335                 multi = 16;
 336                 reg[5] = 0x42;
 337                 reg[6] = 0x02;
 338         } else if (freq < 296667) {     /* freq * 12 < 3560000 */
 339                 multi = 12;
 340                 reg[5] = 0x12;
 341                 reg[6] = 0x00;
 342         } else if (freq < 445000) {     /* freq * 8 < 3560000 */
 343                 multi = 8;
 344                 reg[5] = 0x22;
 345                 reg[6] = 0x02;
 346         } else if (freq < 593334) {     /* freq * 6 < 3560000 */
 347                 multi = 6;
 348                 reg[5] = 0x0a;
 349                 reg[6] = 0x00;
 350         } else if (freq < 950000) {     /* freq * 4 < 3800000 */
 351                 multi = 4;
 352                 reg[5] = 0x12;
 353                 reg[6] = 0x02;
 354         } else {
 355                 multi = 2;
 356                 reg[5] = 0x0a;
 357                 reg[6] = 0x02;
 358         }
 359
 360         f_vco = freq * multi;
 361
 362         if (f_vco >= 3060000) {
 363                 reg[6] |= 0x08;
 364                 vco_select = true;
 365         }
 366
 367         if (freq >= 45000) {
 368                 /* From divided value (XDIV) determined the FA and FP value */
 369                 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
 370                 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
 371                         xdiv++;
 372
 373                 pm = (unsigned char)(xdiv / 8);
 374                 am = (unsigned char)(xdiv - (8 * pm));
 375
 376                 if (am < 2) {
 377                         reg[1] = am + 8;
 378                         reg[2] = pm - 1;
 379                 } else {
 380                         reg[1] = am;
 381                         reg[2] = pm;
 382                 }
 383         } else {
 384                 /* fix for frequency less than 45 MHz */
 385                 reg[1] = 0x06;
 386                 reg[2] = 0x11;
 387         }
 388
 389         /* fix clock out */
 390         reg[6] |= 0x20;
 391
 392         /* From VCO frequency determines the XIN ( fractional part of Delta
 393            Sigma PLL) and divided value (XDIV) */
 394         xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
 395         xin = (xin << 15) / xtal_freq_khz_2;
 396         if (xin >= 16384)
 397                 xin += 32768;
 398
 399         reg[3] = xin >> 8;
 400         reg[4] = xin & 0xff;
 401
 402         if (delsys == SYS_DVBT) {
 403                 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
 404                 switch (p->bandwidth_hz) {
 405                 case 6000000:
 406                         reg[6] |= 0x80;
 407                         break;
 408                 case 7000000:
 409                         reg[6] |= 0x40;
 410                         break;
 411                 case 8000000:
 412                 default:
 413                         break;
 414                 }
 415         } else {
 416                 err("%s: modulation type not supported!", __func__);
 417                 return -EINVAL;
 418         }
 419
 420         /* modified for Realtek demod */
 421         reg[5] |= 0x07;
 422
 423         for (i = 1; i <= 6; i++) {
 424                 ret = fc0013_writereg(priv, i, reg[i]);
 425                 if (ret)
 426                         goto exit;
 427         }
 428
 429         ret = fc0013_readreg(priv, 0x11, &tmp);
 430         if (ret)
 431                 goto exit;
 432         if (multi == 64)
 433                 ret = fc0013_writereg(priv, 0x11, tmp | 0x04);
 434         else
 435                 ret = fc0013_writereg(priv, 0x11, tmp & 0xfb);
 436         if (ret)
 437                 goto exit;
 438
 439         /* VCO Calibration */
 440         ret = fc0013_writereg(priv, 0x0e, 0x80);
 441         if (!ret)
 442                 ret = fc0013_writereg(priv, 0x0e, 0x00);
 443
 444         /* VCO Re-Calibration if needed */
 445         if (!ret)
 446                 ret = fc0013_writereg(priv, 0x0e, 0x00);
 447
 448         if (!ret) {
 449                 msleep(10);
 450                 ret = fc0013_readreg(priv, 0x0e, &tmp);
 451         }
 452         if (ret)
 453                 goto exit;
 454
 455         /* vco selection */
 456         tmp &= 0x3f;
 457
 458         if (vco_select) {
 459                 if (tmp > 0x3c) {
 460                         reg[6] &= ~0x08;
 461                         ret = fc0013_writereg(priv, 0x06, reg[6]);
 462                         if (!ret)
 463                                 ret = fc0013_writereg(priv, 0x0e, 0x80);
 464                         if (!ret)
 465                                 ret = fc0013_writereg(priv, 0x0e, 0x00);
 466                 }
 467         } else {
 468                 if (tmp < 0x02) {
 469                         reg[6] |= 0x08;
 470                         ret = fc0013_writereg(priv, 0x06, reg[6]);
 471                         if (!ret)
 472                                 ret = fc0013_writereg(priv, 0x0e, 0x80);
 473                         if (!ret)
 474                                 ret = fc0013_writereg(priv, 0x0e, 0x00);
 475                 }
 476         }
 477
 478         priv->frequency = p->frequency;
 479         priv->bandwidth = p->bandwidth_hz;
 480
 481 exit:
 482         if (fe->ops.i2c_gate_ctrl)
 483                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 484         if (ret)
 485                 warn("%s: failed: %d", __func__, ret);
 486         return ret;
 487 }
 488
 489 static int fc0013_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 490 {
 491         struct fc0013_priv *priv = fe->tuner_priv;
 492         *frequency = priv->frequency;
 493         return 0;
 494 }
 495
 496 static int fc0013_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
 497 {
 498         /* always ? */
 499         *frequency = 0;
 500         return 0;
 501 }
 502
 503 static int fc0013_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 504 {
 505         struct fc0013_priv *priv = fe->tuner_priv;
 506         *bandwidth = priv->bandwidth;
 507         return 0;
 508 }
 509
 510 #define INPUT_ADC_LEVEL -8
 511
 512 static int fc0013_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
 513 {
 514         struct fc0013_priv *priv = fe->tuner_priv;
 515         int ret;
 516         unsigned char tmp;
 517         int int_temp, lna_gain, int_lna, tot_agc_gain, power;
 518         const int fc0013_lna_gain_table[] = {
 519                 /* low gain */
 520                 -63, -58, -99, -73,
 521                 -63, -65, -54, -60,
 522                 /* middle gain */
 523                  71,  70,  68,  67,
 524                  65,  63,  61,  58,
 525                 /* high gain */
 526                 197, 191, 188, 186,
 527                 184, 182, 181, 179,
 528         };
 529
 530         if (fe->ops.i2c_gate_ctrl)
 531                 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
 532
 533         ret = fc0013_writereg(priv, 0x13, 0x00);
 534         if (ret)
 535                 goto err;
 536
 537         ret = fc0013_readreg(priv, 0x13, &tmp);
 538         if (ret)
 539                 goto err;
 540         int_temp = tmp;
 541
 542         ret = fc0013_readreg(priv, 0x14, &tmp);
 543         if (ret)
 544                 goto err;
 545         lna_gain = tmp & 0x1f;
 546
 547         if (fe->ops.i2c_gate_ctrl)
 548                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 549
 550         if (lna_gain < ARRAY_SIZE(fc0013_lna_gain_table)) {
 551                 int_lna = fc0013_lna_gain_table[lna_gain];
 552                 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
 553                                 (int_temp & 0x1f)) * 2;
 554                 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
 555
 556                 if (power >= 45)
 557                         *strength = 255;        /* 100% */
 558                 else if (power < -95)
 559                         *strength = 0;
 560                 else
 561                         *strength = (power + 95) * 255 / 140;
 562
 563                 *strength |= *strength << 8;
 564         } else {
 565                 ret = -1;
 566         }
 567
 568         goto exit;
 569
 570 err:
 571         if (fe->ops.i2c_gate_ctrl)
 572                 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
 573 exit:
 574         if (ret)
 575                 warn("%s: failed: %d", __func__, ret);
 576         return ret;
 577 }
 578
 579 static const struct dvb_tuner_ops fc0013_tuner_ops = {
 580         .info = {
 581                 .name           = "Fitipower FC0013",
 582
 583                 .frequency_min  = 37000000,     /* estimate */
 584                 .frequency_max  = 1680000000,   /* CHECK */
 585                 .frequency_step = 0,
 586         },
 587
 588         .release        = fc0013_release,
 589
 590         .init           = fc0013_init,
 591         .sleep          = fc0013_sleep,
 592
 593         .set_params     = fc0013_set_params,
 594
 595         .get_frequency  = fc0013_get_frequency,
 596         .get_if_frequency = fc0013_get_if_frequency,
 597         .get_bandwidth  = fc0013_get_bandwidth,
 598
 599         .get_rf_strength = fc0013_get_rf_strength,
 600 };
 601
 602 struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
 603         struct i2c_adapter *i2c, u8 i2c_address, int dual_master,
 604         enum fc001x_xtal_freq xtal_freq)
 605 {
 606         struct fc0013_priv *priv = NULL;
 607
 608         priv = kzalloc(sizeof(struct fc0013_priv), GFP_KERNEL);
 609         if (priv == NULL)
 610                 return NULL;
 611
 612         priv->i2c = i2c;
 613         priv->dual_master = dual_master;
 614         priv->addr = i2c_address;
 615         priv->xtal_freq = xtal_freq;
 616
 617         info("Fitipower FC0013 successfully attached.");
 618
 619         fe->tuner_priv = priv;
 620
 621         memcpy(&fe->ops.tuner_ops, &fc0013_tuner_ops,
 622                 sizeof(struct dvb_tuner_ops));
 623
 624         return fe;
 625 }
 626 EXPORT_SYMBOL(fc0013_attach);
 627
 628 MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver");
 629 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
 630 MODULE_LICENSE("GPL");
 631 MODULE_VERSION("0.2");