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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / mfd / asic3.c
blob0413c8159551efb86a61db1ef5d39317c92c1486
1 /*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
13 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/export.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/mfd/asic3.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/ds1wm.h>
32 #include <linux/mfd/tmio.h>
33
34 enum {
35 ASIC3_CLOCK_SPI,
36 ASIC3_CLOCK_OWM,
37 ASIC3_CLOCK_PWM0,
38 ASIC3_CLOCK_PWM1,
39 ASIC3_CLOCK_LED0,
40 ASIC3_CLOCK_LED1,
41 ASIC3_CLOCK_LED2,
42 ASIC3_CLOCK_SD_HOST,
43 ASIC3_CLOCK_SD_BUS,
44 ASIC3_CLOCK_SMBUS,
45 ASIC3_CLOCK_EX0,
46 ASIC3_CLOCK_EX1,
47 };
48
49 struct asic3_clk {
50 int enabled;
51 unsigned int cdex;
52 unsigned long rate;
53 };
54
55 #define INIT_CDEX(_name, _rate) \
56 [ASIC3_CLOCK_##_name] = { \
57 .cdex = CLOCK_CDEX_##_name, \
58 .rate = _rate, \
59 }
60
61 static struct asic3_clk asic3_clk_init[] __initdata = {
62 INIT_CDEX(SPI, 0),
63 INIT_CDEX(OWM, 5000000),
64 INIT_CDEX(PWM0, 0),
65 INIT_CDEX(PWM1, 0),
66 INIT_CDEX(LED0, 0),
67 INIT_CDEX(LED1, 0),
68 INIT_CDEX(LED2, 0),
69 INIT_CDEX(SD_HOST, 24576000),
70 INIT_CDEX(SD_BUS, 12288000),
71 INIT_CDEX(SMBUS, 0),
72 INIT_CDEX(EX0, 32768),
73 INIT_CDEX(EX1, 24576000),
74 };
75
76 struct asic3 {
77 void __iomem *mapping;
78 unsigned int bus_shift;
79 unsigned int irq_nr;
80 unsigned int irq_base;
81 spinlock_t lock;
82 u16 irq_bothedge[4];
83 struct gpio_chip gpio;
84 struct device *dev;
85 void __iomem *tmio_cnf;
86
87 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
88 };
89
90 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
91
92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
93 {
94 iowrite16(value, asic->mapping +
95 (reg >> asic->bus_shift));
96 }
97 EXPORT_SYMBOL_GPL(asic3_write_register);
98
99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
100 {
101 return ioread16(asic->mapping +
102 (reg >> asic->bus_shift));
103 }
104 EXPORT_SYMBOL_GPL(asic3_read_register);
105
106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
107 {
108 unsigned long flags;
109 u32 val;
110
111 spin_lock_irqsave(&asic->lock, flags);
112 val = asic3_read_register(asic, reg);
113 if (set)
114 val |= bits;
115 else
116 val &= ~bits;
117 asic3_write_register(asic, reg, val);
118 spin_unlock_irqrestore(&asic->lock, flags);
119 }
120
121 /* IRQs */
122 #define MAX_ASIC_ISR_LOOPS 20
123 #define ASIC3_GPIO_BASE_INCR \
124 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
125
126 static void asic3_irq_flip_edge(struct asic3 *asic,
127 u32 base, int bit)
128 {
129 u16 edge;
130 unsigned long flags;
131
132 spin_lock_irqsave(&asic->lock, flags);
133 edge = asic3_read_register(asic,
134 base + ASIC3_GPIO_EDGE_TRIGGER);
135 edge ^= bit;
136 asic3_write_register(asic,
137 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
138 spin_unlock_irqrestore(&asic->lock, flags);
139 }
140
141 static void asic3_irq_demux(struct irq_desc *desc)
142 {
143 struct asic3 *asic = irq_desc_get_handler_data(desc);
144 struct irq_data *data = irq_desc_get_irq_data(desc);
145 int iter, i;
146 unsigned long flags;
147
148 data->chip->irq_ack(data);
149
150 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
151 u32 status;
152 int bank;
153
154 spin_lock_irqsave(&asic->lock, flags);
155 status = asic3_read_register(asic,
156 ASIC3_OFFSET(INTR, P_INT_STAT));
157 spin_unlock_irqrestore(&asic->lock, flags);
158
159 /* Check all ten register bits */
160 if ((status & 0x3ff) == 0)
161 break;
162
163 /* Handle GPIO IRQs */
164 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
165 if (status & (1 << bank)) {
166 unsigned long base, istat;
167
168 base = ASIC3_GPIO_A_BASE
169 + bank * ASIC3_GPIO_BASE_INCR;
170 spin_lock_irqsave(&asic->lock, flags);
171 istat = asic3_read_register(asic,
172 base +
173 ASIC3_GPIO_INT_STATUS);
174 /* Clearing IntStatus */
175 asic3_write_register(asic,
176 base +
177 ASIC3_GPIO_INT_STATUS, 0);
178 spin_unlock_irqrestore(&asic->lock, flags);
179
180 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
181 int bit = (1 << i);
182 unsigned int irqnr;
183
184 if (!(istat & bit))
185 continue;
186
187 irqnr = asic->irq_base +
188 (ASIC3_GPIOS_PER_BANK * bank)
189 + i;
190 generic_handle_irq(irqnr);
191 if (asic->irq_bothedge[bank] & bit)
192 asic3_irq_flip_edge(asic, base,
193 bit);
194 }
195 }
196 }
197
198 /* Handle remaining IRQs in the status register */
199 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
200 /* They start at bit 4 and go up */
201 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
202 generic_handle_irq(asic->irq_base + i);
203 }
204 }
205
206 if (iter >= MAX_ASIC_ISR_LOOPS)
207 dev_err(asic->dev, "interrupt processing overrun\n");
208 }
209
210 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
211 {
212 int n;
213
214 n = (irq - asic->irq_base) >> 4;
215
216 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
217 }
218
219 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
220 {
221 return (irq - asic->irq_base) & 0xf;
222 }
223
224 static void asic3_mask_gpio_irq(struct irq_data *data)
225 {
226 struct asic3 *asic = irq_data_get_irq_chip_data(data);
227 u32 val, bank, index;
228 unsigned long flags;
229
230 bank = asic3_irq_to_bank(asic, data->irq);
231 index = asic3_irq_to_index(asic, data->irq);
232
233 spin_lock_irqsave(&asic->lock, flags);
234 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
235 val |= 1 << index;
236 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
237 spin_unlock_irqrestore(&asic->lock, flags);
238 }
239
240 static void asic3_mask_irq(struct irq_data *data)
241 {
242 struct asic3 *asic = irq_data_get_irq_chip_data(data);
243 int regval;
244 unsigned long flags;
245
246 spin_lock_irqsave(&asic->lock, flags);
247 regval = asic3_read_register(asic,
248 ASIC3_INTR_BASE +
249 ASIC3_INTR_INT_MASK);
250
251 regval &= ~(ASIC3_INTMASK_MASK0 <<
252 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
253
254 asic3_write_register(asic,
255 ASIC3_INTR_BASE +
256 ASIC3_INTR_INT_MASK,
257 regval);
258 spin_unlock_irqrestore(&asic->lock, flags);
259 }
260
261 static void asic3_unmask_gpio_irq(struct irq_data *data)
262 {
263 struct asic3 *asic = irq_data_get_irq_chip_data(data);
264 u32 val, bank, index;
265 unsigned long flags;
266
267 bank = asic3_irq_to_bank(asic, data->irq);
268 index = asic3_irq_to_index(asic, data->irq);
269
270 spin_lock_irqsave(&asic->lock, flags);
271 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
272 val &= ~(1 << index);
273 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
274 spin_unlock_irqrestore(&asic->lock, flags);
275 }
276
277 static void asic3_unmask_irq(struct irq_data *data)
278 {
279 struct asic3 *asic = irq_data_get_irq_chip_data(data);
280 int regval;
281 unsigned long flags;
282
283 spin_lock_irqsave(&asic->lock, flags);
284 regval = asic3_read_register(asic,
285 ASIC3_INTR_BASE +
286 ASIC3_INTR_INT_MASK);
287
288 regval |= (ASIC3_INTMASK_MASK0 <<
289 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
290
291 asic3_write_register(asic,
292 ASIC3_INTR_BASE +
293 ASIC3_INTR_INT_MASK,
294 regval);
295 spin_unlock_irqrestore(&asic->lock, flags);
296 }
297
298 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
299 {
300 struct asic3 *asic = irq_data_get_irq_chip_data(data);
301 u32 bank, index;
302 u16 trigger, level, edge, bit;
303 unsigned long flags;
304
305 bank = asic3_irq_to_bank(asic, data->irq);
306 index = asic3_irq_to_index(asic, data->irq);
307 bit = 1<<index;
308
309 spin_lock_irqsave(&asic->lock, flags);
310 level = asic3_read_register(asic,
311 bank + ASIC3_GPIO_LEVEL_TRIGGER);
312 edge = asic3_read_register(asic,
313 bank + ASIC3_GPIO_EDGE_TRIGGER);
314 trigger = asic3_read_register(asic,
315 bank + ASIC3_GPIO_TRIGGER_TYPE);
316 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
317
318 if (type == IRQ_TYPE_EDGE_RISING) {
319 trigger |= bit;
320 edge |= bit;
321 } else if (type == IRQ_TYPE_EDGE_FALLING) {
322 trigger |= bit;
323 edge &= ~bit;
324 } else if (type == IRQ_TYPE_EDGE_BOTH) {
325 trigger |= bit;
326 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
327 edge &= ~bit;
328 else
329 edge |= bit;
330 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
331 } else if (type == IRQ_TYPE_LEVEL_LOW) {
332 trigger &= ~bit;
333 level &= ~bit;
334 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
335 trigger &= ~bit;
336 level |= bit;
337 } else {
338 /*
339 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
340 * be careful to not unmask them if mask was also called.
341 * Probably need internal state for mask.
342 */
343 dev_notice(asic->dev, "irq type not changed\n");
344 }
345 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
346 level);
347 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
348 edge);
349 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
350 trigger);
351 spin_unlock_irqrestore(&asic->lock, flags);
352 return 0;
353 }
354
355 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
356 {
357 struct asic3 *asic = irq_data_get_irq_chip_data(data);
358 u32 bank, index;
359 u16 bit;
360
361 bank = asic3_irq_to_bank(asic, data->irq);
362 index = asic3_irq_to_index(asic, data->irq);
363 bit = 1<<index;
364
365 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
366
367 return 0;
368 }
369
370 static struct irq_chip asic3_gpio_irq_chip = {
371 .name = "ASIC3-GPIO",
372 .irq_ack = asic3_mask_gpio_irq,
373 .irq_mask = asic3_mask_gpio_irq,
374 .irq_unmask = asic3_unmask_gpio_irq,
375 .irq_set_type = asic3_gpio_irq_type,
376 .irq_set_wake = asic3_gpio_irq_set_wake,
377 };
378
379 static struct irq_chip asic3_irq_chip = {
380 .name = "ASIC3",
381 .irq_ack = asic3_mask_irq,
382 .irq_mask = asic3_mask_irq,
383 .irq_unmask = asic3_unmask_irq,
384 };
385
386 static int __init asic3_irq_probe(struct platform_device *pdev)
387 {
388 struct asic3 *asic = platform_get_drvdata(pdev);
389 unsigned long clksel = 0;
390 unsigned int irq, irq_base;
391 int ret;
392
393 ret = platform_get_irq(pdev, 0);
394 if (ret < 0)
395 return ret;
396 asic->irq_nr = ret;
397
398 /* turn on clock to IRQ controller */
399 clksel |= CLOCK_SEL_CX;
400 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
401 clksel);
402
403 irq_base = asic->irq_base;
404
405 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
406 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
407 irq_set_chip(irq, &asic3_gpio_irq_chip);
408 else
409 irq_set_chip(irq, &asic3_irq_chip);
410
411 irq_set_chip_data(irq, asic);
412 irq_set_handler(irq, handle_level_irq);
413 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
414 }
415
416 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
417 ASIC3_INTMASK_GINTMASK);
418
419 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
420 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
421
422 return 0;
423 }
424
425 static void asic3_irq_remove(struct platform_device *pdev)
426 {
427 struct asic3 *asic = platform_get_drvdata(pdev);
428 unsigned int irq, irq_base;
429
430 irq_base = asic->irq_base;
431
432 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
433 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
434 irq_set_chip_and_handler(irq, NULL, NULL);
435 irq_set_chip_data(irq, NULL);
436 }
437 irq_set_chained_handler(asic->irq_nr, NULL);
438 }
439
440 /* GPIOs */
441 static int asic3_gpio_direction(struct gpio_chip *chip,
442 unsigned offset, int out)
443 {
444 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
445 unsigned int gpio_base;
446 unsigned long flags;
447 struct asic3 *asic;
448
449 asic = gpiochip_get_data(chip);
450 gpio_base = ASIC3_GPIO_TO_BASE(offset);
451
452 if (gpio_base > ASIC3_GPIO_D_BASE) {
453 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
454 gpio_base, offset);
455 return -EINVAL;
456 }
457
458 spin_lock_irqsave(&asic->lock, flags);
459
460 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
461
462 /* Input is 0, Output is 1 */
463 if (out)
464 out_reg |= mask;
465 else
466 out_reg &= ~mask;
467
468 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
469
470 spin_unlock_irqrestore(&asic->lock, flags);
471
472 return 0;
473
474 }
475
476 static int asic3_gpio_direction_input(struct gpio_chip *chip,
477 unsigned offset)
478 {
479 return asic3_gpio_direction(chip, offset, 0);
480 }
481
482 static int asic3_gpio_direction_output(struct gpio_chip *chip,
483 unsigned offset, int value)
484 {
485 return asic3_gpio_direction(chip, offset, 1);
486 }
487
488 static int asic3_gpio_get(struct gpio_chip *chip,
489 unsigned offset)
490 {
491 unsigned int gpio_base;
492 u32 mask = ASIC3_GPIO_TO_MASK(offset);
493 struct asic3 *asic;
494
495 asic = gpiochip_get_data(chip);
496 gpio_base = ASIC3_GPIO_TO_BASE(offset);
497
498 if (gpio_base > ASIC3_GPIO_D_BASE) {
499 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
500 gpio_base, offset);
501 return -EINVAL;
502 }
503
504 return !!(asic3_read_register(asic,
505 gpio_base + ASIC3_GPIO_STATUS) & mask);
506 }
507
508 static void asic3_gpio_set(struct gpio_chip *chip,
509 unsigned offset, int value)
510 {
511 u32 mask, out_reg;
512 unsigned int gpio_base;
513 unsigned long flags;
514 struct asic3 *asic;
515
516 asic = gpiochip_get_data(chip);
517 gpio_base = ASIC3_GPIO_TO_BASE(offset);
518
519 if (gpio_base > ASIC3_GPIO_D_BASE) {
520 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
521 gpio_base, offset);
522 return;
523 }
524
525 mask = ASIC3_GPIO_TO_MASK(offset);
526
527 spin_lock_irqsave(&asic->lock, flags);
528
529 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
530
531 if (value)
532 out_reg |= mask;
533 else
534 out_reg &= ~mask;
535
536 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
537
538 spin_unlock_irqrestore(&asic->lock, flags);
539 }
540
541 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
542 {
543 struct asic3 *asic = gpiochip_get_data(chip);
544
545 return asic->irq_base + offset;
546 }
547
548 static __init int asic3_gpio_probe(struct platform_device *pdev,
549 u16 *gpio_config, int num)
550 {
551 struct asic3 *asic = platform_get_drvdata(pdev);
552 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
553 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
554 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
555 int i;
556
557 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
558 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
559 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
560
561 /* Enable all GPIOs */
562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
564 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
566
567 for (i = 0; i < num; i++) {
568 u8 alt, pin, dir, init, bank_num, bit_num;
569 u16 config = gpio_config[i];
570
571 pin = ASIC3_CONFIG_GPIO_PIN(config);
572 alt = ASIC3_CONFIG_GPIO_ALT(config);
573 dir = ASIC3_CONFIG_GPIO_DIR(config);
574 init = ASIC3_CONFIG_GPIO_INIT(config);
575
576 bank_num = ASIC3_GPIO_TO_BANK(pin);
577 bit_num = ASIC3_GPIO_TO_BIT(pin);
578
579 alt_reg[bank_num] |= (alt << bit_num);
580 out_reg[bank_num] |= (init << bit_num);
581 dir_reg[bank_num] |= (dir << bit_num);
582 }
583
584 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
585 asic3_write_register(asic,
586 ASIC3_BANK_TO_BASE(i) +
587 ASIC3_GPIO_DIRECTION,
588 dir_reg[i]);
589 asic3_write_register(asic,
590 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
591 out_reg[i]);
592 asic3_write_register(asic,
593 ASIC3_BANK_TO_BASE(i) +
594 ASIC3_GPIO_ALT_FUNCTION,
595 alt_reg[i]);
596 }
597
598 return gpiochip_add_data(&asic->gpio, asic);
599 }
600
601 static int asic3_gpio_remove(struct platform_device *pdev)
602 {
603 struct asic3 *asic = platform_get_drvdata(pdev);
604
605 gpiochip_remove(&asic->gpio);
606 return 0;
607 }
608
609 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
610 {
611 unsigned long flags;
612 u32 cdex;
613
614 spin_lock_irqsave(&asic->lock, flags);
615 if (clk->enabled++ == 0) {
616 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
617 cdex |= clk->cdex;
618 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
619 }
620 spin_unlock_irqrestore(&asic->lock, flags);
621 }
622
623 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
624 {
625 unsigned long flags;
626 u32 cdex;
627
628 WARN_ON(clk->enabled == 0);
629
630 spin_lock_irqsave(&asic->lock, flags);
631 if (--clk->enabled == 0) {
632 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
633 cdex &= ~clk->cdex;
634 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
635 }
636 spin_unlock_irqrestore(&asic->lock, flags);
637 }
638
639 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
640 static struct ds1wm_driver_data ds1wm_pdata = {
641 .active_high = 1,
642 .reset_recover_delay = 1,
643 };
644
645 static struct resource ds1wm_resources[] = {
646 {
647 .start = ASIC3_OWM_BASE,
648 .end = ASIC3_OWM_BASE + 0x13,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .start = ASIC3_IRQ_OWM,
653 .end = ASIC3_IRQ_OWM,
654 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
655 },
656 };
657
658 static int ds1wm_enable(struct platform_device *pdev)
659 {
660 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
661
662 /* Turn on external clocks and the OWM clock */
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
664 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
666 usleep_range(1000, 5000);
667
668 /* Reset and enable DS1WM */
669 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
670 ASIC3_EXTCF_OWM_RESET, 1);
671 usleep_range(1000, 5000);
672 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
673 ASIC3_EXTCF_OWM_RESET, 0);
674 usleep_range(1000, 5000);
675 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
676 ASIC3_EXTCF_OWM_EN, 1);
677 usleep_range(1000, 5000);
678
679 return 0;
680 }
681
682 static int ds1wm_disable(struct platform_device *pdev)
683 {
684 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
685
686 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
687 ASIC3_EXTCF_OWM_EN, 0);
688
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
690 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
692
693 return 0;
694 }
695
696 static const struct mfd_cell asic3_cell_ds1wm = {
697 .name = "ds1wm",
698 .enable = ds1wm_enable,
699 .disable = ds1wm_disable,
700 .platform_data = &ds1wm_pdata,
701 .pdata_size = sizeof(ds1wm_pdata),
702 .num_resources = ARRAY_SIZE(ds1wm_resources),
703 .resources = ds1wm_resources,
704 };
705
706 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
707 {
708 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
709
710 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
711 }
712
713 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
714 {
715 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
716
717 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
718 }
719
720 static struct tmio_mmc_data asic3_mmc_data = {
721 .hclk = 24576000,
722 .set_pwr = asic3_mmc_pwr,
723 .set_clk_div = asic3_mmc_clk_div,
724 };
725
726 static struct resource asic3_mmc_resources[] = {
727 {
728 .start = ASIC3_SD_CTRL_BASE,
729 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
730 .flags = IORESOURCE_MEM,
731 },
732 {
733 .start = 0,
734 .end = 0,
735 .flags = IORESOURCE_IRQ,
736 },
737 };
738
739 static int asic3_mmc_enable(struct platform_device *pdev)
740 {
741 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
742
743 /* Not sure if it must be done bit by bit, but leaving as-is */
744 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
745 ASIC3_SDHWCTRL_LEVCD, 1);
746 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
747 ASIC3_SDHWCTRL_LEVWP, 1);
748 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
749 ASIC3_SDHWCTRL_SUSPEND, 0);
750 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
751 ASIC3_SDHWCTRL_PCLR, 0);
752
753 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
754 /* CLK32 used for card detection and for interruption detection
755 * when HCLK is stopped.
756 */
757 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
758 usleep_range(1000, 5000);
759
760 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
761 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
762 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
763
764 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
765 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
766 usleep_range(1000, 5000);
767
768 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
769 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
770
771 /* Enable SD card slot 3.3V power supply */
772 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
773 ASIC3_SDHWCTRL_SDPWR, 1);
774
775 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
776 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
777 ASIC3_SD_CTRL_BASE >> 1);
778
779 return 0;
780 }
781
782 static int asic3_mmc_disable(struct platform_device *pdev)
783 {
784 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
785
786 /* Put in suspend mode */
787 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
788 ASIC3_SDHWCTRL_SUSPEND, 1);
789
790 /* Disable clocks */
791 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
792 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
795 return 0;
796 }
797
798 static const struct mfd_cell asic3_cell_mmc = {
799 .name = "tmio-mmc",
800 .enable = asic3_mmc_enable,
801 .disable = asic3_mmc_disable,
802 .suspend = asic3_mmc_disable,
803 .resume = asic3_mmc_enable,
804 .platform_data = &asic3_mmc_data,
805 .pdata_size = sizeof(asic3_mmc_data),
806 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
807 .resources = asic3_mmc_resources,
808 };
809
810 static const int clock_ledn[ASIC3_NUM_LEDS] = {
811 [0] = ASIC3_CLOCK_LED0,
812 [1] = ASIC3_CLOCK_LED1,
813 [2] = ASIC3_CLOCK_LED2,
814 };
815
816 static int asic3_leds_enable(struct platform_device *pdev)
817 {
818 const struct mfd_cell *cell = mfd_get_cell(pdev);
819 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
820
821 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
822
823 return 0;
824 }
825
826 static int asic3_leds_disable(struct platform_device *pdev)
827 {
828 const struct mfd_cell *cell = mfd_get_cell(pdev);
829 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
830
831 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
832
833 return 0;
834 }
835
836 static int asic3_leds_suspend(struct platform_device *pdev)
837 {
838 const struct mfd_cell *cell = mfd_get_cell(pdev);
839 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
840
841 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
842 usleep_range(1000, 5000);
843
844 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
845
846 return 0;
847 }
848
849 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
850 [0] = {
851 .name = "leds-asic3",
852 .id = 0,
853 .enable = asic3_leds_enable,
854 .disable = asic3_leds_disable,
855 .suspend = asic3_leds_suspend,
856 .resume = asic3_leds_enable,
857 },
858 [1] = {
859 .name = "leds-asic3",
860 .id = 1,
861 .enable = asic3_leds_enable,
862 .disable = asic3_leds_disable,
863 .suspend = asic3_leds_suspend,
864 .resume = asic3_leds_enable,
865 },
866 [2] = {
867 .name = "leds-asic3",
868 .id = 2,
869 .enable = asic3_leds_enable,
870 .disable = asic3_leds_disable,
871 .suspend = asic3_leds_suspend,
872 .resume = asic3_leds_enable,
873 },
874 };
875
876 static int __init asic3_mfd_probe(struct platform_device *pdev,
877 struct asic3_platform_data *pdata,
878 struct resource *mem)
879 {
880 struct asic3 *asic = platform_get_drvdata(pdev);
881 struct resource *mem_sdio;
882 int irq, ret;
883
884 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
885 if (!mem_sdio)
886 dev_dbg(asic->dev, "no SDIO MEM resource\n");
887
888 irq = platform_get_irq(pdev, 1);
889 if (irq < 0)
890 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
891
892 /* DS1WM */
893 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
894 ASIC3_EXTCF_OWM_SMB, 0);
895
896 ds1wm_resources[0].start >>= asic->bus_shift;
897 ds1wm_resources[0].end >>= asic->bus_shift;
898
899 /* MMC */
900 if (mem_sdio) {
901 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
902 asic->bus_shift) + mem_sdio->start,
903 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
904 if (!asic->tmio_cnf) {
905 ret = -ENOMEM;
906 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
907 goto out;
908 }
909 }
910 asic3_mmc_resources[0].start >>= asic->bus_shift;
911 asic3_mmc_resources[0].end >>= asic->bus_shift;
912
913 if (pdata->clock_rate) {
914 ds1wm_pdata.clock_rate = pdata->clock_rate;
915 ret = mfd_add_devices(&pdev->dev, pdev->id,
916 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
917 if (ret < 0)
918 goto out;
919 }
920
921 if (mem_sdio && (irq >= 0)) {
922 ret = mfd_add_devices(&pdev->dev, pdev->id,
923 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
924 if (ret < 0)
925 goto out;
926 }
927
928 ret = 0;
929 if (pdata->leds) {
930 int i;
931
932 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
933 asic3_cell_leds[i].platform_data = &pdata->leds[i];
934 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
935 }
936 ret = mfd_add_devices(&pdev->dev, 0,
937 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
938 }
939
940 out:
941 return ret;
942 }
943
944 static void asic3_mfd_remove(struct platform_device *pdev)
945 {
946 struct asic3 *asic = platform_get_drvdata(pdev);
947
948 mfd_remove_devices(&pdev->dev);
949 iounmap(asic->tmio_cnf);
950 }
951
952 /* Core */
953 static int __init asic3_probe(struct platform_device *pdev)
954 {
955 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
956 struct asic3 *asic;
957 struct resource *mem;
958 unsigned long clksel;
959 int ret = 0;
960
961 asic = devm_kzalloc(&pdev->dev,
962 sizeof(struct asic3), GFP_KERNEL);
963 if (!asic)
964 return -ENOMEM;
965
966 spin_lock_init(&asic->lock);
967 platform_set_drvdata(pdev, asic);
968 asic->dev = &pdev->dev;
969
970 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
971 if (!mem) {
972 dev_err(asic->dev, "no MEM resource\n");
973 return -ENOMEM;
974 }
975
976 asic->mapping = ioremap(mem->start, resource_size(mem));
977 if (!asic->mapping) {
978 dev_err(asic->dev, "Couldn't ioremap\n");
979 return -ENOMEM;
980 }
981
982 asic->irq_base = pdata->irq_base;
983
984 /* calculate bus shift from mem resource */
985 asic->bus_shift = 2 - (resource_size(mem) >> 12);
986
987 clksel = 0;
988 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
989
990 ret = asic3_irq_probe(pdev);
991 if (ret < 0) {
992 dev_err(asic->dev, "Couldn't probe IRQs\n");
993 goto out_unmap;
994 }
995
996 asic->gpio.label = "asic3";
997 asic->gpio.base = pdata->gpio_base;
998 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
999 asic->gpio.get = asic3_gpio_get;
1000 asic->gpio.set = asic3_gpio_set;
1001 asic->gpio.direction_input = asic3_gpio_direction_input;
1002 asic->gpio.direction_output = asic3_gpio_direction_output;
1003 asic->gpio.to_irq = asic3_gpio_to_irq;
1004
1005 ret = asic3_gpio_probe(pdev,
1006 pdata->gpio_config,
1007 pdata->gpio_config_num);
1008 if (ret < 0) {
1009 dev_err(asic->dev, "GPIO probe failed\n");
1010 goto out_irq;
1011 }
1012
1013 /* Making a per-device copy is only needed for the
1014 * theoretical case of multiple ASIC3s on one board:
1015 */
1016 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1017
1018 asic3_mfd_probe(pdev, pdata, mem);
1019
1020 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1021 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1022
1023 dev_info(asic->dev, "ASIC3 Core driver\n");
1024
1025 return 0;
1026
1027 out_irq:
1028 asic3_irq_remove(pdev);
1029
1030 out_unmap:
1031 iounmap(asic->mapping);
1032
1033 return ret;
1034 }
1035
1036 static int asic3_remove(struct platform_device *pdev)
1037 {
1038 int ret;
1039 struct asic3 *asic = platform_get_drvdata(pdev);
1040
1041 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1042 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1043
1044 asic3_mfd_remove(pdev);
1045
1046 ret = asic3_gpio_remove(pdev);
1047 if (ret < 0)
1048 return ret;
1049 asic3_irq_remove(pdev);
1050
1051 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1052
1053 iounmap(asic->mapping);
1054
1055 return 0;
1056 }
1057
1058 static void asic3_shutdown(struct platform_device *pdev)
1059 {
1060 }
1061
1062 static struct platform_driver asic3_device_driver = {
1063 .driver = {
1064 .name = "asic3",
1065 },
1066 .remove = asic3_remove,
1067 .shutdown = asic3_shutdown,
1068 };
1069
1070 static int __init asic3_init(void)
1071 {
1072 int retval = 0;
1073
1074 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1075
1076 return retval;
1077 }
1078
1079 subsys_initcall(asic3_init);
Linux with added FPC-III support