| blob | c59465829387757ddd3d8257c409b400534f048c |
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
14 #ifndef _DW_MMC_H_
15 #define _DW_MMC_H_
17 #define DW_MMC_240A 0x240a
18 #define DW_MMC_280A 0x280a
20 #define SDMMC_CTRL 0x000
21 #define SDMMC_PWREN 0x004
22 #define SDMMC_CLKDIV 0x008
23 #define SDMMC_CLKSRC 0x00c
24 #define SDMMC_CLKENA 0x010
25 #define SDMMC_TMOUT 0x014
26 #define SDMMC_CTYPE 0x018
27 #define SDMMC_BLKSIZ 0x01c
28 #define SDMMC_BYTCNT 0x020
29 #define SDMMC_INTMASK 0x024
30 #define SDMMC_CMDARG 0x028
31 #define SDMMC_CMD 0x02c
32 #define SDMMC_RESP0 0x030
33 #define SDMMC_RESP1 0x034
34 #define SDMMC_RESP2 0x038
35 #define SDMMC_RESP3 0x03c
36 #define SDMMC_MINTSTS 0x040
37 #define SDMMC_RINTSTS 0x044
38 #define SDMMC_STATUS 0x048
39 #define SDMMC_FIFOTH 0x04c
40 #define SDMMC_CDETECT 0x050
41 #define SDMMC_WRTPRT 0x054
42 #define SDMMC_GPIO 0x058
43 #define SDMMC_TCBCNT 0x05c
44 #define SDMMC_TBBCNT 0x060
45 #define SDMMC_DEBNCE 0x064
46 #define SDMMC_USRID 0x068
47 #define SDMMC_VERID 0x06c
48 #define SDMMC_HCON 0x070
49 #define SDMMC_UHS_REG 0x074
50 #define SDMMC_RST_N 0x078
51 #define SDMMC_BMOD 0x080
52 #define SDMMC_PLDMND 0x084
53 #define SDMMC_DBADDR 0x088
54 #define SDMMC_IDSTS 0x08c
55 #define SDMMC_IDINTEN 0x090
56 #define SDMMC_DSCADDR 0x094
57 #define SDMMC_BUFADDR 0x098
58 #define SDMMC_CDTHRCTL 0x100
59 #define SDMMC_DATA(x) (x)
60 /*
61 * Registers to support idmac 64-bit address mode
62 */
63 #define SDMMC_DBADDRL 0x088
64 #define SDMMC_DBADDRU 0x08c
65 #define SDMMC_IDSTS64 0x090
66 #define SDMMC_IDINTEN64 0x094
67 #define SDMMC_DSCADDRL 0x098
68 #define SDMMC_DSCADDRU 0x09c
69 #define SDMMC_BUFADDRL 0x0A0
70 #define SDMMC_BUFADDRU 0x0A4
72 /*
73 * Data offset is difference according to Version
74 * Lower than 2.40a : data register offest is 0x100
75 */
76 #define DATA_OFFSET 0x100
77 #define DATA_240A_OFFSET 0x200
79 /* shift bit field */
80 #define _SBF(f, v) ((v) << (f))
82 /* Control register defines */
83 #define SDMMC_CTRL_USE_IDMAC BIT(25)
84 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
85 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
86 #define SDMMC_CTRL_SEND_CCSD BIT(9)
87 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
88 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
89 #define SDMMC_CTRL_READ_WAIT BIT(6)
90 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
91 #define SDMMC_CTRL_INT_ENABLE BIT(4)
92 #define SDMMC_CTRL_DMA_RESET BIT(2)
93 #define SDMMC_CTRL_FIFO_RESET BIT(1)
94 #define SDMMC_CTRL_RESET BIT(0)
95 /* Clock Enable register defines */
96 #define SDMMC_CLKEN_LOW_PWR BIT(16)
97 #define SDMMC_CLKEN_ENABLE BIT(0)
98 /* time-out register defines */
99 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
100 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
101 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
102 #define SDMMC_TMOUT_RESP_MSK 0xFF
103 /* card-type register defines */
104 #define SDMMC_CTYPE_8BIT BIT(16)
105 #define SDMMC_CTYPE_4BIT BIT(0)
106 #define SDMMC_CTYPE_1BIT 0
107 /* Interrupt status & mask register defines */
108 #define SDMMC_INT_SDIO(n) BIT(16 + (n))
109 #define SDMMC_INT_EBE BIT(15)
110 #define SDMMC_INT_ACD BIT(14)
111 #define SDMMC_INT_SBE BIT(13)
112 #define SDMMC_INT_HLE BIT(12)
113 #define SDMMC_INT_FRUN BIT(11)
114 #define SDMMC_INT_HTO BIT(10)
116 #define SDMMC_INT_DRTO BIT(9)
117 #define SDMMC_INT_RTO BIT(8)
118 #define SDMMC_INT_DCRC BIT(7)
119 #define SDMMC_INT_RCRC BIT(6)
120 #define SDMMC_INT_RXDR BIT(5)
121 #define SDMMC_INT_TXDR BIT(4)
122 #define SDMMC_INT_DATA_OVER BIT(3)
123 #define SDMMC_INT_CMD_DONE BIT(2)
124 #define SDMMC_INT_RESP_ERR BIT(1)
125 #define SDMMC_INT_CD BIT(0)
126 #define SDMMC_INT_ERROR 0xbfc2
127 /* Command register defines */
128 #define SDMMC_CMD_START BIT(31)
129 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
130 #define SDMMC_CMD_VOLT_SWITCH BIT(28)
131 #define SDMMC_CMD_CCS_EXP BIT(23)
132 #define SDMMC_CMD_CEATA_RD BIT(22)
133 #define SDMMC_CMD_UPD_CLK BIT(21)
134 #define SDMMC_CMD_INIT BIT(15)
135 #define SDMMC_CMD_STOP BIT(14)
136 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
137 #define SDMMC_CMD_SEND_STOP BIT(12)
138 #define SDMMC_CMD_STRM_MODE BIT(11)
139 #define SDMMC_CMD_DAT_WR BIT(10)
140 #define SDMMC_CMD_DAT_EXP BIT(9)
141 #define SDMMC_CMD_RESP_CRC BIT(8)
142 #define SDMMC_CMD_RESP_LONG BIT(7)
143 #define SDMMC_CMD_RESP_EXP BIT(6)
144 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
145 /* Status register defines */
146 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
147 #define SDMMC_STATUS_DMA_REQ BIT(31)
148 #define SDMMC_STATUS_BUSY BIT(9)
149 /* FIFOTH register defines */
150 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
151 ((r) & 0xFFF) << 16 | \
152 ((t) & 0xFFF))
153 /* HCON register defines */
154 #define DMA_INTERFACE_IDMA (0x0)
155 #define DMA_INTERFACE_DWDMA (0x1)
156 #define DMA_INTERFACE_GDMA (0x2)
157 #define DMA_INTERFACE_NODMA (0x3)
158 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
159 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
160 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
161 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
162 /* Internal DMAC interrupt defines */
163 #define SDMMC_IDMAC_INT_AI BIT(9)
164 #define SDMMC_IDMAC_INT_NI BIT(8)
165 #define SDMMC_IDMAC_INT_CES BIT(5)
166 #define SDMMC_IDMAC_INT_DU BIT(4)
167 #define SDMMC_IDMAC_INT_FBE BIT(2)
168 #define SDMMC_IDMAC_INT_RI BIT(1)
169 #define SDMMC_IDMAC_INT_TI BIT(0)
170 /* Internal DMAC bus mode bits */
171 #define SDMMC_IDMAC_ENABLE BIT(7)
172 #define SDMMC_IDMAC_FB BIT(1)
173 #define SDMMC_IDMAC_SWRESET BIT(0)
174 /* H/W reset */
175 #define SDMMC_RST_HWACTIVE 0x1
176 /* Version ID register define */
177 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
178 /* Card read threshold */
179 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
180 #define SDMMC_CARD_WR_THR_EN BIT(2)
181 #define SDMMC_CARD_RD_THR_EN BIT(0)
182 /* UHS-1 register defines */
183 #define SDMMC_UHS_18V BIT(0)
184 /* All ctrl reset bits */
185 #define SDMMC_CTRL_ALL_RESET_FLAGS \
186 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
188 /* FIFO register access macros. These should not change the data endian-ness
189 * as they are written to memory to be dealt with by the upper layers */
190 #define mci_fifo_readw(__reg) __raw_readw(__reg)
191 #define mci_fifo_readl(__reg) __raw_readl(__reg)
192 #define mci_fifo_readq(__reg) __raw_readq(__reg)
194 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
195 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
196 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
198 /* Register access macros */
199 #define mci_readl(dev, reg) \
200 readl_relaxed((dev)->regs + SDMMC_##reg)
201 #define mci_writel(dev, reg, value) \
202 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
204 /* 16-bit FIFO access macros */
205 #define mci_readw(dev, reg) \
206 readw_relaxed((dev)->regs + SDMMC_##reg)
207 #define mci_writew(dev, reg, value) \
208 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
210 /* 64-bit FIFO access macros */
211 #ifdef readq
212 #define mci_readq(dev, reg) \
213 readq_relaxed((dev)->regs + SDMMC_##reg)
214 #define mci_writeq(dev, reg, value) \
215 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
216 #else
217 /*
218 * Dummy readq implementation for architectures that don't define it.
219 *
220 * We would assume that none of these architectures would configure
221 * the IP block with a 64bit FIFO width, so this code will never be
222 * executed on those machines. Defining these macros here keeps the
223 * rest of the code free from ifdefs.
224 */
225 #define mci_readq(dev, reg) \
226 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
227 #define mci_writeq(dev, reg, value) \
228 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
230 #define __raw_writeq(__value, __reg) \
231 (*(volatile u64 __force *)(__reg) = (__value))
232 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
233 #endif
237 #ifdef CONFIG_PM
240 #endif
242 /**
243 * struct dw_mci_slot - MMC slot state
244 * @mmc: The mmc_host representing this slot.
245 * @host: The MMC controller this slot is using.
246 * @ctype: Card type for this slot.
247 * @mrq: mmc_request currently being processed or waiting to be
248 * processed, or NULL when the slot is idle.
249 * @queue_node: List node for placing this node in the @queue list of
250 * &struct dw_mci.
251 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
252 * @__clk_old: The last clock value that was requested from core.
253 * Keeping track of this helps us to avoid spamming the console.
254 * @flags: Random state bits associated with the slot.
255 * @id: Number of this slot.
256 * @sdio_id: Number of this slot in the SDIO interrupt registers.
257 */
262 u32 ctype;
271 #define DW_MMC_CARD_PRESENT 0
272 #define DW_MMC_CARD_NEED_INIT 1
273 #define DW_MMC_CARD_NO_LOW_PWR 2
274 #define DW_MMC_CARD_NO_USE_HOLD 3
275 #define DW_MMC_CARD_NEEDS_POLL 4
278 };
280 /**
281 * dw_mci driver data - dw-mshc implementation specific driver data.
282 * @caps: mmc subsystem specified capabilities of the controller(s).
283 * @init: early implementation specific initialization.
284 * @set_ios: handle bus specific extensions.
285 * @parse_dt: parse implementation specific device tree properties.
286 * @execute_tuning: implementation specific tuning procedure.
287 *
288 * Provide controller implementation specific extensions. The usage of this
289 * data structure is fully optional and usage of each member in this structure
290 * is optional as well.
291 */
302 };