sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-bcm-kona.c
blob51dd2fd65000c966a89b8dc7d8263de939695e13
1 /*
2 * Copyright (C) 2013 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/platform_device.h>
19 #include <linux/mmc/host.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/clk.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/mmc/slot-gpio.h>
29 #include "sdhci-pltfm.h"
30 #include "sdhci.h"
32 #define SDHCI_SOFT_RESET 0x01000000
33 #define KONA_SDHOST_CORECTRL 0x8000
34 #define KONA_SDHOST_CD_PINCTRL 0x00000008
35 #define KONA_SDHOST_STOP_HCLK 0x00000004
36 #define KONA_SDHOST_RESET 0x00000002
37 #define KONA_SDHOST_EN 0x00000001
39 #define KONA_SDHOST_CORESTAT 0x8004
40 #define KONA_SDHOST_WP 0x00000002
41 #define KONA_SDHOST_CD_SW 0x00000001
43 #define KONA_SDHOST_COREIMR 0x8008
44 #define KONA_SDHOST_IP 0x00000001
46 #define KONA_SDHOST_COREISR 0x800C
47 #define KONA_SDHOST_COREIMSR 0x8010
48 #define KONA_SDHOST_COREDBG1 0x8014
49 #define KONA_SDHOST_COREGPO_MASK 0x8018
51 #define SD_DETECT_GPIO_DEBOUNCE_128MS 128
53 #define KONA_MMC_AUTOSUSPEND_DELAY (50)
55 struct sdhci_bcm_kona_dev {
56 struct mutex write_lock; /* protect back to back writes */
60 static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
62 unsigned int val;
63 unsigned long timeout;
65 /* This timeout should be sufficent for core to reset */
66 timeout = jiffies + msecs_to_jiffies(100);
68 /* reset the host using the top level reset */
69 val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
70 val |= KONA_SDHOST_RESET;
71 sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
73 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
74 if (time_is_before_jiffies(timeout)) {
75 pr_err("Error: sd host is stuck in reset!!!\n");
76 return -EFAULT;
80 /* bring the host out of reset */
81 val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
82 val &= ~KONA_SDHOST_RESET;
85 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
86 * Back-to-Back writes to same register needs delay when SD bus clock
87 * is very low w.r.t AHB clock, mainly during boot-time and during card
88 * insert-removal.
90 usleep_range(1000, 5000);
91 sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
93 return 0;
96 static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
98 unsigned int val;
100 /* enable the interrupt from the IP core */
101 val = sdhci_readl(host, KONA_SDHOST_COREIMR);
102 val |= KONA_SDHOST_IP;
103 sdhci_writel(host, val, KONA_SDHOST_COREIMR);
105 /* Enable the AHB clock gating module to the host */
106 val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
107 val |= KONA_SDHOST_EN;
110 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
111 * Back-to-Back writes to same register needs delay when SD bus clock
112 * is very low w.r.t AHB clock, mainly during boot-time and during card
113 * insert-removal.
115 usleep_range(1000, 5000);
116 sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
120 * Software emulation of the SD card insertion/removal. Set insert=1 for insert
121 * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
122 * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
123 * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
125 static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
127 struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
128 struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
129 u32 val;
132 * Back-to-Back register write needs a delay of min 10uS.
133 * Back-to-Back writes to same register needs delay when SD bus clock
134 * is very low w.r.t AHB clock, mainly during boot-time and during card
135 * insert-removal.
136 * We keep 20uS
138 mutex_lock(&kona_dev->write_lock);
139 udelay(20);
140 val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
142 if (insert) {
143 int ret;
145 ret = mmc_gpio_get_ro(host->mmc);
146 if (ret >= 0)
147 val = (val & ~KONA_SDHOST_WP) |
148 ((ret) ? KONA_SDHOST_WP : 0);
150 val |= KONA_SDHOST_CD_SW;
151 sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
152 } else {
153 val &= ~KONA_SDHOST_CD_SW;
154 sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
156 mutex_unlock(&kona_dev->write_lock);
158 return 0;
162 * SD card interrupt event callback
164 static void sdhci_bcm_kona_card_event(struct sdhci_host *host)
166 if (mmc_gpio_get_cd(host->mmc) > 0) {
167 dev_dbg(mmc_dev(host->mmc),
168 "card inserted\n");
169 sdhci_bcm_kona_sd_card_emulate(host, 1);
170 } else {
171 dev_dbg(mmc_dev(host->mmc),
172 "card removed\n");
173 sdhci_bcm_kona_sd_card_emulate(host, 0);
177 static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
178 u8 power_mode)
181 * JEDEC and SD spec specify supplying 74 continuous clocks to
182 * device after power up. With minimum bus (100KHz) that
183 * that translates to 740us
185 if (power_mode != MMC_POWER_OFF)
186 udelay(740);
189 static struct sdhci_ops sdhci_bcm_kona_ops = {
190 .set_clock = sdhci_set_clock,
191 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
192 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
193 .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
194 .set_bus_width = sdhci_set_bus_width,
195 .reset = sdhci_reset,
196 .set_uhs_signaling = sdhci_set_uhs_signaling,
197 .card_event = sdhci_bcm_kona_card_event,
200 static struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
201 .ops = &sdhci_bcm_kona_ops,
202 .quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
203 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
204 SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
205 SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
206 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
209 static const struct of_device_id sdhci_bcm_kona_of_match[] = {
210 { .compatible = "brcm,kona-sdhci"},
211 { .compatible = "bcm,kona-sdhci"}, /* deprecated name */
214 MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
216 static int sdhci_bcm_kona_probe(struct platform_device *pdev)
218 struct sdhci_bcm_kona_dev *kona_dev = NULL;
219 struct sdhci_pltfm_host *pltfm_priv;
220 struct device *dev = &pdev->dev;
221 struct sdhci_host *host;
222 int ret;
224 ret = 0;
226 host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona,
227 sizeof(*kona_dev));
228 if (IS_ERR(host))
229 return PTR_ERR(host);
231 dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
233 pltfm_priv = sdhci_priv(host);
235 kona_dev = sdhci_pltfm_priv(pltfm_priv);
236 mutex_init(&kona_dev->write_lock);
238 ret = mmc_of_parse(host->mmc);
239 if (ret)
240 goto err_pltfm_free;
242 if (!host->mmc->f_max) {
243 dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
244 ret = -ENXIO;
245 goto err_pltfm_free;
248 /* Get and enable the core clock */
249 pltfm_priv->clk = devm_clk_get(dev, NULL);
250 if (IS_ERR(pltfm_priv->clk)) {
251 dev_err(dev, "Failed to get core clock\n");
252 ret = PTR_ERR(pltfm_priv->clk);
253 goto err_pltfm_free;
256 ret = clk_set_rate(pltfm_priv->clk, host->mmc->f_max);
257 if (ret) {
258 dev_err(dev, "Failed to set rate core clock\n");
259 goto err_pltfm_free;
262 ret = clk_prepare_enable(pltfm_priv->clk);
263 if (ret) {
264 dev_err(dev, "Failed to enable core clock\n");
265 goto err_pltfm_free;
268 dev_dbg(dev, "non-removable=%c\n",
269 mmc_card_is_removable(host->mmc) ? 'N' : 'Y');
270 dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n",
271 (mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N',
272 (mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N');
274 if (!mmc_card_is_removable(host->mmc))
275 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
277 dev_dbg(dev, "is_8bit=%c\n",
278 (host->mmc->caps & MMC_CAP_8_BIT_DATA) ? 'Y' : 'N');
280 ret = sdhci_bcm_kona_sd_reset(host);
281 if (ret)
282 goto err_clk_disable;
284 sdhci_bcm_kona_sd_init(host);
286 ret = sdhci_add_host(host);
287 if (ret) {
288 dev_err(dev, "Failed sdhci_add_host\n");
289 goto err_reset;
292 /* if device is eMMC, emulate card insert right here */
293 if (!mmc_card_is_removable(host->mmc)) {
294 ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
295 if (ret) {
296 dev_err(dev,
297 "unable to emulate card insertion\n");
298 goto err_remove_host;
302 * Since the card detection GPIO interrupt is configured to be
303 * edge sensitive, check the initial GPIO value here, emulate
304 * only if the card is present
306 if (mmc_gpio_get_cd(host->mmc) > 0)
307 sdhci_bcm_kona_sd_card_emulate(host, 1);
309 dev_dbg(dev, "initialized properly\n");
310 return 0;
312 err_remove_host:
313 sdhci_remove_host(host, 0);
315 err_reset:
316 sdhci_bcm_kona_sd_reset(host);
318 err_clk_disable:
319 clk_disable_unprepare(pltfm_priv->clk);
321 err_pltfm_free:
322 sdhci_pltfm_free(pdev);
324 dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
325 return ret;
328 static struct platform_driver sdhci_bcm_kona_driver = {
329 .driver = {
330 .name = "sdhci-kona",
331 .pm = &sdhci_pltfm_pmops,
332 .of_match_table = sdhci_bcm_kona_of_match,
334 .probe = sdhci_bcm_kona_probe,
335 .remove = sdhci_pltfm_unregister,
337 module_platform_driver(sdhci_bcm_kona_driver);
339 MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
340 MODULE_AUTHOR("Broadcom");
341 MODULE_LICENSE("GPL v2");