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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / mmc / host / usdhi6rol0.c
blob1bd5f1a18d4e239784082a2ddfca46d2492345e7
1 /*
2 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
3 * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/highmem.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/log2.h>
19 #include <linux/mmc/host.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/mmc/sd.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/module.h>
24 #include <linux/pagemap.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/scatterlist.h>
28 #include <linux/string.h>
29 #include <linux/time.h>
30 #include <linux/virtio.h>
31 #include <linux/workqueue.h>
32
33 #define USDHI6_SD_CMD 0x0000
34 #define USDHI6_SD_PORT_SEL 0x0004
35 #define USDHI6_SD_ARG 0x0008
36 #define USDHI6_SD_STOP 0x0010
37 #define USDHI6_SD_SECCNT 0x0014
38 #define USDHI6_SD_RSP10 0x0018
39 #define USDHI6_SD_RSP32 0x0020
40 #define USDHI6_SD_RSP54 0x0028
41 #define USDHI6_SD_RSP76 0x0030
42 #define USDHI6_SD_INFO1 0x0038
43 #define USDHI6_SD_INFO2 0x003c
44 #define USDHI6_SD_INFO1_MASK 0x0040
45 #define USDHI6_SD_INFO2_MASK 0x0044
46 #define USDHI6_SD_CLK_CTRL 0x0048
47 #define USDHI6_SD_SIZE 0x004c
48 #define USDHI6_SD_OPTION 0x0050
49 #define USDHI6_SD_ERR_STS1 0x0058
50 #define USDHI6_SD_ERR_STS2 0x005c
51 #define USDHI6_SD_BUF0 0x0060
52 #define USDHI6_SDIO_MODE 0x0068
53 #define USDHI6_SDIO_INFO1 0x006c
54 #define USDHI6_SDIO_INFO1_MASK 0x0070
55 #define USDHI6_CC_EXT_MODE 0x01b0
56 #define USDHI6_SOFT_RST 0x01c0
57 #define USDHI6_VERSION 0x01c4
58 #define USDHI6_HOST_MODE 0x01c8
59 #define USDHI6_SDIF_MODE 0x01cc
60
61 #define USDHI6_SD_CMD_APP 0x0040
62 #define USDHI6_SD_CMD_MODE_RSP_AUTO 0x0000
63 #define USDHI6_SD_CMD_MODE_RSP_NONE 0x0300
64 #define USDHI6_SD_CMD_MODE_RSP_R1 0x0400 /* Also R5, R6, R7 */
65 #define USDHI6_SD_CMD_MODE_RSP_R1B 0x0500 /* R1b */
66 #define USDHI6_SD_CMD_MODE_RSP_R2 0x0600
67 #define USDHI6_SD_CMD_MODE_RSP_R3 0x0700 /* Also R4 */
68 #define USDHI6_SD_CMD_DATA 0x0800
69 #define USDHI6_SD_CMD_READ 0x1000
70 #define USDHI6_SD_CMD_MULTI 0x2000
71 #define USDHI6_SD_CMD_CMD12_AUTO_OFF 0x4000
72
73 #define USDHI6_CC_EXT_MODE_SDRW BIT(1)
74
75 #define USDHI6_SD_INFO1_RSP_END BIT(0)
76 #define USDHI6_SD_INFO1_ACCESS_END BIT(2)
77 #define USDHI6_SD_INFO1_CARD_OUT BIT(3)
78 #define USDHI6_SD_INFO1_CARD_IN BIT(4)
79 #define USDHI6_SD_INFO1_CD BIT(5)
80 #define USDHI6_SD_INFO1_WP BIT(7)
81 #define USDHI6_SD_INFO1_D3_CARD_OUT BIT(8)
82 #define USDHI6_SD_INFO1_D3_CARD_IN BIT(9)
83
84 #define USDHI6_SD_INFO2_CMD_ERR BIT(0)
85 #define USDHI6_SD_INFO2_CRC_ERR BIT(1)
86 #define USDHI6_SD_INFO2_END_ERR BIT(2)
87 #define USDHI6_SD_INFO2_TOUT BIT(3)
88 #define USDHI6_SD_INFO2_IWA_ERR BIT(4)
89 #define USDHI6_SD_INFO2_IRA_ERR BIT(5)
90 #define USDHI6_SD_INFO2_RSP_TOUT BIT(6)
91 #define USDHI6_SD_INFO2_SDDAT0 BIT(7)
92 #define USDHI6_SD_INFO2_BRE BIT(8)
93 #define USDHI6_SD_INFO2_BWE BIT(9)
94 #define USDHI6_SD_INFO2_SCLKDIVEN BIT(13)
95 #define USDHI6_SD_INFO2_CBSY BIT(14)
96 #define USDHI6_SD_INFO2_ILA BIT(15)
97
98 #define USDHI6_SD_INFO1_CARD_INSERT (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_D3_CARD_IN)
99 #define USDHI6_SD_INFO1_CARD_EJECT (USDHI6_SD_INFO1_CARD_OUT | USDHI6_SD_INFO1_D3_CARD_OUT)
100 #define USDHI6_SD_INFO1_CARD (USDHI6_SD_INFO1_CARD_INSERT | USDHI6_SD_INFO1_CARD_EJECT)
101 #define USDHI6_SD_INFO1_CARD_CD (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_CARD_OUT)
102
103 #define USDHI6_SD_INFO2_ERR (USDHI6_SD_INFO2_CMD_ERR | \
104 USDHI6_SD_INFO2_CRC_ERR | USDHI6_SD_INFO2_END_ERR | \
105 USDHI6_SD_INFO2_TOUT | USDHI6_SD_INFO2_IWA_ERR | \
106 USDHI6_SD_INFO2_IRA_ERR | USDHI6_SD_INFO2_RSP_TOUT | \
107 USDHI6_SD_INFO2_ILA)
108
109 #define USDHI6_SD_INFO1_IRQ (USDHI6_SD_INFO1_RSP_END | USDHI6_SD_INFO1_ACCESS_END | \
110 USDHI6_SD_INFO1_CARD)
111
112 #define USDHI6_SD_INFO2_IRQ (USDHI6_SD_INFO2_ERR | USDHI6_SD_INFO2_BRE | \
113 USDHI6_SD_INFO2_BWE | 0x0800 | USDHI6_SD_INFO2_ILA)
114
115 #define USDHI6_SD_CLK_CTRL_SCLKEN BIT(8)
116
117 #define USDHI6_SD_STOP_STP BIT(0)
118 #define USDHI6_SD_STOP_SEC BIT(8)
119
120 #define USDHI6_SDIO_INFO1_IOIRQ BIT(0)
121 #define USDHI6_SDIO_INFO1_EXPUB52 BIT(14)
122 #define USDHI6_SDIO_INFO1_EXWT BIT(15)
123
124 #define USDHI6_SD_ERR_STS1_CRC_NO_ERROR BIT(13)
125
126 #define USDHI6_SOFT_RST_RESERVED (BIT(1) | BIT(2))
127 #define USDHI6_SOFT_RST_RESET BIT(0)
128
129 #define USDHI6_SD_OPTION_TIMEOUT_SHIFT 4
130 #define USDHI6_SD_OPTION_TIMEOUT_MASK (0xf << USDHI6_SD_OPTION_TIMEOUT_SHIFT)
131 #define USDHI6_SD_OPTION_WIDTH_1 BIT(15)
132
133 #define USDHI6_SD_PORT_SEL_PORTS_SHIFT 8
134
135 #define USDHI6_SD_CLK_CTRL_DIV_MASK 0xff
136
137 #define USDHI6_SDIO_INFO1_IRQ (USDHI6_SDIO_INFO1_IOIRQ | 3 | \
138 USDHI6_SDIO_INFO1_EXPUB52 | USDHI6_SDIO_INFO1_EXWT)
139
140 #define USDHI6_MIN_DMA 64
141
142 enum usdhi6_wait_for {
143 USDHI6_WAIT_FOR_REQUEST,
144 USDHI6_WAIT_FOR_CMD,
145 USDHI6_WAIT_FOR_MREAD,
146 USDHI6_WAIT_FOR_MWRITE,
147 USDHI6_WAIT_FOR_READ,
148 USDHI6_WAIT_FOR_WRITE,
149 USDHI6_WAIT_FOR_DATA_END,
150 USDHI6_WAIT_FOR_STOP,
151 USDHI6_WAIT_FOR_DMA,
152 };
153
154 struct usdhi6_page {
155 struct page *page;
156 void *mapped; /* mapped page */
157 };
158
159 struct usdhi6_host {
160 struct mmc_host *mmc;
161 struct mmc_request *mrq;
162 void __iomem *base;
163 struct clk *clk;
164
165 /* SG memory handling */
166
167 /* Common for multiple and single block requests */
168 struct usdhi6_page pg; /* current page from an SG */
169 void *blk_page; /* either a mapped page, or the bounce buffer */
170 size_t offset; /* offset within a page, including sg->offset */
171
172 /* Blocks, crossing a page boundary */
173 size_t head_len;
174 struct usdhi6_page head_pg;
175
176 /* A bounce buffer for unaligned blocks or blocks, crossing a page boundary */
177 struct scatterlist bounce_sg;
178 u8 bounce_buf[512];
179
180 /* Multiple block requests only */
181 struct scatterlist *sg; /* current SG segment */
182 int page_idx; /* page index within an SG segment */
183
184 enum usdhi6_wait_for wait;
185 u32 status_mask;
186 u32 status2_mask;
187 u32 sdio_mask;
188 u32 io_error;
189 u32 irq_status;
190 unsigned long imclk;
191 unsigned long rate;
192 bool app_cmd;
193
194 /* Timeout handling */
195 struct delayed_work timeout_work;
196 unsigned long timeout;
197
198 /* DMA support */
199 struct dma_chan *chan_rx;
200 struct dma_chan *chan_tx;
201 bool dma_active;
202
203 /* Pin control */
204 struct pinctrl *pinctrl;
205 struct pinctrl_state *pins_default;
206 struct pinctrl_state *pins_uhs;
207 };
208
209 /* I/O primitives */
210
211 static void usdhi6_write(struct usdhi6_host *host, u32 reg, u32 data)
212 {
213 iowrite32(data, host->base + reg);
214 dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__,
215 host->base, reg, data);
216 }
217
218 static void usdhi6_write16(struct usdhi6_host *host, u32 reg, u16 data)
219 {
220 iowrite16(data, host->base + reg);
221 dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__,
222 host->base, reg, data);
223 }
224
225 static u32 usdhi6_read(struct usdhi6_host *host, u32 reg)
226 {
227 u32 data = ioread32(host->base + reg);
228 dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__,
229 host->base, reg, data);
230 return data;
231 }
232
233 static u16 usdhi6_read16(struct usdhi6_host *host, u32 reg)
234 {
235 u16 data = ioread16(host->base + reg);
236 dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__,
237 host->base, reg, data);
238 return data;
239 }
240
241 static void usdhi6_irq_enable(struct usdhi6_host *host, u32 info1, u32 info2)
242 {
243 host->status_mask = USDHI6_SD_INFO1_IRQ & ~info1;
244 host->status2_mask = USDHI6_SD_INFO2_IRQ & ~info2;
245 usdhi6_write(host, USDHI6_SD_INFO1_MASK, host->status_mask);
246 usdhi6_write(host, USDHI6_SD_INFO2_MASK, host->status2_mask);
247 }
248
249 static void usdhi6_wait_for_resp(struct usdhi6_host *host)
250 {
251 usdhi6_irq_enable(host, USDHI6_SD_INFO1_RSP_END |
252 USDHI6_SD_INFO1_ACCESS_END | USDHI6_SD_INFO1_CARD_CD,
253 USDHI6_SD_INFO2_ERR);
254 }
255
256 static void usdhi6_wait_for_brwe(struct usdhi6_host *host, bool read)
257 {
258 usdhi6_irq_enable(host, USDHI6_SD_INFO1_ACCESS_END |
259 USDHI6_SD_INFO1_CARD_CD, USDHI6_SD_INFO2_ERR |
260 (read ? USDHI6_SD_INFO2_BRE : USDHI6_SD_INFO2_BWE));
261 }
262
263 static void usdhi6_only_cd(struct usdhi6_host *host)
264 {
265 /* Mask all except card hotplug */
266 usdhi6_irq_enable(host, USDHI6_SD_INFO1_CARD_CD, 0);
267 }
268
269 static void usdhi6_mask_all(struct usdhi6_host *host)
270 {
271 usdhi6_irq_enable(host, 0, 0);
272 }
273
274 static int usdhi6_error_code(struct usdhi6_host *host)
275 {
276 u32 err;
277
278 usdhi6_write(host, USDHI6_SD_STOP, USDHI6_SD_STOP_STP);
279
280 if (host->io_error &
281 (USDHI6_SD_INFO2_RSP_TOUT | USDHI6_SD_INFO2_TOUT)) {
282 u32 rsp54 = usdhi6_read(host, USDHI6_SD_RSP54);
283 int opc = host->mrq ? host->mrq->cmd->opcode : -1;
284
285 err = usdhi6_read(host, USDHI6_SD_ERR_STS2);
286 /* Response timeout is often normal, don't spam the log */
287 if (host->wait == USDHI6_WAIT_FOR_CMD)
288 dev_dbg(mmc_dev(host->mmc),
289 "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n",
290 err, rsp54, host->wait, opc);
291 else
292 dev_warn(mmc_dev(host->mmc),
293 "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n",
294 err, rsp54, host->wait, opc);
295 return -ETIMEDOUT;
296 }
297
298 err = usdhi6_read(host, USDHI6_SD_ERR_STS1);
299 if (err != USDHI6_SD_ERR_STS1_CRC_NO_ERROR)
300 dev_warn(mmc_dev(host->mmc), "Err sts 0x%x, state %u, CMD%d\n",
301 err, host->wait, host->mrq ? host->mrq->cmd->opcode : -1);
302 if (host->io_error & USDHI6_SD_INFO2_ILA)
303 return -EILSEQ;
304
305 return -EIO;
306 }
307
308 /* Scatter-Gather management */
309
310 /*
311 * In PIO mode we have to map each page separately, using kmap(). That way
312 * adjacent pages are mapped to non-adjacent virtual addresses. That's why we
313 * have to use a bounce buffer for blocks, crossing page boundaries. Such blocks
314 * have been observed with an SDIO WiFi card (b43 driver).
315 */
316 static void usdhi6_blk_bounce(struct usdhi6_host *host,
317 struct scatterlist *sg)
318 {
319 struct mmc_data *data = host->mrq->data;
320 size_t blk_head = host->head_len;
321
322 dev_dbg(mmc_dev(host->mmc), "%s(): CMD%u of %u SG: %ux%u @ 0x%x\n",
323 __func__, host->mrq->cmd->opcode, data->sg_len,
324 data->blksz, data->blocks, sg->offset);
325
326 host->head_pg.page = host->pg.page;
327 host->head_pg.mapped = host->pg.mapped;
328 host->pg.page = nth_page(host->pg.page, 1);
329 host->pg.mapped = kmap(host->pg.page);
330
331 host->blk_page = host->bounce_buf;
332 host->offset = 0;
333
334 if (data->flags & MMC_DATA_READ)
335 return;
336
337 memcpy(host->bounce_buf, host->head_pg.mapped + PAGE_SIZE - blk_head,
338 blk_head);
339 memcpy(host->bounce_buf + blk_head, host->pg.mapped,
340 data->blksz - blk_head);
341 }
342
343 /* Only called for multiple block IO */
344 static void usdhi6_sg_prep(struct usdhi6_host *host)
345 {
346 struct mmc_request *mrq = host->mrq;
347 struct mmc_data *data = mrq->data;
348
349 usdhi6_write(host, USDHI6_SD_SECCNT, data->blocks);
350
351 host->sg = data->sg;
352 /* TODO: if we always map, this is redundant */
353 host->offset = host->sg->offset;
354 }
355
356 /* Map the first page in an SG segment: common for multiple and single block IO */
357 static void *usdhi6_sg_map(struct usdhi6_host *host)
358 {
359 struct mmc_data *data = host->mrq->data;
360 struct scatterlist *sg = data->sg_len > 1 ? host->sg : data->sg;
361 size_t head = PAGE_SIZE - sg->offset;
362 size_t blk_head = head % data->blksz;
363
364 WARN(host->pg.page, "%p not properly unmapped!\n", host->pg.page);
365 if (WARN(sg_dma_len(sg) % data->blksz,
366 "SG size %u isn't a multiple of block size %u\n",
367 sg_dma_len(sg), data->blksz))
368 return NULL;
369
370 host->pg.page = sg_page(sg);
371 host->pg.mapped = kmap(host->pg.page);
372 host->offset = sg->offset;
373
374 /*
375 * Block size must be a power of 2 for multi-block transfers,
376 * therefore blk_head is equal for all pages in this SG
377 */
378 host->head_len = blk_head;
379
380 if (head < data->blksz)
381 /*
382 * The first block in the SG crosses a page boundary.
383 * Max blksz = 512, so blocks can only span 2 pages
384 */
385 usdhi6_blk_bounce(host, sg);
386 else
387 host->blk_page = host->pg.mapped;
388
389 dev_dbg(mmc_dev(host->mmc), "Mapped %p (%lx) at %p + %u for CMD%u @ 0x%p\n",
390 host->pg.page, page_to_pfn(host->pg.page), host->pg.mapped,
391 sg->offset, host->mrq->cmd->opcode, host->mrq);
392
393 return host->blk_page + host->offset;
394 }
395
396 /* Unmap the current page: common for multiple and single block IO */
397 static void usdhi6_sg_unmap(struct usdhi6_host *host, bool force)
398 {
399 struct mmc_data *data = host->mrq->data;
400 struct page *page = host->head_pg.page;
401
402 if (page) {
403 /* Previous block was cross-page boundary */
404 struct scatterlist *sg = data->sg_len > 1 ?
405 host->sg : data->sg;
406 size_t blk_head = host->head_len;
407
408 if (!data->error && data->flags & MMC_DATA_READ) {
409 memcpy(host->head_pg.mapped + PAGE_SIZE - blk_head,
410 host->bounce_buf, blk_head);
411 memcpy(host->pg.mapped, host->bounce_buf + blk_head,
412 data->blksz - blk_head);
413 }
414
415 flush_dcache_page(page);
416 kunmap(page);
417
418 host->head_pg.page = NULL;
419
420 if (!force && sg_dma_len(sg) + sg->offset >
421 (host->page_idx << PAGE_SHIFT) + data->blksz - blk_head)
422 /* More blocks in this SG, don't unmap the next page */
423 return;
424 }
425
426 page = host->pg.page;
427 if (!page)
428 return;
429
430 flush_dcache_page(page);
431 kunmap(page);
432
433 host->pg.page = NULL;
434 }
435
436 /* Called from MMC_WRITE_MULTIPLE_BLOCK or MMC_READ_MULTIPLE_BLOCK */
437 static void usdhi6_sg_advance(struct usdhi6_host *host)
438 {
439 struct mmc_data *data = host->mrq->data;
440 size_t done, total;
441
442 /* New offset: set at the end of the previous block */
443 if (host->head_pg.page) {
444 /* Finished a cross-page block, jump to the new page */
445 host->page_idx++;
446 host->offset = data->blksz - host->head_len;
447 host->blk_page = host->pg.mapped;
448 usdhi6_sg_unmap(host, false);
449 } else {
450 host->offset += data->blksz;
451 /* The completed block didn't cross a page boundary */
452 if (host->offset == PAGE_SIZE) {
453 /* If required, we'll map the page below */
454 host->offset = 0;
455 host->page_idx++;
456 }
457 }
458
459 /*
460 * Now host->blk_page + host->offset point at the end of our last block
461 * and host->page_idx is the index of the page, in which our new block
462 * is located, if any
463 */
464
465 done = (host->page_idx << PAGE_SHIFT) + host->offset;
466 total = host->sg->offset + sg_dma_len(host->sg);
467
468 dev_dbg(mmc_dev(host->mmc), "%s(): %zu of %zu @ %zu\n", __func__,
469 done, total, host->offset);
470
471 if (done < total && host->offset) {
472 /* More blocks in this page */
473 if (host->offset + data->blksz > PAGE_SIZE)
474 /* We approached at a block, that spans 2 pages */
475 usdhi6_blk_bounce(host, host->sg);
476
477 return;
478 }
479
480 /* Finished current page or an SG segment */
481 usdhi6_sg_unmap(host, false);
482
483 if (done == total) {
484 /*
485 * End of an SG segment or the complete SG: jump to the next
486 * segment, we'll map it later in usdhi6_blk_read() or
487 * usdhi6_blk_write()
488 */
489 struct scatterlist *next = sg_next(host->sg);
490
491 host->page_idx = 0;
492
493 if (!next)
494 host->wait = USDHI6_WAIT_FOR_DATA_END;
495 host->sg = next;
496
497 if (WARN(next && sg_dma_len(next) % data->blksz,
498 "SG size %u isn't a multiple of block size %u\n",
499 sg_dma_len(next), data->blksz))
500 data->error = -EINVAL;
501
502 return;
503 }
504
505 /* We cannot get here after crossing a page border */
506
507 /* Next page in the same SG */
508 host->pg.page = nth_page(sg_page(host->sg), host->page_idx);
509 host->pg.mapped = kmap(host->pg.page);
510 host->blk_page = host->pg.mapped;
511
512 dev_dbg(mmc_dev(host->mmc), "Mapped %p (%lx) at %p for CMD%u @ 0x%p\n",
513 host->pg.page, page_to_pfn(host->pg.page), host->pg.mapped,
514 host->mrq->cmd->opcode, host->mrq);
515 }
516
517 /* DMA handling */
518
519 static void usdhi6_dma_release(struct usdhi6_host *host)
520 {
521 host->dma_active = false;
522 if (host->chan_tx) {
523 struct dma_chan *chan = host->chan_tx;
524 host->chan_tx = NULL;
525 dma_release_channel(chan);
526 }
527 if (host->chan_rx) {
528 struct dma_chan *chan = host->chan_rx;
529 host->chan_rx = NULL;
530 dma_release_channel(chan);
531 }
532 }
533
534 static void usdhi6_dma_stop_unmap(struct usdhi6_host *host)
535 {
536 struct mmc_data *data = host->mrq->data;
537
538 if (!host->dma_active)
539 return;
540
541 usdhi6_write(host, USDHI6_CC_EXT_MODE, 0);
542 host->dma_active = false;
543
544 if (data->flags & MMC_DATA_READ)
545 dma_unmap_sg(host->chan_rx->device->dev, data->sg,
546 data->sg_len, DMA_FROM_DEVICE);
547 else
548 dma_unmap_sg(host->chan_tx->device->dev, data->sg,
549 data->sg_len, DMA_TO_DEVICE);
550 }
551
552 static void usdhi6_dma_complete(void *arg)
553 {
554 struct usdhi6_host *host = arg;
555 struct mmc_request *mrq = host->mrq;
556
557 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion for %p!\n",
558 dev_name(mmc_dev(host->mmc)), mrq))
559 return;
560
561 dev_dbg(mmc_dev(host->mmc), "%s(): CMD%u DMA completed\n", __func__,
562 mrq->cmd->opcode);
563
564 usdhi6_dma_stop_unmap(host);
565 usdhi6_wait_for_brwe(host, mrq->data->flags & MMC_DATA_READ);
566 }
567
568 static int usdhi6_dma_setup(struct usdhi6_host *host, struct dma_chan *chan,
569 enum dma_transfer_direction dir)
570 {
571 struct mmc_data *data = host->mrq->data;
572 struct scatterlist *sg = data->sg;
573 struct dma_async_tx_descriptor *desc = NULL;
574 dma_cookie_t cookie = -EINVAL;
575 enum dma_data_direction data_dir;
576 int ret;
577
578 switch (dir) {
579 case DMA_MEM_TO_DEV:
580 data_dir = DMA_TO_DEVICE;
581 break;
582 case DMA_DEV_TO_MEM:
583 data_dir = DMA_FROM_DEVICE;
584 break;
585 default:
586 return -EINVAL;
587 }
588
589 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, data_dir);
590 if (ret > 0) {
591 host->dma_active = true;
592 desc = dmaengine_prep_slave_sg(chan, sg, ret, dir,
593 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
594 }
595
596 if (desc) {
597 desc->callback = usdhi6_dma_complete;
598 desc->callback_param = host;
599 cookie = dmaengine_submit(desc);
600 }
601
602 dev_dbg(mmc_dev(host->mmc), "%s(): mapped %d -> %d, cookie %d @ %p\n",
603 __func__, data->sg_len, ret, cookie, desc);
604
605 if (cookie < 0) {
606 /* DMA failed, fall back to PIO */
607 if (ret >= 0)
608 ret = cookie;
609 usdhi6_dma_release(host);
610 dev_warn(mmc_dev(host->mmc),
611 "DMA failed: %d, falling back to PIO\n", ret);
612 }
613
614 return cookie;
615 }
616
617 static int usdhi6_dma_start(struct usdhi6_host *host)
618 {
619 if (!host->chan_rx || !host->chan_tx)
620 return -ENODEV;
621
622 if (host->mrq->data->flags & MMC_DATA_READ)
623 return usdhi6_dma_setup(host, host->chan_rx, DMA_DEV_TO_MEM);
624
625 return usdhi6_dma_setup(host, host->chan_tx, DMA_MEM_TO_DEV);
626 }
627
628 static void usdhi6_dma_kill(struct usdhi6_host *host)
629 {
630 struct mmc_data *data = host->mrq->data;
631
632 dev_dbg(mmc_dev(host->mmc), "%s(): SG of %u: %ux%u\n",
633 __func__, data->sg_len, data->blocks, data->blksz);
634 /* Abort DMA */
635 if (data->flags & MMC_DATA_READ)
636 dmaengine_terminate_all(host->chan_rx);
637 else
638 dmaengine_terminate_all(host->chan_tx);
639 }
640
641 static void usdhi6_dma_check_error(struct usdhi6_host *host)
642 {
643 struct mmc_data *data = host->mrq->data;
644
645 dev_dbg(mmc_dev(host->mmc), "%s(): IO error %d, status 0x%x\n",
646 __func__, host->io_error, usdhi6_read(host, USDHI6_SD_INFO1));
647
648 if (host->io_error) {
649 data->error = usdhi6_error_code(host);
650 data->bytes_xfered = 0;
651 usdhi6_dma_kill(host);
652 usdhi6_dma_release(host);
653 dev_warn(mmc_dev(host->mmc),
654 "DMA failed: %d, falling back to PIO\n", data->error);
655 return;
656 }
657
658 /*
659 * The datasheet tells us to check a response from the card, whereas
660 * responses only come after the command phase, not after the data
661 * phase. Let's check anyway.
662 */
663 if (host->irq_status & USDHI6_SD_INFO1_RSP_END)
664 dev_warn(mmc_dev(host->mmc), "Unexpected response received!\n");
665 }
666
667 static void usdhi6_dma_kick(struct usdhi6_host *host)
668 {
669 if (host->mrq->data->flags & MMC_DATA_READ)
670 dma_async_issue_pending(host->chan_rx);
671 else
672 dma_async_issue_pending(host->chan_tx);
673 }
674
675 static void usdhi6_dma_request(struct usdhi6_host *host, phys_addr_t start)
676 {
677 struct dma_slave_config cfg = {
678 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
679 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
680 };
681 int ret;
682
683 host->chan_tx = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
684 dev_dbg(mmc_dev(host->mmc), "%s: TX: got channel %p\n", __func__,
685 host->chan_tx);
686
687 if (!host->chan_tx)
688 return;
689
690 cfg.direction = DMA_MEM_TO_DEV;
691 cfg.dst_addr = start + USDHI6_SD_BUF0;
692 cfg.dst_maxburst = 128; /* 128 words * 4 bytes = 512 bytes */
693 cfg.src_addr = 0;
694 ret = dmaengine_slave_config(host->chan_tx, &cfg);
695 if (ret < 0)
696 goto e_release_tx;
697
698 host->chan_rx = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
699 dev_dbg(mmc_dev(host->mmc), "%s: RX: got channel %p\n", __func__,
700 host->chan_rx);
701
702 if (!host->chan_rx)
703 goto e_release_tx;
704
705 cfg.direction = DMA_DEV_TO_MEM;
706 cfg.src_addr = cfg.dst_addr;
707 cfg.src_maxburst = 128; /* 128 words * 4 bytes = 512 bytes */
708 cfg.dst_addr = 0;
709 ret = dmaengine_slave_config(host->chan_rx, &cfg);
710 if (ret < 0)
711 goto e_release_rx;
712
713 return;
714
715 e_release_rx:
716 dma_release_channel(host->chan_rx);
717 host->chan_rx = NULL;
718 e_release_tx:
719 dma_release_channel(host->chan_tx);
720 host->chan_tx = NULL;
721 }
722
723 /* API helpers */
724
725 static void usdhi6_clk_set(struct usdhi6_host *host, struct mmc_ios *ios)
726 {
727 unsigned long rate = ios->clock;
728 u32 val;
729 unsigned int i;
730
731 for (i = 1000; i; i--) {
732 if (usdhi6_read(host, USDHI6_SD_INFO2) & USDHI6_SD_INFO2_SCLKDIVEN)
733 break;
734 usleep_range(10, 100);
735 }
736
737 if (!i) {
738 dev_err(mmc_dev(host->mmc), "SD bus busy, clock set aborted\n");
739 return;
740 }
741
742 val = usdhi6_read(host, USDHI6_SD_CLK_CTRL) & ~USDHI6_SD_CLK_CTRL_DIV_MASK;
743
744 if (rate) {
745 unsigned long new_rate;
746
747 if (host->imclk <= rate) {
748 if (ios->timing != MMC_TIMING_UHS_DDR50) {
749 /* Cannot have 1-to-1 clock in DDR mode */
750 new_rate = host->imclk;
751 val |= 0xff;
752 } else {
753 new_rate = host->imclk / 2;
754 }
755 } else {
756 unsigned long div =
757 roundup_pow_of_two(DIV_ROUND_UP(host->imclk, rate));
758 val |= div >> 2;
759 new_rate = host->imclk / div;
760 }
761
762 if (host->rate == new_rate)
763 return;
764
765 host->rate = new_rate;
766
767 dev_dbg(mmc_dev(host->mmc), "target %lu, div %u, set %lu\n",
768 rate, (val & 0xff) << 2, new_rate);
769 }
770
771 /*
772 * if old or new rate is equal to input rate, have to switch the clock
773 * off before changing and on after
774 */
775 if (host->imclk == rate || host->imclk == host->rate || !rate)
776 usdhi6_write(host, USDHI6_SD_CLK_CTRL,
777 val & ~USDHI6_SD_CLK_CTRL_SCLKEN);
778
779 if (!rate) {
780 host->rate = 0;
781 return;
782 }
783
784 usdhi6_write(host, USDHI6_SD_CLK_CTRL, val);
785
786 if (host->imclk == rate || host->imclk == host->rate ||
787 !(val & USDHI6_SD_CLK_CTRL_SCLKEN))
788 usdhi6_write(host, USDHI6_SD_CLK_CTRL,
789 val | USDHI6_SD_CLK_CTRL_SCLKEN);
790 }
791
792 static void usdhi6_set_power(struct usdhi6_host *host, struct mmc_ios *ios)
793 {
794 struct mmc_host *mmc = host->mmc;
795
796 if (!IS_ERR(mmc->supply.vmmc))
797 /* Errors ignored... */
798 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
799 ios->power_mode ? ios->vdd : 0);
800 }
801
802 static int usdhi6_reset(struct usdhi6_host *host)
803 {
804 int i;
805
806 usdhi6_write(host, USDHI6_SOFT_RST, USDHI6_SOFT_RST_RESERVED);
807 cpu_relax();
808 usdhi6_write(host, USDHI6_SOFT_RST, USDHI6_SOFT_RST_RESERVED | USDHI6_SOFT_RST_RESET);
809 for (i = 1000; i; i--)
810 if (usdhi6_read(host, USDHI6_SOFT_RST) & USDHI6_SOFT_RST_RESET)
811 break;
812
813 return i ? 0 : -ETIMEDOUT;
814 }
815
816 static void usdhi6_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
817 {
818 struct usdhi6_host *host = mmc_priv(mmc);
819 u32 option, mode;
820 int ret;
821
822 dev_dbg(mmc_dev(mmc), "%uHz, OCR: %u, power %u, bus-width %u, timing %u\n",
823 ios->clock, ios->vdd, ios->power_mode, ios->bus_width, ios->timing);
824
825 switch (ios->power_mode) {
826 case MMC_POWER_OFF:
827 usdhi6_set_power(host, ios);
828 usdhi6_only_cd(host);
829 break;
830 case MMC_POWER_UP:
831 /*
832 * We only also touch USDHI6_SD_OPTION from .request(), which
833 * cannot race with MMC_POWER_UP
834 */
835 ret = usdhi6_reset(host);
836 if (ret < 0) {
837 dev_err(mmc_dev(mmc), "Cannot reset the interface!\n");
838 } else {
839 usdhi6_set_power(host, ios);
840 usdhi6_only_cd(host);
841 }
842 break;
843 case MMC_POWER_ON:
844 option = usdhi6_read(host, USDHI6_SD_OPTION);
845 /*
846 * The eMMC standard only allows 4 or 8 bits in the DDR mode,
847 * the same probably holds for SD cards. We check here anyway,
848 * since the datasheet explicitly requires 4 bits for DDR.
849 */
850 if (ios->bus_width == MMC_BUS_WIDTH_1) {
851 if (ios->timing == MMC_TIMING_UHS_DDR50)
852 dev_err(mmc_dev(mmc),
853 "4 bits are required for DDR\n");
854 option |= USDHI6_SD_OPTION_WIDTH_1;
855 mode = 0;
856 } else {
857 option &= ~USDHI6_SD_OPTION_WIDTH_1;
858 mode = ios->timing == MMC_TIMING_UHS_DDR50;
859 }
860 usdhi6_write(host, USDHI6_SD_OPTION, option);
861 usdhi6_write(host, USDHI6_SDIF_MODE, mode);
862 break;
863 }
864
865 if (host->rate != ios->clock)
866 usdhi6_clk_set(host, ios);
867 }
868
869 /* This is data timeout. Response timeout is fixed to 640 clock cycles */
870 static void usdhi6_timeout_set(struct usdhi6_host *host)
871 {
872 struct mmc_request *mrq = host->mrq;
873 u32 val;
874 unsigned long ticks;
875
876 if (!mrq->data)
877 ticks = host->rate / 1000 * mrq->cmd->busy_timeout;
878 else
879 ticks = host->rate / 1000000 * (mrq->data->timeout_ns / 1000) +
880 mrq->data->timeout_clks;
881
882 if (!ticks || ticks > 1 << 27)
883 /* Max timeout */
884 val = 14;
885 else if (ticks < 1 << 13)
886 /* Min timeout */
887 val = 0;
888 else
889 val = order_base_2(ticks) - 13;
890
891 dev_dbg(mmc_dev(host->mmc), "Set %s timeout %lu ticks @ %lu Hz\n",
892 mrq->data ? "data" : "cmd", ticks, host->rate);
893
894 /* Timeout Counter mask: 0xf0 */
895 usdhi6_write(host, USDHI6_SD_OPTION, (val << USDHI6_SD_OPTION_TIMEOUT_SHIFT) |
896 (usdhi6_read(host, USDHI6_SD_OPTION) & ~USDHI6_SD_OPTION_TIMEOUT_MASK));
897 }
898
899 static void usdhi6_request_done(struct usdhi6_host *host)
900 {
901 struct mmc_request *mrq = host->mrq;
902 struct mmc_data *data = mrq->data;
903
904 if (WARN(host->pg.page || host->head_pg.page,
905 "Page %p or %p not unmapped: wait %u, CMD%d(%c) @ +0x%zx %ux%u in SG%u!\n",
906 host->pg.page, host->head_pg.page, host->wait, mrq->cmd->opcode,
907 data ? (data->flags & MMC_DATA_READ ? 'R' : 'W') : '-',
908 data ? host->offset : 0, data ? data->blocks : 0,
909 data ? data->blksz : 0, data ? data->sg_len : 0))
910 usdhi6_sg_unmap(host, true);
911
912 if (mrq->cmd->error ||
913 (data && data->error) ||
914 (mrq->stop && mrq->stop->error))
915 dev_dbg(mmc_dev(host->mmc), "%s(CMD%d: %ux%u): err %d %d %d\n",
916 __func__, mrq->cmd->opcode, data ? data->blocks : 0,
917 data ? data->blksz : 0,
918 mrq->cmd->error,
919 data ? data->error : 1,
920 mrq->stop ? mrq->stop->error : 1);
921
922 /* Disable DMA */
923 usdhi6_write(host, USDHI6_CC_EXT_MODE, 0);
924 host->wait = USDHI6_WAIT_FOR_REQUEST;
925 host->mrq = NULL;
926
927 mmc_request_done(host->mmc, mrq);
928 }
929
930 static int usdhi6_cmd_flags(struct usdhi6_host *host)
931 {
932 struct mmc_request *mrq = host->mrq;
933 struct mmc_command *cmd = mrq->cmd;
934 u16 opc = cmd->opcode;
935
936 if (host->app_cmd) {
937 host->app_cmd = false;
938 opc |= USDHI6_SD_CMD_APP;
939 }
940
941 if (mrq->data) {
942 opc |= USDHI6_SD_CMD_DATA;
943
944 if (mrq->data->flags & MMC_DATA_READ)
945 opc |= USDHI6_SD_CMD_READ;
946
947 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
948 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
949 (cmd->opcode == SD_IO_RW_EXTENDED &&
950 mrq->data->blocks > 1)) {
951 opc |= USDHI6_SD_CMD_MULTI;
952 if (!mrq->stop)
953 opc |= USDHI6_SD_CMD_CMD12_AUTO_OFF;
954 }
955
956 switch (mmc_resp_type(cmd)) {
957 case MMC_RSP_NONE:
958 opc |= USDHI6_SD_CMD_MODE_RSP_NONE;
959 break;
960 case MMC_RSP_R1:
961 opc |= USDHI6_SD_CMD_MODE_RSP_R1;
962 break;
963 case MMC_RSP_R1B:
964 opc |= USDHI6_SD_CMD_MODE_RSP_R1B;
965 break;
966 case MMC_RSP_R2:
967 opc |= USDHI6_SD_CMD_MODE_RSP_R2;
968 break;
969 case MMC_RSP_R3:
970 opc |= USDHI6_SD_CMD_MODE_RSP_R3;
971 break;
972 default:
973 dev_warn(mmc_dev(host->mmc),
974 "Unknown response type %d\n",
975 mmc_resp_type(cmd));
976 return -EINVAL;
977 }
978 }
979
980 return opc;
981 }
982
983 static int usdhi6_rq_start(struct usdhi6_host *host)
984 {
985 struct mmc_request *mrq = host->mrq;
986 struct mmc_command *cmd = mrq->cmd;
987 struct mmc_data *data = mrq->data;
988 int opc = usdhi6_cmd_flags(host);
989 int i;
990
991 if (opc < 0)
992 return opc;
993
994 for (i = 1000; i; i--) {
995 if (!(usdhi6_read(host, USDHI6_SD_INFO2) & USDHI6_SD_INFO2_CBSY))
996 break;
997 usleep_range(10, 100);
998 }
999
1000 if (!i) {
1001 dev_dbg(mmc_dev(host->mmc), "Command active, request aborted\n");
1002 return -EAGAIN;
1003 }
1004
1005 if (data) {
1006 bool use_dma;
1007 int ret = 0;
1008
1009 host->page_idx = 0;
1010
1011 if (cmd->opcode == SD_IO_RW_EXTENDED && data->blocks > 1) {
1012 switch (data->blksz) {
1013 case 512:
1014 break;
1015 case 32:
1016 case 64:
1017 case 128:
1018 case 256:
1019 if (mrq->stop)
1020 ret = -EINVAL;
1021 break;
1022 default:
1023 ret = -EINVAL;
1024 }
1025 } else if ((cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1026 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) &&
1027 data->blksz != 512) {
1028 ret = -EINVAL;
1029 }
1030
1031 if (ret < 0) {
1032 dev_warn(mmc_dev(host->mmc), "%s(): %u blocks of %u bytes\n",
1033 __func__, data->blocks, data->blksz);
1034 return -EINVAL;
1035 }
1036
1037 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1038 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
1039 (cmd->opcode == SD_IO_RW_EXTENDED &&
1040 data->blocks > 1))
1041 usdhi6_sg_prep(host);
1042
1043 usdhi6_write(host, USDHI6_SD_SIZE, data->blksz);
1044
1045 if ((data->blksz >= USDHI6_MIN_DMA ||
1046 data->blocks > 1) &&
1047 (data->blksz % 4 ||
1048 data->sg->offset % 4))
1049 dev_dbg(mmc_dev(host->mmc),
1050 "Bad SG of %u: %ux%u @ %u\n", data->sg_len,
1051 data->blksz, data->blocks, data->sg->offset);
1052
1053 /* Enable DMA for USDHI6_MIN_DMA bytes or more */
1054 use_dma = data->blksz >= USDHI6_MIN_DMA &&
1055 !(data->blksz % 4) &&
1056 usdhi6_dma_start(host) >= DMA_MIN_COOKIE;
1057
1058 if (use_dma)
1059 usdhi6_write(host, USDHI6_CC_EXT_MODE, USDHI6_CC_EXT_MODE_SDRW);
1060
1061 dev_dbg(mmc_dev(host->mmc),
1062 "%s(): request opcode %u, %u blocks of %u bytes in %u segments, %s %s @+0x%x%s\n",
1063 __func__, cmd->opcode, data->blocks, data->blksz,
1064 data->sg_len, use_dma ? "DMA" : "PIO",
1065 data->flags & MMC_DATA_READ ? "read" : "write",
1066 data->sg->offset, mrq->stop ? " + stop" : "");
1067 } else {
1068 dev_dbg(mmc_dev(host->mmc), "%s(): request opcode %u\n",
1069 __func__, cmd->opcode);
1070 }
1071
1072 /* We have to get a command completion interrupt with DMA too */
1073 usdhi6_wait_for_resp(host);
1074
1075 host->wait = USDHI6_WAIT_FOR_CMD;
1076 schedule_delayed_work(&host->timeout_work, host->timeout);
1077
1078 /* SEC bit is required to enable block counting by the core */
1079 usdhi6_write(host, USDHI6_SD_STOP,
1080 data && data->blocks > 1 ? USDHI6_SD_STOP_SEC : 0);
1081 usdhi6_write(host, USDHI6_SD_ARG, cmd->arg);
1082
1083 /* Kick command execution */
1084 usdhi6_write(host, USDHI6_SD_CMD, opc);
1085
1086 return 0;
1087 }
1088
1089 static void usdhi6_request(struct mmc_host *mmc, struct mmc_request *mrq)
1090 {
1091 struct usdhi6_host *host = mmc_priv(mmc);
1092 int ret;
1093
1094 cancel_delayed_work_sync(&host->timeout_work);
1095
1096 host->mrq = mrq;
1097 host->sg = NULL;
1098
1099 usdhi6_timeout_set(host);
1100 ret = usdhi6_rq_start(host);
1101 if (ret < 0) {
1102 mrq->cmd->error = ret;
1103 usdhi6_request_done(host);
1104 }
1105 }
1106
1107 static int usdhi6_get_cd(struct mmc_host *mmc)
1108 {
1109 struct usdhi6_host *host = mmc_priv(mmc);
1110 /* Read is atomic, no need to lock */
1111 u32 status = usdhi6_read(host, USDHI6_SD_INFO1) & USDHI6_SD_INFO1_CD;
1112
1113 /*
1114 * level status.CD CD_ACTIVE_HIGH card present
1115 * 1 0 0 0
1116 * 1 0 1 1
1117 * 0 1 0 1
1118 * 0 1 1 0
1119 */
1120 return !status ^ !(mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH);
1121 }
1122
1123 static int usdhi6_get_ro(struct mmc_host *mmc)
1124 {
1125 struct usdhi6_host *host = mmc_priv(mmc);
1126 /* No locking as above */
1127 u32 status = usdhi6_read(host, USDHI6_SD_INFO1) & USDHI6_SD_INFO1_WP;
1128
1129 /*
1130 * level status.WP RO_ACTIVE_HIGH card read-only
1131 * 1 0 0 0
1132 * 1 0 1 1
1133 * 0 1 0 1
1134 * 0 1 1 0
1135 */
1136 return !status ^ !(mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH);
1137 }
1138
1139 static void usdhi6_enable_sdio_irq(struct mmc_host *mmc, int enable)
1140 {
1141 struct usdhi6_host *host = mmc_priv(mmc);
1142
1143 dev_dbg(mmc_dev(mmc), "%s(): %sable\n", __func__, enable ? "en" : "dis");
1144
1145 if (enable) {
1146 host->sdio_mask = USDHI6_SDIO_INFO1_IRQ & ~USDHI6_SDIO_INFO1_IOIRQ;
1147 usdhi6_write(host, USDHI6_SDIO_INFO1_MASK, host->sdio_mask);
1148 usdhi6_write(host, USDHI6_SDIO_MODE, 1);
1149 } else {
1150 usdhi6_write(host, USDHI6_SDIO_MODE, 0);
1151 usdhi6_write(host, USDHI6_SDIO_INFO1_MASK, USDHI6_SDIO_INFO1_IRQ);
1152 host->sdio_mask = USDHI6_SDIO_INFO1_IRQ;
1153 }
1154 }
1155
1156 static int usdhi6_set_pinstates(struct usdhi6_host *host, int voltage)
1157 {
1158 if (IS_ERR(host->pins_uhs))
1159 return 0;
1160
1161 switch (voltage) {
1162 case MMC_SIGNAL_VOLTAGE_180:
1163 case MMC_SIGNAL_VOLTAGE_120:
1164 return pinctrl_select_state(host->pinctrl,
1165 host->pins_uhs);
1166
1167 default:
1168 return pinctrl_select_state(host->pinctrl,
1169 host->pins_default);
1170 }
1171 }
1172
1173 static int usdhi6_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1174 {
1175 int ret;
1176
1177 ret = mmc_regulator_set_vqmmc(mmc, ios);
1178 if (ret < 0)
1179 return ret;
1180
1181 ret = usdhi6_set_pinstates(mmc_priv(mmc), ios->signal_voltage);
1182 if (ret)
1183 dev_warn_once(mmc_dev(mmc),
1184 "Failed to set pinstate err=%d\n", ret);
1185 return ret;
1186 }
1187
1188 static struct mmc_host_ops usdhi6_ops = {
1189 .request = usdhi6_request,
1190 .set_ios = usdhi6_set_ios,
1191 .get_cd = usdhi6_get_cd,
1192 .get_ro = usdhi6_get_ro,
1193 .enable_sdio_irq = usdhi6_enable_sdio_irq,
1194 .start_signal_voltage_switch = usdhi6_sig_volt_switch,
1195 };
1196
1197 /* State machine handlers */
1198
1199 static void usdhi6_resp_cmd12(struct usdhi6_host *host)
1200 {
1201 struct mmc_command *cmd = host->mrq->stop;
1202 cmd->resp[0] = usdhi6_read(host, USDHI6_SD_RSP10);
1203 }
1204
1205 static void usdhi6_resp_read(struct usdhi6_host *host)
1206 {
1207 struct mmc_command *cmd = host->mrq->cmd;
1208 u32 *rsp = cmd->resp, tmp = 0;
1209 int i;
1210
1211 /*
1212 * RSP10 39-8
1213 * RSP32 71-40
1214 * RSP54 103-72
1215 * RSP76 127-104
1216 * R2-type response:
1217 * resp[0] = r[127..96]
1218 * resp[1] = r[95..64]
1219 * resp[2] = r[63..32]
1220 * resp[3] = r[31..0]
1221 * Other responses:
1222 * resp[0] = r[39..8]
1223 */
1224
1225 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
1226 return;
1227
1228 if (!(host->irq_status & USDHI6_SD_INFO1_RSP_END)) {
1229 dev_err(mmc_dev(host->mmc),
1230 "CMD%d: response expected but is missing!\n", cmd->opcode);
1231 return;
1232 }
1233
1234 if (mmc_resp_type(cmd) & MMC_RSP_136)
1235 for (i = 0; i < 4; i++) {
1236 if (i)
1237 rsp[3 - i] = tmp >> 24;
1238 tmp = usdhi6_read(host, USDHI6_SD_RSP10 + i * 8);
1239 rsp[3 - i] |= tmp << 8;
1240 }
1241 else if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1242 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
1243 /* Read RSP54 to avoid conflict with auto CMD12 */
1244 rsp[0] = usdhi6_read(host, USDHI6_SD_RSP54);
1245 else
1246 rsp[0] = usdhi6_read(host, USDHI6_SD_RSP10);
1247
1248 dev_dbg(mmc_dev(host->mmc), "Response 0x%x\n", rsp[0]);
1249 }
1250
1251 static int usdhi6_blk_read(struct usdhi6_host *host)
1252 {
1253 struct mmc_data *data = host->mrq->data;
1254 u32 *p;
1255 int i, rest;
1256
1257 if (host->io_error) {
1258 data->error = usdhi6_error_code(host);
1259 goto error;
1260 }
1261
1262 if (host->pg.page) {
1263 p = host->blk_page + host->offset;
1264 } else {
1265 p = usdhi6_sg_map(host);
1266 if (!p) {
1267 data->error = -ENOMEM;
1268 goto error;
1269 }
1270 }
1271
1272 for (i = 0; i < data->blksz / 4; i++, p++)
1273 *p = usdhi6_read(host, USDHI6_SD_BUF0);
1274
1275 rest = data->blksz % 4;
1276 for (i = 0; i < (rest + 1) / 2; i++) {
1277 u16 d = usdhi6_read16(host, USDHI6_SD_BUF0);
1278 ((u8 *)p)[2 * i] = ((u8 *)&d)[0];
1279 if (rest > 1 && !i)
1280 ((u8 *)p)[2 * i + 1] = ((u8 *)&d)[1];
1281 }
1282
1283 return 0;
1284
1285 error:
1286 dev_dbg(mmc_dev(host->mmc), "%s(): %d\n", __func__, data->error);
1287 host->wait = USDHI6_WAIT_FOR_REQUEST;
1288 return data->error;
1289 }
1290
1291 static int usdhi6_blk_write(struct usdhi6_host *host)
1292 {
1293 struct mmc_data *data = host->mrq->data;
1294 u32 *p;
1295 int i, rest;
1296
1297 if (host->io_error) {
1298 data->error = usdhi6_error_code(host);
1299 goto error;
1300 }
1301
1302 if (host->pg.page) {
1303 p = host->blk_page + host->offset;
1304 } else {
1305 p = usdhi6_sg_map(host);
1306 if (!p) {
1307 data->error = -ENOMEM;
1308 goto error;
1309 }
1310 }
1311
1312 for (i = 0; i < data->blksz / 4; i++, p++)
1313 usdhi6_write(host, USDHI6_SD_BUF0, *p);
1314
1315 rest = data->blksz % 4;
1316 for (i = 0; i < (rest + 1) / 2; i++) {
1317 u16 d;
1318 ((u8 *)&d)[0] = ((u8 *)p)[2 * i];
1319 if (rest > 1 && !i)
1320 ((u8 *)&d)[1] = ((u8 *)p)[2 * i + 1];
1321 else
1322 ((u8 *)&d)[1] = 0;
1323 usdhi6_write16(host, USDHI6_SD_BUF0, d);
1324 }
1325
1326 return 0;
1327
1328 error:
1329 dev_dbg(mmc_dev(host->mmc), "%s(): %d\n", __func__, data->error);
1330 host->wait = USDHI6_WAIT_FOR_REQUEST;
1331 return data->error;
1332 }
1333
1334 static int usdhi6_stop_cmd(struct usdhi6_host *host)
1335 {
1336 struct mmc_request *mrq = host->mrq;
1337
1338 switch (mrq->cmd->opcode) {
1339 case MMC_READ_MULTIPLE_BLOCK:
1340 case MMC_WRITE_MULTIPLE_BLOCK:
1341 if (mrq->stop->opcode == MMC_STOP_TRANSMISSION) {
1342 host->wait = USDHI6_WAIT_FOR_STOP;
1343 return 0;
1344 }
1345 /* Unsupported STOP command */
1346 default:
1347 dev_err(mmc_dev(host->mmc),
1348 "unsupported stop CMD%d for CMD%d\n",
1349 mrq->stop->opcode, mrq->cmd->opcode);
1350 mrq->stop->error = -EOPNOTSUPP;
1351 }
1352
1353 return -EOPNOTSUPP;
1354 }
1355
1356 static bool usdhi6_end_cmd(struct usdhi6_host *host)
1357 {
1358 struct mmc_request *mrq = host->mrq;
1359 struct mmc_command *cmd = mrq->cmd;
1360
1361 if (host->io_error) {
1362 cmd->error = usdhi6_error_code(host);
1363 return false;
1364 }
1365
1366 usdhi6_resp_read(host);
1367
1368 if (!mrq->data)
1369 return false;
1370
1371 if (host->dma_active) {
1372 usdhi6_dma_kick(host);
1373 if (!mrq->stop)
1374 host->wait = USDHI6_WAIT_FOR_DMA;
1375 else if (usdhi6_stop_cmd(host) < 0)
1376 return false;
1377 } else if (mrq->data->flags & MMC_DATA_READ) {
1378 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1379 (cmd->opcode == SD_IO_RW_EXTENDED &&
1380 mrq->data->blocks > 1))
1381 host->wait = USDHI6_WAIT_FOR_MREAD;
1382 else
1383 host->wait = USDHI6_WAIT_FOR_READ;
1384 } else {
1385 if (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
1386 (cmd->opcode == SD_IO_RW_EXTENDED &&
1387 mrq->data->blocks > 1))
1388 host->wait = USDHI6_WAIT_FOR_MWRITE;
1389 else
1390 host->wait = USDHI6_WAIT_FOR_WRITE;
1391 }
1392
1393 return true;
1394 }
1395
1396 static bool usdhi6_read_block(struct usdhi6_host *host)
1397 {
1398 /* ACCESS_END IRQ is already unmasked */
1399 int ret = usdhi6_blk_read(host);
1400
1401 /*
1402 * Have to force unmapping both pages: the single block could have been
1403 * cross-page, in which case for single-block IO host->page_idx == 0.
1404 * So, if we don't force, the second page won't be unmapped.
1405 */
1406 usdhi6_sg_unmap(host, true);
1407
1408 if (ret < 0)
1409 return false;
1410
1411 host->wait = USDHI6_WAIT_FOR_DATA_END;
1412 return true;
1413 }
1414
1415 static bool usdhi6_mread_block(struct usdhi6_host *host)
1416 {
1417 int ret = usdhi6_blk_read(host);
1418
1419 if (ret < 0)
1420 return false;
1421
1422 usdhi6_sg_advance(host);
1423
1424 return !host->mrq->data->error &&
1425 (host->wait != USDHI6_WAIT_FOR_DATA_END || !host->mrq->stop);
1426 }
1427
1428 static bool usdhi6_write_block(struct usdhi6_host *host)
1429 {
1430 int ret = usdhi6_blk_write(host);
1431
1432 /* See comment in usdhi6_read_block() */
1433 usdhi6_sg_unmap(host, true);
1434
1435 if (ret < 0)
1436 return false;
1437
1438 host->wait = USDHI6_WAIT_FOR_DATA_END;
1439 return true;
1440 }
1441
1442 static bool usdhi6_mwrite_block(struct usdhi6_host *host)
1443 {
1444 int ret = usdhi6_blk_write(host);
1445
1446 if (ret < 0)
1447 return false;
1448
1449 usdhi6_sg_advance(host);
1450
1451 return !host->mrq->data->error &&
1452 (host->wait != USDHI6_WAIT_FOR_DATA_END || !host->mrq->stop);
1453 }
1454
1455 /* Interrupt & timeout handlers */
1456
1457 static irqreturn_t usdhi6_sd_bh(int irq, void *dev_id)
1458 {
1459 struct usdhi6_host *host = dev_id;
1460 struct mmc_request *mrq;
1461 struct mmc_command *cmd;
1462 struct mmc_data *data;
1463 bool io_wait = false;
1464
1465 cancel_delayed_work_sync(&host->timeout_work);
1466
1467 mrq = host->mrq;
1468 if (!mrq)
1469 return IRQ_HANDLED;
1470
1471 cmd = mrq->cmd;
1472 data = mrq->data;
1473
1474 switch (host->wait) {
1475 case USDHI6_WAIT_FOR_REQUEST:
1476 /* We're too late, the timeout has already kicked in */
1477 return IRQ_HANDLED;
1478 case USDHI6_WAIT_FOR_CMD:
1479 /* Wait for data? */
1480 io_wait = usdhi6_end_cmd(host);
1481 break;
1482 case USDHI6_WAIT_FOR_MREAD:
1483 /* Wait for more data? */
1484 io_wait = usdhi6_mread_block(host);
1485 break;
1486 case USDHI6_WAIT_FOR_READ:
1487 /* Wait for data end? */
1488 io_wait = usdhi6_read_block(host);
1489 break;
1490 case USDHI6_WAIT_FOR_MWRITE:
1491 /* Wait data to write? */
1492 io_wait = usdhi6_mwrite_block(host);
1493 break;
1494 case USDHI6_WAIT_FOR_WRITE:
1495 /* Wait for data end? */
1496 io_wait = usdhi6_write_block(host);
1497 break;
1498 case USDHI6_WAIT_FOR_DMA:
1499 usdhi6_dma_check_error(host);
1500 break;
1501 case USDHI6_WAIT_FOR_STOP:
1502 usdhi6_write(host, USDHI6_SD_STOP, 0);
1503 if (host->io_error) {
1504 int ret = usdhi6_error_code(host);
1505 if (mrq->stop)
1506 mrq->stop->error = ret;
1507 else
1508 mrq->data->error = ret;
1509 dev_warn(mmc_dev(host->mmc), "%s(): %d\n", __func__, ret);
1510 break;
1511 }
1512 usdhi6_resp_cmd12(host);
1513 mrq->stop->error = 0;
1514 break;
1515 case USDHI6_WAIT_FOR_DATA_END:
1516 if (host->io_error) {
1517 mrq->data->error = usdhi6_error_code(host);
1518 dev_warn(mmc_dev(host->mmc), "%s(): %d\n", __func__,
1519 mrq->data->error);
1520 }
1521 break;
1522 default:
1523 cmd->error = -EFAULT;
1524 dev_err(mmc_dev(host->mmc), "Invalid state %u\n", host->wait);
1525 usdhi6_request_done(host);
1526 return IRQ_HANDLED;
1527 }
1528
1529 if (io_wait) {
1530 schedule_delayed_work(&host->timeout_work, host->timeout);
1531 /* Wait for more data or ACCESS_END */
1532 if (!host->dma_active)
1533 usdhi6_wait_for_brwe(host, mrq->data->flags & MMC_DATA_READ);
1534 return IRQ_HANDLED;
1535 }
1536
1537 if (!cmd->error) {
1538 if (data) {
1539 if (!data->error) {
1540 if (host->wait != USDHI6_WAIT_FOR_STOP &&
1541 host->mrq->stop &&
1542 !host->mrq->stop->error &&
1543 !usdhi6_stop_cmd(host)) {
1544 /* Sending STOP */
1545 usdhi6_wait_for_resp(host);
1546
1547 schedule_delayed_work(&host->timeout_work,
1548 host->timeout);
1549
1550 return IRQ_HANDLED;
1551 }
1552
1553 data->bytes_xfered = data->blocks * data->blksz;
1554 } else {
1555 /* Data error: might need to unmap the last page */
1556 dev_warn(mmc_dev(host->mmc), "%s(): data error %d\n",
1557 __func__, data->error);
1558 usdhi6_sg_unmap(host, true);
1559 }
1560 } else if (cmd->opcode == MMC_APP_CMD) {
1561 host->app_cmd = true;
1562 }
1563 }
1564
1565 usdhi6_request_done(host);
1566
1567 return IRQ_HANDLED;
1568 }
1569
1570 static irqreturn_t usdhi6_sd(int irq, void *dev_id)
1571 {
1572 struct usdhi6_host *host = dev_id;
1573 u16 status, status2, error;
1574
1575 status = usdhi6_read(host, USDHI6_SD_INFO1) & ~host->status_mask &
1576 ~USDHI6_SD_INFO1_CARD;
1577 status2 = usdhi6_read(host, USDHI6_SD_INFO2) & ~host->status2_mask;
1578
1579 usdhi6_only_cd(host);
1580
1581 dev_dbg(mmc_dev(host->mmc),
1582 "IRQ status = 0x%08x, status2 = 0x%08x\n", status, status2);
1583
1584 if (!status && !status2)
1585 return IRQ_NONE;
1586
1587 error = status2 & USDHI6_SD_INFO2_ERR;
1588
1589 /* Ack / clear interrupts */
1590 if (USDHI6_SD_INFO1_IRQ & status)
1591 usdhi6_write(host, USDHI6_SD_INFO1,
1592 0xffff & ~(USDHI6_SD_INFO1_IRQ & status));
1593
1594 if (USDHI6_SD_INFO2_IRQ & status2) {
1595 if (error)
1596 /* In error cases BWE and BRE aren't cleared automatically */
1597 status2 |= USDHI6_SD_INFO2_BWE | USDHI6_SD_INFO2_BRE;
1598
1599 usdhi6_write(host, USDHI6_SD_INFO2,
1600 0xffff & ~(USDHI6_SD_INFO2_IRQ & status2));
1601 }
1602
1603 host->io_error = error;
1604 host->irq_status = status;
1605
1606 if (error) {
1607 /* Don't pollute the log with unsupported command timeouts */
1608 if (host->wait != USDHI6_WAIT_FOR_CMD ||
1609 error != USDHI6_SD_INFO2_RSP_TOUT)
1610 dev_warn(mmc_dev(host->mmc),
1611 "%s(): INFO2 error bits 0x%08x\n",
1612 __func__, error);
1613 else
1614 dev_dbg(mmc_dev(host->mmc),
1615 "%s(): INFO2 error bits 0x%08x\n",
1616 __func__, error);
1617 }
1618
1619 return IRQ_WAKE_THREAD;
1620 }
1621
1622 static irqreturn_t usdhi6_sdio(int irq, void *dev_id)
1623 {
1624 struct usdhi6_host *host = dev_id;
1625 u32 status = usdhi6_read(host, USDHI6_SDIO_INFO1) & ~host->sdio_mask;
1626
1627 dev_dbg(mmc_dev(host->mmc), "%s(): status 0x%x\n", __func__, status);
1628
1629 if (!status)
1630 return IRQ_NONE;
1631
1632 usdhi6_write(host, USDHI6_SDIO_INFO1, ~status);
1633
1634 mmc_signal_sdio_irq(host->mmc);
1635
1636 return IRQ_HANDLED;
1637 }
1638
1639 static irqreturn_t usdhi6_cd(int irq, void *dev_id)
1640 {
1641 struct usdhi6_host *host = dev_id;
1642 struct mmc_host *mmc = host->mmc;
1643 u16 status;
1644
1645 /* We're only interested in hotplug events here */
1646 status = usdhi6_read(host, USDHI6_SD_INFO1) & ~host->status_mask &
1647 USDHI6_SD_INFO1_CARD;
1648
1649 if (!status)
1650 return IRQ_NONE;
1651
1652 /* Ack */
1653 usdhi6_write(host, USDHI6_SD_INFO1, ~status);
1654
1655 if (!work_pending(&mmc->detect.work) &&
1656 (((status & USDHI6_SD_INFO1_CARD_INSERT) &&
1657 !mmc->card) ||
1658 ((status & USDHI6_SD_INFO1_CARD_EJECT) &&
1659 mmc->card)))
1660 mmc_detect_change(mmc, msecs_to_jiffies(100));
1661
1662 return IRQ_HANDLED;
1663 }
1664
1665 /*
1666 * Actually this should not be needed, if the built-in timeout works reliably in
1667 * the both PIO cases and DMA never fails. But if DMA does fail, a timeout
1668 * handler might be the only way to catch the error.
1669 */
1670 static void usdhi6_timeout_work(struct work_struct *work)
1671 {
1672 struct delayed_work *d = to_delayed_work(work);
1673 struct usdhi6_host *host = container_of(d, struct usdhi6_host, timeout_work);
1674 struct mmc_request *mrq = host->mrq;
1675 struct mmc_data *data = mrq ? mrq->data : NULL;
1676 struct scatterlist *sg;
1677
1678 dev_warn(mmc_dev(host->mmc),
1679 "%s timeout wait %u CMD%d: IRQ 0x%08x:0x%08x, last IRQ 0x%08x\n",
1680 host->dma_active ? "DMA" : "PIO",
1681 host->wait, mrq ? mrq->cmd->opcode : -1,
1682 usdhi6_read(host, USDHI6_SD_INFO1),
1683 usdhi6_read(host, USDHI6_SD_INFO2), host->irq_status);
1684
1685 if (host->dma_active) {
1686 usdhi6_dma_kill(host);
1687 usdhi6_dma_stop_unmap(host);
1688 }
1689
1690 switch (host->wait) {
1691 default:
1692 dev_err(mmc_dev(host->mmc), "Invalid state %u\n", host->wait);
1693 /* mrq can be NULL in this actually impossible case */
1694 case USDHI6_WAIT_FOR_CMD:
1695 usdhi6_error_code(host);
1696 if (mrq)
1697 mrq->cmd->error = -ETIMEDOUT;
1698 break;
1699 case USDHI6_WAIT_FOR_STOP:
1700 usdhi6_error_code(host);
1701 mrq->stop->error = -ETIMEDOUT;
1702 break;
1703 case USDHI6_WAIT_FOR_DMA:
1704 case USDHI6_WAIT_FOR_MREAD:
1705 case USDHI6_WAIT_FOR_MWRITE:
1706 case USDHI6_WAIT_FOR_READ:
1707 case USDHI6_WAIT_FOR_WRITE:
1708 sg = host->sg ?: data->sg;
1709 dev_dbg(mmc_dev(host->mmc),
1710 "%c: page #%u @ +0x%zx %ux%u in SG%u. Current SG %u bytes @ %u\n",
1711 data->flags & MMC_DATA_READ ? 'R' : 'W', host->page_idx,
1712 host->offset, data->blocks, data->blksz, data->sg_len,
1713 sg_dma_len(sg), sg->offset);
1714 usdhi6_sg_unmap(host, true);
1715 /*
1716 * If USDHI6_WAIT_FOR_DATA_END times out, we have already unmapped
1717 * the page
1718 */
1719 case USDHI6_WAIT_FOR_DATA_END:
1720 usdhi6_error_code(host);
1721 data->error = -ETIMEDOUT;
1722 }
1723
1724 if (mrq)
1725 usdhi6_request_done(host);
1726 }
1727
1728 /* Probe / release */
1729
1730 static const struct of_device_id usdhi6_of_match[] = {
1731 {.compatible = "renesas,usdhi6rol0"},
1732 {}
1733 };
1734 MODULE_DEVICE_TABLE(of, usdhi6_of_match);
1735
1736 static int usdhi6_probe(struct platform_device *pdev)
1737 {
1738 struct device *dev = &pdev->dev;
1739 struct mmc_host *mmc;
1740 struct usdhi6_host *host;
1741 struct resource *res;
1742 int irq_cd, irq_sd, irq_sdio;
1743 u32 version;
1744 int ret;
1745
1746 if (!dev->of_node)
1747 return -ENODEV;
1748
1749 irq_cd = platform_get_irq_byname(pdev, "card detect");
1750 irq_sd = platform_get_irq_byname(pdev, "data");
1751 irq_sdio = platform_get_irq_byname(pdev, "SDIO");
1752 if (irq_sd < 0 || irq_sdio < 0)
1753 return -ENODEV;
1754
1755 mmc = mmc_alloc_host(sizeof(struct usdhi6_host), dev);
1756 if (!mmc)
1757 return -ENOMEM;
1758
1759 ret = mmc_regulator_get_supply(mmc);
1760 if (ret == -EPROBE_DEFER)
1761 goto e_free_mmc;
1762
1763 ret = mmc_of_parse(mmc);
1764 if (ret < 0)
1765 goto e_free_mmc;
1766
1767 host = mmc_priv(mmc);
1768 host->mmc = mmc;
1769 host->wait = USDHI6_WAIT_FOR_REQUEST;
1770 host->timeout = msecs_to_jiffies(4000);
1771
1772 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1773 if (IS_ERR(host->pinctrl)) {
1774 ret = PTR_ERR(host->pinctrl);
1775 goto e_free_mmc;
1776 }
1777
1778 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1779 if (!IS_ERR(host->pins_uhs)) {
1780 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1781 PINCTRL_STATE_DEFAULT);
1782
1783 if (IS_ERR(host->pins_default)) {
1784 dev_err(dev,
1785 "UHS pinctrl requires a default pin state.\n");
1786 ret = PTR_ERR(host->pins_default);
1787 goto e_free_mmc;
1788 }
1789 }
1790
1791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1792 host->base = devm_ioremap_resource(dev, res);
1793 if (IS_ERR(host->base)) {
1794 ret = PTR_ERR(host->base);
1795 goto e_free_mmc;
1796 }
1797
1798 host->clk = devm_clk_get(dev, NULL);
1799 if (IS_ERR(host->clk)) {
1800 ret = PTR_ERR(host->clk);
1801 goto e_free_mmc;
1802 }
1803
1804 host->imclk = clk_get_rate(host->clk);
1805
1806 ret = clk_prepare_enable(host->clk);
1807 if (ret < 0)
1808 goto e_free_mmc;
1809
1810 version = usdhi6_read(host, USDHI6_VERSION);
1811 if ((version & 0xfff) != 0xa0d) {
1812 dev_err(dev, "Version not recognized %x\n", version);
1813 goto e_clk_off;
1814 }
1815
1816 dev_info(dev, "A USDHI6ROL0 SD host detected with %d ports\n",
1817 usdhi6_read(host, USDHI6_SD_PORT_SEL) >> USDHI6_SD_PORT_SEL_PORTS_SHIFT);
1818
1819 usdhi6_mask_all(host);
1820
1821 if (irq_cd >= 0) {
1822 ret = devm_request_irq(dev, irq_cd, usdhi6_cd, 0,
1823 dev_name(dev), host);
1824 if (ret < 0)
1825 goto e_clk_off;
1826 } else {
1827 mmc->caps |= MMC_CAP_NEEDS_POLL;
1828 }
1829
1830 ret = devm_request_threaded_irq(dev, irq_sd, usdhi6_sd, usdhi6_sd_bh, 0,
1831 dev_name(dev), host);
1832 if (ret < 0)
1833 goto e_clk_off;
1834
1835 ret = devm_request_irq(dev, irq_sdio, usdhi6_sdio, 0,
1836 dev_name(dev), host);
1837 if (ret < 0)
1838 goto e_clk_off;
1839
1840 INIT_DELAYED_WORK(&host->timeout_work, usdhi6_timeout_work);
1841
1842 usdhi6_dma_request(host, res->start);
1843
1844 mmc->ops = &usdhi6_ops;
1845 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
1846 MMC_CAP_SDIO_IRQ;
1847 /* Set .max_segs to some random number. Feel free to adjust. */
1848 mmc->max_segs = 32;
1849 mmc->max_blk_size = 512;
1850 mmc->max_req_size = PAGE_SIZE * mmc->max_segs;
1851 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1852 /*
1853 * Setting .max_seg_size to 1 page would simplify our page-mapping code,
1854 * But OTOH, having large segments makes DMA more efficient. We could
1855 * check, whether we managed to get DMA and fall back to 1 page
1856 * segments, but if we do manage to obtain DMA and then it fails at
1857 * run-time and we fall back to PIO, we will continue getting large
1858 * segments. So, we wouldn't be able to get rid of the code anyway.
1859 */
1860 mmc->max_seg_size = mmc->max_req_size;
1861 if (!mmc->f_max)
1862 mmc->f_max = host->imclk;
1863 mmc->f_min = host->imclk / 512;
1864
1865 platform_set_drvdata(pdev, host);
1866
1867 ret = mmc_add_host(mmc);
1868 if (ret < 0)
1869 goto e_clk_off;
1870
1871 return 0;
1872
1873 e_clk_off:
1874 clk_disable_unprepare(host->clk);
1875 e_free_mmc:
1876 mmc_free_host(mmc);
1877
1878 return ret;
1879 }
1880
1881 static int usdhi6_remove(struct platform_device *pdev)
1882 {
1883 struct usdhi6_host *host = platform_get_drvdata(pdev);
1884
1885 mmc_remove_host(host->mmc);
1886
1887 usdhi6_mask_all(host);
1888 cancel_delayed_work_sync(&host->timeout_work);
1889 usdhi6_dma_release(host);
1890 clk_disable_unprepare(host->clk);
1891 mmc_free_host(host->mmc);
1892
1893 return 0;
1894 }
1895
1896 static struct platform_driver usdhi6_driver = {
1897 .probe = usdhi6_probe,
1898 .remove = usdhi6_remove,
1899 .driver = {
1900 .name = "usdhi6rol0",
1901 .of_match_table = usdhi6_of_match,
1902 },
1903 };
1904
1905 module_platform_driver(usdhi6_driver);
1906
1907 MODULE_DESCRIPTION("Renesas usdhi6rol0 SD/SDIO host driver");
1908 MODULE_LICENSE("GPL v2");
1909 MODULE_ALIAS("platform:usdhi6rol0");
1910 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
Linux with added FPC-III support