drivers/ntb/hw/amd/ntb_hw_amd.h

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *   redistributing this file, you may do so under either license.
   4  *
   5  *   GPL LICENSE SUMMARY
   6  *
   7  *   Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of version 2 of the GNU General Public License as
  11  *   published by the Free Software Foundation.
  12  *
  13  *   BSD LICENSE
  14  *
  15  *   Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
  16  *
  17  *   Redistribution and use in source and binary forms, with or without
  18  *   modification, are permitted provided that the following conditions
  19  *   are met:
  20  *
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copy
  24  *       notice, this list of conditions and the following disclaimer in
  25  *       the documentation and/or other materials provided with the
  26  *       distribution.
  27  *     * Neither the name of AMD Corporation nor the names of its
  28  *       contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * AMD PCIe NTB Linux driver
  44  *
  45  * Contact Information:
  46  * Xiangliang Yu <Xiangliang.Yu@amd.com>
  47  */
  48
  49 #ifndef NTB_HW_AMD_H
  50 #define NTB_HW_AMD_H
  51
  52 #include <linux/ntb.h>
  53 #include <linux/pci.h>
  54
  55 #define PCI_DEVICE_ID_AMD_NTB   0x145B
  56 #define AMD_LINK_HB_TIMEOUT     msecs_to_jiffies(1000)
  57 #define AMD_LINK_STATUS_OFFSET  0x68
  58 #define NTB_LIN_STA_ACTIVE_BIT  0x00000002
  59 #define NTB_LNK_STA_SPEED_MASK  0x000F0000
  60 #define NTB_LNK_STA_WIDTH_MASK  0x03F00000
  61 #define NTB_LNK_STA_ACTIVE(x)   (!!((x) & NTB_LIN_STA_ACTIVE_BIT))
  62 #define NTB_LNK_STA_SPEED(x)    (((x) & NTB_LNK_STA_SPEED_MASK) >> 16)
  63 #define NTB_LNK_STA_WIDTH(x)    (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20)
  64
  65 #ifndef read64
  66 #ifdef readq
  67 #define read64 readq
  68 #else
  69 #define read64 _read64
  70 static inline u64 _read64(void __iomem *mmio)
  71 {
  72         u64 low, high;
  73
  74         low = readl(mmio);
  75         high = readl(mmio + sizeof(u32));
  76         return low | (high << 32);
  77 }
  78 #endif
  79 #endif
  80
  81 #ifndef write64
  82 #ifdef writeq
  83 #define write64 writeq
  84 #else
  85 #define write64 _write64
  86 static inline void _write64(u64 val, void __iomem *mmio)
  87 {
  88         writel(val, mmio);
  89         writel(val >> 32, mmio + sizeof(u32));
  90 }
  91 #endif
  92 #endif
  93
  94 enum {
  95         /* AMD NTB Capability */
  96         AMD_MW_CNT              = 3,
  97         AMD_DB_CNT              = 16,
  98         AMD_MSIX_VECTOR_CNT     = 24,
  99         AMD_SPADS_CNT           = 16,
 100
 101         /*  AMD NTB register offset */
 102         AMD_CNTL_OFFSET         = 0x200,
 103
 104         /* NTB control register bits */
 105         PMM_REG_CTL             = BIT(21),
 106         SMM_REG_CTL             = BIT(20),
 107         SMM_REG_ACC_PATH        = BIT(18),
 108         PMM_REG_ACC_PATH        = BIT(17),
 109         NTB_CLK_EN              = BIT(16),
 110
 111         AMD_STA_OFFSET          = 0x204,
 112         AMD_PGSLV_OFFSET        = 0x208,
 113         AMD_SPAD_MUX_OFFSET     = 0x20C,
 114         AMD_SPAD_OFFSET         = 0x210,
 115         AMD_RSMU_HCID           = 0x250,
 116         AMD_RSMU_SIID           = 0x254,
 117         AMD_PSION_OFFSET        = 0x300,
 118         AMD_SSION_OFFSET        = 0x330,
 119         AMD_MMINDEX_OFFSET      = 0x400,
 120         AMD_MMDATA_OFFSET       = 0x404,
 121         AMD_SIDEINFO_OFFSET     = 0x408,
 122
 123         AMD_SIDE_MASK           = BIT(0),
 124         AMD_SIDE_READY          = BIT(1),
 125
 126         /* limit register */
 127         AMD_ROMBARLMT_OFFSET    = 0x410,
 128         AMD_BAR1LMT_OFFSET      = 0x414,
 129         AMD_BAR23LMT_OFFSET     = 0x418,
 130         AMD_BAR45LMT_OFFSET     = 0x420,
 131         /* xlat address */
 132         AMD_POMBARXLAT_OFFSET   = 0x428,
 133         AMD_BAR1XLAT_OFFSET     = 0x430,
 134         AMD_BAR23XLAT_OFFSET    = 0x438,
 135         AMD_BAR45XLAT_OFFSET    = 0x440,
 136         /* doorbell and interrupt */
 137         AMD_DBFM_OFFSET         = 0x450,
 138         AMD_DBREQ_OFFSET        = 0x454,
 139         AMD_MIRRDBSTAT_OFFSET   = 0x458,
 140         AMD_DBMASK_OFFSET       = 0x45C,
 141         AMD_DBSTAT_OFFSET       = 0x460,
 142         AMD_INTMASK_OFFSET      = 0x470,
 143         AMD_INTSTAT_OFFSET      = 0x474,
 144
 145         /* event type */
 146         AMD_PEER_FLUSH_EVENT    = BIT(0),
 147         AMD_PEER_RESET_EVENT    = BIT(1),
 148         AMD_PEER_D3_EVENT       = BIT(2),
 149         AMD_PEER_PMETO_EVENT    = BIT(3),
 150         AMD_PEER_D0_EVENT       = BIT(4),
 151         AMD_LINK_UP_EVENT       = BIT(5),
 152         AMD_LINK_DOWN_EVENT     = BIT(6),
 153         AMD_EVENT_INTMASK       = (AMD_PEER_FLUSH_EVENT |
 154                                 AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |
 155                                 AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |
 156                                 AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),
 157
 158         AMD_PMESTAT_OFFSET      = 0x480,
 159         AMD_PMSGTRIG_OFFSET     = 0x490,
 160         AMD_LTRLATENCY_OFFSET   = 0x494,
 161         AMD_FLUSHTRIG_OFFSET    = 0x498,
 162
 163         /* SMU register*/
 164         AMD_SMUACK_OFFSET       = 0x4A0,
 165         AMD_SINRST_OFFSET       = 0x4A4,
 166         AMD_RSPNUM_OFFSET       = 0x4A8,
 167         AMD_SMU_SPADMUTEX       = 0x4B0,
 168         AMD_SMU_SPADOFFSET      = 0x4B4,
 169
 170         AMD_PEER_OFFSET         = 0x400,
 171 };
 172
 173 struct amd_ntb_dev;
 174
 175 struct amd_ntb_vec {
 176         struct amd_ntb_dev      *ndev;
 177         int                     num;
 178 };
 179
 180 struct amd_ntb_dev {
 181         struct ntb_dev ntb;
 182
 183         u32 ntb_side;
 184         u32 lnk_sta;
 185         u32 cntl_sta;
 186         u32 peer_sta;
 187
 188         unsigned char mw_count;
 189         unsigned char spad_count;
 190         unsigned char db_count;
 191         unsigned char msix_vec_count;
 192
 193         u64 db_valid_mask;
 194         u64 db_mask;
 195         u32 int_mask;
 196
 197         struct msix_entry *msix;
 198         struct amd_ntb_vec *vec;
 199
 200         /* synchronize rmw access of db_mask and hw reg */
 201         spinlock_t db_mask_lock;
 202
 203         void __iomem *self_mmio;
 204         void __iomem *peer_mmio;
 205         unsigned int self_spad;
 206         unsigned int peer_spad;
 207
 208         struct delayed_work hb_timer;
 209
 210         struct dentry *debugfs_dir;
 211         struct dentry *debugfs_info;
 212 };
 213
 214 #define ndev_pdev(ndev) ((ndev)->ntb.pdev)
 215 #define ndev_name(ndev) pci_name(ndev_pdev(ndev))
 216 #define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
 217 #define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
 218 #define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
 219
 220 #endif