sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / pci / host / pci-keystone.h
blobbc54bafda068a791f3a19c78b17fa156754c2a6e
1 /*
2 * Keystone PCI Controller's common includes
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #define MAX_LEGACY_IRQS 4
16 #define MAX_MSI_HOST_IRQS 8
17 #define MAX_LEGACY_HOST_IRQS 4
19 struct keystone_pcie {
20 struct pcie_port pp; /* pp.dbi_base is DT 0th res */
21 struct clk *clk;
22 /* PCI Device ID */
23 u32 device_id;
24 int num_legacy_host_irqs;
25 int legacy_host_irqs[MAX_LEGACY_HOST_IRQS];
26 struct device_node *legacy_intc_np;
28 int num_msi_host_irqs;
29 int msi_host_irqs[MAX_MSI_HOST_IRQS];
30 struct device_node *msi_intc_np;
31 struct irq_domain *legacy_irq_domain;
32 struct device_node *np;
34 int error_irq;
36 /* Application register space */
37 void __iomem *va_app_base; /* DT 1st resource */
38 struct resource app;
41 /* Keystone DW specific MSI controller APIs/definitions */
42 void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
43 phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
45 /* Keystone specific PCI controller APIs */
46 void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
47 void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
48 void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
49 irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
50 int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
51 struct device_node *msi_intc_np);
52 int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
53 unsigned int devfn, int where, int size, u32 val);
54 int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
55 unsigned int devfn, int where, int size, u32 *val);
56 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
57 int ks_dw_pcie_link_up(struct pcie_port *pp);
58 void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
59 void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
60 void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
61 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
62 int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
63 struct msi_controller *chip);