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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / pci / host / pci-tegra.c
blobed8a93f2bfb5fd4167f7362cddbc6eabe6dd85c8
1 /*
2 * PCIe host controller driver for Tegra SoCs
3 *
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 *
10 * Bits taken from arch/arm/mach-dove/pcie.c
11 *
12 * Author: Thierry Reding <treding@nvidia.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 */
28
29 #include <linux/clk.h>
30 #include <linux/debugfs.h>
31 #include <linux/delay.h>
32 #include <linux/export.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/irqdomain.h>
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/msi.h>
39 #include <linux/of_address.h>
40 #include <linux/of_pci.h>
41 #include <linux/of_platform.h>
42 #include <linux/pci.h>
43 #include <linux/phy/phy.h>
44 #include <linux/platform_device.h>
45 #include <linux/reset.h>
46 #include <linux/sizes.h>
47 #include <linux/slab.h>
48 #include <linux/vmalloc.h>
49 #include <linux/regulator/consumer.h>
50
51 #include <soc/tegra/cpuidle.h>
52 #include <soc/tegra/pmc.h>
53
54 #define INT_PCI_MSI_NR (8 * 32)
55
56 /* register definitions */
57
58 #define AFI_AXI_BAR0_SZ 0x00
59 #define AFI_AXI_BAR1_SZ 0x04
60 #define AFI_AXI_BAR2_SZ 0x08
61 #define AFI_AXI_BAR3_SZ 0x0c
62 #define AFI_AXI_BAR4_SZ 0x10
63 #define AFI_AXI_BAR5_SZ 0x14
64
65 #define AFI_AXI_BAR0_START 0x18
66 #define AFI_AXI_BAR1_START 0x1c
67 #define AFI_AXI_BAR2_START 0x20
68 #define AFI_AXI_BAR3_START 0x24
69 #define AFI_AXI_BAR4_START 0x28
70 #define AFI_AXI_BAR5_START 0x2c
71
72 #define AFI_FPCI_BAR0 0x30
73 #define AFI_FPCI_BAR1 0x34
74 #define AFI_FPCI_BAR2 0x38
75 #define AFI_FPCI_BAR3 0x3c
76 #define AFI_FPCI_BAR4 0x40
77 #define AFI_FPCI_BAR5 0x44
78
79 #define AFI_CACHE_BAR0_SZ 0x48
80 #define AFI_CACHE_BAR0_ST 0x4c
81 #define AFI_CACHE_BAR1_SZ 0x50
82 #define AFI_CACHE_BAR1_ST 0x54
83
84 #define AFI_MSI_BAR_SZ 0x60
85 #define AFI_MSI_FPCI_BAR_ST 0x64
86 #define AFI_MSI_AXI_BAR_ST 0x68
87
88 #define AFI_MSI_VEC0 0x6c
89 #define AFI_MSI_VEC1 0x70
90 #define AFI_MSI_VEC2 0x74
91 #define AFI_MSI_VEC3 0x78
92 #define AFI_MSI_VEC4 0x7c
93 #define AFI_MSI_VEC5 0x80
94 #define AFI_MSI_VEC6 0x84
95 #define AFI_MSI_VEC7 0x88
96
97 #define AFI_MSI_EN_VEC0 0x8c
98 #define AFI_MSI_EN_VEC1 0x90
99 #define AFI_MSI_EN_VEC2 0x94
100 #define AFI_MSI_EN_VEC3 0x98
101 #define AFI_MSI_EN_VEC4 0x9c
102 #define AFI_MSI_EN_VEC5 0xa0
103 #define AFI_MSI_EN_VEC6 0xa4
104 #define AFI_MSI_EN_VEC7 0xa8
105
106 #define AFI_CONFIGURATION 0xac
107 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
108
109 #define AFI_FPCI_ERROR_MASKS 0xb0
110
111 #define AFI_INTR_MASK 0xb4
112 #define AFI_INTR_MASK_INT_MASK (1 << 0)
113 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
114
115 #define AFI_INTR_CODE 0xb8
116 #define AFI_INTR_CODE_MASK 0xf
117 #define AFI_INTR_INI_SLAVE_ERROR 1
118 #define AFI_INTR_INI_DECODE_ERROR 2
119 #define AFI_INTR_TARGET_ABORT 3
120 #define AFI_INTR_MASTER_ABORT 4
121 #define AFI_INTR_INVALID_WRITE 5
122 #define AFI_INTR_LEGACY 6
123 #define AFI_INTR_FPCI_DECODE_ERROR 7
124 #define AFI_INTR_AXI_DECODE_ERROR 8
125 #define AFI_INTR_FPCI_TIMEOUT 9
126 #define AFI_INTR_PE_PRSNT_SENSE 10
127 #define AFI_INTR_PE_CLKREQ_SENSE 11
128 #define AFI_INTR_CLKCLAMP_SENSE 12
129 #define AFI_INTR_RDY4PD_SENSE 13
130 #define AFI_INTR_P2P_ERROR 14
131
132 #define AFI_INTR_SIGNATURE 0xbc
133 #define AFI_UPPER_FPCI_ADDRESS 0xc0
134 #define AFI_SM_INTR_ENABLE 0xc4
135 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
136 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
137 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
138 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
139 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
140 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
141 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
142 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
143
144 #define AFI_AFI_INTR_ENABLE 0xc8
145 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
146 #define AFI_INTR_EN_INI_DECERR (1 << 1)
147 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
148 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
149 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
150 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
151 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
152 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
153 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
154
155 #define AFI_PCIE_CONFIG 0x0f8
156 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
157 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
158 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
159 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
162 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
163 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
164 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
165 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
166
167 #define AFI_FUSE 0x104
168 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
169
170 #define AFI_PEX0_CTRL 0x110
171 #define AFI_PEX1_CTRL 0x118
172 #define AFI_PEX2_CTRL 0x128
173 #define AFI_PEX_CTRL_RST (1 << 0)
174 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
175 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
176 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
177
178 #define AFI_PLLE_CONTROL 0x160
179 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
180 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
181
182 #define AFI_PEXBIAS_CTRL_0 0x168
183
184 #define RP_VEND_XP 0x00000f00
185 #define RP_VEND_XP_DL_UP (1 << 30)
186
187 #define RP_VEND_CTL2 0x00000fa8
188 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
189
190 #define RP_PRIV_MISC 0x00000fe0
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
192 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
193
194 #define RP_LINK_CONTROL_STATUS 0x00000090
195 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
196 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
197
198 #define PADS_CTL_SEL 0x0000009c
199
200 #define PADS_CTL 0x000000a0
201 #define PADS_CTL_IDDQ_1L (1 << 0)
202 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
203 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
204
205 #define PADS_PLL_CTL_TEGRA20 0x000000b8
206 #define PADS_PLL_CTL_TEGRA30 0x000000b4
207 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
208 #define PADS_PLL_CTL_LOCKDET (1 << 8)
209 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
210 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
211 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
212 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
213 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
214 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
215 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
216 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
217
218 #define PADS_REFCLK_CFG0 0x000000c8
219 #define PADS_REFCLK_CFG1 0x000000cc
220 #define PADS_REFCLK_BIAS 0x000000d0
221
222 /*
223 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
224 * entries, one entry per PCIe port. These field definitions and desired
225 * values aren't in the TRM, but do come from NVIDIA.
226 */
227 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
228 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
229 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
230 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
231
232 struct tegra_msi {
233 struct msi_controller chip;
234 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
235 struct irq_domain *domain;
236 unsigned long pages;
237 struct mutex lock;
238 int irq;
239 };
240
241 /* used to differentiate between Tegra SoC generations */
242 struct tegra_pcie_soc {
243 unsigned int num_ports;
244 unsigned int msi_base_shift;
245 u32 pads_pll_ctl;
246 u32 tx_ref_sel;
247 u32 pads_refclk_cfg0;
248 u32 pads_refclk_cfg1;
249 bool has_pex_clkreq_en;
250 bool has_pex_bias_ctrl;
251 bool has_intr_prsnt_sense;
252 bool has_cml_clk;
253 bool has_gen2;
254 bool force_pca_enable;
255 };
256
257 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
258 {
259 return container_of(chip, struct tegra_msi, chip);
260 }
261
262 struct tegra_pcie {
263 struct device *dev;
264
265 void __iomem *pads;
266 void __iomem *afi;
267 int irq;
268
269 struct list_head buses;
270 struct resource *cs;
271
272 struct resource io;
273 struct resource pio;
274 struct resource mem;
275 struct resource prefetch;
276 struct resource busn;
277
278 struct {
279 resource_size_t mem;
280 resource_size_t io;
281 } offset;
282
283 struct clk *pex_clk;
284 struct clk *afi_clk;
285 struct clk *pll_e;
286 struct clk *cml_clk;
287
288 struct reset_control *pex_rst;
289 struct reset_control *afi_rst;
290 struct reset_control *pcie_xrst;
291
292 bool legacy_phy;
293 struct phy *phy;
294
295 struct tegra_msi msi;
296
297 struct list_head ports;
298 u32 xbar_config;
299
300 struct regulator_bulk_data *supplies;
301 unsigned int num_supplies;
302
303 const struct tegra_pcie_soc *soc;
304 struct dentry *debugfs;
305 };
306
307 struct tegra_pcie_port {
308 struct tegra_pcie *pcie;
309 struct device_node *np;
310 struct list_head list;
311 struct resource regs;
312 void __iomem *base;
313 unsigned int index;
314 unsigned int lanes;
315
316 struct phy **phys;
317 };
318
319 struct tegra_pcie_bus {
320 struct vm_struct *area;
321 struct list_head list;
322 unsigned int nr;
323 };
324
325 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
326 unsigned long offset)
327 {
328 writel(value, pcie->afi + offset);
329 }
330
331 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
332 {
333 return readl(pcie->afi + offset);
334 }
335
336 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
337 unsigned long offset)
338 {
339 writel(value, pcie->pads + offset);
340 }
341
342 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
343 {
344 return readl(pcie->pads + offset);
345 }
346
347 /*
348 * The configuration space mapping on Tegra is somewhat similar to the ECAM
349 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
350 * register accesses are mapped:
351 *
352 * [27:24] extended register number
353 * [23:16] bus number
354 * [15:11] device number
355 * [10: 8] function number
356 * [ 7: 0] register number
357 *
358 * Mapping the whole extended configuration space would require 256 MiB of
359 * virtual address space, only a small part of which will actually be used.
360 * To work around this, a 1 MiB of virtual addresses are allocated per bus
361 * when the bus is first accessed. When the physical range is mapped, the
362 * the bus number bits are hidden so that the extended register number bits
363 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
364 *
365 * [19:16] extended register number
366 * [15:11] device number
367 * [10: 8] function number
368 * [ 7: 0] register number
369 *
370 * This is achieved by stitching together 16 chunks of 64 KiB of physical
371 * address space via the MMU.
372 */
373 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
374 {
375 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
376 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
377 }
378
379 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
380 unsigned int busnr)
381 {
382 struct device *dev = pcie->dev;
383 pgprot_t prot = pgprot_device(PAGE_KERNEL);
384 phys_addr_t cs = pcie->cs->start;
385 struct tegra_pcie_bus *bus;
386 unsigned int i;
387 int err;
388
389 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
390 if (!bus)
391 return ERR_PTR(-ENOMEM);
392
393 INIT_LIST_HEAD(&bus->list);
394 bus->nr = busnr;
395
396 /* allocate 1 MiB of virtual addresses */
397 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
398 if (!bus->area) {
399 err = -ENOMEM;
400 goto free;
401 }
402
403 /* map each of the 16 chunks of 64 KiB each */
404 for (i = 0; i < 16; i++) {
405 unsigned long virt = (unsigned long)bus->area->addr +
406 i * SZ_64K;
407 phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
408
409 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
410 if (err < 0) {
411 dev_err(dev, "ioremap_page_range() failed: %d\n", err);
412 goto unmap;
413 }
414 }
415
416 return bus;
417
418 unmap:
419 vunmap(bus->area->addr);
420 free:
421 kfree(bus);
422 return ERR_PTR(err);
423 }
424
425 static int tegra_pcie_add_bus(struct pci_bus *bus)
426 {
427 struct pci_host_bridge *host = pci_find_host_bridge(bus);
428 struct tegra_pcie *pcie = pci_host_bridge_priv(host);
429 struct tegra_pcie_bus *b;
430
431 b = tegra_pcie_bus_alloc(pcie, bus->number);
432 if (IS_ERR(b))
433 return PTR_ERR(b);
434
435 list_add_tail(&b->list, &pcie->buses);
436
437 return 0;
438 }
439
440 static void tegra_pcie_remove_bus(struct pci_bus *child)
441 {
442 struct pci_host_bridge *host = pci_find_host_bridge(child);
443 struct tegra_pcie *pcie = pci_host_bridge_priv(host);
444 struct tegra_pcie_bus *bus, *tmp;
445
446 list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
447 if (bus->nr == child->number) {
448 vunmap(bus->area->addr);
449 list_del(&bus->list);
450 kfree(bus);
451 break;
452 }
453 }
454 }
455
456 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
457 unsigned int devfn,
458 int where)
459 {
460 struct pci_host_bridge *host = pci_find_host_bridge(bus);
461 struct tegra_pcie *pcie = pci_host_bridge_priv(host);
462 struct device *dev = pcie->dev;
463 void __iomem *addr = NULL;
464
465 if (bus->number == 0) {
466 unsigned int slot = PCI_SLOT(devfn);
467 struct tegra_pcie_port *port;
468
469 list_for_each_entry(port, &pcie->ports, list) {
470 if (port->index + 1 == slot) {
471 addr = port->base + (where & ~3);
472 break;
473 }
474 }
475 } else {
476 struct tegra_pcie_bus *b;
477
478 list_for_each_entry(b, &pcie->buses, list)
479 if (b->nr == bus->number)
480 addr = (void __iomem *)b->area->addr;
481
482 if (!addr) {
483 dev_err(dev, "failed to map cfg. space for bus %u\n",
484 bus->number);
485 return NULL;
486 }
487
488 addr += tegra_pcie_conf_offset(devfn, where);
489 }
490
491 return addr;
492 }
493
494 static struct pci_ops tegra_pcie_ops = {
495 .add_bus = tegra_pcie_add_bus,
496 .remove_bus = tegra_pcie_remove_bus,
497 .map_bus = tegra_pcie_map_bus,
498 .read = pci_generic_config_read32,
499 .write = pci_generic_config_write32,
500 };
501
502 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
503 {
504 unsigned long ret = 0;
505
506 switch (port->index) {
507 case 0:
508 ret = AFI_PEX0_CTRL;
509 break;
510
511 case 1:
512 ret = AFI_PEX1_CTRL;
513 break;
514
515 case 2:
516 ret = AFI_PEX2_CTRL;
517 break;
518 }
519
520 return ret;
521 }
522
523 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
524 {
525 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
526 unsigned long value;
527
528 /* pulse reset signal */
529 value = afi_readl(port->pcie, ctrl);
530 value &= ~AFI_PEX_CTRL_RST;
531 afi_writel(port->pcie, value, ctrl);
532
533 usleep_range(1000, 2000);
534
535 value = afi_readl(port->pcie, ctrl);
536 value |= AFI_PEX_CTRL_RST;
537 afi_writel(port->pcie, value, ctrl);
538 }
539
540 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
541 {
542 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
543 const struct tegra_pcie_soc *soc = port->pcie->soc;
544 unsigned long value;
545
546 /* enable reference clock */
547 value = afi_readl(port->pcie, ctrl);
548 value |= AFI_PEX_CTRL_REFCLK_EN;
549
550 if (soc->has_pex_clkreq_en)
551 value |= AFI_PEX_CTRL_CLKREQ_EN;
552
553 value |= AFI_PEX_CTRL_OVERRIDE_EN;
554
555 afi_writel(port->pcie, value, ctrl);
556
557 tegra_pcie_port_reset(port);
558
559 if (soc->force_pca_enable) {
560 value = readl(port->base + RP_VEND_CTL2);
561 value |= RP_VEND_CTL2_PCA_ENABLE;
562 writel(value, port->base + RP_VEND_CTL2);
563 }
564 }
565
566 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
567 {
568 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
569 const struct tegra_pcie_soc *soc = port->pcie->soc;
570 unsigned long value;
571
572 /* assert port reset */
573 value = afi_readl(port->pcie, ctrl);
574 value &= ~AFI_PEX_CTRL_RST;
575 afi_writel(port->pcie, value, ctrl);
576
577 /* disable reference clock */
578 value = afi_readl(port->pcie, ctrl);
579
580 if (soc->has_pex_clkreq_en)
581 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
582
583 value &= ~AFI_PEX_CTRL_REFCLK_EN;
584 afi_writel(port->pcie, value, ctrl);
585 }
586
587 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
588 {
589 struct tegra_pcie *pcie = port->pcie;
590 struct device *dev = pcie->dev;
591
592 devm_iounmap(dev, port->base);
593 devm_release_mem_region(dev, port->regs.start,
594 resource_size(&port->regs));
595 list_del(&port->list);
596 devm_kfree(dev, port);
597 }
598
599 /* Tegra PCIE root complex wrongly reports device class */
600 static void tegra_pcie_fixup_class(struct pci_dev *dev)
601 {
602 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
603 }
604 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
605 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
606 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
608
609 /* Tegra PCIE requires relaxed ordering */
610 static void tegra_pcie_relax_enable(struct pci_dev *dev)
611 {
612 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
613 }
614 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
615
616 static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
617 {
618 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
619 struct list_head *windows = &host->windows;
620 struct device *dev = pcie->dev;
621 int err;
622
623 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
624 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
625 pci_add_resource_offset(windows, &pcie->prefetch, pcie->offset.mem);
626 pci_add_resource(windows, &pcie->busn);
627
628 err = devm_request_pci_bus_resources(dev, windows);
629 if (err < 0)
630 return err;
631
632 pci_remap_iospace(&pcie->pio, pcie->io.start);
633
634 return 0;
635 }
636
637 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
638 {
639 struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
640 struct tegra_pcie *pcie = pci_host_bridge_priv(host);
641 int irq;
642
643 tegra_cpuidle_pcie_irqs_in_use();
644
645 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
646 if (!irq)
647 irq = pcie->irq;
648
649 return irq;
650 }
651
652 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
653 {
654 const char *err_msg[] = {
655 "Unknown",
656 "AXI slave error",
657 "AXI decode error",
658 "Target abort",
659 "Master abort",
660 "Invalid write",
661 "Legacy interrupt",
662 "Response decoding error",
663 "AXI response decoding error",
664 "Transaction timeout",
665 "Slot present pin change",
666 "Slot clock request change",
667 "TMS clock ramp change",
668 "TMS ready for power down",
669 "Peer2Peer error",
670 };
671 struct tegra_pcie *pcie = arg;
672 struct device *dev = pcie->dev;
673 u32 code, signature;
674
675 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
676 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
677 afi_writel(pcie, 0, AFI_INTR_CODE);
678
679 if (code == AFI_INTR_LEGACY)
680 return IRQ_NONE;
681
682 if (code >= ARRAY_SIZE(err_msg))
683 code = 0;
684
685 /*
686 * do not pollute kernel log with master abort reports since they
687 * happen a lot during enumeration
688 */
689 if (code == AFI_INTR_MASTER_ABORT)
690 dev_dbg(dev, "%s, signature: %08x\n", err_msg[code], signature);
691 else
692 dev_err(dev, "%s, signature: %08x\n", err_msg[code], signature);
693
694 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
695 code == AFI_INTR_FPCI_DECODE_ERROR) {
696 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
697 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
698
699 if (code == AFI_INTR_MASTER_ABORT)
700 dev_dbg(dev, " FPCI address: %10llx\n", address);
701 else
702 dev_err(dev, " FPCI address: %10llx\n", address);
703 }
704
705 return IRQ_HANDLED;
706 }
707
708 /*
709 * FPCI map is as follows:
710 * - 0xfdfc000000: I/O space
711 * - 0xfdfe000000: type 0 configuration space
712 * - 0xfdff000000: type 1 configuration space
713 * - 0xfe00000000: type 0 extended configuration space
714 * - 0xfe10000000: type 1 extended configuration space
715 */
716 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
717 {
718 u32 fpci_bar, size, axi_address;
719
720 /* Bar 0: type 1 extended configuration space */
721 fpci_bar = 0xfe100000;
722 size = resource_size(pcie->cs);
723 axi_address = pcie->cs->start;
724 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
725 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
726 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
727
728 /* Bar 1: downstream IO bar */
729 fpci_bar = 0xfdfc0000;
730 size = resource_size(&pcie->io);
731 axi_address = pcie->io.start;
732 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
733 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
734 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
735
736 /* Bar 2: prefetchable memory BAR */
737 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
738 size = resource_size(&pcie->prefetch);
739 axi_address = pcie->prefetch.start;
740 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
741 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
742 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
743
744 /* Bar 3: non prefetchable memory BAR */
745 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
746 size = resource_size(&pcie->mem);
747 axi_address = pcie->mem.start;
748 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
749 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
750 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
751
752 /* NULL out the remaining BARs as they are not used */
753 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
754 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
755 afi_writel(pcie, 0, AFI_FPCI_BAR4);
756
757 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
758 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
759 afi_writel(pcie, 0, AFI_FPCI_BAR5);
760
761 /* map all upstream transactions as uncached */
762 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
763 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
764 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
765 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
766
767 /* MSI translations are setup only when needed */
768 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
769 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
770 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
771 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
772 }
773
774 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
775 {
776 const struct tegra_pcie_soc *soc = pcie->soc;
777 u32 value;
778
779 timeout = jiffies + msecs_to_jiffies(timeout);
780
781 while (time_before(jiffies, timeout)) {
782 value = pads_readl(pcie, soc->pads_pll_ctl);
783 if (value & PADS_PLL_CTL_LOCKDET)
784 return 0;
785 }
786
787 return -ETIMEDOUT;
788 }
789
790 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
791 {
792 struct device *dev = pcie->dev;
793 const struct tegra_pcie_soc *soc = pcie->soc;
794 u32 value;
795 int err;
796
797 /* initialize internal PHY, enable up to 16 PCIE lanes */
798 pads_writel(pcie, 0x0, PADS_CTL_SEL);
799
800 /* override IDDQ to 1 on all 4 lanes */
801 value = pads_readl(pcie, PADS_CTL);
802 value |= PADS_CTL_IDDQ_1L;
803 pads_writel(pcie, value, PADS_CTL);
804
805 /*
806 * Set up PHY PLL inputs select PLLE output as refclock,
807 * set TX ref sel to div10 (not div5).
808 */
809 value = pads_readl(pcie, soc->pads_pll_ctl);
810 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
811 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
812 pads_writel(pcie, value, soc->pads_pll_ctl);
813
814 /* reset PLL */
815 value = pads_readl(pcie, soc->pads_pll_ctl);
816 value &= ~PADS_PLL_CTL_RST_B4SM;
817 pads_writel(pcie, value, soc->pads_pll_ctl);
818
819 usleep_range(20, 100);
820
821 /* take PLL out of reset */
822 value = pads_readl(pcie, soc->pads_pll_ctl);
823 value |= PADS_PLL_CTL_RST_B4SM;
824 pads_writel(pcie, value, soc->pads_pll_ctl);
825
826 /* wait for the PLL to lock */
827 err = tegra_pcie_pll_wait(pcie, 500);
828 if (err < 0) {
829 dev_err(dev, "PLL failed to lock: %d\n", err);
830 return err;
831 }
832
833 /* turn off IDDQ override */
834 value = pads_readl(pcie, PADS_CTL);
835 value &= ~PADS_CTL_IDDQ_1L;
836 pads_writel(pcie, value, PADS_CTL);
837
838 /* enable TX/RX data */
839 value = pads_readl(pcie, PADS_CTL);
840 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
841 pads_writel(pcie, value, PADS_CTL);
842
843 return 0;
844 }
845
846 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
847 {
848 const struct tegra_pcie_soc *soc = pcie->soc;
849 u32 value;
850
851 /* disable TX/RX data */
852 value = pads_readl(pcie, PADS_CTL);
853 value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
854 pads_writel(pcie, value, PADS_CTL);
855
856 /* override IDDQ */
857 value = pads_readl(pcie, PADS_CTL);
858 value |= PADS_CTL_IDDQ_1L;
859 pads_writel(pcie, value, PADS_CTL);
860
861 /* reset PLL */
862 value = pads_readl(pcie, soc->pads_pll_ctl);
863 value &= ~PADS_PLL_CTL_RST_B4SM;
864 pads_writel(pcie, value, soc->pads_pll_ctl);
865
866 usleep_range(20, 100);
867
868 return 0;
869 }
870
871 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
872 {
873 struct device *dev = port->pcie->dev;
874 unsigned int i;
875 int err;
876
877 for (i = 0; i < port->lanes; i++) {
878 err = phy_power_on(port->phys[i]);
879 if (err < 0) {
880 dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
881 return err;
882 }
883 }
884
885 return 0;
886 }
887
888 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
889 {
890 struct device *dev = port->pcie->dev;
891 unsigned int i;
892 int err;
893
894 for (i = 0; i < port->lanes; i++) {
895 err = phy_power_off(port->phys[i]);
896 if (err < 0) {
897 dev_err(dev, "failed to power off PHY#%u: %d\n", i,
898 err);
899 return err;
900 }
901 }
902
903 return 0;
904 }
905
906 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
907 {
908 struct device *dev = pcie->dev;
909 const struct tegra_pcie_soc *soc = pcie->soc;
910 struct tegra_pcie_port *port;
911 int err;
912
913 if (pcie->legacy_phy) {
914 if (pcie->phy)
915 err = phy_power_on(pcie->phy);
916 else
917 err = tegra_pcie_phy_enable(pcie);
918
919 if (err < 0)
920 dev_err(dev, "failed to power on PHY: %d\n", err);
921
922 return err;
923 }
924
925 list_for_each_entry(port, &pcie->ports, list) {
926 err = tegra_pcie_port_phy_power_on(port);
927 if (err < 0) {
928 dev_err(dev,
929 "failed to power on PCIe port %u PHY: %d\n",
930 port->index, err);
931 return err;
932 }
933 }
934
935 /* Configure the reference clock driver */
936 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
937
938 if (soc->num_ports > 2)
939 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
940
941 return 0;
942 }
943
944 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
945 {
946 struct device *dev = pcie->dev;
947 struct tegra_pcie_port *port;
948 int err;
949
950 if (pcie->legacy_phy) {
951 if (pcie->phy)
952 err = phy_power_off(pcie->phy);
953 else
954 err = tegra_pcie_phy_disable(pcie);
955
956 if (err < 0)
957 dev_err(dev, "failed to power off PHY: %d\n", err);
958
959 return err;
960 }
961
962 list_for_each_entry(port, &pcie->ports, list) {
963 err = tegra_pcie_port_phy_power_off(port);
964 if (err < 0) {
965 dev_err(dev,
966 "failed to power off PCIe port %u PHY: %d\n",
967 port->index, err);
968 return err;
969 }
970 }
971
972 return 0;
973 }
974
975 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
976 {
977 struct device *dev = pcie->dev;
978 const struct tegra_pcie_soc *soc = pcie->soc;
979 struct tegra_pcie_port *port;
980 unsigned long value;
981 int err;
982
983 /* enable PLL power down */
984 if (pcie->phy) {
985 value = afi_readl(pcie, AFI_PLLE_CONTROL);
986 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
987 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
988 afi_writel(pcie, value, AFI_PLLE_CONTROL);
989 }
990
991 /* power down PCIe slot clock bias pad */
992 if (soc->has_pex_bias_ctrl)
993 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
994
995 /* configure mode and disable all ports */
996 value = afi_readl(pcie, AFI_PCIE_CONFIG);
997 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
998 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
999
1000 list_for_each_entry(port, &pcie->ports, list)
1001 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1002
1003 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1004
1005 if (soc->has_gen2) {
1006 value = afi_readl(pcie, AFI_FUSE);
1007 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1008 afi_writel(pcie, value, AFI_FUSE);
1009 } else {
1010 value = afi_readl(pcie, AFI_FUSE);
1011 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
1012 afi_writel(pcie, value, AFI_FUSE);
1013 }
1014
1015 err = tegra_pcie_phy_power_on(pcie);
1016 if (err < 0) {
1017 dev_err(dev, "failed to power on PHY(s): %d\n", err);
1018 return err;
1019 }
1020
1021 /* take the PCIe interface module out of reset */
1022 reset_control_deassert(pcie->pcie_xrst);
1023
1024 /* finally enable PCIe */
1025 value = afi_readl(pcie, AFI_CONFIGURATION);
1026 value |= AFI_CONFIGURATION_EN_FPCI;
1027 afi_writel(pcie, value, AFI_CONFIGURATION);
1028
1029 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
1030 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
1031 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
1032
1033 if (soc->has_intr_prsnt_sense)
1034 value |= AFI_INTR_EN_PRSNT_SENSE;
1035
1036 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1037 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
1038
1039 /* don't enable MSI for now, only when needed */
1040 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
1041
1042 /* disable all exceptions */
1043 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
1044
1045 return 0;
1046 }
1047
1048 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
1049 {
1050 struct device *dev = pcie->dev;
1051 int err;
1052
1053 /* TODO: disable and unprepare clocks? */
1054
1055 err = tegra_pcie_phy_power_off(pcie);
1056 if (err < 0)
1057 dev_err(dev, "failed to power off PHY(s): %d\n", err);
1058
1059 reset_control_assert(pcie->pcie_xrst);
1060 reset_control_assert(pcie->afi_rst);
1061 reset_control_assert(pcie->pex_rst);
1062
1063 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1064
1065 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1066 if (err < 0)
1067 dev_warn(dev, "failed to disable regulators: %d\n", err);
1068 }
1069
1070 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
1071 {
1072 struct device *dev = pcie->dev;
1073 const struct tegra_pcie_soc *soc = pcie->soc;
1074 int err;
1075
1076 reset_control_assert(pcie->pcie_xrst);
1077 reset_control_assert(pcie->afi_rst);
1078 reset_control_assert(pcie->pex_rst);
1079
1080 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1081
1082 /* enable regulators */
1083 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1084 if (err < 0)
1085 dev_err(dev, "failed to enable regulators: %d\n", err);
1086
1087 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
1088 pcie->pex_clk,
1089 pcie->pex_rst);
1090 if (err) {
1091 dev_err(dev, "powerup sequence failed: %d\n", err);
1092 return err;
1093 }
1094
1095 reset_control_deassert(pcie->afi_rst);
1096
1097 err = clk_prepare_enable(pcie->afi_clk);
1098 if (err < 0) {
1099 dev_err(dev, "failed to enable AFI clock: %d\n", err);
1100 return err;
1101 }
1102
1103 if (soc->has_cml_clk) {
1104 err = clk_prepare_enable(pcie->cml_clk);
1105 if (err < 0) {
1106 dev_err(dev, "failed to enable CML clock: %d\n", err);
1107 return err;
1108 }
1109 }
1110
1111 err = clk_prepare_enable(pcie->pll_e);
1112 if (err < 0) {
1113 dev_err(dev, "failed to enable PLLE clock: %d\n", err);
1114 return err;
1115 }
1116
1117 return 0;
1118 }
1119
1120 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1121 {
1122 struct device *dev = pcie->dev;
1123 const struct tegra_pcie_soc *soc = pcie->soc;
1124
1125 pcie->pex_clk = devm_clk_get(dev, "pex");
1126 if (IS_ERR(pcie->pex_clk))
1127 return PTR_ERR(pcie->pex_clk);
1128
1129 pcie->afi_clk = devm_clk_get(dev, "afi");
1130 if (IS_ERR(pcie->afi_clk))
1131 return PTR_ERR(pcie->afi_clk);
1132
1133 pcie->pll_e = devm_clk_get(dev, "pll_e");
1134 if (IS_ERR(pcie->pll_e))
1135 return PTR_ERR(pcie->pll_e);
1136
1137 if (soc->has_cml_clk) {
1138 pcie->cml_clk = devm_clk_get(dev, "cml");
1139 if (IS_ERR(pcie->cml_clk))
1140 return PTR_ERR(pcie->cml_clk);
1141 }
1142
1143 return 0;
1144 }
1145
1146 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1147 {
1148 struct device *dev = pcie->dev;
1149
1150 pcie->pex_rst = devm_reset_control_get(dev, "pex");
1151 if (IS_ERR(pcie->pex_rst))
1152 return PTR_ERR(pcie->pex_rst);
1153
1154 pcie->afi_rst = devm_reset_control_get(dev, "afi");
1155 if (IS_ERR(pcie->afi_rst))
1156 return PTR_ERR(pcie->afi_rst);
1157
1158 pcie->pcie_xrst = devm_reset_control_get(dev, "pcie_x");
1159 if (IS_ERR(pcie->pcie_xrst))
1160 return PTR_ERR(pcie->pcie_xrst);
1161
1162 return 0;
1163 }
1164
1165 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1166 {
1167 struct device *dev = pcie->dev;
1168 int err;
1169
1170 pcie->phy = devm_phy_optional_get(dev, "pcie");
1171 if (IS_ERR(pcie->phy)) {
1172 err = PTR_ERR(pcie->phy);
1173 dev_err(dev, "failed to get PHY: %d\n", err);
1174 return err;
1175 }
1176
1177 err = phy_init(pcie->phy);
1178 if (err < 0) {
1179 dev_err(dev, "failed to initialize PHY: %d\n", err);
1180 return err;
1181 }
1182
1183 pcie->legacy_phy = true;
1184
1185 return 0;
1186 }
1187
1188 static struct phy *devm_of_phy_optional_get_index(struct device *dev,
1189 struct device_node *np,
1190 const char *consumer,
1191 unsigned int index)
1192 {
1193 struct phy *phy;
1194 char *name;
1195
1196 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index);
1197 if (!name)
1198 return ERR_PTR(-ENOMEM);
1199
1200 phy = devm_of_phy_get(dev, np, name);
1201 kfree(name);
1202
1203 if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
1204 phy = NULL;
1205
1206 return phy;
1207 }
1208
1209 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1210 {
1211 struct device *dev = port->pcie->dev;
1212 struct phy *phy;
1213 unsigned int i;
1214 int err;
1215
1216 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1217 if (!port->phys)
1218 return -ENOMEM;
1219
1220 for (i = 0; i < port->lanes; i++) {
1221 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1222 if (IS_ERR(phy)) {
1223 dev_err(dev, "failed to get PHY#%u: %ld\n", i,
1224 PTR_ERR(phy));
1225 return PTR_ERR(phy);
1226 }
1227
1228 err = phy_init(phy);
1229 if (err < 0) {
1230 dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
1231 err);
1232 return err;
1233 }
1234
1235 port->phys[i] = phy;
1236 }
1237
1238 return 0;
1239 }
1240
1241 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1242 {
1243 const struct tegra_pcie_soc *soc = pcie->soc;
1244 struct device_node *np = pcie->dev->of_node;
1245 struct tegra_pcie_port *port;
1246 int err;
1247
1248 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL)
1249 return tegra_pcie_phys_get_legacy(pcie);
1250
1251 list_for_each_entry(port, &pcie->ports, list) {
1252 err = tegra_pcie_port_get_phys(port);
1253 if (err < 0)
1254 return err;
1255 }
1256
1257 return 0;
1258 }
1259
1260 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1261 {
1262 struct device *dev = pcie->dev;
1263 struct platform_device *pdev = to_platform_device(dev);
1264 struct resource *pads, *afi, *res;
1265 int err;
1266
1267 err = tegra_pcie_clocks_get(pcie);
1268 if (err) {
1269 dev_err(dev, "failed to get clocks: %d\n", err);
1270 return err;
1271 }
1272
1273 err = tegra_pcie_resets_get(pcie);
1274 if (err) {
1275 dev_err(dev, "failed to get resets: %d\n", err);
1276 return err;
1277 }
1278
1279 err = tegra_pcie_phys_get(pcie);
1280 if (err < 0) {
1281 dev_err(dev, "failed to get PHYs: %d\n", err);
1282 return err;
1283 }
1284
1285 err = tegra_pcie_power_on(pcie);
1286 if (err) {
1287 dev_err(dev, "failed to power up: %d\n", err);
1288 return err;
1289 }
1290
1291 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1292 pcie->pads = devm_ioremap_resource(dev, pads);
1293 if (IS_ERR(pcie->pads)) {
1294 err = PTR_ERR(pcie->pads);
1295 goto poweroff;
1296 }
1297
1298 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1299 pcie->afi = devm_ioremap_resource(dev, afi);
1300 if (IS_ERR(pcie->afi)) {
1301 err = PTR_ERR(pcie->afi);
1302 goto poweroff;
1303 }
1304
1305 /* request configuration space, but remap later, on demand */
1306 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1307 if (!res) {
1308 err = -EADDRNOTAVAIL;
1309 goto poweroff;
1310 }
1311
1312 pcie->cs = devm_request_mem_region(dev, res->start,
1313 resource_size(res), res->name);
1314 if (!pcie->cs) {
1315 err = -EADDRNOTAVAIL;
1316 goto poweroff;
1317 }
1318
1319 /* request interrupt */
1320 err = platform_get_irq_byname(pdev, "intr");
1321 if (err < 0) {
1322 dev_err(dev, "failed to get IRQ: %d\n", err);
1323 goto poweroff;
1324 }
1325
1326 pcie->irq = err;
1327
1328 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1329 if (err) {
1330 dev_err(dev, "failed to register IRQ: %d\n", err);
1331 goto poweroff;
1332 }
1333
1334 return 0;
1335
1336 poweroff:
1337 tegra_pcie_power_off(pcie);
1338 return err;
1339 }
1340
1341 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1342 {
1343 struct device *dev = pcie->dev;
1344 int err;
1345
1346 if (pcie->irq > 0)
1347 free_irq(pcie->irq, pcie);
1348
1349 tegra_pcie_power_off(pcie);
1350
1351 err = phy_exit(pcie->phy);
1352 if (err < 0)
1353 dev_err(dev, "failed to teardown PHY: %d\n", err);
1354
1355 return 0;
1356 }
1357
1358 static int tegra_msi_alloc(struct tegra_msi *chip)
1359 {
1360 int msi;
1361
1362 mutex_lock(&chip->lock);
1363
1364 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1365 if (msi < INT_PCI_MSI_NR)
1366 set_bit(msi, chip->used);
1367 else
1368 msi = -ENOSPC;
1369
1370 mutex_unlock(&chip->lock);
1371
1372 return msi;
1373 }
1374
1375 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1376 {
1377 struct device *dev = chip->chip.dev;
1378
1379 mutex_lock(&chip->lock);
1380
1381 if (!test_bit(irq, chip->used))
1382 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1383 else
1384 clear_bit(irq, chip->used);
1385
1386 mutex_unlock(&chip->lock);
1387 }
1388
1389 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1390 {
1391 struct tegra_pcie *pcie = data;
1392 struct device *dev = pcie->dev;
1393 struct tegra_msi *msi = &pcie->msi;
1394 unsigned int i, processed = 0;
1395
1396 for (i = 0; i < 8; i++) {
1397 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1398
1399 while (reg) {
1400 unsigned int offset = find_first_bit(&reg, 32);
1401 unsigned int index = i * 32 + offset;
1402 unsigned int irq;
1403
1404 /* clear the interrupt */
1405 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1406
1407 irq = irq_find_mapping(msi->domain, index);
1408 if (irq) {
1409 if (test_bit(index, msi->used))
1410 generic_handle_irq(irq);
1411 else
1412 dev_info(dev, "unhandled MSI\n");
1413 } else {
1414 /*
1415 * that's weird who triggered this?
1416 * just clear it
1417 */
1418 dev_info(dev, "unexpected MSI\n");
1419 }
1420
1421 /* see if there's any more pending in this vector */
1422 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1423
1424 processed++;
1425 }
1426 }
1427
1428 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1429 }
1430
1431 static int tegra_msi_setup_irq(struct msi_controller *chip,
1432 struct pci_dev *pdev, struct msi_desc *desc)
1433 {
1434 struct tegra_msi *msi = to_tegra_msi(chip);
1435 struct msi_msg msg;
1436 unsigned int irq;
1437 int hwirq;
1438
1439 hwirq = tegra_msi_alloc(msi);
1440 if (hwirq < 0)
1441 return hwirq;
1442
1443 irq = irq_create_mapping(msi->domain, hwirq);
1444 if (!irq) {
1445 tegra_msi_free(msi, hwirq);
1446 return -EINVAL;
1447 }
1448
1449 irq_set_msi_desc(irq, desc);
1450
1451 msg.address_lo = virt_to_phys((void *)msi->pages);
1452 /* 32 bit address only */
1453 msg.address_hi = 0;
1454 msg.data = hwirq;
1455
1456 pci_write_msi_msg(irq, &msg);
1457
1458 return 0;
1459 }
1460
1461 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1462 unsigned int irq)
1463 {
1464 struct tegra_msi *msi = to_tegra_msi(chip);
1465 struct irq_data *d = irq_get_irq_data(irq);
1466 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1467
1468 irq_dispose_mapping(irq);
1469 tegra_msi_free(msi, hwirq);
1470 }
1471
1472 static struct irq_chip tegra_msi_irq_chip = {
1473 .name = "Tegra PCIe MSI",
1474 .irq_enable = pci_msi_unmask_irq,
1475 .irq_disable = pci_msi_mask_irq,
1476 .irq_mask = pci_msi_mask_irq,
1477 .irq_unmask = pci_msi_unmask_irq,
1478 };
1479
1480 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1481 irq_hw_number_t hwirq)
1482 {
1483 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1484 irq_set_chip_data(irq, domain->host_data);
1485
1486 tegra_cpuidle_pcie_irqs_in_use();
1487
1488 return 0;
1489 }
1490
1491 static const struct irq_domain_ops msi_domain_ops = {
1492 .map = tegra_msi_map,
1493 };
1494
1495 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1496 {
1497 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1498 struct platform_device *pdev = to_platform_device(pcie->dev);
1499 const struct tegra_pcie_soc *soc = pcie->soc;
1500 struct tegra_msi *msi = &pcie->msi;
1501 struct device *dev = pcie->dev;
1502 unsigned long base;
1503 int err;
1504 u32 reg;
1505
1506 mutex_init(&msi->lock);
1507
1508 msi->chip.dev = dev;
1509 msi->chip.setup_irq = tegra_msi_setup_irq;
1510 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1511
1512 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
1513 &msi_domain_ops, &msi->chip);
1514 if (!msi->domain) {
1515 dev_err(dev, "failed to create IRQ domain\n");
1516 return -ENOMEM;
1517 }
1518
1519 err = platform_get_irq_byname(pdev, "msi");
1520 if (err < 0) {
1521 dev_err(dev, "failed to get IRQ: %d\n", err);
1522 goto err;
1523 }
1524
1525 msi->irq = err;
1526
1527 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
1528 tegra_msi_irq_chip.name, pcie);
1529 if (err < 0) {
1530 dev_err(dev, "failed to request IRQ: %d\n", err);
1531 goto err;
1532 }
1533
1534 /* setup AFI/FPCI range */
1535 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1536 base = virt_to_phys((void *)msi->pages);
1537
1538 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1539 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1540 /* this register is in 4K increments */
1541 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1542
1543 /* enable all MSI vectors */
1544 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1545 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1546 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1547 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1548 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1549 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1550 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1551 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1552
1553 /* and unmask the MSI interrupt */
1554 reg = afi_readl(pcie, AFI_INTR_MASK);
1555 reg |= AFI_INTR_MASK_MSI_MASK;
1556 afi_writel(pcie, reg, AFI_INTR_MASK);
1557
1558 host->msi = &msi->chip;
1559
1560 return 0;
1561
1562 err:
1563 irq_domain_remove(msi->domain);
1564 return err;
1565 }
1566
1567 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1568 {
1569 struct tegra_msi *msi = &pcie->msi;
1570 unsigned int i, irq;
1571 u32 value;
1572
1573 /* mask the MSI interrupt */
1574 value = afi_readl(pcie, AFI_INTR_MASK);
1575 value &= ~AFI_INTR_MASK_MSI_MASK;
1576 afi_writel(pcie, value, AFI_INTR_MASK);
1577
1578 /* disable all MSI vectors */
1579 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1580 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1581 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1582 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1583 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1584 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1585 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1586 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1587
1588 free_pages(msi->pages, 0);
1589
1590 if (msi->irq > 0)
1591 free_irq(msi->irq, pcie);
1592
1593 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1594 irq = irq_find_mapping(msi->domain, i);
1595 if (irq > 0)
1596 irq_dispose_mapping(irq);
1597 }
1598
1599 irq_domain_remove(msi->domain);
1600
1601 return 0;
1602 }
1603
1604 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1605 u32 *xbar)
1606 {
1607 struct device *dev = pcie->dev;
1608 struct device_node *np = dev->of_node;
1609
1610 if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
1611 of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1612 switch (lanes) {
1613 case 0x0000104:
1614 dev_info(dev, "4x1, 1x1 configuration\n");
1615 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1616 return 0;
1617
1618 case 0x0000102:
1619 dev_info(dev, "2x1, 1x1 configuration\n");
1620 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1621 return 0;
1622 }
1623 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1624 switch (lanes) {
1625 case 0x00000204:
1626 dev_info(dev, "4x1, 2x1 configuration\n");
1627 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1628 return 0;
1629
1630 case 0x00020202:
1631 dev_info(dev, "2x3 configuration\n");
1632 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1633 return 0;
1634
1635 case 0x00010104:
1636 dev_info(dev, "4x1, 1x2 configuration\n");
1637 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1638 return 0;
1639 }
1640 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1641 switch (lanes) {
1642 case 0x00000004:
1643 dev_info(dev, "single-mode configuration\n");
1644 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1645 return 0;
1646
1647 case 0x00000202:
1648 dev_info(dev, "dual-mode configuration\n");
1649 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1650 return 0;
1651 }
1652 }
1653
1654 return -EINVAL;
1655 }
1656
1657 /*
1658 * Check whether a given set of supplies is available in a device tree node.
1659 * This is used to check whether the new or the legacy device tree bindings
1660 * should be used.
1661 */
1662 static bool of_regulator_bulk_available(struct device_node *np,
1663 struct regulator_bulk_data *supplies,
1664 unsigned int num_supplies)
1665 {
1666 char property[32];
1667 unsigned int i;
1668
1669 for (i = 0; i < num_supplies; i++) {
1670 snprintf(property, 32, "%s-supply", supplies[i].supply);
1671
1672 if (of_find_property(np, property, NULL) == NULL)
1673 return false;
1674 }
1675
1676 return true;
1677 }
1678
1679 /*
1680 * Old versions of the device tree binding for this device used a set of power
1681 * supplies that didn't match the hardware inputs. This happened to work for a
1682 * number of cases but is not future proof. However to preserve backwards-
1683 * compatibility with old device trees, this function will try to use the old
1684 * set of supplies.
1685 */
1686 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1687 {
1688 struct device *dev = pcie->dev;
1689 struct device_node *np = dev->of_node;
1690
1691 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1692 pcie->num_supplies = 3;
1693 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1694 pcie->num_supplies = 2;
1695
1696 if (pcie->num_supplies == 0) {
1697 dev_err(dev, "device %s not supported in legacy mode\n",
1698 np->full_name);
1699 return -ENODEV;
1700 }
1701
1702 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1703 sizeof(*pcie->supplies),
1704 GFP_KERNEL);
1705 if (!pcie->supplies)
1706 return -ENOMEM;
1707
1708 pcie->supplies[0].supply = "pex-clk";
1709 pcie->supplies[1].supply = "vdd";
1710
1711 if (pcie->num_supplies > 2)
1712 pcie->supplies[2].supply = "avdd";
1713
1714 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies);
1715 }
1716
1717 /*
1718 * Obtains the list of regulators required for a particular generation of the
1719 * IP block.
1720 *
1721 * This would've been nice to do simply by providing static tables for use
1722 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1723 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1724 * and either seems to be optional depending on which ports are being used.
1725 */
1726 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1727 {
1728 struct device *dev = pcie->dev;
1729 struct device_node *np = dev->of_node;
1730 unsigned int i = 0;
1731
1732 if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1733 pcie->num_supplies = 6;
1734
1735 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1736 sizeof(*pcie->supplies),
1737 GFP_KERNEL);
1738 if (!pcie->supplies)
1739 return -ENOMEM;
1740
1741 pcie->supplies[i++].supply = "avdd-pll-uerefe";
1742 pcie->supplies[i++].supply = "hvddio-pex";
1743 pcie->supplies[i++].supply = "dvddio-pex";
1744 pcie->supplies[i++].supply = "dvdd-pex-pll";
1745 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1746 pcie->supplies[i++].supply = "vddio-pex-ctl";
1747 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1748 pcie->num_supplies = 7;
1749
1750 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1751 sizeof(*pcie->supplies),
1752 GFP_KERNEL);
1753 if (!pcie->supplies)
1754 return -ENOMEM;
1755
1756 pcie->supplies[i++].supply = "avddio-pex";
1757 pcie->supplies[i++].supply = "dvddio-pex";
1758 pcie->supplies[i++].supply = "avdd-pex-pll";
1759 pcie->supplies[i++].supply = "hvdd-pex";
1760 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1761 pcie->supplies[i++].supply = "vddio-pex-ctl";
1762 pcie->supplies[i++].supply = "avdd-pll-erefe";
1763 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1764 bool need_pexa = false, need_pexb = false;
1765
1766 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1767 if (lane_mask & 0x0f)
1768 need_pexa = true;
1769
1770 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1771 if (lane_mask & 0x30)
1772 need_pexb = true;
1773
1774 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1775 (need_pexb ? 2 : 0);
1776
1777 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1778 sizeof(*pcie->supplies),
1779 GFP_KERNEL);
1780 if (!pcie->supplies)
1781 return -ENOMEM;
1782
1783 pcie->supplies[i++].supply = "avdd-pex-pll";
1784 pcie->supplies[i++].supply = "hvdd-pex";
1785 pcie->supplies[i++].supply = "vddio-pex-ctl";
1786 pcie->supplies[i++].supply = "avdd-plle";
1787
1788 if (need_pexa) {
1789 pcie->supplies[i++].supply = "avdd-pexa";
1790 pcie->supplies[i++].supply = "vdd-pexa";
1791 }
1792
1793 if (need_pexb) {
1794 pcie->supplies[i++].supply = "avdd-pexb";
1795 pcie->supplies[i++].supply = "vdd-pexb";
1796 }
1797 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1798 pcie->num_supplies = 5;
1799
1800 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1801 sizeof(*pcie->supplies),
1802 GFP_KERNEL);
1803 if (!pcie->supplies)
1804 return -ENOMEM;
1805
1806 pcie->supplies[0].supply = "avdd-pex";
1807 pcie->supplies[1].supply = "vdd-pex";
1808 pcie->supplies[2].supply = "avdd-pex-pll";
1809 pcie->supplies[3].supply = "avdd-plle";
1810 pcie->supplies[4].supply = "vddio-pex-clk";
1811 }
1812
1813 if (of_regulator_bulk_available(dev->of_node, pcie->supplies,
1814 pcie->num_supplies))
1815 return devm_regulator_bulk_get(dev, pcie->num_supplies,
1816 pcie->supplies);
1817
1818 /*
1819 * If not all regulators are available for this new scheme, assume
1820 * that the device tree complies with an older version of the device
1821 * tree binding.
1822 */
1823 dev_info(dev, "using legacy DT binding for power supplies\n");
1824
1825 devm_kfree(dev, pcie->supplies);
1826 pcie->num_supplies = 0;
1827
1828 return tegra_pcie_get_legacy_regulators(pcie);
1829 }
1830
1831 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1832 {
1833 struct device *dev = pcie->dev;
1834 struct device_node *np = dev->of_node, *port;
1835 const struct tegra_pcie_soc *soc = pcie->soc;
1836 struct of_pci_range_parser parser;
1837 struct of_pci_range range;
1838 u32 lanes = 0, mask = 0;
1839 unsigned int lane = 0;
1840 struct resource res;
1841 int err;
1842
1843 if (of_pci_range_parser_init(&parser, np)) {
1844 dev_err(dev, "missing \"ranges\" property\n");
1845 return -EINVAL;
1846 }
1847
1848 for_each_of_pci_range(&parser, &range) {
1849 err = of_pci_range_to_resource(&range, np, &res);
1850 if (err < 0)
1851 return err;
1852
1853 switch (res.flags & IORESOURCE_TYPE_BITS) {
1854 case IORESOURCE_IO:
1855 /* Track the bus -> CPU I/O mapping offset. */
1856 pcie->offset.io = res.start - range.pci_addr;
1857
1858 memcpy(&pcie->pio, &res, sizeof(res));
1859 pcie->pio.name = np->full_name;
1860
1861 /*
1862 * The Tegra PCIe host bridge uses this to program the
1863 * mapping of the I/O space to the physical address,
1864 * so we override the .start and .end fields here that
1865 * of_pci_range_to_resource() converted to I/O space.
1866 * We also set the IORESOURCE_MEM type to clarify that
1867 * the resource is in the physical memory space.
1868 */
1869 pcie->io.start = range.cpu_addr;
1870 pcie->io.end = range.cpu_addr + range.size - 1;
1871 pcie->io.flags = IORESOURCE_MEM;
1872 pcie->io.name = "I/O";
1873
1874 memcpy(&res, &pcie->io, sizeof(res));
1875 break;
1876
1877 case IORESOURCE_MEM:
1878 /*
1879 * Track the bus -> CPU memory mapping offset. This
1880 * assumes that the prefetchable and non-prefetchable
1881 * regions will be the last of type IORESOURCE_MEM in
1882 * the ranges property.
1883 * */
1884 pcie->offset.mem = res.start - range.pci_addr;
1885
1886 if (res.flags & IORESOURCE_PREFETCH) {
1887 memcpy(&pcie->prefetch, &res, sizeof(res));
1888 pcie->prefetch.name = "prefetchable";
1889 } else {
1890 memcpy(&pcie->mem, &res, sizeof(res));
1891 pcie->mem.name = "non-prefetchable";
1892 }
1893 break;
1894 }
1895 }
1896
1897 err = of_pci_parse_bus_range(np, &pcie->busn);
1898 if (err < 0) {
1899 dev_err(dev, "failed to parse ranges property: %d\n", err);
1900 pcie->busn.name = np->name;
1901 pcie->busn.start = 0;
1902 pcie->busn.end = 0xff;
1903 pcie->busn.flags = IORESOURCE_BUS;
1904 }
1905
1906 /* parse root ports */
1907 for_each_child_of_node(np, port) {
1908 struct tegra_pcie_port *rp;
1909 unsigned int index;
1910 u32 value;
1911
1912 err = of_pci_get_devfn(port);
1913 if (err < 0) {
1914 dev_err(dev, "failed to parse address: %d\n", err);
1915 return err;
1916 }
1917
1918 index = PCI_SLOT(err);
1919
1920 if (index < 1 || index > soc->num_ports) {
1921 dev_err(dev, "invalid port number: %d\n", index);
1922 return -EINVAL;
1923 }
1924
1925 index--;
1926
1927 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1928 if (err < 0) {
1929 dev_err(dev, "failed to parse # of lanes: %d\n",
1930 err);
1931 return err;
1932 }
1933
1934 if (value > 16) {
1935 dev_err(dev, "invalid # of lanes: %u\n", value);
1936 return -EINVAL;
1937 }
1938
1939 lanes |= value << (index << 3);
1940
1941 if (!of_device_is_available(port)) {
1942 lane += value;
1943 continue;
1944 }
1945
1946 mask |= ((1 << value) - 1) << lane;
1947 lane += value;
1948
1949 rp = devm_kzalloc(dev, sizeof(*rp), GFP_KERNEL);
1950 if (!rp)
1951 return -ENOMEM;
1952
1953 err = of_address_to_resource(port, 0, &rp->regs);
1954 if (err < 0) {
1955 dev_err(dev, "failed to parse address: %d\n", err);
1956 return err;
1957 }
1958
1959 INIT_LIST_HEAD(&rp->list);
1960 rp->index = index;
1961 rp->lanes = value;
1962 rp->pcie = pcie;
1963 rp->np = port;
1964
1965 rp->base = devm_ioremap_resource(dev, &rp->regs);
1966 if (IS_ERR(rp->base))
1967 return PTR_ERR(rp->base);
1968
1969 list_add_tail(&rp->list, &pcie->ports);
1970 }
1971
1972 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1973 if (err < 0) {
1974 dev_err(dev, "invalid lane configuration\n");
1975 return err;
1976 }
1977
1978 err = tegra_pcie_get_regulators(pcie, mask);
1979 if (err < 0)
1980 return err;
1981
1982 return 0;
1983 }
1984
1985 /*
1986 * FIXME: If there are no PCIe cards attached, then calling this function
1987 * can result in the increase of the bootup time as there are big timeout
1988 * loops.
1989 */
1990 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1991 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1992 {
1993 struct device *dev = port->pcie->dev;
1994 unsigned int retries = 3;
1995 unsigned long value;
1996
1997 /* override presence detection */
1998 value = readl(port->base + RP_PRIV_MISC);
1999 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
2000 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
2001 writel(value, port->base + RP_PRIV_MISC);
2002
2003 do {
2004 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2005
2006 do {
2007 value = readl(port->base + RP_VEND_XP);
2008
2009 if (value & RP_VEND_XP_DL_UP)
2010 break;
2011
2012 usleep_range(1000, 2000);
2013 } while (--timeout);
2014
2015 if (!timeout) {
2016 dev_err(dev, "link %u down, retrying\n", port->index);
2017 goto retry;
2018 }
2019
2020 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2021
2022 do {
2023 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2024
2025 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2026 return true;
2027
2028 usleep_range(1000, 2000);
2029 } while (--timeout);
2030
2031 retry:
2032 tegra_pcie_port_reset(port);
2033 } while (--retries);
2034
2035 return false;
2036 }
2037
2038 static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
2039 {
2040 struct device *dev = pcie->dev;
2041 struct tegra_pcie_port *port, *tmp;
2042
2043 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2044 dev_info(dev, "probing port %u, using %u lanes\n",
2045 port->index, port->lanes);
2046
2047 tegra_pcie_port_enable(port);
2048
2049 if (tegra_pcie_port_check_link(port))
2050 continue;
2051
2052 dev_info(dev, "link %u down, ignoring\n", port->index);
2053
2054 tegra_pcie_port_disable(port);
2055 tegra_pcie_port_free(port);
2056 }
2057 }
2058
2059 static const struct tegra_pcie_soc tegra20_pcie = {
2060 .num_ports = 2,
2061 .msi_base_shift = 0,
2062 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
2063 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
2064 .pads_refclk_cfg0 = 0xfa5cfa5c,
2065 .has_pex_clkreq_en = false,
2066 .has_pex_bias_ctrl = false,
2067 .has_intr_prsnt_sense = false,
2068 .has_cml_clk = false,
2069 .has_gen2 = false,
2070 .force_pca_enable = false,
2071 };
2072
2073 static const struct tegra_pcie_soc tegra30_pcie = {
2074 .num_ports = 3,
2075 .msi_base_shift = 8,
2076 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2077 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2078 .pads_refclk_cfg0 = 0xfa5cfa5c,
2079 .pads_refclk_cfg1 = 0xfa5cfa5c,
2080 .has_pex_clkreq_en = true,
2081 .has_pex_bias_ctrl = true,
2082 .has_intr_prsnt_sense = true,
2083 .has_cml_clk = true,
2084 .has_gen2 = false,
2085 .force_pca_enable = false,
2086 };
2087
2088 static const struct tegra_pcie_soc tegra124_pcie = {
2089 .num_ports = 2,
2090 .msi_base_shift = 8,
2091 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2092 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2093 .pads_refclk_cfg0 = 0x44ac44ac,
2094 .has_pex_clkreq_en = true,
2095 .has_pex_bias_ctrl = true,
2096 .has_intr_prsnt_sense = true,
2097 .has_cml_clk = true,
2098 .has_gen2 = true,
2099 .force_pca_enable = false,
2100 };
2101
2102 static const struct tegra_pcie_soc tegra210_pcie = {
2103 .num_ports = 2,
2104 .msi_base_shift = 8,
2105 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2106 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2107 .pads_refclk_cfg0 = 0x90b890b8,
2108 .has_pex_clkreq_en = true,
2109 .has_pex_bias_ctrl = true,
2110 .has_intr_prsnt_sense = true,
2111 .has_cml_clk = true,
2112 .has_gen2 = true,
2113 .force_pca_enable = true,
2114 };
2115
2116 static const struct of_device_id tegra_pcie_of_match[] = {
2117 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2118 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2119 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2120 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2121 { },
2122 };
2123
2124 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
2125 {
2126 struct tegra_pcie *pcie = s->private;
2127
2128 if (list_empty(&pcie->ports))
2129 return NULL;
2130
2131 seq_printf(s, "Index Status\n");
2132
2133 return seq_list_start(&pcie->ports, *pos);
2134 }
2135
2136 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
2137 {
2138 struct tegra_pcie *pcie = s->private;
2139
2140 return seq_list_next(v, &pcie->ports, pos);
2141 }
2142
2143 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
2144 {
2145 }
2146
2147 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
2148 {
2149 bool up = false, active = false;
2150 struct tegra_pcie_port *port;
2151 unsigned int value;
2152
2153 port = list_entry(v, struct tegra_pcie_port, list);
2154
2155 value = readl(port->base + RP_VEND_XP);
2156
2157 if (value & RP_VEND_XP_DL_UP)
2158 up = true;
2159
2160 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2161
2162 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2163 active = true;
2164
2165 seq_printf(s, "%2u ", port->index);
2166
2167 if (up)
2168 seq_printf(s, "up");
2169
2170 if (active) {
2171 if (up)
2172 seq_printf(s, ", ");
2173
2174 seq_printf(s, "active");
2175 }
2176
2177 seq_printf(s, "\n");
2178 return 0;
2179 }
2180
2181 static const struct seq_operations tegra_pcie_ports_seq_ops = {
2182 .start = tegra_pcie_ports_seq_start,
2183 .next = tegra_pcie_ports_seq_next,
2184 .stop = tegra_pcie_ports_seq_stop,
2185 .show = tegra_pcie_ports_seq_show,
2186 };
2187
2188 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
2189 {
2190 struct tegra_pcie *pcie = inode->i_private;
2191 struct seq_file *s;
2192 int err;
2193
2194 err = seq_open(file, &tegra_pcie_ports_seq_ops);
2195 if (err)
2196 return err;
2197
2198 s = file->private_data;
2199 s->private = pcie;
2200
2201 return 0;
2202 }
2203
2204 static const struct file_operations tegra_pcie_ports_ops = {
2205 .owner = THIS_MODULE,
2206 .open = tegra_pcie_ports_open,
2207 .read = seq_read,
2208 .llseek = seq_lseek,
2209 .release = seq_release,
2210 };
2211
2212 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2213 {
2214 struct dentry *file;
2215
2216 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2217 if (!pcie->debugfs)
2218 return -ENOMEM;
2219
2220 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
2221 pcie, &tegra_pcie_ports_ops);
2222 if (!file)
2223 goto remove;
2224
2225 return 0;
2226
2227 remove:
2228 debugfs_remove_recursive(pcie->debugfs);
2229 pcie->debugfs = NULL;
2230 return -ENOMEM;
2231 }
2232
2233 static int tegra_pcie_probe(struct platform_device *pdev)
2234 {
2235 struct device *dev = &pdev->dev;
2236 struct pci_host_bridge *host;
2237 struct tegra_pcie *pcie;
2238 struct pci_bus *child;
2239 int err;
2240
2241 host = pci_alloc_host_bridge(sizeof(*pcie));
2242 if (!host)
2243 return -ENOMEM;
2244
2245 pcie = pci_host_bridge_priv(host);
2246
2247 pcie->soc = of_device_get_match_data(dev);
2248 INIT_LIST_HEAD(&pcie->buses);
2249 INIT_LIST_HEAD(&pcie->ports);
2250 pcie->dev = dev;
2251
2252 err = tegra_pcie_parse_dt(pcie);
2253 if (err < 0)
2254 return err;
2255
2256 err = tegra_pcie_get_resources(pcie);
2257 if (err < 0) {
2258 dev_err(dev, "failed to request resources: %d\n", err);
2259 return err;
2260 }
2261
2262 err = tegra_pcie_enable_controller(pcie);
2263 if (err)
2264 goto put_resources;
2265
2266 err = tegra_pcie_request_resources(pcie);
2267 if (err)
2268 goto put_resources;
2269
2270 /* setup the AFI address translations */
2271 tegra_pcie_setup_translations(pcie);
2272
2273 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2274 err = tegra_pcie_enable_msi(pcie);
2275 if (err < 0) {
2276 dev_err(dev, "failed to enable MSI support: %d\n", err);
2277 goto put_resources;
2278 }
2279 }
2280
2281 tegra_pcie_enable_ports(pcie);
2282
2283 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
2284 host->busnr = pcie->busn.start;
2285 host->dev.parent = &pdev->dev;
2286 host->ops = &tegra_pcie_ops;
2287
2288 err = pci_register_host_bridge(host);
2289 if (err < 0) {
2290 dev_err(dev, "failed to register host: %d\n", err);
2291 goto disable_msi;
2292 }
2293
2294 pci_scan_child_bus(host->bus);
2295
2296 pci_fixup_irqs(pci_common_swizzle, tegra_pcie_map_irq);
2297 pci_bus_size_bridges(host->bus);
2298 pci_bus_assign_resources(host->bus);
2299
2300 list_for_each_entry(child, &host->bus->children, node)
2301 pcie_bus_configure_settings(child);
2302
2303 pci_bus_add_devices(host->bus);
2304
2305 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2306 err = tegra_pcie_debugfs_init(pcie);
2307 if (err < 0)
2308 dev_err(dev, "failed to setup debugfs: %d\n", err);
2309 }
2310
2311 return 0;
2312
2313 disable_msi:
2314 if (IS_ENABLED(CONFIG_PCI_MSI))
2315 tegra_pcie_disable_msi(pcie);
2316 put_resources:
2317 tegra_pcie_put_resources(pcie);
2318 return err;
2319 }
2320
2321 static struct platform_driver tegra_pcie_driver = {
2322 .driver = {
2323 .name = "tegra-pcie",
2324 .of_match_table = tegra_pcie_of_match,
2325 .suppress_bind_attrs = true,
2326 },
2327 .probe = tegra_pcie_probe,
2328 };
2329 builtin_platform_driver(tegra_pcie_driver);
Linux with added FPC-III support