drivers/pci/host/pci-thunder-pem.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  13  *
  14  * Copyright (C) 2015 - 2016 Cavium, Inc.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci-acpi.h>
  22 #include <linux/pci-ecam.h>
  23 #include <linux/platform_device.h>
  24 #include "../pci.h"
  25
  26 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  27
  28 #define PEM_CFG_WR 0x28
  29 #define PEM_CFG_RD 0x30
  30
  31 struct thunder_pem_pci {
  32         u32             ea_entry[3];
  33         void __iomem    *pem_reg_base;
  34 };
  35
  36 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
  37                                    int where, int size, u32 *val)
  38 {
  39         u64 read_val;
  40         struct pci_config_window *cfg = bus->sysdata;
  41         struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
  42
  43         if (devfn != 0 || where >= 2048) {
  44                 *val = ~0;
  45                 return PCIBIOS_DEVICE_NOT_FOUND;
  46         }
  47
  48         /*
  49          * 32-bit accesses only.  Write the address to the low order
  50          * bits of PEM_CFG_RD, then trigger the read by reading back.
  51          * The config data lands in the upper 32-bits of PEM_CFG_RD.
  52          */
  53         read_val = where & ~3ull;
  54         writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
  55         read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
  56         read_val >>= 32;
  57
  58         /*
  59          * The config space contains some garbage, fix it up.  Also
  60          * synthesize an EA capability for the BAR used by MSI-X.
  61          */
  62         switch (where & ~3) {
  63         case 0x40:
  64                 read_val &= 0xffff00ff;
  65                 read_val |= 0x00007000; /* Skip MSI CAP */
  66                 break;
  67         case 0x70: /* Express Cap */
  68                 /* PME interrupt on vector 2*/
  69                 read_val |= (2u << 25);
  70                 break;
  71         case 0xb0: /* MSI-X Cap */
  72                 /* TableSize=4, Next Cap is EA */
  73                 read_val &= 0xc00000ff;
  74                 read_val |= 0x0003bc00;
  75                 break;
  76         case 0xb4:
  77                 /* Table offset=0, BIR=0 */
  78                 read_val = 0x00000000;
  79                 break;
  80         case 0xb8:
  81                 /* BPA offset=0xf0000, BIR=0 */
  82                 read_val = 0x000f0000;
  83                 break;
  84         case 0xbc:
  85                 /* EA, 1 entry, no next Cap */
  86                 read_val = 0x00010014;
  87                 break;
  88         case 0xc0:
  89                 /* DW2 for type-1 */
  90                 read_val = 0x00000000;
  91                 break;
  92         case 0xc4:
  93                 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
  94                 read_val = 0x80ff0003;
  95                 break;
  96         case 0xc8:
  97                 read_val = pem_pci->ea_entry[0];
  98                 break;
  99         case 0xcc:
 100                 read_val = pem_pci->ea_entry[1];
 101                 break;
 102         case 0xd0:
 103                 read_val = pem_pci->ea_entry[2];
 104                 break;
 105         default:
 106                 break;
 107         }
 108         read_val >>= (8 * (where & 3));
 109         switch (size) {
 110         case 1:
 111                 read_val &= 0xff;
 112                 break;
 113         case 2:
 114                 read_val &= 0xffff;
 115                 break;
 116         default:
 117                 break;
 118         }
 119         *val = read_val;
 120         return PCIBIOS_SUCCESSFUL;
 121 }
 122
 123 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
 124                                    int where, int size, u32 *val)
 125 {
 126         struct pci_config_window *cfg = bus->sysdata;
 127
 128         if (bus->number < cfg->busr.start ||
 129             bus->number > cfg->busr.end)
 130                 return PCIBIOS_DEVICE_NOT_FOUND;
 131
 132         /*
 133          * The first device on the bus is the PEM PCIe bridge.
 134          * Special case its config access.
 135          */
 136         if (bus->number == cfg->busr.start)
 137                 return thunder_pem_bridge_read(bus, devfn, where, size, val);
 138
 139         return pci_generic_config_read(bus, devfn, where, size, val);
 140 }
 141
 142 /*
 143  * Some of the w1c_bits below also include read-only or non-writable
 144  * reserved bits, this makes the code simpler and is OK as the bits
 145  * are not affected by writing zeros to them.
 146  */
 147 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
 148 {
 149         u32 w1c_bits = 0;
 150
 151         switch (where_aligned) {
 152         case 0x04: /* Command/Status */
 153         case 0x1c: /* Base and I/O Limit/Secondary Status */
 154                 w1c_bits = 0xff000000;
 155                 break;
 156         case 0x44: /* Power Management Control and Status */
 157                 w1c_bits = 0xfffffe00;
 158                 break;
 159         case 0x78: /* Device Control/Device Status */
 160         case 0x80: /* Link Control/Link Status */
 161         case 0x88: /* Slot Control/Slot Status */
 162         case 0x90: /* Root Status */
 163         case 0xa0: /* Link Control 2 Registers/Link Status 2 */
 164                 w1c_bits = 0xffff0000;
 165                 break;
 166         case 0x104: /* Uncorrectable Error Status */
 167         case 0x110: /* Correctable Error Status */
 168         case 0x130: /* Error Status */
 169         case 0x160: /* Link Control 4 */
 170                 w1c_bits = 0xffffffff;
 171                 break;
 172         default:
 173                 break;
 174         }
 175         return w1c_bits;
 176 }
 177
 178 /* Some bits must be written to one so they appear to be read-only. */
 179 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
 180 {
 181         u32 w1_bits;
 182
 183         switch (where_aligned) {
 184         case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
 185                 /* Force 32-bit I/O addressing. */
 186                 w1_bits = 0x0101;
 187                 break;
 188         case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
 189                 /* Force 64-bit addressing */
 190                 w1_bits = 0x00010001;
 191                 break;
 192         default:
 193                 w1_bits = 0;
 194                 break;
 195         }
 196         return w1_bits;
 197 }
 198
 199 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
 200                                     int where, int size, u32 val)
 201 {
 202         struct pci_config_window *cfg = bus->sysdata;
 203         struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
 204         u64 write_val, read_val;
 205         u64 where_aligned = where & ~3ull;
 206         u32 mask = 0;
 207
 208
 209         if (devfn != 0 || where >= 2048)
 210                 return PCIBIOS_DEVICE_NOT_FOUND;
 211
 212         /*
 213          * 32-bit accesses only.  If the write is for a size smaller
 214          * than 32-bits, we must first read the 32-bit value and merge
 215          * in the desired bits and then write the whole 32-bits back
 216          * out.
 217          */
 218         switch (size) {
 219         case 1:
 220                 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
 221                 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 222                 read_val >>= 32;
 223                 mask = ~(0xff << (8 * (where & 3)));
 224                 read_val &= mask;
 225                 val = (val & 0xff) << (8 * (where & 3));
 226                 val |= (u32)read_val;
 227                 break;
 228         case 2:
 229                 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
 230                 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 231                 read_val >>= 32;
 232                 mask = ~(0xffff << (8 * (where & 3)));
 233                 read_val &= mask;
 234                 val = (val & 0xffff) << (8 * (where & 3));
 235                 val |= (u32)read_val;
 236                 break;
 237         default:
 238                 break;
 239         }
 240
 241         /*
 242          * By expanding the write width to 32 bits, we may
 243          * inadvertently hit some W1C bits that were not intended to
 244          * be written.  Calculate the mask that must be applied to the
 245          * data to be written to avoid these cases.
 246          */
 247         if (mask) {
 248                 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
 249
 250                 if (w1c_bits) {
 251                         mask &= w1c_bits;
 252                         val &= ~mask;
 253                 }
 254         }
 255
 256         /*
 257          * Some bits must be read-only with value of one.  Since the
 258          * access method allows these to be cleared if a zero is
 259          * written, force them to one before writing.
 260          */
 261         val |= thunder_pem_bridge_w1_bits(where_aligned);
 262
 263         /*
 264          * Low order bits are the config address, the high order 32
 265          * bits are the data to be written.
 266          */
 267         write_val = (((u64)val) << 32) | where_aligned;
 268         writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
 269         return PCIBIOS_SUCCESSFUL;
 270 }
 271
 272 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
 273                                     int where, int size, u32 val)
 274 {
 275         struct pci_config_window *cfg = bus->sysdata;
 276
 277         if (bus->number < cfg->busr.start ||
 278             bus->number > cfg->busr.end)
 279                 return PCIBIOS_DEVICE_NOT_FOUND;
 280         /*
 281          * The first device on the bus is the PEM PCIe bridge.
 282          * Special case its config access.
 283          */
 284         if (bus->number == cfg->busr.start)
 285                 return thunder_pem_bridge_write(bus, devfn, where, size, val);
 286
 287
 288         return pci_generic_config_write(bus, devfn, where, size, val);
 289 }
 290
 291 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
 292                             struct resource *res_pem)
 293 {
 294         struct thunder_pem_pci *pem_pci;
 295         resource_size_t bar4_start;
 296
 297         pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
 298         if (!pem_pci)
 299                 return -ENOMEM;
 300
 301         pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
 302         if (!pem_pci->pem_reg_base)
 303                 return -ENOMEM;
 304
 305         /*
 306          * The MSI-X BAR for the PEM and AER interrupts is located at
 307          * a fixed offset from the PEM register base.  Generate a
 308          * fragment of the synthesized Enhanced Allocation capability
 309          * structure here for the BAR.
 310          */
 311         bar4_start = res_pem->start + 0xf00000;
 312         pem_pci->ea_entry[0] = (u32)bar4_start | 2;
 313         pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u;
 314         pem_pci->ea_entry[2] = (u32)(bar4_start >> 32);
 315
 316         cfg->priv = pem_pci;
 317         return 0;
 318 }
 319
 320 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
 321
 322 static int thunder_pem_acpi_init(struct pci_config_window *cfg)
 323 {
 324         struct device *dev = cfg->parent;
 325         struct acpi_device *adev = to_acpi_device(dev);
 326         struct acpi_pci_root *root = acpi_driver_data(adev);
 327         struct resource *res_pem;
 328         int ret;
 329
 330         res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
 331         if (!res_pem)
 332                 return -ENOMEM;
 333
 334         ret = acpi_get_rc_resources(dev, "THRX0002", root->segment, res_pem);
 335         if (ret) {
 336                 dev_err(dev, "can't get rc base address\n");
 337                 return ret;
 338         }
 339
 340         return thunder_pem_init(dev, cfg, res_pem);
 341 }
 342
 343 struct pci_ecam_ops thunder_pem_ecam_ops = {
 344         .bus_shift      = 24,
 345         .init           = thunder_pem_acpi_init,
 346         .pci_ops        = {
 347                 .map_bus        = pci_ecam_map_bus,
 348                 .read           = thunder_pem_config_read,
 349                 .write          = thunder_pem_config_write,
 350         }
 351 };
 352
 353 #endif
 354
 355 #ifdef CONFIG_PCI_HOST_THUNDER_PEM
 356
 357 static int thunder_pem_platform_init(struct pci_config_window *cfg)
 358 {
 359         struct device *dev = cfg->parent;
 360         struct platform_device *pdev = to_platform_device(dev);
 361         struct resource *res_pem;
 362
 363         if (!dev->of_node)
 364                 return -EINVAL;
 365
 366         /*
 367          * The second register range is the PEM bridge to the PCIe
 368          * bus.  It has a different config access method than those
 369          * devices behind the bridge.
 370          */
 371         res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 372         if (!res_pem) {
 373                 dev_err(dev, "missing \"reg[1]\"property\n");
 374                 return -EINVAL;
 375         }
 376
 377         return thunder_pem_init(dev, cfg, res_pem);
 378 }
 379
 380 static struct pci_ecam_ops pci_thunder_pem_ops = {
 381         .bus_shift      = 24,
 382         .init           = thunder_pem_platform_init,
 383         .pci_ops        = {
 384                 .map_bus        = pci_ecam_map_bus,
 385                 .read           = thunder_pem_config_read,
 386                 .write          = thunder_pem_config_write,
 387         }
 388 };
 389
 390 static const struct of_device_id thunder_pem_of_match[] = {
 391         { .compatible = "cavium,pci-host-thunder-pem" },
 392         { },
 393 };
 394
 395 static int thunder_pem_probe(struct platform_device *pdev)
 396 {
 397         return pci_host_common_probe(pdev, &pci_thunder_pem_ops);
 398 }
 399
 400 static struct platform_driver thunder_pem_driver = {
 401         .driver = {
 402                 .name = KBUILD_MODNAME,
 403                 .of_match_table = thunder_pem_of_match,
 404         },
 405         .probe = thunder_pem_probe,
 406 };
 407 builtin_platform_driver(thunder_pem_driver);
 408
 409 #endif
 410 #endif