drivers/pci/host/pcie-altera.c

   1 /*
   2  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
   3  *
   4  * Author: Ley Foon Tan <lftan@altera.com>
   5  * Description: Altera PCIe host controller driver
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/init.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/pci.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30
  31 #define RP_TX_REG0                      0x2000
  32 #define RP_TX_REG1                      0x2004
  33 #define RP_TX_CNTRL                     0x2008
  34 #define RP_TX_EOP                       0x2
  35 #define RP_TX_SOP                       0x1
  36 #define RP_RXCPL_STATUS                 0x2010
  37 #define RP_RXCPL_EOP                    0x2
  38 #define RP_RXCPL_SOP                    0x1
  39 #define RP_RXCPL_REG0                   0x2014
  40 #define RP_RXCPL_REG1                   0x2018
  41 #define P2A_INT_STATUS                  0x3060
  42 #define P2A_INT_STS_ALL                 0xf
  43 #define P2A_INT_ENABLE                  0x3070
  44 #define P2A_INT_ENA_ALL                 0xf
  45 #define RP_LTSSM                        0x3c64
  46 #define RP_LTSSM_MASK                   0x1f
  47 #define LTSSM_L0                        0xf
  48
  49 #define PCIE_CAP_OFFSET                 0x80
  50 /* TLP configuration type 0 and 1 */
  51 #define TLP_FMTTYPE_CFGRD0              0x04    /* Configuration Read Type 0 */
  52 #define TLP_FMTTYPE_CFGWR0              0x44    /* Configuration Write Type 0 */
  53 #define TLP_FMTTYPE_CFGRD1              0x05    /* Configuration Read Type 1 */
  54 #define TLP_FMTTYPE_CFGWR1              0x45    /* Configuration Write Type 1 */
  55 #define TLP_PAYLOAD_SIZE                0x01
  56 #define TLP_READ_TAG                    0x1d
  57 #define TLP_WRITE_TAG                   0x10
  58 #define RP_DEVFN                        0
  59 #define TLP_REQ_ID(bus, devfn)          (((bus) << 8) | (devfn))
  60 #define TLP_CFG_DW0(pcie, bus)                                          \
  61     ((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0                  \
  62                                     : TLP_FMTTYPE_CFGRD1) << 24) |      \
  63      TLP_PAYLOAD_SIZE)
  64 #define TLP_CFG_DW1(pcie, tag, be)      \
  65     (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
  66 #define TLP_CFG_DW2(bus, devfn, offset) \
  67                                 (((bus) << 24) | ((devfn) << 16) | (offset))
  68 #define TLP_COMP_STATUS(s)              (((s) >> 12) & 7)
  69 #define TLP_HDR_SIZE                    3
  70 #define TLP_LOOP                        500
  71
  72 #define LINK_UP_TIMEOUT                 HZ
  73 #define LINK_RETRAIN_TIMEOUT            HZ
  74
  75 #define INTX_NUM                        4
  76
  77 #define DWORD_MASK                      3
  78
  79 struct altera_pcie {
  80         struct platform_device  *pdev;
  81         void __iomem            *cra_base;      /* DT Cra */
  82         int                     irq;
  83         u8                      root_bus_nr;
  84         struct irq_domain       *irq_domain;
  85         struct resource         bus_range;
  86         struct list_head        resources;
  87 };
  88
  89 struct tlp_rp_regpair_t {
  90         u32 ctrl;
  91         u32 reg0;
  92         u32 reg1;
  93 };
  94
  95 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
  96                               const u32 reg)
  97 {
  98         writel_relaxed(value, pcie->cra_base + reg);
  99 }
 100
 101 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
 102 {
 103         return readl_relaxed(pcie->cra_base + reg);
 104 }
 105
 106 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
 107 {
 108         return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 109 }
 110
 111 /*
 112  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 113  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 114  * using these registers, so it can be reached by DMA from EP devices.
 115  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 116  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 117  * should be hidden during enumeration to avoid the sizing and resource
 118  * allocation by PCIe core.
 119  */
 120 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
 121                                     int offset)
 122 {
 123         if (pci_is_root_bus(bus) && (devfn == 0) &&
 124             (offset == PCI_BASE_ADDRESS_0))
 125                 return true;
 126
 127         return false;
 128 }
 129
 130 static void tlp_write_tx(struct altera_pcie *pcie,
 131                          struct tlp_rp_regpair_t *tlp_rp_regdata)
 132 {
 133         cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
 134         cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
 135         cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 136 }
 137
 138 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
 139                                      struct pci_bus *bus, int dev)
 140 {
 141         /* If there is no link, then there is no device */
 142         if (bus->number != pcie->root_bus_nr) {
 143                 if (!altera_pcie_link_is_up(pcie))
 144                         return false;
 145         }
 146
 147         /* access only one slot on each root port */
 148         if (bus->number == pcie->root_bus_nr && dev > 0)
 149                 return false;
 150
 151          return true;
 152 }
 153
 154 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 155 {
 156         int i;
 157         bool sop = 0;
 158         u32 ctrl;
 159         u32 reg0, reg1;
 160         u32 comp_status = 1;
 161
 162         /*
 163          * Minimum 2 loops to read TLP headers and 1 loop to read data
 164          * payload.
 165          */
 166         for (i = 0; i < TLP_LOOP; i++) {
 167                 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
 168                 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
 169                         reg0 = cra_readl(pcie, RP_RXCPL_REG0);
 170                         reg1 = cra_readl(pcie, RP_RXCPL_REG1);
 171
 172                         if (ctrl & RP_RXCPL_SOP) {
 173                                 sop = true;
 174                                 comp_status = TLP_COMP_STATUS(reg1);
 175                         }
 176
 177                         if (ctrl & RP_RXCPL_EOP) {
 178                                 if (comp_status)
 179                                         return PCIBIOS_DEVICE_NOT_FOUND;
 180
 181                                 if (value)
 182                                         *value = reg0;
 183
 184                                 return PCIBIOS_SUCCESSFUL;
 185                         }
 186                 }
 187                 udelay(5);
 188         }
 189
 190         return PCIBIOS_DEVICE_NOT_FOUND;
 191 }
 192
 193 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 194                              u32 data, bool align)
 195 {
 196         struct tlp_rp_regpair_t tlp_rp_regdata;
 197
 198         tlp_rp_regdata.reg0 = headers[0];
 199         tlp_rp_regdata.reg1 = headers[1];
 200         tlp_rp_regdata.ctrl = RP_TX_SOP;
 201         tlp_write_tx(pcie, &tlp_rp_regdata);
 202
 203         if (align) {
 204                 tlp_rp_regdata.reg0 = headers[2];
 205                 tlp_rp_regdata.reg1 = 0;
 206                 tlp_rp_regdata.ctrl = 0;
 207                 tlp_write_tx(pcie, &tlp_rp_regdata);
 208
 209                 tlp_rp_regdata.reg0 = data;
 210                 tlp_rp_regdata.reg1 = 0;
 211         } else {
 212                 tlp_rp_regdata.reg0 = headers[2];
 213                 tlp_rp_regdata.reg1 = data;
 214         }
 215
 216         tlp_rp_regdata.ctrl = RP_TX_EOP;
 217         tlp_write_tx(pcie, &tlp_rp_regdata);
 218 }
 219
 220 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
 221                               int where, u8 byte_en, u32 *value)
 222 {
 223         u32 headers[TLP_HDR_SIZE];
 224
 225         headers[0] = TLP_CFG_DW0(pcie, bus);
 226         headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
 227         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 228
 229         tlp_write_packet(pcie, headers, 0, false);
 230
 231         return tlp_read_packet(pcie, value);
 232 }
 233
 234 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
 235                                int where, u8 byte_en, u32 value)
 236 {
 237         u32 headers[TLP_HDR_SIZE];
 238         int ret;
 239
 240         headers[0] = TLP_CFG_DW0(pcie, bus);
 241         headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
 242         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 243
 244         /* check alignment to Qword */
 245         if ((where & 0x7) == 0)
 246                 tlp_write_packet(pcie, headers, value, true);
 247         else
 248                 tlp_write_packet(pcie, headers, value, false);
 249
 250         ret = tlp_read_packet(pcie, NULL);
 251         if (ret != PCIBIOS_SUCCESSFUL)
 252                 return ret;
 253
 254         /*
 255          * Monitor changes to PCI_PRIMARY_BUS register on root port
 256          * and update local copy of root bus number accordingly.
 257          */
 258         if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
 259                 pcie->root_bus_nr = (u8)(value);
 260
 261         return PCIBIOS_SUCCESSFUL;
 262 }
 263
 264 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 265                                  unsigned int devfn, int where, int size,
 266                                  u32 *value)
 267 {
 268         int ret;
 269         u32 data;
 270         u8 byte_en;
 271
 272         switch (size) {
 273         case 1:
 274                 byte_en = 1 << (where & 3);
 275                 break;
 276         case 2:
 277                 byte_en = 3 << (where & 3);
 278                 break;
 279         default:
 280                 byte_en = 0xf;
 281                 break;
 282         }
 283
 284         ret = tlp_cfg_dword_read(pcie, busno, devfn,
 285                                  (where & ~DWORD_MASK), byte_en, &data);
 286         if (ret != PCIBIOS_SUCCESSFUL)
 287                 return ret;
 288
 289         switch (size) {
 290         case 1:
 291                 *value = (data >> (8 * (where & 0x3))) & 0xff;
 292                 break;
 293         case 2:
 294                 *value = (data >> (8 * (where & 0x2))) & 0xffff;
 295                 break;
 296         default:
 297                 *value = data;
 298                 break;
 299         }
 300
 301         return PCIBIOS_SUCCESSFUL;
 302 }
 303
 304 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
 305                                   unsigned int devfn, int where, int size,
 306                                   u32 value)
 307 {
 308         u32 data32;
 309         u32 shift = 8 * (where & 3);
 310         u8 byte_en;
 311
 312         switch (size) {
 313         case 1:
 314                 data32 = (value & 0xff) << shift;
 315                 byte_en = 1 << (where & 3);
 316                 break;
 317         case 2:
 318                 data32 = (value & 0xffff) << shift;
 319                 byte_en = 3 << (where & 3);
 320                 break;
 321         default:
 322                 data32 = value;
 323                 byte_en = 0xf;
 324                 break;
 325         }
 326
 327         return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
 328                                    byte_en, data32);
 329 }
 330
 331 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
 332                                 int where, int size, u32 *value)
 333 {
 334         struct altera_pcie *pcie = bus->sysdata;
 335
 336         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 337                 return PCIBIOS_BAD_REGISTER_NUMBER;
 338
 339         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
 340                 *value = 0xffffffff;
 341                 return PCIBIOS_DEVICE_NOT_FOUND;
 342         }
 343
 344         return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
 345                                      value);
 346 }
 347
 348 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
 349                                  int where, int size, u32 value)
 350 {
 351         struct altera_pcie *pcie = bus->sysdata;
 352
 353         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 354                 return PCIBIOS_BAD_REGISTER_NUMBER;
 355
 356         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
 357                 return PCIBIOS_DEVICE_NOT_FOUND;
 358
 359         return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
 360                                      value);
 361 }
 362
 363 static struct pci_ops altera_pcie_ops = {
 364         .read = altera_pcie_cfg_read,
 365         .write = altera_pcie_cfg_write,
 366 };
 367
 368 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
 369                                 unsigned int devfn, int offset, u16 *value)
 370 {
 371         u32 data;
 372         int ret;
 373
 374         ret = _altera_pcie_cfg_read(pcie, busno, devfn,
 375                                     PCIE_CAP_OFFSET + offset, sizeof(*value),
 376                                     &data);
 377         *value = data;
 378         return ret;
 379 }
 380
 381 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
 382                                  unsigned int devfn, int offset, u16 value)
 383 {
 384         return _altera_pcie_cfg_write(pcie, busno, devfn,
 385                                       PCIE_CAP_OFFSET + offset, sizeof(value),
 386                                       value);
 387 }
 388
 389 static void altera_wait_link_retrain(struct altera_pcie *pcie)
 390 {
 391         struct device *dev = &pcie->pdev->dev;
 392         u16 reg16;
 393         unsigned long start_jiffies;
 394
 395         /* Wait for link training end. */
 396         start_jiffies = jiffies;
 397         for (;;) {
 398                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 399                                      PCI_EXP_LNKSTA, &reg16);
 400                 if (!(reg16 & PCI_EXP_LNKSTA_LT))
 401                         break;
 402
 403                 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
 404                         dev_err(dev, "link retrain timeout\n");
 405                         break;
 406                 }
 407                 udelay(100);
 408         }
 409
 410         /* Wait for link is up */
 411         start_jiffies = jiffies;
 412         for (;;) {
 413                 if (altera_pcie_link_is_up(pcie))
 414                         break;
 415
 416                 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
 417                         dev_err(dev, "link up timeout\n");
 418                         break;
 419                 }
 420                 udelay(100);
 421         }
 422 }
 423
 424 static void altera_pcie_retrain(struct altera_pcie *pcie)
 425 {
 426         u16 linkcap, linkstat, linkctl;
 427
 428         if (!altera_pcie_link_is_up(pcie))
 429                 return;
 430
 431         /*
 432          * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
 433          * current speed is 2.5 GB/s.
 434          */
 435         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
 436                              &linkcap);
 437         if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
 438                 return;
 439
 440         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
 441                              &linkstat);
 442         if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
 443                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 444                                      PCI_EXP_LNKCTL, &linkctl);
 445                 linkctl |= PCI_EXP_LNKCTL_RL;
 446                 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 447                                       PCI_EXP_LNKCTL, linkctl);
 448
 449                 altera_wait_link_retrain(pcie);
 450         }
 451 }
 452
 453 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 454                                 irq_hw_number_t hwirq)
 455 {
 456         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 457         irq_set_chip_data(irq, domain->host_data);
 458         return 0;
 459 }
 460
 461 static const struct irq_domain_ops intx_domain_ops = {
 462         .map = altera_pcie_intx_map,
 463 };
 464
 465 static void altera_pcie_isr(struct irq_desc *desc)
 466 {
 467         struct irq_chip *chip = irq_desc_get_chip(desc);
 468         struct altera_pcie *pcie;
 469         struct device *dev;
 470         unsigned long status;
 471         u32 bit;
 472         u32 virq;
 473
 474         chained_irq_enter(chip, desc);
 475         pcie = irq_desc_get_handler_data(desc);
 476         dev = &pcie->pdev->dev;
 477
 478         while ((status = cra_readl(pcie, P2A_INT_STATUS)
 479                 & P2A_INT_STS_ALL) != 0) {
 480                 for_each_set_bit(bit, &status, INTX_NUM) {
 481                         /* clear interrupts */
 482                         cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
 483
 484                         virq = irq_find_mapping(pcie->irq_domain, bit + 1);
 485                         if (virq)
 486                                 generic_handle_irq(virq);
 487                         else
 488                                 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
 489                 }
 490         }
 491
 492         chained_irq_exit(chip, desc);
 493 }
 494
 495 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
 496 {
 497         int err, res_valid = 0;
 498         struct device *dev = &pcie->pdev->dev;
 499         struct device_node *np = dev->of_node;
 500         struct resource_entry *win;
 501
 502         err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
 503                                                NULL);
 504         if (err)
 505                 return err;
 506
 507         err = devm_request_pci_bus_resources(dev, &pcie->resources);
 508         if (err)
 509                 goto out_release_res;
 510
 511         resource_list_for_each_entry(win, &pcie->resources) {
 512                 struct resource *res = win->res;
 513
 514                 if (resource_type(res) == IORESOURCE_MEM)
 515                         res_valid |= !(res->flags & IORESOURCE_PREFETCH);
 516         }
 517
 518         if (res_valid)
 519                 return 0;
 520
 521         dev_err(dev, "non-prefetchable memory resource required\n");
 522         err = -EINVAL;
 523
 524 out_release_res:
 525         pci_free_resource_list(&pcie->resources);
 526         return err;
 527 }
 528
 529 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
 530 {
 531         struct device *dev = &pcie->pdev->dev;
 532         struct device_node *node = dev->of_node;
 533
 534         /* Setup INTx */
 535         pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
 536                                         &intx_domain_ops, pcie);
 537         if (!pcie->irq_domain) {
 538                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 539                 return -ENOMEM;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 546 {
 547         struct device *dev = &pcie->pdev->dev;
 548         struct platform_device *pdev = pcie->pdev;
 549         struct resource *cra;
 550
 551         cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
 552         pcie->cra_base = devm_ioremap_resource(dev, cra);
 553         if (IS_ERR(pcie->cra_base))
 554                 return PTR_ERR(pcie->cra_base);
 555
 556         /* setup IRQ */
 557         pcie->irq = platform_get_irq(pdev, 0);
 558         if (pcie->irq <= 0) {
 559                 dev_err(dev, "failed to get IRQ: %d\n", pcie->irq);
 560                 return -EINVAL;
 561         }
 562
 563         irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
 564         return 0;
 565 }
 566
 567 static void altera_pcie_host_init(struct altera_pcie *pcie)
 568 {
 569         altera_pcie_retrain(pcie);
 570 }
 571
 572 static int altera_pcie_probe(struct platform_device *pdev)
 573 {
 574         struct device *dev = &pdev->dev;
 575         struct altera_pcie *pcie;
 576         struct pci_bus *bus;
 577         struct pci_bus *child;
 578         int ret;
 579
 580         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 581         if (!pcie)
 582                 return -ENOMEM;
 583
 584         pcie->pdev = pdev;
 585
 586         ret = altera_pcie_parse_dt(pcie);
 587         if (ret) {
 588                 dev_err(dev, "Parsing DT failed\n");
 589                 return ret;
 590         }
 591
 592         INIT_LIST_HEAD(&pcie->resources);
 593
 594         ret = altera_pcie_parse_request_of_pci_ranges(pcie);
 595         if (ret) {
 596                 dev_err(dev, "Failed add resources\n");
 597                 return ret;
 598         }
 599
 600         ret = altera_pcie_init_irq_domain(pcie);
 601         if (ret) {
 602                 dev_err(dev, "Failed creating IRQ Domain\n");
 603                 return ret;
 604         }
 605
 606         /* clear all interrupts */
 607         cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
 608         /* enable all interrupts */
 609         cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
 610         altera_pcie_host_init(pcie);
 611
 612         bus = pci_scan_root_bus(dev, pcie->root_bus_nr, &altera_pcie_ops,
 613                                 pcie, &pcie->resources);
 614         if (!bus)
 615                 return -ENOMEM;
 616
 617         pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
 618         pci_assign_unassigned_bus_resources(bus);
 619
 620         /* Configure PCI Express setting. */
 621         list_for_each_entry(child, &bus->children, node)
 622                 pcie_bus_configure_settings(child);
 623
 624         pci_bus_add_devices(bus);
 625         return ret;
 626 }
 627
 628 static const struct of_device_id altera_pcie_of_match[] = {
 629         { .compatible = "altr,pcie-root-port-1.0", },
 630         {},
 631 };
 632
 633 static struct platform_driver altera_pcie_driver = {
 634         .probe          = altera_pcie_probe,
 635         .driver = {
 636                 .name   = "altera-pcie",
 637                 .of_match_table = altera_pcie_of_match,
 638                 .suppress_bind_attrs = true,
 639         },
 640 };
 641
 642 builtin_platform_driver(altera_pcie_driver);