drivers/pci/host/pcie-designware.h

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef _PCIE_DESIGNWARE_H
  15 #define _PCIE_DESIGNWARE_H
  16
  17 /*
  18  * Maximum number of MSI IRQs can be 256 per controller. But keep
  19  * it 32 as of now. Probably we will never need more than 32. If needed,
  20  * then increment it in multiple of 32.
  21  */
  22 #define MAX_MSI_IRQS                    32
  23 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
  24
  25 struct pcie_port {
  26         struct device           *dev;
  27         u8                      root_bus_nr;
  28         void __iomem            *dbi_base;
  29         u64                     cfg0_base;
  30         void __iomem            *va_cfg0_base;
  31         u32                     cfg0_size;
  32         u64                     cfg1_base;
  33         void __iomem            *va_cfg1_base;
  34         u32                     cfg1_size;
  35         resource_size_t         io_base;
  36         phys_addr_t             io_bus_addr;
  37         u32                     io_size;
  38         u64                     mem_base;
  39         phys_addr_t             mem_bus_addr;
  40         u32                     mem_size;
  41         struct resource         *cfg;
  42         struct resource         *io;
  43         struct resource         *mem;
  44         struct resource         *busn;
  45         int                     irq;
  46         u32                     lanes;
  47         u32                     num_viewport;
  48         struct pcie_host_ops    *ops;
  49         int                     msi_irq;
  50         struct irq_domain       *irq_domain;
  51         unsigned long           msi_data;
  52         u8                      iatu_unroll_enabled;
  53         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
  54 };
  55
  56 struct pcie_host_ops {
  57         u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
  58         void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
  59         int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
  60         int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
  61         int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
  62                         unsigned int devfn, int where, int size, u32 *val);
  63         int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
  64                         unsigned int devfn, int where, int size, u32 val);
  65         int (*link_up)(struct pcie_port *pp);
  66         void (*host_init)(struct pcie_port *pp);
  67         void (*msi_set_irq)(struct pcie_port *pp, int irq);
  68         void (*msi_clear_irq)(struct pcie_port *pp, int irq);
  69         phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
  70         u32 (*get_msi_data)(struct pcie_port *pp, int pos);
  71         void (*scan_bus)(struct pcie_port *pp);
  72         int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
  73 };
  74
  75 u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);
  76 void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);
  77 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
  78 int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
  79 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
  80 void dw_pcie_msi_init(struct pcie_port *pp);
  81 int dw_pcie_wait_for_link(struct pcie_port *pp);
  82 int dw_pcie_link_up(struct pcie_port *pp);
  83 void dw_pcie_setup_rc(struct pcie_port *pp);
  84 int dw_pcie_host_init(struct pcie_port *pp);
  85
  86 #endif /* _PCIE_DESIGNWARE_H */